max78000_pac/uart0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `RX_THD_VAL` reader - This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"]
6pub type RxThdValR = crate::FieldReader;
7#[doc = "Field `RX_THD_VAL` writer - This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"]
8pub type RxThdValW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `PAR_EN` reader - Parity Enable"]
10pub type ParEnR = crate::BitReader;
11#[doc = "Field `PAR_EN` writer - Parity Enable"]
12pub type ParEnW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PAR_EO` reader - when PAREN=1 selects odd or even parity odd is 1 even is 0"]
14pub type ParEoR = crate::BitReader;
15#[doc = "Field `PAR_EO` writer - when PAREN=1 selects odd or even parity odd is 1 even is 0"]
16pub type ParEoW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PAR_MD` reader - Selects parity based on 1s or 0s count (when PAREN=1)"]
18pub type ParMdR = crate::BitReader;
19#[doc = "Field `PAR_MD` writer - Selects parity based on 1s or 0s count (when PAREN=1)"]
20pub type ParMdW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CTS_DIS` reader - CTS Sampling Disable"]
22pub type CtsDisR = crate::BitReader;
23#[doc = "Field `CTS_DIS` writer - CTS Sampling Disable"]
24pub type CtsDisW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_FLUSH` reader - Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
26pub type TxFlushR = crate::BitReader;
27#[doc = "Field `TX_FLUSH` writer - Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
28pub type TxFlushW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_FLUSH` reader - Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
30pub type RxFlushR = crate::BitReader;
31#[doc = "Field `RX_FLUSH` writer - Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
32pub type RxFlushW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Selects UART character size\n\nValue on reset: 0"]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35#[repr(u8)]
36pub enum CharSize {
37    #[doc = "0: 5 bits"]
38    _5bits = 0,
39    #[doc = "1: 6 bits"]
40    _6bits = 1,
41    #[doc = "2: 7 bits"]
42    _7bits = 2,
43    #[doc = "3: 8 bits"]
44    _8bits = 3,
45}
46impl From<CharSize> for u8 {
47    #[inline(always)]
48    fn from(variant: CharSize) -> Self {
49        variant as _
50    }
51}
52impl crate::FieldSpec for CharSize {
53    type Ux = u8;
54}
55impl crate::IsEnum for CharSize {}
56#[doc = "Field `CHAR_SIZE` reader - Selects UART character size"]
57pub type CharSizeR = crate::FieldReader<CharSize>;
58impl CharSizeR {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub const fn variant(&self) -> CharSize {
62        match self.bits {
63            0 => CharSize::_5bits,
64            1 => CharSize::_6bits,
65            2 => CharSize::_7bits,
66            3 => CharSize::_8bits,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "5 bits"]
71    #[inline(always)]
72    pub fn is_5bits(&self) -> bool {
73        *self == CharSize::_5bits
74    }
75    #[doc = "6 bits"]
76    #[inline(always)]
77    pub fn is_6bits(&self) -> bool {
78        *self == CharSize::_6bits
79    }
80    #[doc = "7 bits"]
81    #[inline(always)]
82    pub fn is_7bits(&self) -> bool {
83        *self == CharSize::_7bits
84    }
85    #[doc = "8 bits"]
86    #[inline(always)]
87    pub fn is_8bits(&self) -> bool {
88        *self == CharSize::_8bits
89    }
90}
91#[doc = "Field `CHAR_SIZE` writer - Selects UART character size"]
92pub type CharSizeW<'a, REG> = crate::FieldWriter<'a, REG, 2, CharSize, crate::Safe>;
93impl<'a, REG> CharSizeW<'a, REG>
94where
95    REG: crate::Writable + crate::RegisterSpec,
96    REG::Ux: From<u8>,
97{
98    #[doc = "5 bits"]
99    #[inline(always)]
100    pub fn _5bits(self) -> &'a mut crate::W<REG> {
101        self.variant(CharSize::_5bits)
102    }
103    #[doc = "6 bits"]
104    #[inline(always)]
105    pub fn _6bits(self) -> &'a mut crate::W<REG> {
106        self.variant(CharSize::_6bits)
107    }
108    #[doc = "7 bits"]
109    #[inline(always)]
110    pub fn _7bits(self) -> &'a mut crate::W<REG> {
111        self.variant(CharSize::_7bits)
112    }
113    #[doc = "8 bits"]
114    #[inline(always)]
115    pub fn _8bits(self) -> &'a mut crate::W<REG> {
116        self.variant(CharSize::_8bits)
117    }
118}
119#[doc = "Field `STOPBITS` reader - Selects the number of stop bits that will be generated"]
120pub type StopbitsR = crate::BitReader;
121#[doc = "Field `STOPBITS` writer - Selects the number of stop bits that will be generated"]
122pub type StopbitsW<'a, REG> = crate::BitWriter<'a, REG>;
123#[doc = "Field `HFC_EN` reader - Enables/disables hardware flow control"]
124pub type HfcEnR = crate::BitReader;
125#[doc = "Field `HFC_EN` writer - Enables/disables hardware flow control"]
126pub type HfcEnW<'a, REG> = crate::BitWriter<'a, REG>;
127#[doc = "Field `RTSDC` reader - Hardware Flow Control RTS Mode"]
128pub type RtsdcR = crate::BitReader;
129#[doc = "Field `RTSDC` writer - Hardware Flow Control RTS Mode"]
130pub type RtsdcW<'a, REG> = crate::BitWriter<'a, REG>;
131#[doc = "Field `BCLKEN` reader - Baud clock enable"]
132pub type BclkenR = crate::BitReader;
133#[doc = "Field `BCLKEN` writer - Baud clock enable"]
134pub type BclkenW<'a, REG> = crate::BitWriter<'a, REG>;
135#[doc = "To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.\n\nValue on reset: 0"]
136#[derive(Clone, Copy, Debug, PartialEq, Eq)]
137#[repr(u8)]
138pub enum Bclksrc {
139    #[doc = "0: apb clock"]
140    PeripheralClock = 0,
141    #[doc = "1: Clock 1"]
142    ExternalClock = 1,
143    #[doc = "2: Clock 2"]
144    Clk2 = 2,
145    #[doc = "3: Clock 3"]
146    Clk3 = 3,
147}
148impl From<Bclksrc> for u8 {
149    #[inline(always)]
150    fn from(variant: Bclksrc) -> Self {
151        variant as _
152    }
153}
154impl crate::FieldSpec for Bclksrc {
155    type Ux = u8;
156}
157impl crate::IsEnum for Bclksrc {}
158#[doc = "Field `BCLKSRC` reader - To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock."]
159pub type BclksrcR = crate::FieldReader<Bclksrc>;
160impl BclksrcR {
161    #[doc = "Get enumerated values variant"]
162    #[inline(always)]
163    pub const fn variant(&self) -> Bclksrc {
164        match self.bits {
165            0 => Bclksrc::PeripheralClock,
166            1 => Bclksrc::ExternalClock,
167            2 => Bclksrc::Clk2,
168            3 => Bclksrc::Clk3,
169            _ => unreachable!(),
170        }
171    }
172    #[doc = "apb clock"]
173    #[inline(always)]
174    pub fn is_peripheral_clock(&self) -> bool {
175        *self == Bclksrc::PeripheralClock
176    }
177    #[doc = "Clock 1"]
178    #[inline(always)]
179    pub fn is_external_clock(&self) -> bool {
180        *self == Bclksrc::ExternalClock
181    }
182    #[doc = "Clock 2"]
183    #[inline(always)]
184    pub fn is_clk2(&self) -> bool {
185        *self == Bclksrc::Clk2
186    }
187    #[doc = "Clock 3"]
188    #[inline(always)]
189    pub fn is_clk3(&self) -> bool {
190        *self == Bclksrc::Clk3
191    }
192}
193#[doc = "Field `BCLKSRC` writer - To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock."]
194pub type BclksrcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Bclksrc, crate::Safe>;
195impl<'a, REG> BclksrcW<'a, REG>
196where
197    REG: crate::Writable + crate::RegisterSpec,
198    REG::Ux: From<u8>,
199{
200    #[doc = "apb clock"]
201    #[inline(always)]
202    pub fn peripheral_clock(self) -> &'a mut crate::W<REG> {
203        self.variant(Bclksrc::PeripheralClock)
204    }
205    #[doc = "Clock 1"]
206    #[inline(always)]
207    pub fn external_clock(self) -> &'a mut crate::W<REG> {
208        self.variant(Bclksrc::ExternalClock)
209    }
210    #[doc = "Clock 2"]
211    #[inline(always)]
212    pub fn clk2(self) -> &'a mut crate::W<REG> {
213        self.variant(Bclksrc::Clk2)
214    }
215    #[doc = "Clock 3"]
216    #[inline(always)]
217    pub fn clk3(self) -> &'a mut crate::W<REG> {
218        self.variant(Bclksrc::Clk3)
219    }
220}
221#[doc = "Field `DPFE_EN` reader - Data/Parity bit frame error detection enable"]
222pub type DpfeEnR = crate::BitReader;
223#[doc = "Field `DPFE_EN` writer - Data/Parity bit frame error detection enable"]
224pub type DpfeEnW<'a, REG> = crate::BitWriter<'a, REG>;
225#[doc = "Field `BCLKRDY` reader - Baud clock Ready read only bit"]
226pub type BclkrdyR = crate::BitReader;
227#[doc = "Field `BCLKRDY` writer - Baud clock Ready read only bit"]
228pub type BclkrdyW<'a, REG> = crate::BitWriter<'a, REG>;
229#[doc = "Field `UCAGM` reader - UART Clock Auto Gating mode"]
230pub type UcagmR = crate::BitReader;
231#[doc = "Field `UCAGM` writer - UART Clock Auto Gating mode"]
232pub type UcagmW<'a, REG> = crate::BitWriter<'a, REG>;
233#[doc = "Field `FDM` reader - Fractional Division Mode"]
234pub type FdmR = crate::BitReader;
235#[doc = "Field `FDM` writer - Fractional Division Mode"]
236pub type FdmW<'a, REG> = crate::BitWriter<'a, REG>;
237#[doc = "Field `DESM` reader - RX Dual Edge Sampling Mode"]
238pub type DesmR = crate::BitReader;
239#[doc = "Field `DESM` writer - RX Dual Edge Sampling Mode"]
240pub type DesmW<'a, REG> = crate::BitWriter<'a, REG>;
241impl R {
242    #[doc = "Bits 0:3 - This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"]
243    #[inline(always)]
244    pub fn rx_thd_val(&self) -> RxThdValR {
245        RxThdValR::new((self.bits & 0x0f) as u8)
246    }
247    #[doc = "Bit 4 - Parity Enable"]
248    #[inline(always)]
249    pub fn par_en(&self) -> ParEnR {
250        ParEnR::new(((self.bits >> 4) & 1) != 0)
251    }
252    #[doc = "Bit 5 - when PAREN=1 selects odd or even parity odd is 1 even is 0"]
253    #[inline(always)]
254    pub fn par_eo(&self) -> ParEoR {
255        ParEoR::new(((self.bits >> 5) & 1) != 0)
256    }
257    #[doc = "Bit 6 - Selects parity based on 1s or 0s count (when PAREN=1)"]
258    #[inline(always)]
259    pub fn par_md(&self) -> ParMdR {
260        ParMdR::new(((self.bits >> 6) & 1) != 0)
261    }
262    #[doc = "Bit 7 - CTS Sampling Disable"]
263    #[inline(always)]
264    pub fn cts_dis(&self) -> CtsDisR {
265        CtsDisR::new(((self.bits >> 7) & 1) != 0)
266    }
267    #[doc = "Bit 8 - Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
268    #[inline(always)]
269    pub fn tx_flush(&self) -> TxFlushR {
270        TxFlushR::new(((self.bits >> 8) & 1) != 0)
271    }
272    #[doc = "Bit 9 - Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
273    #[inline(always)]
274    pub fn rx_flush(&self) -> RxFlushR {
275        RxFlushR::new(((self.bits >> 9) & 1) != 0)
276    }
277    #[doc = "Bits 10:11 - Selects UART character size"]
278    #[inline(always)]
279    pub fn char_size(&self) -> CharSizeR {
280        CharSizeR::new(((self.bits >> 10) & 3) as u8)
281    }
282    #[doc = "Bit 12 - Selects the number of stop bits that will be generated"]
283    #[inline(always)]
284    pub fn stopbits(&self) -> StopbitsR {
285        StopbitsR::new(((self.bits >> 12) & 1) != 0)
286    }
287    #[doc = "Bit 13 - Enables/disables hardware flow control"]
288    #[inline(always)]
289    pub fn hfc_en(&self) -> HfcEnR {
290        HfcEnR::new(((self.bits >> 13) & 1) != 0)
291    }
292    #[doc = "Bit 14 - Hardware Flow Control RTS Mode"]
293    #[inline(always)]
294    pub fn rtsdc(&self) -> RtsdcR {
295        RtsdcR::new(((self.bits >> 14) & 1) != 0)
296    }
297    #[doc = "Bit 15 - Baud clock enable"]
298    #[inline(always)]
299    pub fn bclken(&self) -> BclkenR {
300        BclkenR::new(((self.bits >> 15) & 1) != 0)
301    }
302    #[doc = "Bits 16:17 - To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock."]
303    #[inline(always)]
304    pub fn bclksrc(&self) -> BclksrcR {
305        BclksrcR::new(((self.bits >> 16) & 3) as u8)
306    }
307    #[doc = "Bit 18 - Data/Parity bit frame error detection enable"]
308    #[inline(always)]
309    pub fn dpfe_en(&self) -> DpfeEnR {
310        DpfeEnR::new(((self.bits >> 18) & 1) != 0)
311    }
312    #[doc = "Bit 19 - Baud clock Ready read only bit"]
313    #[inline(always)]
314    pub fn bclkrdy(&self) -> BclkrdyR {
315        BclkrdyR::new(((self.bits >> 19) & 1) != 0)
316    }
317    #[doc = "Bit 20 - UART Clock Auto Gating mode"]
318    #[inline(always)]
319    pub fn ucagm(&self) -> UcagmR {
320        UcagmR::new(((self.bits >> 20) & 1) != 0)
321    }
322    #[doc = "Bit 21 - Fractional Division Mode"]
323    #[inline(always)]
324    pub fn fdm(&self) -> FdmR {
325        FdmR::new(((self.bits >> 21) & 1) != 0)
326    }
327    #[doc = "Bit 22 - RX Dual Edge Sampling Mode"]
328    #[inline(always)]
329    pub fn desm(&self) -> DesmR {
330        DesmR::new(((self.bits >> 22) & 1) != 0)
331    }
332}
333impl W {
334    #[doc = "Bits 0:3 - This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"]
335    #[inline(always)]
336    pub fn rx_thd_val(&mut self) -> RxThdValW<CtrlSpec> {
337        RxThdValW::new(self, 0)
338    }
339    #[doc = "Bit 4 - Parity Enable"]
340    #[inline(always)]
341    pub fn par_en(&mut self) -> ParEnW<CtrlSpec> {
342        ParEnW::new(self, 4)
343    }
344    #[doc = "Bit 5 - when PAREN=1 selects odd or even parity odd is 1 even is 0"]
345    #[inline(always)]
346    pub fn par_eo(&mut self) -> ParEoW<CtrlSpec> {
347        ParEoW::new(self, 5)
348    }
349    #[doc = "Bit 6 - Selects parity based on 1s or 0s count (when PAREN=1)"]
350    #[inline(always)]
351    pub fn par_md(&mut self) -> ParMdW<CtrlSpec> {
352        ParMdW::new(self, 6)
353    }
354    #[doc = "Bit 7 - CTS Sampling Disable"]
355    #[inline(always)]
356    pub fn cts_dis(&mut self) -> CtsDisW<CtrlSpec> {
357        CtsDisW::new(self, 7)
358    }
359    #[doc = "Bit 8 - Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
360    #[inline(always)]
361    pub fn tx_flush(&mut self) -> TxFlushW<CtrlSpec> {
362        TxFlushW::new(self, 8)
363    }
364    #[doc = "Bit 9 - Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed."]
365    #[inline(always)]
366    pub fn rx_flush(&mut self) -> RxFlushW<CtrlSpec> {
367        RxFlushW::new(self, 9)
368    }
369    #[doc = "Bits 10:11 - Selects UART character size"]
370    #[inline(always)]
371    pub fn char_size(&mut self) -> CharSizeW<CtrlSpec> {
372        CharSizeW::new(self, 10)
373    }
374    #[doc = "Bit 12 - Selects the number of stop bits that will be generated"]
375    #[inline(always)]
376    pub fn stopbits(&mut self) -> StopbitsW<CtrlSpec> {
377        StopbitsW::new(self, 12)
378    }
379    #[doc = "Bit 13 - Enables/disables hardware flow control"]
380    #[inline(always)]
381    pub fn hfc_en(&mut self) -> HfcEnW<CtrlSpec> {
382        HfcEnW::new(self, 13)
383    }
384    #[doc = "Bit 14 - Hardware Flow Control RTS Mode"]
385    #[inline(always)]
386    pub fn rtsdc(&mut self) -> RtsdcW<CtrlSpec> {
387        RtsdcW::new(self, 14)
388    }
389    #[doc = "Bit 15 - Baud clock enable"]
390    #[inline(always)]
391    pub fn bclken(&mut self) -> BclkenW<CtrlSpec> {
392        BclkenW::new(self, 15)
393    }
394    #[doc = "Bits 16:17 - To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock."]
395    #[inline(always)]
396    pub fn bclksrc(&mut self) -> BclksrcW<CtrlSpec> {
397        BclksrcW::new(self, 16)
398    }
399    #[doc = "Bit 18 - Data/Parity bit frame error detection enable"]
400    #[inline(always)]
401    pub fn dpfe_en(&mut self) -> DpfeEnW<CtrlSpec> {
402        DpfeEnW::new(self, 18)
403    }
404    #[doc = "Bit 19 - Baud clock Ready read only bit"]
405    #[inline(always)]
406    pub fn bclkrdy(&mut self) -> BclkrdyW<CtrlSpec> {
407        BclkrdyW::new(self, 19)
408    }
409    #[doc = "Bit 20 - UART Clock Auto Gating mode"]
410    #[inline(always)]
411    pub fn ucagm(&mut self) -> UcagmW<CtrlSpec> {
412        UcagmW::new(self, 20)
413    }
414    #[doc = "Bit 21 - Fractional Division Mode"]
415    #[inline(always)]
416    pub fn fdm(&mut self) -> FdmW<CtrlSpec> {
417        FdmW::new(self, 21)
418    }
419    #[doc = "Bit 22 - RX Dual Edge Sampling Mode"]
420    #[inline(always)]
421    pub fn desm(&mut self) -> DesmW<CtrlSpec> {
422        DesmW::new(self, 22)
423    }
424}
425#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
426pub struct CtrlSpec;
427impl crate::RegisterSpec for CtrlSpec {
428    type Ux = u32;
429}
430#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
431impl crate::Readable for CtrlSpec {}
432#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
433impl crate::Writable for CtrlSpec {
434    type Safety = crate::Unsafe;
435    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
436    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
437}
438#[doc = "`reset()` method sets CTRL to value 0"]
439impl crate::Resettable for CtrlSpec {
440    const RESET_VALUE: u32 = 0;
441}
max78000_pac/uart0/ctrl.rs

max78000_pac/uart0/
ctrl.rs
