max78000_pac/trimsir/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `VDDA_LIMITLO` reader - VDDA Low Trim Limit."]
6pub type VddaLimitloR = crate::FieldReader;
7#[doc = "Field `VDDA_LIMITLO` writer - VDDA Low Trim Limit."]
8pub type VddaLimitloW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9#[doc = "Field `VDDA_LIMITHI` reader - VDDA High Trim Limit."]
10pub type VddaLimithiR = crate::FieldReader;
11#[doc = "Field `VDDA_LIMITHI` writer - VDDA High Trim Limit."]
12pub type VddaLimithiW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
13#[doc = "Field `IPO_LIMITHI` reader - IPO High Trim Limit."]
14pub type IpoLimithiR = crate::FieldReader<u16>;
15#[doc = "Field `IPO_LIMITHI` writer - IPO High Trim Limit."]
16pub type IpoLimithiW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
17#[doc = "INRO Clock Select.\n\nValue on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19#[repr(u8)]
20pub enum InroSel {
21    #[doc = "0: `0`"]
22    _8khz = 0,
23    #[doc = "1: `1`"]
24    _16khz = 1,
25    #[doc = "2: `10`"]
26    _30khz = 2,
27}
28impl From<InroSel> for u8 {
29    #[inline(always)]
30    fn from(variant: InroSel) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for InroSel {
35    type Ux = u8;
36}
37impl crate::IsEnum for InroSel {}
38#[doc = "Field `INRO_SEL` reader - INRO Clock Select."]
39pub type InroSelR = crate::FieldReader<InroSel>;
40impl InroSelR {
41    #[doc = "Get enumerated values variant"]
42    #[inline(always)]
43    pub const fn variant(&self) -> Option<InroSel> {
44        match self.bits {
45            0 => Some(InroSel::_8khz),
46            1 => Some(InroSel::_16khz),
47            2 => Some(InroSel::_30khz),
48            _ => None,
49        }
50    }
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn is_8khz(&self) -> bool {
54        *self == InroSel::_8khz
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn is_16khz(&self) -> bool {
59        *self == InroSel::_16khz
60    }
61    #[doc = "`10`"]
62    #[inline(always)]
63    pub fn is_30khz(&self) -> bool {
64        *self == InroSel::_30khz
65    }
66}
67#[doc = "Field `INRO_SEL` writer - INRO Clock Select."]
68pub type InroSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, InroSel>;
69impl<'a, REG> InroSelW<'a, REG>
70where
71    REG: crate::Writable + crate::RegisterSpec,
72    REG::Ux: From<u8>,
73{
74    #[doc = "`0`"]
75    #[inline(always)]
76    pub fn _8khz(self) -> &'a mut crate::W<REG> {
77        self.variant(InroSel::_8khz)
78    }
79    #[doc = "`1`"]
80    #[inline(always)]
81    pub fn _16khz(self) -> &'a mut crate::W<REG> {
82        self.variant(InroSel::_16khz)
83    }
84    #[doc = "`10`"]
85    #[inline(always)]
86    pub fn _30khz(self) -> &'a mut crate::W<REG> {
87        self.variant(InroSel::_30khz)
88    }
89}
90#[doc = "Field `INRO_TRIM` reader - INRO Clock Trim."]
91pub type InroTrimR = crate::FieldReader;
92#[doc = "Field `INRO_TRIM` writer - INRO Clock Trim."]
93pub type InroTrimW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
94impl R {
95    #[doc = "Bits 0:6 - VDDA Low Trim Limit."]
96    #[inline(always)]
97    pub fn vdda_limitlo(&self) -> VddaLimitloR {
98        VddaLimitloR::new((self.bits & 0x7f) as u8)
99    }
100    #[doc = "Bits 8:14 - VDDA High Trim Limit."]
101    #[inline(always)]
102    pub fn vdda_limithi(&self) -> VddaLimithiR {
103        VddaLimithiR::new(((self.bits >> 8) & 0x7f) as u8)
104    }
105    #[doc = "Bits 15:23 - IPO High Trim Limit."]
106    #[inline(always)]
107    pub fn ipo_limithi(&self) -> IpoLimithiR {
108        IpoLimithiR::new(((self.bits >> 15) & 0x01ff) as u16)
109    }
110    #[doc = "Bits 24:25 - INRO Clock Select."]
111    #[inline(always)]
112    pub fn inro_sel(&self) -> InroSelR {
113        InroSelR::new(((self.bits >> 24) & 3) as u8)
114    }
115    #[doc = "Bits 29:31 - INRO Clock Trim."]
116    #[inline(always)]
117    pub fn inro_trim(&self) -> InroTrimR {
118        InroTrimR::new(((self.bits >> 29) & 7) as u8)
119    }
120}
121impl W {
122    #[doc = "Bits 0:6 - VDDA Low Trim Limit."]
123    #[inline(always)]
124    pub fn vdda_limitlo(&mut self) -> VddaLimitloW<CtrlSpec> {
125        VddaLimitloW::new(self, 0)
126    }
127    #[doc = "Bits 8:14 - VDDA High Trim Limit."]
128    #[inline(always)]
129    pub fn vdda_limithi(&mut self) -> VddaLimithiW<CtrlSpec> {
130        VddaLimithiW::new(self, 8)
131    }
132    #[doc = "Bits 15:23 - IPO High Trim Limit."]
133    #[inline(always)]
134    pub fn ipo_limithi(&mut self) -> IpoLimithiW<CtrlSpec> {
135        IpoLimithiW::new(self, 15)
136    }
137    #[doc = "Bits 24:25 - INRO Clock Select."]
138    #[inline(always)]
139    pub fn inro_sel(&mut self) -> InroSelW<CtrlSpec> {
140        InroSelW::new(self, 24)
141    }
142    #[doc = "Bits 29:31 - INRO Clock Trim."]
143    #[inline(always)]
144    pub fn inro_trim(&mut self) -> InroTrimW<CtrlSpec> {
145        InroTrimW::new(self, 29)
146    }
147}
148#[doc = "Control Trim System Initialization Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
149pub struct CtrlSpec;
150impl crate::RegisterSpec for CtrlSpec {
151    type Ux = u32;
152}
153#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
154impl crate::Readable for CtrlSpec {}
155#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
156impl crate::Writable for CtrlSpec {
157    type Safety = crate::Unsafe;
158    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
159    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
160}
161#[doc = "`reset()` method sets CTRL to value 0"]
162impl crate::Resettable for CtrlSpec {
163    const RESET_VALUE: u32 = 0;
164}
max78000_pac/trimsir/ctrl.rs

max78000_pac/trimsir/
ctrl.rs
