max78000_pac/i2c0/
mstctrl.rs

1#[doc = "Register `MSTCTRL` reader"]
2pub type R = crate::R<MstctrlSpec>;
3#[doc = "Register `MSTCTRL` writer"]
4pub type W = crate::W<MstctrlSpec>;
5#[doc = "Field `START` reader - Setting this bit to 1 will start a master transfer."]
6pub type StartR = crate::BitReader;
7#[doc = "Field `START` writer - Setting this bit to 1 will start a master transfer."]
8pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RESTART` reader - Setting this bit to 1 will generate a repeated START."]
10pub type RestartR = crate::BitReader;
11#[doc = "Field `RESTART` writer - Setting this bit to 1 will generate a repeated START."]
12pub type RestartW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `STOP` reader - Setting this bit to 1 will generate a STOP condition."]
14pub type StopR = crate::BitReader;
15#[doc = "Field `STOP` writer - Setting this bit to 1 will generate a STOP condition."]
16pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Slave Extend Address Select.\n\nValue on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19pub enum ExAddrEn {
20    #[doc = "0: 7-bit address."]
21    _7BitsAddress = 0,
22    #[doc = "1: 10-bit address."]
23    _10BitsAddress = 1,
24}
25impl From<ExAddrEn> for bool {
26    #[inline(always)]
27    fn from(variant: ExAddrEn) -> Self {
28        variant as u8 != 0
29    }
30}
31#[doc = "Field `EX_ADDR_EN` reader - Slave Extend Address Select."]
32pub type ExAddrEnR = crate::BitReader<ExAddrEn>;
33impl ExAddrEnR {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> ExAddrEn {
37        match self.bits {
38            false => ExAddrEn::_7BitsAddress,
39            true => ExAddrEn::_10BitsAddress,
40        }
41    }
42    #[doc = "7-bit address."]
43    #[inline(always)]
44    pub fn is_7_bits_address(&self) -> bool {
45        *self == ExAddrEn::_7BitsAddress
46    }
47    #[doc = "10-bit address."]
48    #[inline(always)]
49    pub fn is_10_bits_address(&self) -> bool {
50        *self == ExAddrEn::_10BitsAddress
51    }
52}
53#[doc = "Field `EX_ADDR_EN` writer - Slave Extend Address Select."]
54pub type ExAddrEnW<'a, REG> = crate::BitWriter<'a, REG, ExAddrEn>;
55impl<'a, REG> ExAddrEnW<'a, REG>
56where
57    REG: crate::Writable + crate::RegisterSpec,
58{
59    #[doc = "7-bit address."]
60    #[inline(always)]
61    pub fn _7_bits_address(self) -> &'a mut crate::W<REG> {
62        self.variant(ExAddrEn::_7BitsAddress)
63    }
64    #[doc = "10-bit address."]
65    #[inline(always)]
66    pub fn _10_bits_address(self) -> &'a mut crate::W<REG> {
67        self.variant(ExAddrEn::_10BitsAddress)
68    }
69}
70impl R {
71    #[doc = "Bit 0 - Setting this bit to 1 will start a master transfer."]
72    #[inline(always)]
73    pub fn start(&self) -> StartR {
74        StartR::new((self.bits & 1) != 0)
75    }
76    #[doc = "Bit 1 - Setting this bit to 1 will generate a repeated START."]
77    #[inline(always)]
78    pub fn restart(&self) -> RestartR {
79        RestartR::new(((self.bits >> 1) & 1) != 0)
80    }
81    #[doc = "Bit 2 - Setting this bit to 1 will generate a STOP condition."]
82    #[inline(always)]
83    pub fn stop(&self) -> StopR {
84        StopR::new(((self.bits >> 2) & 1) != 0)
85    }
86    #[doc = "Bit 7 - Slave Extend Address Select."]
87    #[inline(always)]
88    pub fn ex_addr_en(&self) -> ExAddrEnR {
89        ExAddrEnR::new(((self.bits >> 7) & 1) != 0)
90    }
91}
92impl W {
93    #[doc = "Bit 0 - Setting this bit to 1 will start a master transfer."]
94    #[inline(always)]
95    pub fn start(&mut self) -> StartW<MstctrlSpec> {
96        StartW::new(self, 0)
97    }
98    #[doc = "Bit 1 - Setting this bit to 1 will generate a repeated START."]
99    #[inline(always)]
100    pub fn restart(&mut self) -> RestartW<MstctrlSpec> {
101        RestartW::new(self, 1)
102    }
103    #[doc = "Bit 2 - Setting this bit to 1 will generate a STOP condition."]
104    #[inline(always)]
105    pub fn stop(&mut self) -> StopW<MstctrlSpec> {
106        StopW::new(self, 2)
107    }
108    #[doc = "Bit 7 - Slave Extend Address Select."]
109    #[inline(always)]
110    pub fn ex_addr_en(&mut self) -> ExAddrEnW<MstctrlSpec> {
111        ExAddrEnW::new(self, 7)
112    }
113}
114#[doc = "Master Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mstctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct MstctrlSpec;
116impl crate::RegisterSpec for MstctrlSpec {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`mstctrl::R`](R) reader structure"]
120impl crate::Readable for MstctrlSpec {}
121#[doc = "`write(|w| ..)` method takes [`mstctrl::W`](W) writer structure"]
122impl crate::Writable for MstctrlSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets MSTCTRL to value 0"]
128impl crate::Resettable for MstctrlSpec {
129    const RESET_VALUE: u32 = 0;
130}
max78000_pac/i2c0/mstctrl.rs

max78000_pac/i2c0/
mstctrl.rs
