max78000_pac/dma/
inten.rs

1#[doc = "Register `INTEN` reader"]
2pub type R = crate::R<IntenSpec>;
3#[doc = "Register `INTEN` writer"]
4pub type W = crate::W<IntenSpec>;
5#[doc = "Channel 0 Interrupt Enable.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Ch0 {
8    #[doc = "0: Disable."]
9    Dis = 0,
10    #[doc = "1: Enable."]
11    En = 1,
12}
13impl From<Ch0> for bool {
14    #[inline(always)]
15    fn from(variant: Ch0) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CH0` reader - Channel 0 Interrupt Enable."]
20pub type Ch0R = crate::BitReader<Ch0>;
21impl Ch0R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Ch0 {
25        match self.bits {
26            false => Ch0::Dis,
27            true => Ch0::En,
28        }
29    }
30    #[doc = "Disable."]
31    #[inline(always)]
32    pub fn is_dis(&self) -> bool {
33        *self == Ch0::Dis
34    }
35    #[doc = "Enable."]
36    #[inline(always)]
37    pub fn is_en(&self) -> bool {
38        *self == Ch0::En
39    }
40}
41#[doc = "Field `CH0` writer - Channel 0 Interrupt Enable."]
42pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG, Ch0>;
43impl<'a, REG> Ch0W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable."]
48    #[inline(always)]
49    pub fn dis(self) -> &'a mut crate::W<REG> {
50        self.variant(Ch0::Dis)
51    }
52    #[doc = "Enable."]
53    #[inline(always)]
54    pub fn en(self) -> &'a mut crate::W<REG> {
55        self.variant(Ch0::En)
56    }
57}
58#[doc = "Channel 1 Interrupt Enable."]
59pub use Ch0 as Ch1;
60#[doc = "Channel 2 Interrupt Enable."]
61pub use Ch0 as Ch2;
62#[doc = "Channel 3 Interrupt Enable."]
63pub use Ch0 as Ch3;
64#[doc = "Field `CH1` reader - Channel 1 Interrupt Enable."]
65pub use Ch0R as Ch1R;
66#[doc = "Field `CH2` reader - Channel 2 Interrupt Enable."]
67pub use Ch0R as Ch2R;
68#[doc = "Field `CH3` reader - Channel 3 Interrupt Enable."]
69pub use Ch0R as Ch3R;
70#[doc = "Field `CH1` writer - Channel 1 Interrupt Enable."]
71pub use Ch0W as Ch1W;
72#[doc = "Field `CH2` writer - Channel 2 Interrupt Enable."]
73pub use Ch0W as Ch2W;
74#[doc = "Field `CH3` writer - Channel 3 Interrupt Enable."]
75pub use Ch0W as Ch3W;
76impl R {
77    #[doc = "Bit 0 - Channel 0 Interrupt Enable."]
78    #[inline(always)]
79    pub fn ch0(&self) -> Ch0R {
80        Ch0R::new((self.bits & 1) != 0)
81    }
82    #[doc = "Bit 1 - Channel 1 Interrupt Enable."]
83    #[inline(always)]
84    pub fn ch1(&self) -> Ch1R {
85        Ch1R::new(((self.bits >> 1) & 1) != 0)
86    }
87    #[doc = "Bit 2 - Channel 2 Interrupt Enable."]
88    #[inline(always)]
89    pub fn ch2(&self) -> Ch2R {
90        Ch2R::new(((self.bits >> 2) & 1) != 0)
91    }
92    #[doc = "Bit 3 - Channel 3 Interrupt Enable."]
93    #[inline(always)]
94    pub fn ch3(&self) -> Ch3R {
95        Ch3R::new(((self.bits >> 3) & 1) != 0)
96    }
97}
98impl W {
99    #[doc = "Bit 0 - Channel 0 Interrupt Enable."]
100    #[inline(always)]
101    pub fn ch0(&mut self) -> Ch0W<IntenSpec> {
102        Ch0W::new(self, 0)
103    }
104    #[doc = "Bit 1 - Channel 1 Interrupt Enable."]
105    #[inline(always)]
106    pub fn ch1(&mut self) -> Ch1W<IntenSpec> {
107        Ch1W::new(self, 1)
108    }
109    #[doc = "Bit 2 - Channel 2 Interrupt Enable."]
110    #[inline(always)]
111    pub fn ch2(&mut self) -> Ch2W<IntenSpec> {
112        Ch2W::new(self, 2)
113    }
114    #[doc = "Bit 3 - Channel 3 Interrupt Enable."]
115    #[inline(always)]
116    pub fn ch3(&mut self) -> Ch3W<IntenSpec> {
117        Ch3W::new(self, 3)
118    }
119}
120#[doc = "DMA Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
121pub struct IntenSpec;
122impl crate::RegisterSpec for IntenSpec {
123    type Ux = u32;
124}
125#[doc = "`read()` method returns [`inten::R`](R) reader structure"]
126impl crate::Readable for IntenSpec {}
127#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
128impl crate::Writable for IntenSpec {
129    type Safety = crate::Unsafe;
130    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
131    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132}
133#[doc = "`reset()` method sets INTEN to value 0"]
134impl crate::Resettable for IntenSpec {
135    const RESET_VALUE: u32 = 0;
136}
max78000_pac/dma/inten.rs

max78000_pac/dma/
inten.rs
