1#[doc = "Register `SYSCTRL` reader"]
2pub type R = crate::R<SysctrlSpec>;
3#[doc = "Register `SYSCTRL` writer"]
4pub type W = crate::W<SysctrlSpec>;
5#[doc = "Field `BSTAPEN` reader - Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE."]
6pub type BstapenR = crate::BitReader;
7#[doc = "Field `BSTAPEN` writer - Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE."]
8pub type BstapenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum FlashPageFlip {
12 #[doc = "0: Physical layout matches logical layout."]
13 Normal = 0,
14 #[doc = "1: Bottom half mapped to logical top half and vice versa."]
15 Swapped = 1,
16}
17impl From<FlashPageFlip> for bool {
18 #[inline(always)]
19 fn from(variant: FlashPageFlip) -> Self {
20 variant as u8 != 0
21 }
22}
23#[doc = "Field `FLASH_PAGE_FLIP` reader - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer."]
24pub type FlashPageFlipR = crate::BitReader<FlashPageFlip>;
25impl FlashPageFlipR {
26 #[doc = "Get enumerated values variant"]
27 #[inline(always)]
28 pub const fn variant(&self) -> FlashPageFlip {
29 match self.bits {
30 false => FlashPageFlip::Normal,
31 true => FlashPageFlip::Swapped,
32 }
33 }
34 #[doc = "Physical layout matches logical layout."]
35 #[inline(always)]
36 pub fn is_normal(&self) -> bool {
37 *self == FlashPageFlip::Normal
38 }
39 #[doc = "Bottom half mapped to logical top half and vice versa."]
40 #[inline(always)]
41 pub fn is_swapped(&self) -> bool {
42 *self == FlashPageFlip::Swapped
43 }
44}
45#[doc = "Field `FLASH_PAGE_FLIP` writer - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer."]
46pub type FlashPageFlipW<'a, REG> = crate::BitWriter<'a, REG, FlashPageFlip>;
47impl<'a, REG> FlashPageFlipW<'a, REG>
48where
49 REG: crate::Writable + crate::RegisterSpec,
50{
51 #[doc = "Physical layout matches logical layout."]
52 #[inline(always)]
53 pub fn normal(self) -> &'a mut crate::W<REG> {
54 self.variant(FlashPageFlip::Normal)
55 }
56 #[doc = "Bottom half mapped to logical top half and vice versa."]
57 #[inline(always)]
58 pub fn swapped(self) -> &'a mut crate::W<REG> {
59 self.variant(FlashPageFlip::Swapped)
60 }
61}
62#[doc = "Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.\n\nValue on reset: 0"]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum Icc0Flush {
65 #[doc = "0: Normal Code Cache Operation"]
66 Normal = 0,
67 #[doc = "1: Code Caches and CPU instruction buffer are flushed"]
68 Flush = 1,
69}
70impl From<Icc0Flush> for bool {
71 #[inline(always)]
72 fn from(variant: Icc0Flush) -> Self {
73 variant as u8 != 0
74 }
75}
76#[doc = "Field `ICC0_FLUSH` reader - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4."]
77pub type Icc0FlushR = crate::BitReader<Icc0Flush>;
78impl Icc0FlushR {
79 #[doc = "Get enumerated values variant"]
80 #[inline(always)]
81 pub const fn variant(&self) -> Icc0Flush {
82 match self.bits {
83 false => Icc0Flush::Normal,
84 true => Icc0Flush::Flush,
85 }
86 }
87 #[doc = "Normal Code Cache Operation"]
88 #[inline(always)]
89 pub fn is_normal(&self) -> bool {
90 *self == Icc0Flush::Normal
91 }
92 #[doc = "Code Caches and CPU instruction buffer are flushed"]
93 #[inline(always)]
94 pub fn is_flush(&self) -> bool {
95 *self == Icc0Flush::Flush
96 }
97}
98#[doc = "Field `ICC0_FLUSH` writer - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4."]
99pub type Icc0FlushW<'a, REG> = crate::BitWriter<'a, REG, Icc0Flush>;
100impl<'a, REG> Icc0FlushW<'a, REG>
101where
102 REG: crate::Writable + crate::RegisterSpec,
103{
104 #[doc = "Normal Code Cache Operation"]
105 #[inline(always)]
106 pub fn normal(self) -> &'a mut crate::W<REG> {
107 self.variant(Icc0Flush::Normal)
108 }
109 #[doc = "Code Caches and CPU instruction buffer are flushed"]
110 #[inline(always)]
111 pub fn flush(self) -> &'a mut crate::W<REG> {
112 self.variant(Icc0Flush::Flush)
113 }
114}
115#[doc = "Field `ROMDONE` reader - ROM_DONE status. Used to disable SWD interface during system initialization procedure"]
116pub type RomdoneR = crate::BitReader;
117#[doc = "Field `ROMDONE` writer - ROM_DONE status. Used to disable SWD interface during system initialization procedure"]
118pub type RomdoneW<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.\n\nValue on reset: 0"]
120#[derive(Clone, Copy, Debug, PartialEq, Eq)]
121pub enum Cchk {
122 #[doc = "0: No operation/complete."]
123 Complete = 0,
124 #[doc = "1: Start operation."]
125 Start = 1,
126}
127impl From<Cchk> for bool {
128 #[inline(always)]
129 fn from(variant: Cchk) -> Self {
130 variant as u8 != 0
131 }
132}
133#[doc = "Field `CCHK` reader - Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed."]
134pub type CchkR = crate::BitReader<Cchk>;
135impl CchkR {
136 #[doc = "Get enumerated values variant"]
137 #[inline(always)]
138 pub const fn variant(&self) -> Cchk {
139 match self.bits {
140 false => Cchk::Complete,
141 true => Cchk::Start,
142 }
143 }
144 #[doc = "No operation/complete."]
145 #[inline(always)]
146 pub fn is_complete(&self) -> bool {
147 *self == Cchk::Complete
148 }
149 #[doc = "Start operation."]
150 #[inline(always)]
151 pub fn is_start(&self) -> bool {
152 *self == Cchk::Start
153 }
154}
155#[doc = "Field `CCHK` writer - Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed."]
156pub type CchkW<'a, REG> = crate::BitWriter<'a, REG, Cchk>;
157impl<'a, REG> CchkW<'a, REG>
158where
159 REG: crate::Writable + crate::RegisterSpec,
160{
161 #[doc = "No operation/complete."]
162 #[inline(always)]
163 pub fn complete(self) -> &'a mut crate::W<REG> {
164 self.variant(Cchk::Complete)
165 }
166 #[doc = "Start operation."]
167 #[inline(always)]
168 pub fn start(self) -> &'a mut crate::W<REG> {
169 self.variant(Cchk::Start)
170 }
171}
172#[doc = "Field `SWD_DIS` reader - Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)."]
173pub type SwdDisR = crate::BitReader;
174#[doc = "Field `SWD_DIS` writer - Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)."]
175pub type SwdDisW<'a, REG> = crate::BitWriter<'a, REG>;
176#[doc = "ROM Checksum Result. This bit is only valid when CHKRD=1.\n\nValue on reset: 0"]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum Chkres {
179 #[doc = "0: ROM Checksum Correct."]
180 Pass = 0,
181 #[doc = "1: ROM Checksum Fail."]
182 Fail = 1,
183}
184impl From<Chkres> for bool {
185 #[inline(always)]
186 fn from(variant: Chkres) -> Self {
187 variant as u8 != 0
188 }
189}
190#[doc = "Field `CHKRES` reader - ROM Checksum Result. This bit is only valid when CHKRD=1."]
191pub type ChkresR = crate::BitReader<Chkres>;
192impl ChkresR {
193 #[doc = "Get enumerated values variant"]
194 #[inline(always)]
195 pub const fn variant(&self) -> Chkres {
196 match self.bits {
197 false => Chkres::Pass,
198 true => Chkres::Fail,
199 }
200 }
201 #[doc = "ROM Checksum Correct."]
202 #[inline(always)]
203 pub fn is_pass(&self) -> bool {
204 *self == Chkres::Pass
205 }
206 #[doc = "ROM Checksum Fail."]
207 #[inline(always)]
208 pub fn is_fail(&self) -> bool {
209 *self == Chkres::Fail
210 }
211}
212#[doc = "Field `CHKRES` writer - ROM Checksum Result. This bit is only valid when CHKRD=1."]
213pub type ChkresW<'a, REG> = crate::BitWriter<'a, REG, Chkres>;
214impl<'a, REG> ChkresW<'a, REG>
215where
216 REG: crate::Writable + crate::RegisterSpec,
217{
218 #[doc = "ROM Checksum Correct."]
219 #[inline(always)]
220 pub fn pass(self) -> &'a mut crate::W<REG> {
221 self.variant(Chkres::Pass)
222 }
223 #[doc = "ROM Checksum Fail."]
224 #[inline(always)]
225 pub fn fail(self) -> &'a mut crate::W<REG> {
226 self.variant(Chkres::Fail)
227 }
228}
229#[doc = "Field `OVR` reader - Operating Voltage Range."]
230pub type OvrR = crate::FieldReader;
231#[doc = "Field `OVR` writer - Operating Voltage Range."]
232pub type OvrW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
233impl R {
234 #[doc = "Bit 1 - Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE."]
235 #[inline(always)]
236 pub fn bstapen(&self) -> BstapenR {
237 BstapenR::new(((self.bits >> 1) & 1) != 0)
238 }
239 #[doc = "Bit 4 - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer."]
240 #[inline(always)]
241 pub fn flash_page_flip(&self) -> FlashPageFlipR {
242 FlashPageFlipR::new(((self.bits >> 4) & 1) != 0)
243 }
244 #[doc = "Bit 6 - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4."]
245 #[inline(always)]
246 pub fn icc0_flush(&self) -> Icc0FlushR {
247 Icc0FlushR::new(((self.bits >> 6) & 1) != 0)
248 }
249 #[doc = "Bit 12 - ROM_DONE status. Used to disable SWD interface during system initialization procedure"]
250 #[inline(always)]
251 pub fn romdone(&self) -> RomdoneR {
252 RomdoneR::new(((self.bits >> 12) & 1) != 0)
253 }
254 #[doc = "Bit 13 - Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed."]
255 #[inline(always)]
256 pub fn cchk(&self) -> CchkR {
257 CchkR::new(((self.bits >> 13) & 1) != 0)
258 }
259 #[doc = "Bit 14 - Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)."]
260 #[inline(always)]
261 pub fn swd_dis(&self) -> SwdDisR {
262 SwdDisR::new(((self.bits >> 14) & 1) != 0)
263 }
264 #[doc = "Bit 15 - ROM Checksum Result. This bit is only valid when CHKRD=1."]
265 #[inline(always)]
266 pub fn chkres(&self) -> ChkresR {
267 ChkresR::new(((self.bits >> 15) & 1) != 0)
268 }
269 #[doc = "Bits 16:17 - Operating Voltage Range."]
270 #[inline(always)]
271 pub fn ovr(&self) -> OvrR {
272 OvrR::new(((self.bits >> 16) & 3) as u8)
273 }
274}
275impl W {
276 #[doc = "Bit 1 - Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE."]
277 #[inline(always)]
278 pub fn bstapen(&mut self) -> BstapenW<SysctrlSpec> {
279 BstapenW::new(self, 1)
280 }
281 #[doc = "Bit 4 - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer."]
282 #[inline(always)]
283 pub fn flash_page_flip(&mut self) -> FlashPageFlipW<SysctrlSpec> {
284 FlashPageFlipW::new(self, 4)
285 }
286 #[doc = "Bit 6 - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4."]
287 #[inline(always)]
288 pub fn icc0_flush(&mut self) -> Icc0FlushW<SysctrlSpec> {
289 Icc0FlushW::new(self, 6)
290 }
291 #[doc = "Bit 12 - ROM_DONE status. Used to disable SWD interface during system initialization procedure"]
292 #[inline(always)]
293 pub fn romdone(&mut self) -> RomdoneW<SysctrlSpec> {
294 RomdoneW::new(self, 12)
295 }
296 #[doc = "Bit 13 - Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed."]
297 #[inline(always)]
298 pub fn cchk(&mut self) -> CchkW<SysctrlSpec> {
299 CchkW::new(self, 13)
300 }
301 #[doc = "Bit 14 - Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)."]
302 #[inline(always)]
303 pub fn swd_dis(&mut self) -> SwdDisW<SysctrlSpec> {
304 SwdDisW::new(self, 14)
305 }
306 #[doc = "Bit 15 - ROM Checksum Result. This bit is only valid when CHKRD=1."]
307 #[inline(always)]
308 pub fn chkres(&mut self) -> ChkresW<SysctrlSpec> {
309 ChkresW::new(self, 15)
310 }
311 #[doc = "Bits 16:17 - Operating Voltage Range."]
312 #[inline(always)]
313 pub fn ovr(&mut self) -> OvrW<SysctrlSpec> {
314 OvrW::new(self, 16)
315 }
316}
317#[doc = "System Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
318pub struct SysctrlSpec;
319impl crate::RegisterSpec for SysctrlSpec {
320 type Ux = u32;
321}
322#[doc = "`read()` method returns [`sysctrl::R`](R) reader structure"]
323impl crate::Readable for SysctrlSpec {}
324#[doc = "`write(|w| ..)` method takes [`sysctrl::W`](W) writer structure"]
325impl crate::Writable for SysctrlSpec {
326 type Safety = crate::Unsafe;
327 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
328 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
329}
330#[doc = "`reset()` method sets SYSCTRL to value 0"]
331impl crate::Resettable for SysctrlSpec {
332 const RESET_VALUE: u32 = 0;
333}