max78000_pac/
gcr.rs

1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    sysctrl: Sysctrl,
5    rst0: Rst0,
6    clkctrl: Clkctrl,
7    pm: Pm,
8    _reserved4: [u8; 0x08],
9    pclkdiv: Pclkdiv,
10    _reserved5: [u8; 0x08],
11    pclkdis0: Pclkdis0,
12    memctrl: Memctrl,
13    memz: Memz,
14    _reserved8: [u8; 0x10],
15    sysst: Sysst,
16    rst1: Rst1,
17    pclkdis1: Pclkdis1,
18    eventen: Eventen,
19    revision: Revision,
20    sysie: Sysie,
21    _reserved14: [u8; 0x0c],
22    eccerr: Eccerr,
23    eccced: Eccced,
24    eccie: Eccie,
25    eccaddr: Eccaddr,
26    _reserved18: [u8; 0x0c],
27    gpr: Gpr,
28}
29impl RegisterBlock {
30    #[doc = "0x00 - System Control."]
31    #[inline(always)]
32    pub const fn sysctrl(&self) -> &Sysctrl {
33        &self.sysctrl
34    }
35    #[doc = "0x04 - Reset."]
36    #[inline(always)]
37    pub const fn rst0(&self) -> &Rst0 {
38        &self.rst0
39    }
40    #[doc = "0x08 - Clock Control."]
41    #[inline(always)]
42    pub const fn clkctrl(&self) -> &Clkctrl {
43        &self.clkctrl
44    }
45    #[doc = "0x0c - Power Management."]
46    #[inline(always)]
47    pub const fn pm(&self) -> &Pm {
48        &self.pm
49    }
50    #[doc = "0x18 - Peripheral Clock Divider."]
51    #[inline(always)]
52    pub const fn pclkdiv(&self) -> &Pclkdiv {
53        &self.pclkdiv
54    }
55    #[doc = "0x24 - Peripheral Clock Disable."]
56    #[inline(always)]
57    pub const fn pclkdis0(&self) -> &Pclkdis0 {
58        &self.pclkdis0
59    }
60    #[doc = "0x28 - Memory Clock Control Register."]
61    #[inline(always)]
62    pub const fn memctrl(&self) -> &Memctrl {
63        &self.memctrl
64    }
65    #[doc = "0x2c - Memory Zeroize Control."]
66    #[inline(always)]
67    pub const fn memz(&self) -> &Memz {
68        &self.memz
69    }
70    #[doc = "0x40 - System Status Register."]
71    #[inline(always)]
72    pub const fn sysst(&self) -> &Sysst {
73        &self.sysst
74    }
75    #[doc = "0x44 - Reset 1."]
76    #[inline(always)]
77    pub const fn rst1(&self) -> &Rst1 {
78        &self.rst1
79    }
80    #[doc = "0x48 - Peripheral Clock Disable."]
81    #[inline(always)]
82    pub const fn pclkdis1(&self) -> &Pclkdis1 {
83        &self.pclkdis1
84    }
85    #[doc = "0x4c - Event Enable Register."]
86    #[inline(always)]
87    pub const fn eventen(&self) -> &Eventen {
88        &self.eventen
89    }
90    #[doc = "0x50 - Revision Register."]
91    #[inline(always)]
92    pub const fn revision(&self) -> &Revision {
93        &self.revision
94    }
95    #[doc = "0x54 - System Status Interrupt Enable Register."]
96    #[inline(always)]
97    pub const fn sysie(&self) -> &Sysie {
98        &self.sysie
99    }
100    #[doc = "0x64 - ECC Error Register"]
101    #[inline(always)]
102    pub const fn eccerr(&self) -> &Eccerr {
103        &self.eccerr
104    }
105    #[doc = "0x68 - ECC Not Double Error Detect Register"]
106    #[inline(always)]
107    pub const fn eccced(&self) -> &Eccced {
108        &self.eccced
109    }
110    #[doc = "0x6c - ECC IRQ Enable Register"]
111    #[inline(always)]
112    pub const fn eccie(&self) -> &Eccie {
113        &self.eccie
114    }
115    #[doc = "0x70 - ECC Error Address Register"]
116    #[inline(always)]
117    pub const fn eccaddr(&self) -> &Eccaddr {
118        &self.eccaddr
119    }
120    #[doc = "0x80 - General Purpose Register."]
121    #[inline(always)]
122    pub const fn gpr(&self) -> &Gpr {
123        &self.gpr
124    }
125}
126#[doc = "SYSCTRL (rw) register accessor: System Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysctrl`]
127module"]
128#[doc(alias = "SYSCTRL")]
129pub type Sysctrl = crate::Reg<sysctrl::SysctrlSpec>;
130#[doc = "System Control."]
131pub mod sysctrl;
132#[doc = "RST0 (rw) register accessor: Reset.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst0`]
133module"]
134#[doc(alias = "RST0")]
135pub type Rst0 = crate::Reg<rst0::Rst0Spec>;
136#[doc = "Reset."]
137pub mod rst0;
138#[doc = "CLKCTRL (rw) register accessor: Clock Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkctrl`]
139module"]
140#[doc(alias = "CLKCTRL")]
141pub type Clkctrl = crate::Reg<clkctrl::ClkctrlSpec>;
142#[doc = "Clock Control."]
143pub mod clkctrl;
144#[doc = "PM (rw) register accessor: Power Management.\n\nYou can [`read`](crate::Reg::read) this register and get [`pm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pm`]
145module"]
146#[doc(alias = "PM")]
147pub type Pm = crate::Reg<pm::PmSpec>;
148#[doc = "Power Management."]
149pub mod pm;
150#[doc = "PCLKDIV (rw) register accessor: Peripheral Clock Divider.\n\nYou can [`read`](crate::Reg::read) this register and get [`pclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pclkdiv`]
151module"]
152#[doc(alias = "PCLKDIV")]
153pub type Pclkdiv = crate::Reg<pclkdiv::PclkdivSpec>;
154#[doc = "Peripheral Clock Divider."]
155pub mod pclkdiv;
156#[doc = "PCLKDIS0 (rw) register accessor: Peripheral Clock Disable.\n\nYou can [`read`](crate::Reg::read) this register and get [`pclkdis0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pclkdis0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pclkdis0`]
157module"]
158#[doc(alias = "PCLKDIS0")]
159pub type Pclkdis0 = crate::Reg<pclkdis0::Pclkdis0Spec>;
160#[doc = "Peripheral Clock Disable."]
161pub mod pclkdis0;
162#[doc = "MEMCTRL (rw) register accessor: Memory Clock Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`memctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`memctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@memctrl`]
163module"]
164#[doc(alias = "MEMCTRL")]
165pub type Memctrl = crate::Reg<memctrl::MemctrlSpec>;
166#[doc = "Memory Clock Control Register."]
167pub mod memctrl;
168#[doc = "MEMZ (rw) register accessor: Memory Zeroize Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`memz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`memz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@memz`]
169module"]
170#[doc(alias = "MEMZ")]
171pub type Memz = crate::Reg<memz::MemzSpec>;
172#[doc = "Memory Zeroize Control."]
173pub mod memz;
174#[doc = "SYSST (rw) register accessor: System Status Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysst`]
175module"]
176#[doc(alias = "SYSST")]
177pub type Sysst = crate::Reg<sysst::SysstSpec>;
178#[doc = "System Status Register."]
179pub mod sysst;
180#[doc = "RST1 (rw) register accessor: Reset 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst1`]
181module"]
182#[doc(alias = "RST1")]
183pub type Rst1 = crate::Reg<rst1::Rst1Spec>;
184#[doc = "Reset 1."]
185pub mod rst1;
186#[doc = "PCLKDIS1 (rw) register accessor: Peripheral Clock Disable.\n\nYou can [`read`](crate::Reg::read) this register and get [`pclkdis1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pclkdis1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pclkdis1`]
187module"]
188#[doc(alias = "PCLKDIS1")]
189pub type Pclkdis1 = crate::Reg<pclkdis1::Pclkdis1Spec>;
190#[doc = "Peripheral Clock Disable."]
191pub mod pclkdis1;
192#[doc = "EVENTEN (rw) register accessor: Event Enable Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`eventen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eventen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eventen`]
193module"]
194#[doc(alias = "EVENTEN")]
195pub type Eventen = crate::Reg<eventen::EventenSpec>;
196#[doc = "Event Enable Register."]
197pub mod eventen;
198#[doc = "REVISION (r) register accessor: Revision Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`revision::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@revision`]
199module"]
200#[doc(alias = "REVISION")]
201pub type Revision = crate::Reg<revision::RevisionSpec>;
202#[doc = "Revision Register."]
203pub mod revision;
204#[doc = "SYSIE (rw) register accessor: System Status Interrupt Enable Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sysie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysie`]
205module"]
206#[doc(alias = "SYSIE")]
207pub type Sysie = crate::Reg<sysie::SysieSpec>;
208#[doc = "System Status Interrupt Enable Register."]
209pub mod sysie;
210#[doc = "ECCERR (rw) register accessor: ECC Error Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eccerr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eccerr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eccerr`]
211module"]
212#[doc(alias = "ECCERR")]
213pub type Eccerr = crate::Reg<eccerr::EccerrSpec>;
214#[doc = "ECC Error Register"]
215pub mod eccerr;
216#[doc = "ECCCED (rw) register accessor: ECC Not Double Error Detect Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eccced::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eccced::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eccced`]
217module"]
218#[doc(alias = "ECCCED")]
219pub type Eccced = crate::Reg<eccced::EcccedSpec>;
220#[doc = "ECC Not Double Error Detect Register"]
221pub mod eccced;
222#[doc = "ECCIE (rw) register accessor: ECC IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eccie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eccie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eccie`]
223module"]
224#[doc(alias = "ECCIE")]
225pub type Eccie = crate::Reg<eccie::EccieSpec>;
226#[doc = "ECC IRQ Enable Register"]
227pub mod eccie;
228#[doc = "ECCADDR (rw) register accessor: ECC Error Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`eccaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eccaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eccaddr`]
229module"]
230#[doc(alias = "ECCADDR")]
231pub type Eccaddr = crate::Reg<eccaddr::EccaddrSpec>;
232#[doc = "ECC Error Address Register"]
233pub mod eccaddr;
234#[doc = "GPR (rw) register accessor: General Purpose Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`gpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpr`]
235module"]
236#[doc(alias = "GPR")]
237pub type Gpr = crate::Reg<gpr::GprSpec>;
238#[doc = "General Purpose Register."]
239pub mod gpr;