max32660/uart0/
ctrl0.rs

1#[doc = "Register `CTRL0` reader"]
2pub type R = crate::R<CTRL0_SPEC>;
3#[doc = "Register `CTRL0` writer"]
4pub type W = crate::W<CTRL0_SPEC>;
5#[doc = "Field `enabled` reader - UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used."]
6pub type ENABLED_R = crate::BitReader<ENABLED_A>;
7#[doc = "UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum ENABLED_A {
10    #[doc = "0: UART disabled."]
11    DISABLED = 0,
12    #[doc = "1: UART enabled."]
13    ENABLED = 1,
14}
15impl From<ENABLED_A> for bool {
16    #[inline(always)]
17    fn from(variant: ENABLED_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl ENABLED_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub fn variant(&self) -> ENABLED_A {
25        match self.bits {
26            false => ENABLED_A::DISABLED,
27            true => ENABLED_A::ENABLED,
28        }
29    }
30    #[doc = "UART disabled."]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == ENABLED_A::DISABLED
34    }
35    #[doc = "UART enabled."]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == ENABLED_A::ENABLED
39    }
40}
41#[doc = "Field `enabled` writer - UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used."]
42pub type ENABLED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ENABLED_A>;
43impl<'a, REG, const O: u8> ENABLED_W<'a, REG, O>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "UART disabled."]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(ENABLED_A::DISABLED)
51    }
52    #[doc = "UART enabled."]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(ENABLED_A::ENABLED)
56    }
57}
58#[doc = "Field `PARITY_EN` reader - Enable/disable Parity bit (9th character)."]
59pub type PARITY_EN_R = crate::BitReader<PARITY_EN_A>;
60#[doc = "Enable/disable Parity bit (9th character).\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum PARITY_EN_A {
63    #[doc = "0: No Parity."]
64    DISABLED = 0,
65    #[doc = "1: Parity enabled as 9th bit."]
66    ENABLED = 1,
67}
68impl From<PARITY_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: PARITY_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl PARITY_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> PARITY_EN_A {
78        match self.bits {
79            false => PARITY_EN_A::DISABLED,
80            true => PARITY_EN_A::ENABLED,
81        }
82    }
83    #[doc = "No Parity."]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == PARITY_EN_A::DISABLED
87    }
88    #[doc = "Parity enabled as 9th bit."]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == PARITY_EN_A::ENABLED
92    }
93}
94#[doc = "Field `PARITY_EN` writer - Enable/disable Parity bit (9th character)."]
95pub type PARITY_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PARITY_EN_A>;
96impl<'a, REG, const O: u8> PARITY_EN_W<'a, REG, O>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "No Parity."]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(PARITY_EN_A::DISABLED)
104    }
105    #[doc = "Parity enabled as 9th bit."]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(PARITY_EN_A::ENABLED)
109    }
110}
111#[doc = "Field `PARITY_MODE` reader - When PARITY_EN=1, selects odd, even, Mark or Space parity."]
112pub type PARITY_MODE_R = crate::FieldReader<PARITY_MODE_A>;
113#[doc = "When PARITY_EN=1, selects odd, even, Mark or Space parity.\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum PARITY_MODE_A {
117    #[doc = "0: Even parity selected."]
118    EVEN = 0,
119    #[doc = "1: Odd parity selected."]
120    ODD = 1,
121    #[doc = "2: Mark parity selected."]
122    MARK = 2,
123    #[doc = "3: Space parity selected."]
124    SPACE = 3,
125}
126impl From<PARITY_MODE_A> for u8 {
127    #[inline(always)]
128    fn from(variant: PARITY_MODE_A) -> Self {
129        variant as _
130    }
131}
132impl crate::FieldSpec for PARITY_MODE_A {
133    type Ux = u8;
134}
135impl PARITY_MODE_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub fn variant(&self) -> PARITY_MODE_A {
139        match self.bits {
140            0 => PARITY_MODE_A::EVEN,
141            1 => PARITY_MODE_A::ODD,
142            2 => PARITY_MODE_A::MARK,
143            3 => PARITY_MODE_A::SPACE,
144            _ => unreachable!(),
145        }
146    }
147    #[doc = "Even parity selected."]
148    #[inline(always)]
149    pub fn is_even(&self) -> bool {
150        *self == PARITY_MODE_A::EVEN
151    }
152    #[doc = "Odd parity selected."]
153    #[inline(always)]
154    pub fn is_odd(&self) -> bool {
155        *self == PARITY_MODE_A::ODD
156    }
157    #[doc = "Mark parity selected."]
158    #[inline(always)]
159    pub fn is_mark(&self) -> bool {
160        *self == PARITY_MODE_A::MARK
161    }
162    #[doc = "Space parity selected."]
163    #[inline(always)]
164    pub fn is_space(&self) -> bool {
165        *self == PARITY_MODE_A::SPACE
166    }
167}
168#[doc = "Field `PARITY_MODE` writer - When PARITY_EN=1, selects odd, even, Mark or Space parity."]
169pub type PARITY_MODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, PARITY_MODE_A>;
170impl<'a, REG, const O: u8> PARITY_MODE_W<'a, REG, O>
171where
172    REG: crate::Writable + crate::RegisterSpec,
173    REG::Ux: From<u8>,
174{
175    #[doc = "Even parity selected."]
176    #[inline(always)]
177    pub fn even(self) -> &'a mut crate::W<REG> {
178        self.variant(PARITY_MODE_A::EVEN)
179    }
180    #[doc = "Odd parity selected."]
181    #[inline(always)]
182    pub fn odd(self) -> &'a mut crate::W<REG> {
183        self.variant(PARITY_MODE_A::ODD)
184    }
185    #[doc = "Mark parity selected."]
186    #[inline(always)]
187    pub fn mark(self) -> &'a mut crate::W<REG> {
188        self.variant(PARITY_MODE_A::MARK)
189    }
190    #[doc = "Space parity selected."]
191    #[inline(always)]
192    pub fn space(self) -> &'a mut crate::W<REG> {
193        self.variant(PARITY_MODE_A::SPACE)
194    }
195}
196#[doc = "Field `PARITY_LVL` reader - Selects parity based on 1s or 0s count (when PARITY_EN=1)."]
197pub type PARITY_LVL_R = crate::BitReader<PARITY_LVL_A>;
198#[doc = "Selects parity based on 1s or 0s count (when PARITY_EN=1).\n\nValue on reset: 0"]
199#[derive(Clone, Copy, Debug, PartialEq, Eq)]
200pub enum PARITY_LVL_A {
201    #[doc = "0: Parity calculation is based on number of 1s in frame."]
202    _1 = 0,
203    #[doc = "1: Parity calculation is based on number of 0s in frame."]
204    _0 = 1,
205}
206impl From<PARITY_LVL_A> for bool {
207    #[inline(always)]
208    fn from(variant: PARITY_LVL_A) -> Self {
209        variant as u8 != 0
210    }
211}
212impl PARITY_LVL_R {
213    #[doc = "Get enumerated values variant"]
214    #[inline(always)]
215    pub fn variant(&self) -> PARITY_LVL_A {
216        match self.bits {
217            false => PARITY_LVL_A::_1,
218            true => PARITY_LVL_A::_0,
219        }
220    }
221    #[doc = "Parity calculation is based on number of 1s in frame."]
222    #[inline(always)]
223    pub fn is_1(&self) -> bool {
224        *self == PARITY_LVL_A::_1
225    }
226    #[doc = "Parity calculation is based on number of 0s in frame."]
227    #[inline(always)]
228    pub fn is_0(&self) -> bool {
229        *self == PARITY_LVL_A::_0
230    }
231}
232#[doc = "Field `PARITY_LVL` writer - Selects parity based on 1s or 0s count (when PARITY_EN=1)."]
233pub type PARITY_LVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PARITY_LVL_A>;
234impl<'a, REG, const O: u8> PARITY_LVL_W<'a, REG, O>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237{
238    #[doc = "Parity calculation is based on number of 1s in frame."]
239    #[inline(always)]
240    pub fn _1(self) -> &'a mut crate::W<REG> {
241        self.variant(PARITY_LVL_A::_1)
242    }
243    #[doc = "Parity calculation is based on number of 0s in frame."]
244    #[inline(always)]
245    pub fn _0(self) -> &'a mut crate::W<REG> {
246        self.variant(PARITY_LVL_A::_0)
247    }
248}
249#[doc = "Field `TXFLUSH` reader - Flushes the TX FIFO buffer."]
250pub type TXFLUSH_R = crate::BitReader;
251#[doc = "Field `TXFLUSH` writer - Flushes the TX FIFO buffer."]
252pub type TXFLUSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
253#[doc = "Field `RXFLUSH` reader - Flushes the RX FIFO buffer."]
254pub type RXFLUSH_R = crate::BitReader;
255#[doc = "Field `RXFLUSH` writer - Flushes the RX FIFO buffer."]
256pub type RXFLUSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
257#[doc = "Field `BITACC` reader - Bit accuracy selection."]
258pub type BITACC_R = crate::BitReader<BITACC_A>;
259#[doc = "Bit accuracy selection.\n\nValue on reset: 0"]
260#[derive(Clone, Copy, Debug, PartialEq, Eq)]
261pub enum BITACC_A {
262    #[doc = "0: Frame accuracy."]
263    FRAME = 0,
264    #[doc = "1: Bit accuracy."]
265    BIT = 1,
266}
267impl From<BITACC_A> for bool {
268    #[inline(always)]
269    fn from(variant: BITACC_A) -> Self {
270        variant as u8 != 0
271    }
272}
273impl BITACC_R {
274    #[doc = "Get enumerated values variant"]
275    #[inline(always)]
276    pub fn variant(&self) -> BITACC_A {
277        match self.bits {
278            false => BITACC_A::FRAME,
279            true => BITACC_A::BIT,
280        }
281    }
282    #[doc = "Frame accuracy."]
283    #[inline(always)]
284    pub fn is_frame(&self) -> bool {
285        *self == BITACC_A::FRAME
286    }
287    #[doc = "Bit accuracy."]
288    #[inline(always)]
289    pub fn is_bit_(&self) -> bool {
290        *self == BITACC_A::BIT
291    }
292}
293#[doc = "Field `BITACC` writer - Bit accuracy selection."]
294pub type BITACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BITACC_A>;
295impl<'a, REG, const O: u8> BITACC_W<'a, REG, O>
296where
297    REG: crate::Writable + crate::RegisterSpec,
298{
299    #[doc = "Frame accuracy."]
300    #[inline(always)]
301    pub fn frame(self) -> &'a mut crate::W<REG> {
302        self.variant(BITACC_A::FRAME)
303    }
304    #[doc = "Bit accuracy."]
305    #[inline(always)]
306    pub fn bit_(self) -> &'a mut crate::W<REG> {
307        self.variant(BITACC_A::BIT)
308    }
309}
310#[doc = "Field `SIZE` reader - Selects UART character size."]
311pub type SIZE_R = crate::FieldReader<SIZE_A>;
312#[doc = "Selects UART character size.\n\nValue on reset: 0"]
313#[derive(Clone, Copy, Debug, PartialEq, Eq)]
314#[repr(u8)]
315pub enum SIZE_A {
316    #[doc = "0: 5 bits."]
317    _5 = 0,
318    #[doc = "1: 6 bits."]
319    _6 = 1,
320    #[doc = "2: 7 bits."]
321    _7 = 2,
322    #[doc = "3: 8 bits."]
323    _8 = 3,
324}
325impl From<SIZE_A> for u8 {
326    #[inline(always)]
327    fn from(variant: SIZE_A) -> Self {
328        variant as _
329    }
330}
331impl crate::FieldSpec for SIZE_A {
332    type Ux = u8;
333}
334impl SIZE_R {
335    #[doc = "Get enumerated values variant"]
336    #[inline(always)]
337    pub fn variant(&self) -> SIZE_A {
338        match self.bits {
339            0 => SIZE_A::_5,
340            1 => SIZE_A::_6,
341            2 => SIZE_A::_7,
342            3 => SIZE_A::_8,
343            _ => unreachable!(),
344        }
345    }
346    #[doc = "5 bits."]
347    #[inline(always)]
348    pub fn is_5(&self) -> bool {
349        *self == SIZE_A::_5
350    }
351    #[doc = "6 bits."]
352    #[inline(always)]
353    pub fn is_6(&self) -> bool {
354        *self == SIZE_A::_6
355    }
356    #[doc = "7 bits."]
357    #[inline(always)]
358    pub fn is_7(&self) -> bool {
359        *self == SIZE_A::_7
360    }
361    #[doc = "8 bits."]
362    #[inline(always)]
363    pub fn is_8(&self) -> bool {
364        *self == SIZE_A::_8
365    }
366}
367#[doc = "Field `SIZE` writer - Selects UART character size."]
368pub type SIZE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, SIZE_A>;
369impl<'a, REG, const O: u8> SIZE_W<'a, REG, O>
370where
371    REG: crate::Writable + crate::RegisterSpec,
372    REG::Ux: From<u8>,
373{
374    #[doc = "5 bits."]
375    #[inline(always)]
376    pub fn _5(self) -> &'a mut crate::W<REG> {
377        self.variant(SIZE_A::_5)
378    }
379    #[doc = "6 bits."]
380    #[inline(always)]
381    pub fn _6(self) -> &'a mut crate::W<REG> {
382        self.variant(SIZE_A::_6)
383    }
384    #[doc = "7 bits."]
385    #[inline(always)]
386    pub fn _7(self) -> &'a mut crate::W<REG> {
387        self.variant(SIZE_A::_7)
388    }
389    #[doc = "8 bits."]
390    #[inline(always)]
391    pub fn _8(self) -> &'a mut crate::W<REG> {
392        self.variant(SIZE_A::_8)
393    }
394}
395#[doc = "Field `STOP` reader - Selects the number of stop bits that will be generated."]
396pub type STOP_R = crate::BitReader<STOP_A>;
397#[doc = "Selects the number of stop bits that will be generated.\n\nValue on reset: 0"]
398#[derive(Clone, Copy, Debug, PartialEq, Eq)]
399pub enum STOP_A {
400    #[doc = "0: 1 stop bit."]
401    _1 = 0,
402    #[doc = "1: 1."]
403    _1_5 = 1,
404}
405impl From<STOP_A> for bool {
406    #[inline(always)]
407    fn from(variant: STOP_A) -> Self {
408        variant as u8 != 0
409    }
410}
411impl STOP_R {
412    #[doc = "Get enumerated values variant"]
413    #[inline(always)]
414    pub fn variant(&self) -> STOP_A {
415        match self.bits {
416            false => STOP_A::_1,
417            true => STOP_A::_1_5,
418        }
419    }
420    #[doc = "1 stop bit."]
421    #[inline(always)]
422    pub fn is_1(&self) -> bool {
423        *self == STOP_A::_1
424    }
425    #[doc = "1."]
426    #[inline(always)]
427    pub fn is_1_5(&self) -> bool {
428        *self == STOP_A::_1_5
429    }
430}
431#[doc = "Field `STOP` writer - Selects the number of stop bits that will be generated."]
432pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, STOP_A>;
433impl<'a, REG, const O: u8> STOP_W<'a, REG, O>
434where
435    REG: crate::Writable + crate::RegisterSpec,
436{
437    #[doc = "1 stop bit."]
438    #[inline(always)]
439    pub fn _1(self) -> &'a mut crate::W<REG> {
440        self.variant(STOP_A::_1)
441    }
442    #[doc = "1."]
443    #[inline(always)]
444    pub fn _1_5(self) -> &'a mut crate::W<REG> {
445        self.variant(STOP_A::_1_5)
446    }
447}
448#[doc = "Field `FLOW` reader - Enables/disables hardware flow control."]
449pub type FLOW_R = crate::BitReader<FLOW_A>;
450#[doc = "Enables/disables hardware flow control.\n\nValue on reset: 0"]
451#[derive(Clone, Copy, Debug, PartialEq, Eq)]
452pub enum FLOW_A {
453    #[doc = "1: HW Flow Control with RTS/CTS enabled."]
454    ENABLED = 1,
455    #[doc = "0: HW Flow Control disabled."]
456    DISABLED = 0,
457}
458impl From<FLOW_A> for bool {
459    #[inline(always)]
460    fn from(variant: FLOW_A) -> Self {
461        variant as u8 != 0
462    }
463}
464impl FLOW_R {
465    #[doc = "Get enumerated values variant"]
466    #[inline(always)]
467    pub fn variant(&self) -> FLOW_A {
468        match self.bits {
469            true => FLOW_A::ENABLED,
470            false => FLOW_A::DISABLED,
471        }
472    }
473    #[doc = "HW Flow Control with RTS/CTS enabled."]
474    #[inline(always)]
475    pub fn is_enabled(&self) -> bool {
476        *self == FLOW_A::ENABLED
477    }
478    #[doc = "HW Flow Control disabled."]
479    #[inline(always)]
480    pub fn is_disabled(&self) -> bool {
481        *self == FLOW_A::DISABLED
482    }
483}
484#[doc = "Field `FLOW` writer - Enables/disables hardware flow control."]
485pub type FLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FLOW_A>;
486impl<'a, REG, const O: u8> FLOW_W<'a, REG, O>
487where
488    REG: crate::Writable + crate::RegisterSpec,
489{
490    #[doc = "HW Flow Control with RTS/CTS enabled."]
491    #[inline(always)]
492    pub fn enabled(self) -> &'a mut crate::W<REG> {
493        self.variant(FLOW_A::ENABLED)
494    }
495    #[doc = "HW Flow Control disabled."]
496    #[inline(always)]
497    pub fn disabled(self) -> &'a mut crate::W<REG> {
498        self.variant(FLOW_A::DISABLED)
499    }
500}
501#[doc = "Field `FLOWPOL` reader - RTS/CTS polarity."]
502pub type FLOWPOL_R = crate::BitReader<FLOWPOL_A>;
503#[doc = "RTS/CTS polarity.\n\nValue on reset: 0"]
504#[derive(Clone, Copy, Debug, PartialEq, Eq)]
505pub enum FLOWPOL_A {
506    #[doc = "0: RTS/CTS asserted is logic 0."]
507    _0 = 0,
508    #[doc = "1: RTS/CTS asserted is logic 1."]
509    _1 = 1,
510}
511impl From<FLOWPOL_A> for bool {
512    #[inline(always)]
513    fn from(variant: FLOWPOL_A) -> Self {
514        variant as u8 != 0
515    }
516}
517impl FLOWPOL_R {
518    #[doc = "Get enumerated values variant"]
519    #[inline(always)]
520    pub fn variant(&self) -> FLOWPOL_A {
521        match self.bits {
522            false => FLOWPOL_A::_0,
523            true => FLOWPOL_A::_1,
524        }
525    }
526    #[doc = "RTS/CTS asserted is logic 0."]
527    #[inline(always)]
528    pub fn is_0(&self) -> bool {
529        *self == FLOWPOL_A::_0
530    }
531    #[doc = "RTS/CTS asserted is logic 1."]
532    #[inline(always)]
533    pub fn is_1(&self) -> bool {
534        *self == FLOWPOL_A::_1
535    }
536}
537#[doc = "Field `FLOWPOL` writer - RTS/CTS polarity."]
538pub type FLOWPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FLOWPOL_A>;
539impl<'a, REG, const O: u8> FLOWPOL_W<'a, REG, O>
540where
541    REG: crate::Writable + crate::RegisterSpec,
542{
543    #[doc = "RTS/CTS asserted is logic 0."]
544    #[inline(always)]
545    pub fn _0(self) -> &'a mut crate::W<REG> {
546        self.variant(FLOWPOL_A::_0)
547    }
548    #[doc = "RTS/CTS asserted is logic 1."]
549    #[inline(always)]
550    pub fn _1(self) -> &'a mut crate::W<REG> {
551        self.variant(FLOWPOL_A::_1)
552    }
553}
554#[doc = "Field `NULLMOD` reader - NULL Modem Support (RTS/CTS and TXD/RXD swap)."]
555pub type NULLMOD_R = crate::BitReader<NULLMOD_A>;
556#[doc = "NULL Modem Support (RTS/CTS and TXD/RXD swap).\n\nValue on reset: 0"]
557#[derive(Clone, Copy, Debug, PartialEq, Eq)]
558pub enum NULLMOD_A {
559    #[doc = "0: Direct convention."]
560    DISABLED = 0,
561    #[doc = "1: Null Modem Mode."]
562    ENABLED = 1,
563}
564impl From<NULLMOD_A> for bool {
565    #[inline(always)]
566    fn from(variant: NULLMOD_A) -> Self {
567        variant as u8 != 0
568    }
569}
570impl NULLMOD_R {
571    #[doc = "Get enumerated values variant"]
572    #[inline(always)]
573    pub fn variant(&self) -> NULLMOD_A {
574        match self.bits {
575            false => NULLMOD_A::DISABLED,
576            true => NULLMOD_A::ENABLED,
577        }
578    }
579    #[doc = "Direct convention."]
580    #[inline(always)]
581    pub fn is_disabled(&self) -> bool {
582        *self == NULLMOD_A::DISABLED
583    }
584    #[doc = "Null Modem Mode."]
585    #[inline(always)]
586    pub fn is_enabled(&self) -> bool {
587        *self == NULLMOD_A::ENABLED
588    }
589}
590#[doc = "Field `NULLMOD` writer - NULL Modem Support (RTS/CTS and TXD/RXD swap)."]
591pub type NULLMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, NULLMOD_A>;
592impl<'a, REG, const O: u8> NULLMOD_W<'a, REG, O>
593where
594    REG: crate::Writable + crate::RegisterSpec,
595{
596    #[doc = "Direct convention."]
597    #[inline(always)]
598    pub fn disabled(self) -> &'a mut crate::W<REG> {
599        self.variant(NULLMOD_A::DISABLED)
600    }
601    #[doc = "Null Modem Mode."]
602    #[inline(always)]
603    pub fn enabled(self) -> &'a mut crate::W<REG> {
604        self.variant(NULLMOD_A::ENABLED)
605    }
606}
607#[doc = "Field `BREAK` reader - Break control bit."]
608pub type BREAK_R = crate::BitReader<BREAK_A>;
609#[doc = "Break control bit.\n\nValue on reset: 0"]
610#[derive(Clone, Copy, Debug, PartialEq, Eq)]
611pub enum BREAK_A {
612    #[doc = "0: Break characters are not generated."]
613    DISABLED = 0,
614    #[doc = "1: Break characters are sent (all the bits are at '0' including start/parity/stop)."]
615    ENABLED = 1,
616}
617impl From<BREAK_A> for bool {
618    #[inline(always)]
619    fn from(variant: BREAK_A) -> Self {
620        variant as u8 != 0
621    }
622}
623impl BREAK_R {
624    #[doc = "Get enumerated values variant"]
625    #[inline(always)]
626    pub fn variant(&self) -> BREAK_A {
627        match self.bits {
628            false => BREAK_A::DISABLED,
629            true => BREAK_A::ENABLED,
630        }
631    }
632    #[doc = "Break characters are not generated."]
633    #[inline(always)]
634    pub fn is_disabled(&self) -> bool {
635        *self == BREAK_A::DISABLED
636    }
637    #[doc = "Break characters are sent (all the bits are at '0' including start/parity/stop)."]
638    #[inline(always)]
639    pub fn is_enabled(&self) -> bool {
640        *self == BREAK_A::ENABLED
641    }
642}
643#[doc = "Field `BREAK` writer - Break control bit."]
644pub type BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BREAK_A>;
645impl<'a, REG, const O: u8> BREAK_W<'a, REG, O>
646where
647    REG: crate::Writable + crate::RegisterSpec,
648{
649    #[doc = "Break characters are not generated."]
650    #[inline(always)]
651    pub fn disabled(self) -> &'a mut crate::W<REG> {
652        self.variant(BREAK_A::DISABLED)
653    }
654    #[doc = "Break characters are sent (all the bits are at '0' including start/parity/stop)."]
655    #[inline(always)]
656    pub fn enabled(self) -> &'a mut crate::W<REG> {
657        self.variant(BREAK_A::ENABLED)
658    }
659}
660#[doc = "Field `CLK_SEL` reader - Baud Rate Clock Source Select."]
661pub type CLK_SEL_R = crate::BitReader<CLK_SEL_A>;
662#[doc = "Baud Rate Clock Source Select.\n\nValue on reset: 0"]
663#[derive(Clone, Copy, Debug, PartialEq, Eq)]
664pub enum CLK_SEL_A {
665    #[doc = "0: System clock."]
666    SYSTEM = 0,
667    #[doc = "1: Alternate 7.3727MHz internal clock."]
668    ALTERNATE = 1,
669}
670impl From<CLK_SEL_A> for bool {
671    #[inline(always)]
672    fn from(variant: CLK_SEL_A) -> Self {
673        variant as u8 != 0
674    }
675}
676impl CLK_SEL_R {
677    #[doc = "Get enumerated values variant"]
678    #[inline(always)]
679    pub fn variant(&self) -> CLK_SEL_A {
680        match self.bits {
681            false => CLK_SEL_A::SYSTEM,
682            true => CLK_SEL_A::ALTERNATE,
683        }
684    }
685    #[doc = "System clock."]
686    #[inline(always)]
687    pub fn is_system(&self) -> bool {
688        *self == CLK_SEL_A::SYSTEM
689    }
690    #[doc = "Alternate 7.3727MHz internal clock."]
691    #[inline(always)]
692    pub fn is_alternate(&self) -> bool {
693        *self == CLK_SEL_A::ALTERNATE
694    }
695}
696#[doc = "Field `CLK_SEL` writer - Baud Rate Clock Source Select."]
697pub type CLK_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CLK_SEL_A>;
698impl<'a, REG, const O: u8> CLK_SEL_W<'a, REG, O>
699where
700    REG: crate::Writable + crate::RegisterSpec,
701{
702    #[doc = "System clock."]
703    #[inline(always)]
704    pub fn system(self) -> &'a mut crate::W<REG> {
705        self.variant(CLK_SEL_A::SYSTEM)
706    }
707    #[doc = "Alternate 7.3727MHz internal clock."]
708    #[inline(always)]
709    pub fn alternate(self) -> &'a mut crate::W<REG> {
710        self.variant(CLK_SEL_A::ALTERNATE)
711    }
712}
713#[doc = "Field `TO_CNT` reader - RX Time Out."]
714pub type TO_CNT_R = crate::FieldReader;
715#[doc = "Field `TO_CNT` writer - RX Time Out."]
716pub type TO_CNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>;
717impl R {
718    #[doc = "Bit 0 - UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used."]
719    #[inline(always)]
720    pub fn enabled(&self) -> ENABLED_R {
721        ENABLED_R::new((self.bits & 1) != 0)
722    }
723    #[doc = "Bit 1 - Enable/disable Parity bit (9th character)."]
724    #[inline(always)]
725    pub fn parity_en(&self) -> PARITY_EN_R {
726        PARITY_EN_R::new(((self.bits >> 1) & 1) != 0)
727    }
728    #[doc = "Bits 2:3 - When PARITY_EN=1, selects odd, even, Mark or Space parity."]
729    #[inline(always)]
730    pub fn parity_mode(&self) -> PARITY_MODE_R {
731        PARITY_MODE_R::new(((self.bits >> 2) & 3) as u8)
732    }
733    #[doc = "Bit 4 - Selects parity based on 1s or 0s count (when PARITY_EN=1)."]
734    #[inline(always)]
735    pub fn parity_lvl(&self) -> PARITY_LVL_R {
736        PARITY_LVL_R::new(((self.bits >> 4) & 1) != 0)
737    }
738    #[doc = "Bit 5 - Flushes the TX FIFO buffer."]
739    #[inline(always)]
740    pub fn txflush(&self) -> TXFLUSH_R {
741        TXFLUSH_R::new(((self.bits >> 5) & 1) != 0)
742    }
743    #[doc = "Bit 6 - Flushes the RX FIFO buffer."]
744    #[inline(always)]
745    pub fn rxflush(&self) -> RXFLUSH_R {
746        RXFLUSH_R::new(((self.bits >> 6) & 1) != 0)
747    }
748    #[doc = "Bit 7 - Bit accuracy selection."]
749    #[inline(always)]
750    pub fn bitacc(&self) -> BITACC_R {
751        BITACC_R::new(((self.bits >> 7) & 1) != 0)
752    }
753    #[doc = "Bits 8:9 - Selects UART character size."]
754    #[inline(always)]
755    pub fn size(&self) -> SIZE_R {
756        SIZE_R::new(((self.bits >> 8) & 3) as u8)
757    }
758    #[doc = "Bit 10 - Selects the number of stop bits that will be generated."]
759    #[inline(always)]
760    pub fn stop(&self) -> STOP_R {
761        STOP_R::new(((self.bits >> 10) & 1) != 0)
762    }
763    #[doc = "Bit 11 - Enables/disables hardware flow control."]
764    #[inline(always)]
765    pub fn flow(&self) -> FLOW_R {
766        FLOW_R::new(((self.bits >> 11) & 1) != 0)
767    }
768    #[doc = "Bit 12 - RTS/CTS polarity."]
769    #[inline(always)]
770    pub fn flowpol(&self) -> FLOWPOL_R {
771        FLOWPOL_R::new(((self.bits >> 12) & 1) != 0)
772    }
773    #[doc = "Bit 13 - NULL Modem Support (RTS/CTS and TXD/RXD swap)."]
774    #[inline(always)]
775    pub fn nullmod(&self) -> NULLMOD_R {
776        NULLMOD_R::new(((self.bits >> 13) & 1) != 0)
777    }
778    #[doc = "Bit 14 - Break control bit."]
779    #[inline(always)]
780    pub fn break_(&self) -> BREAK_R {
781        BREAK_R::new(((self.bits >> 14) & 1) != 0)
782    }
783    #[doc = "Bit 15 - Baud Rate Clock Source Select."]
784    #[inline(always)]
785    pub fn clk_sel(&self) -> CLK_SEL_R {
786        CLK_SEL_R::new(((self.bits >> 15) & 1) != 0)
787    }
788    #[doc = "Bits 16:23 - RX Time Out."]
789    #[inline(always)]
790    pub fn to_cnt(&self) -> TO_CNT_R {
791        TO_CNT_R::new(((self.bits >> 16) & 0xff) as u8)
792    }
793}
794impl W {
795    #[doc = "Bit 0 - UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used."]
796    #[inline(always)]
797    #[must_use]
798    pub fn enabled(&mut self) -> ENABLED_W<CTRL0_SPEC, 0> {
799        ENABLED_W::new(self)
800    }
801    #[doc = "Bit 1 - Enable/disable Parity bit (9th character)."]
802    #[inline(always)]
803    #[must_use]
804    pub fn parity_en(&mut self) -> PARITY_EN_W<CTRL0_SPEC, 1> {
805        PARITY_EN_W::new(self)
806    }
807    #[doc = "Bits 2:3 - When PARITY_EN=1, selects odd, even, Mark or Space parity."]
808    #[inline(always)]
809    #[must_use]
810    pub fn parity_mode(&mut self) -> PARITY_MODE_W<CTRL0_SPEC, 2> {
811        PARITY_MODE_W::new(self)
812    }
813    #[doc = "Bit 4 - Selects parity based on 1s or 0s count (when PARITY_EN=1)."]
814    #[inline(always)]
815    #[must_use]
816    pub fn parity_lvl(&mut self) -> PARITY_LVL_W<CTRL0_SPEC, 4> {
817        PARITY_LVL_W::new(self)
818    }
819    #[doc = "Bit 5 - Flushes the TX FIFO buffer."]
820    #[inline(always)]
821    #[must_use]
822    pub fn txflush(&mut self) -> TXFLUSH_W<CTRL0_SPEC, 5> {
823        TXFLUSH_W::new(self)
824    }
825    #[doc = "Bit 6 - Flushes the RX FIFO buffer."]
826    #[inline(always)]
827    #[must_use]
828    pub fn rxflush(&mut self) -> RXFLUSH_W<CTRL0_SPEC, 6> {
829        RXFLUSH_W::new(self)
830    }
831    #[doc = "Bit 7 - Bit accuracy selection."]
832    #[inline(always)]
833    #[must_use]
834    pub fn bitacc(&mut self) -> BITACC_W<CTRL0_SPEC, 7> {
835        BITACC_W::new(self)
836    }
837    #[doc = "Bits 8:9 - Selects UART character size."]
838    #[inline(always)]
839    #[must_use]
840    pub fn size(&mut self) -> SIZE_W<CTRL0_SPEC, 8> {
841        SIZE_W::new(self)
842    }
843    #[doc = "Bit 10 - Selects the number of stop bits that will be generated."]
844    #[inline(always)]
845    #[must_use]
846    pub fn stop(&mut self) -> STOP_W<CTRL0_SPEC, 10> {
847        STOP_W::new(self)
848    }
849    #[doc = "Bit 11 - Enables/disables hardware flow control."]
850    #[inline(always)]
851    #[must_use]
852    pub fn flow(&mut self) -> FLOW_W<CTRL0_SPEC, 11> {
853        FLOW_W::new(self)
854    }
855    #[doc = "Bit 12 - RTS/CTS polarity."]
856    #[inline(always)]
857    #[must_use]
858    pub fn flowpol(&mut self) -> FLOWPOL_W<CTRL0_SPEC, 12> {
859        FLOWPOL_W::new(self)
860    }
861    #[doc = "Bit 13 - NULL Modem Support (RTS/CTS and TXD/RXD swap)."]
862    #[inline(always)]
863    #[must_use]
864    pub fn nullmod(&mut self) -> NULLMOD_W<CTRL0_SPEC, 13> {
865        NULLMOD_W::new(self)
866    }
867    #[doc = "Bit 14 - Break control bit."]
868    #[inline(always)]
869    #[must_use]
870    pub fn break_(&mut self) -> BREAK_W<CTRL0_SPEC, 14> {
871        BREAK_W::new(self)
872    }
873    #[doc = "Bit 15 - Baud Rate Clock Source Select."]
874    #[inline(always)]
875    #[must_use]
876    pub fn clk_sel(&mut self) -> CLK_SEL_W<CTRL0_SPEC, 15> {
877        CLK_SEL_W::new(self)
878    }
879    #[doc = "Bits 16:23 - RX Time Out."]
880    #[inline(always)]
881    #[must_use]
882    pub fn to_cnt(&mut self) -> TO_CNT_W<CTRL0_SPEC, 16> {
883        TO_CNT_W::new(self)
884    }
885    #[doc = r" Writes raw bits to the register."]
886    #[doc = r""]
887    #[doc = r" # Safety"]
888    #[doc = r""]
889    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
890    #[inline(always)]
891    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
892        self.bits = bits;
893        self
894    }
895}
896#[doc = "Control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
897pub struct CTRL0_SPEC;
898impl crate::RegisterSpec for CTRL0_SPEC {
899    type Ux = u32;
900}
901#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"]
902impl crate::Readable for CTRL0_SPEC {}
903#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
904impl crate::Writable for CTRL0_SPEC {
905    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
906    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
907}
908#[doc = "`reset()` method sets CTRL0 to value 0"]
909impl crate::Resettable for CTRL0_SPEC {
910    const RESET_VALUE: Self::Ux = 0;
911}
max32660/uart0/ctrl0.rs

max32660/uart0/
ctrl0.rs
