1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Flash Write Address."]
5 pub addr: crate::Reg<addr::ADDR_SPEC>,
6 #[doc = "0x04 - Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."]
7 pub clkdiv: crate::Reg<clkdiv::CLKDIV_SPEC>,
8 #[doc = "0x08 - Flash Control Register."]
9 pub cn: crate::Reg<cn::CN_SPEC>,
10 _reserved3: [u8; 0x18],
11 #[doc = "0x24 - Flash Interrupt Register."]
12 pub intr: crate::Reg<intr::INTR_SPEC>,
13 _reserved4: [u8; 0x08],
14 #[doc = "0x30..0x40 - Flash Write Data."]
15 pub data: [crate::Reg<data::DATA_SPEC>; 4],
16 #[doc = "0x40 - Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero."]
17 pub acntl: crate::Reg<acntl::ACNTL_SPEC>,
18}
19#[doc = "ADDR register accessor: an alias for `Reg<ADDR_SPEC>`"]
20pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
21#[doc = "Flash Write Address."]
22pub mod addr;
23#[doc = "CLKDIV register accessor: an alias for `Reg<CLKDIV_SPEC>`"]
24pub type CLKDIV = crate::Reg<clkdiv::CLKDIV_SPEC>;
25#[doc = "Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."]
26pub mod clkdiv;
27#[doc = "CN register accessor: an alias for `Reg<CN_SPEC>`"]
28pub type CN = crate::Reg<cn::CN_SPEC>;
29#[doc = "Flash Control Register."]
30pub mod cn;
31#[doc = "INTR register accessor: an alias for `Reg<INTR_SPEC>`"]
32pub type INTR = crate::Reg<intr::INTR_SPEC>;
33#[doc = "Flash Interrupt Register."]
34pub mod intr;
35#[doc = "DATA register accessor: an alias for `Reg<DATA_SPEC>`"]
36pub type DATA = crate::Reg<data::DATA_SPEC>;
37#[doc = "Flash Write Data."]
38pub mod data;
39#[doc = "ACNTL register accessor: an alias for `Reg<ACNTL_SPEC>`"]
40pub type ACNTL = crate::Reg<acntl::ACNTL_SPEC>;
41#[doc = "Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero."]
42pub mod acntl;