max32660_pac/rtc/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum RTCE_A {
40    #[doc = "0: Disable."]
41    DIS = 0,
42    #[doc = "1: Enable."]
43    EN = 1,
44}
45impl From<RTCE_A> for bool {
46    #[inline(always)]
47    fn from(variant: RTCE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `RTCE` reader - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
52pub struct RTCE_R(crate::FieldReader<bool, RTCE_A>);
53impl RTCE_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        RTCE_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> RTCE_A {
61        match self.bits {
62            false => RTCE_A::DIS,
63            true => RTCE_A::EN,
64        }
65    }
66    #[doc = "Checks if the value of the field is `DIS`"]
67    #[inline(always)]
68    pub fn is_dis(&self) -> bool {
69        **self == RTCE_A::DIS
70    }
71    #[doc = "Checks if the value of the field is `EN`"]
72    #[inline(always)]
73    pub fn is_en(&self) -> bool {
74        **self == RTCE_A::EN
75    }
76}
77impl core::ops::Deref for RTCE_R {
78    type Target = crate::FieldReader<bool, RTCE_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `RTCE` writer - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
85pub struct RTCE_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> RTCE_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: RTCE_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Disable."]
95    #[inline(always)]
96    pub fn dis(self) -> &'a mut W {
97        self.variant(RTCE_A::DIS)
98    }
99    #[doc = "Enable."]
100    #[inline(always)]
101    pub fn en(self) -> &'a mut W {
102        self.variant(RTCE_A::EN)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum ADE_A {
124    #[doc = "0: Disable."]
125    DIS = 0,
126    #[doc = "1: Enable."]
127    EN = 1,
128}
129impl From<ADE_A> for bool {
130    #[inline(always)]
131    fn from(variant: ADE_A) -> Self {
132        variant as u8 != 0
133    }
134}
135#[doc = "Field `ADE` reader - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
136pub struct ADE_R(crate::FieldReader<bool, ADE_A>);
137impl ADE_R {
138    #[inline(always)]
139    pub(crate) fn new(bits: bool) -> Self {
140        ADE_R(crate::FieldReader::new(bits))
141    }
142    #[doc = r"Get enumerated values variant"]
143    #[inline(always)]
144    pub fn variant(&self) -> ADE_A {
145        match self.bits {
146            false => ADE_A::DIS,
147            true => ADE_A::EN,
148        }
149    }
150    #[doc = "Checks if the value of the field is `DIS`"]
151    #[inline(always)]
152    pub fn is_dis(&self) -> bool {
153        **self == ADE_A::DIS
154    }
155    #[doc = "Checks if the value of the field is `EN`"]
156    #[inline(always)]
157    pub fn is_en(&self) -> bool {
158        **self == ADE_A::EN
159    }
160}
161impl core::ops::Deref for ADE_R {
162    type Target = crate::FieldReader<bool, ADE_A>;
163    #[inline(always)]
164    fn deref(&self) -> &Self::Target {
165        &self.0
166    }
167}
168#[doc = "Field `ADE` writer - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
169pub struct ADE_W<'a> {
170    w: &'a mut W,
171}
172impl<'a> ADE_W<'a> {
173    #[doc = r"Writes `variant` to the field"]
174    #[inline(always)]
175    pub fn variant(self, variant: ADE_A) -> &'a mut W {
176        self.bit(variant.into())
177    }
178    #[doc = "Disable."]
179    #[inline(always)]
180    pub fn dis(self) -> &'a mut W {
181        self.variant(ADE_A::DIS)
182    }
183    #[doc = "Enable."]
184    #[inline(always)]
185    pub fn en(self) -> &'a mut W {
186        self.variant(ADE_A::EN)
187    }
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
202        self.w
203    }
204}
205#[doc = "Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n\nValue on reset: 0"]
206#[derive(Clone, Copy, Debug, PartialEq)]
207pub enum ASE_A {
208    #[doc = "0: Disable."]
209    DIS = 0,
210    #[doc = "1: Enable."]
211    EN = 1,
212}
213impl From<ASE_A> for bool {
214    #[inline(always)]
215    fn from(variant: ASE_A) -> Self {
216        variant as u8 != 0
217    }
218}
219#[doc = "Field `ASE` reader - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
220pub struct ASE_R(crate::FieldReader<bool, ASE_A>);
221impl ASE_R {
222    #[inline(always)]
223    pub(crate) fn new(bits: bool) -> Self {
224        ASE_R(crate::FieldReader::new(bits))
225    }
226    #[doc = r"Get enumerated values variant"]
227    #[inline(always)]
228    pub fn variant(&self) -> ASE_A {
229        match self.bits {
230            false => ASE_A::DIS,
231            true => ASE_A::EN,
232        }
233    }
234    #[doc = "Checks if the value of the field is `DIS`"]
235    #[inline(always)]
236    pub fn is_dis(&self) -> bool {
237        **self == ASE_A::DIS
238    }
239    #[doc = "Checks if the value of the field is `EN`"]
240    #[inline(always)]
241    pub fn is_en(&self) -> bool {
242        **self == ASE_A::EN
243    }
244}
245impl core::ops::Deref for ASE_R {
246    type Target = crate::FieldReader<bool, ASE_A>;
247    #[inline(always)]
248    fn deref(&self) -> &Self::Target {
249        &self.0
250    }
251}
252#[doc = "Field `ASE` writer - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
253pub struct ASE_W<'a> {
254    w: &'a mut W,
255}
256impl<'a> ASE_W<'a> {
257    #[doc = r"Writes `variant` to the field"]
258    #[inline(always)]
259    pub fn variant(self, variant: ASE_A) -> &'a mut W {
260        self.bit(variant.into())
261    }
262    #[doc = "Disable."]
263    #[inline(always)]
264    pub fn dis(self) -> &'a mut W {
265        self.variant(ASE_A::DIS)
266    }
267    #[doc = "Enable."]
268    #[inline(always)]
269    pub fn en(self) -> &'a mut W {
270        self.variant(ASE_A::EN)
271    }
272    #[doc = r"Sets the field bit"]
273    #[inline(always)]
274    pub fn set_bit(self) -> &'a mut W {
275        self.bit(true)
276    }
277    #[doc = r"Clears the field bit"]
278    #[inline(always)]
279    pub fn clear_bit(self) -> &'a mut W {
280        self.bit(false)
281    }
282    #[doc = r"Writes raw bits to the field"]
283    #[inline(always)]
284    pub fn bit(self, value: bool) -> &'a mut W {
285        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
286        self.w
287    }
288}
289#[doc = "RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.\n\nValue on reset: 1"]
290#[derive(Clone, Copy, Debug, PartialEq)]
291pub enum BUSY_A {
292    #[doc = "0: Idle."]
293    IDLE = 0,
294    #[doc = "1: Busy."]
295    BUSY = 1,
296}
297impl From<BUSY_A> for bool {
298    #[inline(always)]
299    fn from(variant: BUSY_A) -> Self {
300        variant as u8 != 0
301    }
302}
303#[doc = "Field `BUSY` reader - RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware."]
304pub struct BUSY_R(crate::FieldReader<bool, BUSY_A>);
305impl BUSY_R {
306    #[inline(always)]
307    pub(crate) fn new(bits: bool) -> Self {
308        BUSY_R(crate::FieldReader::new(bits))
309    }
310    #[doc = r"Get enumerated values variant"]
311    #[inline(always)]
312    pub fn variant(&self) -> BUSY_A {
313        match self.bits {
314            false => BUSY_A::IDLE,
315            true => BUSY_A::BUSY,
316        }
317    }
318    #[doc = "Checks if the value of the field is `IDLE`"]
319    #[inline(always)]
320    pub fn is_idle(&self) -> bool {
321        **self == BUSY_A::IDLE
322    }
323    #[doc = "Checks if the value of the field is `BUSY`"]
324    #[inline(always)]
325    pub fn is_busy(&self) -> bool {
326        **self == BUSY_A::BUSY
327    }
328}
329impl core::ops::Deref for BUSY_R {
330    type Target = crate::FieldReader<bool, BUSY_A>;
331    #[inline(always)]
332    fn deref(&self) -> &Self::Target {
333        &self.0
334    }
335}
336#[doc = "RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.\n\nValue on reset: 0"]
337#[derive(Clone, Copy, Debug, PartialEq)]
338pub enum RDY_A {
339    #[doc = "0: Register has not updated."]
340    BUSY = 0,
341    #[doc = "1: Ready."]
342    READY = 1,
343}
344impl From<RDY_A> for bool {
345    #[inline(always)]
346    fn from(variant: RDY_A) -> Self {
347        variant as u8 != 0
348    }
349}
350#[doc = "Field `RDY` reader - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
351pub struct RDY_R(crate::FieldReader<bool, RDY_A>);
352impl RDY_R {
353    #[inline(always)]
354    pub(crate) fn new(bits: bool) -> Self {
355        RDY_R(crate::FieldReader::new(bits))
356    }
357    #[doc = r"Get enumerated values variant"]
358    #[inline(always)]
359    pub fn variant(&self) -> RDY_A {
360        match self.bits {
361            false => RDY_A::BUSY,
362            true => RDY_A::READY,
363        }
364    }
365    #[doc = "Checks if the value of the field is `BUSY`"]
366    #[inline(always)]
367    pub fn is_busy(&self) -> bool {
368        **self == RDY_A::BUSY
369    }
370    #[doc = "Checks if the value of the field is `READY`"]
371    #[inline(always)]
372    pub fn is_ready(&self) -> bool {
373        **self == RDY_A::READY
374    }
375}
376impl core::ops::Deref for RDY_R {
377    type Target = crate::FieldReader<bool, RDY_A>;
378    #[inline(always)]
379    fn deref(&self) -> &Self::Target {
380        &self.0
381    }
382}
383#[doc = "Field `RDY` writer - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
384pub struct RDY_W<'a> {
385    w: &'a mut W,
386}
387impl<'a> RDY_W<'a> {
388    #[doc = r"Writes `variant` to the field"]
389    #[inline(always)]
390    pub fn variant(self, variant: RDY_A) -> &'a mut W {
391        self.bit(variant.into())
392    }
393    #[doc = "Register has not updated."]
394    #[inline(always)]
395    pub fn busy(self) -> &'a mut W {
396        self.variant(RDY_A::BUSY)
397    }
398    #[doc = "Ready."]
399    #[inline(always)]
400    pub fn ready(self) -> &'a mut W {
401        self.variant(RDY_A::READY)
402    }
403    #[doc = r"Sets the field bit"]
404    #[inline(always)]
405    pub fn set_bit(self) -> &'a mut W {
406        self.bit(true)
407    }
408    #[doc = r"Clears the field bit"]
409    #[inline(always)]
410    pub fn clear_bit(self) -> &'a mut W {
411        self.bit(false)
412    }
413    #[doc = r"Writes raw bits to the field"]
414    #[inline(always)]
415    pub fn bit(self, value: bool) -> &'a mut W {
416        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
417        self.w
418    }
419}
420#[doc = "RTC Ready Interrupt Enable.\n\nValue on reset: 0"]
421#[derive(Clone, Copy, Debug, PartialEq)]
422pub enum RDYE_A {
423    #[doc = "0: Disable."]
424    DIS = 0,
425    #[doc = "1: Enable."]
426    EN = 1,
427}
428impl From<RDYE_A> for bool {
429    #[inline(always)]
430    fn from(variant: RDYE_A) -> Self {
431        variant as u8 != 0
432    }
433}
434#[doc = "Field `RDYE` reader - RTC Ready Interrupt Enable."]
435pub struct RDYE_R(crate::FieldReader<bool, RDYE_A>);
436impl RDYE_R {
437    #[inline(always)]
438    pub(crate) fn new(bits: bool) -> Self {
439        RDYE_R(crate::FieldReader::new(bits))
440    }
441    #[doc = r"Get enumerated values variant"]
442    #[inline(always)]
443    pub fn variant(&self) -> RDYE_A {
444        match self.bits {
445            false => RDYE_A::DIS,
446            true => RDYE_A::EN,
447        }
448    }
449    #[doc = "Checks if the value of the field is `DIS`"]
450    #[inline(always)]
451    pub fn is_dis(&self) -> bool {
452        **self == RDYE_A::DIS
453    }
454    #[doc = "Checks if the value of the field is `EN`"]
455    #[inline(always)]
456    pub fn is_en(&self) -> bool {
457        **self == RDYE_A::EN
458    }
459}
460impl core::ops::Deref for RDYE_R {
461    type Target = crate::FieldReader<bool, RDYE_A>;
462    #[inline(always)]
463    fn deref(&self) -> &Self::Target {
464        &self.0
465    }
466}
467#[doc = "Field `RDYE` writer - RTC Ready Interrupt Enable."]
468pub struct RDYE_W<'a> {
469    w: &'a mut W,
470}
471impl<'a> RDYE_W<'a> {
472    #[doc = r"Writes `variant` to the field"]
473    #[inline(always)]
474    pub fn variant(self, variant: RDYE_A) -> &'a mut W {
475        self.bit(variant.into())
476    }
477    #[doc = "Disable."]
478    #[inline(always)]
479    pub fn dis(self) -> &'a mut W {
480        self.variant(RDYE_A::DIS)
481    }
482    #[doc = "Enable."]
483    #[inline(always)]
484    pub fn en(self) -> &'a mut W {
485        self.variant(RDYE_A::EN)
486    }
487    #[doc = r"Sets the field bit"]
488    #[inline(always)]
489    pub fn set_bit(self) -> &'a mut W {
490        self.bit(true)
491    }
492    #[doc = r"Clears the field bit"]
493    #[inline(always)]
494    pub fn clear_bit(self) -> &'a mut W {
495        self.bit(false)
496    }
497    #[doc = r"Writes raw bits to the field"]
498    #[inline(always)]
499    pub fn bit(self, value: bool) -> &'a mut W {
500        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
501        self.w
502    }
503}
504#[doc = "Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n\nValue on reset: 0"]
505#[derive(Clone, Copy, Debug, PartialEq)]
506pub enum ALDF_A {
507    #[doc = "0: Not active"]
508    INACTIVE = 0,
509    #[doc = "1: Active"]
510    PENDING = 1,
511}
512impl From<ALDF_A> for bool {
513    #[inline(always)]
514    fn from(variant: ALDF_A) -> Self {
515        variant as u8 != 0
516    }
517}
518#[doc = "Field `ALDF` reader - Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
519pub struct ALDF_R(crate::FieldReader<bool, ALDF_A>);
520impl ALDF_R {
521    #[inline(always)]
522    pub(crate) fn new(bits: bool) -> Self {
523        ALDF_R(crate::FieldReader::new(bits))
524    }
525    #[doc = r"Get enumerated values variant"]
526    #[inline(always)]
527    pub fn variant(&self) -> ALDF_A {
528        match self.bits {
529            false => ALDF_A::INACTIVE,
530            true => ALDF_A::PENDING,
531        }
532    }
533    #[doc = "Checks if the value of the field is `INACTIVE`"]
534    #[inline(always)]
535    pub fn is_inactive(&self) -> bool {
536        **self == ALDF_A::INACTIVE
537    }
538    #[doc = "Checks if the value of the field is `PENDING`"]
539    #[inline(always)]
540    pub fn is_pending(&self) -> bool {
541        **self == ALDF_A::PENDING
542    }
543}
544impl core::ops::Deref for ALDF_R {
545    type Target = crate::FieldReader<bool, ALDF_A>;
546    #[inline(always)]
547    fn deref(&self) -> &Self::Target {
548        &self.0
549    }
550}
551#[doc = "Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n\nValue on reset: 0"]
552#[derive(Clone, Copy, Debug, PartialEq)]
553pub enum ALSF_A {
554    #[doc = "0: Not active"]
555    INACTIVE = 0,
556    #[doc = "1: Active"]
557    PENDING = 1,
558}
559impl From<ALSF_A> for bool {
560    #[inline(always)]
561    fn from(variant: ALSF_A) -> Self {
562        variant as u8 != 0
563    }
564}
565#[doc = "Field `ALSF` reader - Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
566pub struct ALSF_R(crate::FieldReader<bool, ALSF_A>);
567impl ALSF_R {
568    #[inline(always)]
569    pub(crate) fn new(bits: bool) -> Self {
570        ALSF_R(crate::FieldReader::new(bits))
571    }
572    #[doc = r"Get enumerated values variant"]
573    #[inline(always)]
574    pub fn variant(&self) -> ALSF_A {
575        match self.bits {
576            false => ALSF_A::INACTIVE,
577            true => ALSF_A::PENDING,
578        }
579    }
580    #[doc = "Checks if the value of the field is `INACTIVE`"]
581    #[inline(always)]
582    pub fn is_inactive(&self) -> bool {
583        **self == ALSF_A::INACTIVE
584    }
585    #[doc = "Checks if the value of the field is `PENDING`"]
586    #[inline(always)]
587    pub fn is_pending(&self) -> bool {
588        **self == ALSF_A::PENDING
589    }
590}
591impl core::ops::Deref for ALSF_R {
592    type Target = crate::FieldReader<bool, ALSF_A>;
593    #[inline(always)]
594    fn deref(&self) -> &Self::Target {
595        &self.0
596    }
597}
598#[doc = "Square Wave Output Enable.\n\nValue on reset: 0"]
599#[derive(Clone, Copy, Debug, PartialEq)]
600pub enum SQE_A {
601    #[doc = "0: Not active"]
602    INACTIVE = 0,
603    #[doc = "1: Active"]
604    PENDING = 1,
605}
606impl From<SQE_A> for bool {
607    #[inline(always)]
608    fn from(variant: SQE_A) -> Self {
609        variant as u8 != 0
610    }
611}
612#[doc = "Field `SQE` reader - Square Wave Output Enable."]
613pub struct SQE_R(crate::FieldReader<bool, SQE_A>);
614impl SQE_R {
615    #[inline(always)]
616    pub(crate) fn new(bits: bool) -> Self {
617        SQE_R(crate::FieldReader::new(bits))
618    }
619    #[doc = r"Get enumerated values variant"]
620    #[inline(always)]
621    pub fn variant(&self) -> SQE_A {
622        match self.bits {
623            false => SQE_A::INACTIVE,
624            true => SQE_A::PENDING,
625        }
626    }
627    #[doc = "Checks if the value of the field is `INACTIVE`"]
628    #[inline(always)]
629    pub fn is_inactive(&self) -> bool {
630        **self == SQE_A::INACTIVE
631    }
632    #[doc = "Checks if the value of the field is `PENDING`"]
633    #[inline(always)]
634    pub fn is_pending(&self) -> bool {
635        **self == SQE_A::PENDING
636    }
637}
638impl core::ops::Deref for SQE_R {
639    type Target = crate::FieldReader<bool, SQE_A>;
640    #[inline(always)]
641    fn deref(&self) -> &Self::Target {
642        &self.0
643    }
644}
645#[doc = "Field `SQE` writer - Square Wave Output Enable."]
646pub struct SQE_W<'a> {
647    w: &'a mut W,
648}
649impl<'a> SQE_W<'a> {
650    #[doc = r"Writes `variant` to the field"]
651    #[inline(always)]
652    pub fn variant(self, variant: SQE_A) -> &'a mut W {
653        self.bit(variant.into())
654    }
655    #[doc = "Not active"]
656    #[inline(always)]
657    pub fn inactive(self) -> &'a mut W {
658        self.variant(SQE_A::INACTIVE)
659    }
660    #[doc = "Active"]
661    #[inline(always)]
662    pub fn pending(self) -> &'a mut W {
663        self.variant(SQE_A::PENDING)
664    }
665    #[doc = r"Sets the field bit"]
666    #[inline(always)]
667    pub fn set_bit(self) -> &'a mut W {
668        self.bit(true)
669    }
670    #[doc = r"Clears the field bit"]
671    #[inline(always)]
672    pub fn clear_bit(self) -> &'a mut W {
673        self.bit(false)
674    }
675    #[doc = r"Writes raw bits to the field"]
676    #[inline(always)]
677    pub fn bit(self, value: bool) -> &'a mut W {
678        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
679        self.w
680    }
681}
682#[doc = "Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.\n\nValue on reset: 0"]
683#[derive(Clone, Copy, Debug, PartialEq)]
684#[repr(u8)]
685pub enum FT_A {
686    #[doc = "0: 1 Hz (Compensated)."]
687    FREQ1HZ = 0,
688    #[doc = "1: 512 Hz (Compensated)."]
689    FREQ512HZ = 1,
690    #[doc = "2: 4 KHz."]
691    FREQ4KHZ = 2,
692    #[doc = "3: RTC Input Clock / 8."]
693    CLKDIV8 = 3,
694}
695impl From<FT_A> for u8 {
696    #[inline(always)]
697    fn from(variant: FT_A) -> Self {
698        variant as _
699    }
700}
701#[doc = "Field `FT` reader - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
702pub struct FT_R(crate::FieldReader<u8, FT_A>);
703impl FT_R {
704    #[inline(always)]
705    pub(crate) fn new(bits: u8) -> Self {
706        FT_R(crate::FieldReader::new(bits))
707    }
708    #[doc = r"Get enumerated values variant"]
709    #[inline(always)]
710    pub fn variant(&self) -> FT_A {
711        match self.bits {
712            0 => FT_A::FREQ1HZ,
713            1 => FT_A::FREQ512HZ,
714            2 => FT_A::FREQ4KHZ,
715            3 => FT_A::CLKDIV8,
716            _ => unreachable!(),
717        }
718    }
719    #[doc = "Checks if the value of the field is `FREQ1HZ`"]
720    #[inline(always)]
721    pub fn is_freq1hz(&self) -> bool {
722        **self == FT_A::FREQ1HZ
723    }
724    #[doc = "Checks if the value of the field is `FREQ512HZ`"]
725    #[inline(always)]
726    pub fn is_freq512hz(&self) -> bool {
727        **self == FT_A::FREQ512HZ
728    }
729    #[doc = "Checks if the value of the field is `FREQ4KHZ`"]
730    #[inline(always)]
731    pub fn is_freq4khz(&self) -> bool {
732        **self == FT_A::FREQ4KHZ
733    }
734    #[doc = "Checks if the value of the field is `CLKDIV8`"]
735    #[inline(always)]
736    pub fn is_clk_div8(&self) -> bool {
737        **self == FT_A::CLKDIV8
738    }
739}
740impl core::ops::Deref for FT_R {
741    type Target = crate::FieldReader<u8, FT_A>;
742    #[inline(always)]
743    fn deref(&self) -> &Self::Target {
744        &self.0
745    }
746}
747#[doc = "Field `FT` writer - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
748pub struct FT_W<'a> {
749    w: &'a mut W,
750}
751impl<'a> FT_W<'a> {
752    #[doc = r"Writes `variant` to the field"]
753    #[inline(always)]
754    pub fn variant(self, variant: FT_A) -> &'a mut W {
755        self.bits(variant.into())
756    }
757    #[doc = "1 Hz (Compensated)."]
758    #[inline(always)]
759    pub fn freq1hz(self) -> &'a mut W {
760        self.variant(FT_A::FREQ1HZ)
761    }
762    #[doc = "512 Hz (Compensated)."]
763    #[inline(always)]
764    pub fn freq512hz(self) -> &'a mut W {
765        self.variant(FT_A::FREQ512HZ)
766    }
767    #[doc = "4 KHz."]
768    #[inline(always)]
769    pub fn freq4khz(self) -> &'a mut W {
770        self.variant(FT_A::FREQ4KHZ)
771    }
772    #[doc = "RTC Input Clock / 8."]
773    #[inline(always)]
774    pub fn clk_div8(self) -> &'a mut W {
775        self.variant(FT_A::CLKDIV8)
776    }
777    #[doc = r"Writes raw bits to the field"]
778    #[inline(always)]
779    pub fn bits(self, value: u8) -> &'a mut W {
780        self.w.bits = (self.w.bits & !(0x03 << 9)) | ((value as u32 & 0x03) << 9);
781        self.w
782    }
783}
784#[doc = "32KHz Oscillator Mode.\n\nValue on reset: 0"]
785#[derive(Clone, Copy, Debug, PartialEq)]
786#[repr(u8)]
787pub enum X32KMD_A {
788    #[doc = "0: Always operate in Noise Immune Mode. Oscillator warm-up required."]
789    NOISEIMMUNEMODE = 0,
790    #[doc = "1: Always operate in Quiet Mode. No oscillator warm-up required."]
791    QUIETMODE = 1,
792    #[doc = "2: Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit."]
793    QUIETINSTOPWITHWARMUP = 2,
794    #[doc = "3: Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit."]
795    QUIETINSTOPNOWARMUP = 3,
796}
797impl From<X32KMD_A> for u8 {
798    #[inline(always)]
799    fn from(variant: X32KMD_A) -> Self {
800        variant as _
801    }
802}
803#[doc = "Field `X32KMD` reader - 32KHz Oscillator Mode."]
804pub struct X32KMD_R(crate::FieldReader<u8, X32KMD_A>);
805impl X32KMD_R {
806    #[inline(always)]
807    pub(crate) fn new(bits: u8) -> Self {
808        X32KMD_R(crate::FieldReader::new(bits))
809    }
810    #[doc = r"Get enumerated values variant"]
811    #[inline(always)]
812    pub fn variant(&self) -> X32KMD_A {
813        match self.bits {
814            0 => X32KMD_A::NOISEIMMUNEMODE,
815            1 => X32KMD_A::QUIETMODE,
816            2 => X32KMD_A::QUIETINSTOPWITHWARMUP,
817            3 => X32KMD_A::QUIETINSTOPNOWARMUP,
818            _ => unreachable!(),
819        }
820    }
821    #[doc = "Checks if the value of the field is `NOISEIMMUNEMODE`"]
822    #[inline(always)]
823    pub fn is_noise_immune_mode(&self) -> bool {
824        **self == X32KMD_A::NOISEIMMUNEMODE
825    }
826    #[doc = "Checks if the value of the field is `QUIETMODE`"]
827    #[inline(always)]
828    pub fn is_quiet_mode(&self) -> bool {
829        **self == X32KMD_A::QUIETMODE
830    }
831    #[doc = "Checks if the value of the field is `QUIETINSTOPWITHWARMUP`"]
832    #[inline(always)]
833    pub fn is_quiet_in_stop_with_warmup(&self) -> bool {
834        **self == X32KMD_A::QUIETINSTOPWITHWARMUP
835    }
836    #[doc = "Checks if the value of the field is `QUIETINSTOPNOWARMUP`"]
837    #[inline(always)]
838    pub fn is_quiet_in_stop_no_warmup(&self) -> bool {
839        **self == X32KMD_A::QUIETINSTOPNOWARMUP
840    }
841}
842impl core::ops::Deref for X32KMD_R {
843    type Target = crate::FieldReader<u8, X32KMD_A>;
844    #[inline(always)]
845    fn deref(&self) -> &Self::Target {
846        &self.0
847    }
848}
849#[doc = "Field `X32KMD` writer - 32KHz Oscillator Mode."]
850pub struct X32KMD_W<'a> {
851    w: &'a mut W,
852}
853impl<'a> X32KMD_W<'a> {
854    #[doc = r"Writes `variant` to the field"]
855    #[inline(always)]
856    pub fn variant(self, variant: X32KMD_A) -> &'a mut W {
857        self.bits(variant.into())
858    }
859    #[doc = "Always operate in Noise Immune Mode. Oscillator warm-up required."]
860    #[inline(always)]
861    pub fn noise_immune_mode(self) -> &'a mut W {
862        self.variant(X32KMD_A::NOISEIMMUNEMODE)
863    }
864    #[doc = "Always operate in Quiet Mode. No oscillator warm-up required."]
865    #[inline(always)]
866    pub fn quiet_mode(self) -> &'a mut W {
867        self.variant(X32KMD_A::QUIETMODE)
868    }
869    #[doc = "Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit."]
870    #[inline(always)]
871    pub fn quiet_in_stop_with_warmup(self) -> &'a mut W {
872        self.variant(X32KMD_A::QUIETINSTOPWITHWARMUP)
873    }
874    #[doc = "Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit."]
875    #[inline(always)]
876    pub fn quiet_in_stop_no_warmup(self) -> &'a mut W {
877        self.variant(X32KMD_A::QUIETINSTOPNOWARMUP)
878    }
879    #[doc = r"Writes raw bits to the field"]
880    #[inline(always)]
881    pub fn bits(self, value: u8) -> &'a mut W {
882        self.w.bits = (self.w.bits & !(0x03 << 11)) | ((value as u32 & 0x03) << 11);
883        self.w
884    }
885}
886#[doc = "Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.\n\nValue on reset: 0"]
887#[derive(Clone, Copy, Debug, PartialEq)]
888pub enum WE_A {
889    #[doc = "0: Not active"]
890    INACTIVE = 0,
891    #[doc = "1: Active"]
892    PENDING = 1,
893}
894impl From<WE_A> for bool {
895    #[inline(always)]
896    fn from(variant: WE_A) -> Self {
897        variant as u8 != 0
898    }
899}
900#[doc = "Field `WE` reader - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
901pub struct WE_R(crate::FieldReader<bool, WE_A>);
902impl WE_R {
903    #[inline(always)]
904    pub(crate) fn new(bits: bool) -> Self {
905        WE_R(crate::FieldReader::new(bits))
906    }
907    #[doc = r"Get enumerated values variant"]
908    #[inline(always)]
909    pub fn variant(&self) -> WE_A {
910        match self.bits {
911            false => WE_A::INACTIVE,
912            true => WE_A::PENDING,
913        }
914    }
915    #[doc = "Checks if the value of the field is `INACTIVE`"]
916    #[inline(always)]
917    pub fn is_inactive(&self) -> bool {
918        **self == WE_A::INACTIVE
919    }
920    #[doc = "Checks if the value of the field is `PENDING`"]
921    #[inline(always)]
922    pub fn is_pending(&self) -> bool {
923        **self == WE_A::PENDING
924    }
925}
926impl core::ops::Deref for WE_R {
927    type Target = crate::FieldReader<bool, WE_A>;
928    #[inline(always)]
929    fn deref(&self) -> &Self::Target {
930        &self.0
931    }
932}
933#[doc = "Field `WE` writer - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
934pub struct WE_W<'a> {
935    w: &'a mut W,
936}
937impl<'a> WE_W<'a> {
938    #[doc = r"Writes `variant` to the field"]
939    #[inline(always)]
940    pub fn variant(self, variant: WE_A) -> &'a mut W {
941        self.bit(variant.into())
942    }
943    #[doc = "Not active"]
944    #[inline(always)]
945    pub fn inactive(self) -> &'a mut W {
946        self.variant(WE_A::INACTIVE)
947    }
948    #[doc = "Active"]
949    #[inline(always)]
950    pub fn pending(self) -> &'a mut W {
951        self.variant(WE_A::PENDING)
952    }
953    #[doc = r"Sets the field bit"]
954    #[inline(always)]
955    pub fn set_bit(self) -> &'a mut W {
956        self.bit(true)
957    }
958    #[doc = r"Clears the field bit"]
959    #[inline(always)]
960    pub fn clear_bit(self) -> &'a mut W {
961        self.bit(false)
962    }
963    #[doc = r"Writes raw bits to the field"]
964    #[inline(always)]
965    pub fn bit(self, value: bool) -> &'a mut W {
966        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
967        self.w
968    }
969}
970impl R {
971    #[doc = "Bit 0 - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
972    #[inline(always)]
973    pub fn rtce(&self) -> RTCE_R {
974        RTCE_R::new((self.bits & 0x01) != 0)
975    }
976    #[doc = "Bit 1 - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
977    #[inline(always)]
978    pub fn ade(&self) -> ADE_R {
979        ADE_R::new(((self.bits >> 1) & 0x01) != 0)
980    }
981    #[doc = "Bit 2 - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
982    #[inline(always)]
983    pub fn ase(&self) -> ASE_R {
984        ASE_R::new(((self.bits >> 2) & 0x01) != 0)
985    }
986    #[doc = "Bit 3 - RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware."]
987    #[inline(always)]
988    pub fn busy(&self) -> BUSY_R {
989        BUSY_R::new(((self.bits >> 3) & 0x01) != 0)
990    }
991    #[doc = "Bit 4 - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
992    #[inline(always)]
993    pub fn rdy(&self) -> RDY_R {
994        RDY_R::new(((self.bits >> 4) & 0x01) != 0)
995    }
996    #[doc = "Bit 5 - RTC Ready Interrupt Enable."]
997    #[inline(always)]
998    pub fn rdye(&self) -> RDYE_R {
999        RDYE_R::new(((self.bits >> 5) & 0x01) != 0)
1000    }
1001    #[doc = "Bit 6 - Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
1002    #[inline(always)]
1003    pub fn aldf(&self) -> ALDF_R {
1004        ALDF_R::new(((self.bits >> 6) & 0x01) != 0)
1005    }
1006    #[doc = "Bit 7 - Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
1007    #[inline(always)]
1008    pub fn alsf(&self) -> ALSF_R {
1009        ALSF_R::new(((self.bits >> 7) & 0x01) != 0)
1010    }
1011    #[doc = "Bit 8 - Square Wave Output Enable."]
1012    #[inline(always)]
1013    pub fn sqe(&self) -> SQE_R {
1014        SQE_R::new(((self.bits >> 8) & 0x01) != 0)
1015    }
1016    #[doc = "Bits 9:10 - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
1017    #[inline(always)]
1018    pub fn ft(&self) -> FT_R {
1019        FT_R::new(((self.bits >> 9) & 0x03) as u8)
1020    }
1021    #[doc = "Bits 11:12 - 32KHz Oscillator Mode."]
1022    #[inline(always)]
1023    pub fn x32kmd(&self) -> X32KMD_R {
1024        X32KMD_R::new(((self.bits >> 11) & 0x03) as u8)
1025    }
1026    #[doc = "Bit 15 - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
1027    #[inline(always)]
1028    pub fn we(&self) -> WE_R {
1029        WE_R::new(((self.bits >> 15) & 0x01) != 0)
1030    }
1031}
1032impl W {
1033    #[doc = "Bit 0 - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
1034    #[inline(always)]
1035    pub fn rtce(&mut self) -> RTCE_W {
1036        RTCE_W { w: self }
1037    }
1038    #[doc = "Bit 1 - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
1039    #[inline(always)]
1040    pub fn ade(&mut self) -> ADE_W {
1041        ADE_W { w: self }
1042    }
1043    #[doc = "Bit 2 - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
1044    #[inline(always)]
1045    pub fn ase(&mut self) -> ASE_W {
1046        ASE_W { w: self }
1047    }
1048    #[doc = "Bit 4 - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
1049    #[inline(always)]
1050    pub fn rdy(&mut self) -> RDY_W {
1051        RDY_W { w: self }
1052    }
1053    #[doc = "Bit 5 - RTC Ready Interrupt Enable."]
1054    #[inline(always)]
1055    pub fn rdye(&mut self) -> RDYE_W {
1056        RDYE_W { w: self }
1057    }
1058    #[doc = "Bit 8 - Square Wave Output Enable."]
1059    #[inline(always)]
1060    pub fn sqe(&mut self) -> SQE_W {
1061        SQE_W { w: self }
1062    }
1063    #[doc = "Bits 9:10 - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
1064    #[inline(always)]
1065    pub fn ft(&mut self) -> FT_W {
1066        FT_W { w: self }
1067    }
1068    #[doc = "Bits 11:12 - 32KHz Oscillator Mode."]
1069    #[inline(always)]
1070    pub fn x32kmd(&mut self) -> X32KMD_W {
1071        X32KMD_W { w: self }
1072    }
1073    #[doc = "Bit 15 - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
1074    #[inline(always)]
1075    pub fn we(&mut self) -> WE_W {
1076        WE_W { w: self }
1077    }
1078    #[doc = "Writes raw bits to the register."]
1079    #[inline(always)]
1080    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1081        self.0.bits(bits);
1082        self
1083    }
1084}
1085#[doc = "RTC Control Register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
1086pub struct CTRL_SPEC;
1087impl crate::RegisterSpec for CTRL_SPEC {
1088    type Ux = u32;
1089}
1090#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
1091impl crate::Readable for CTRL_SPEC {
1092    type Reader = R;
1093}
1094#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
1095impl crate::Writable for CTRL_SPEC {
1096    type Writer = W;
1097}
1098#[doc = "`reset()` method sets CTRL to value 0x08"]
1099impl crate::Resettable for CTRL_SPEC {
1100    #[inline(always)]
1101    fn reset_value() -> Self::Ux {
1102        0x08
1103    }
1104}
max32660_pac/rtc/ctrl.rs

max32660_pac/rtc/
ctrl.rs
