max3263x/usb/
ep1.rs

1#[doc = "Register `EP1` reader"]
2pub struct R(crate::R<EP1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<EP1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<EP1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<EP1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `EP1` writer"]
17pub struct W(crate::W<EP1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<EP1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<EP1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<EP1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ep_dir` reader - Endpoint Direction"]
38pub type EP_DIR_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `ep_dir` writer - Endpoint Direction"]
40pub type EP_DIR_W<'a> = crate::FieldWriter<'a, u32, EP1_SPEC, u8, u8, 2, 0>;
41#[doc = "Field `ep_buf2` reader - Endpoint Double Buffered Enable"]
42pub type EP_BUF2_R = crate::BitReader<bool>;
43#[doc = "Field `ep_buf2` writer - Endpoint Double Buffered Enable"]
44pub type EP_BUF2_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 3>;
45#[doc = "Field `ep_int_en` reader - Endpoint Transfer Complete Interrupt Enable"]
46pub type EP_INT_EN_R = crate::BitReader<bool>;
47#[doc = "Field `ep_int_en` writer - Endpoint Transfer Complete Interrupt Enable"]
48pub type EP_INT_EN_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 4>;
49#[doc = "Field `ep_nak_en` reader - Endpoint NAK Interrupt Enable"]
50pub type EP_NAK_EN_R = crate::BitReader<bool>;
51#[doc = "Field `ep_nak_en` writer - Endpoint NAK Interrupt Enable"]
52pub type EP_NAK_EN_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 5>;
53#[doc = "Field `ep_dt` reader - Endpoint Data Toggle Clear"]
54pub type EP_DT_R = crate::BitReader<bool>;
55#[doc = "Field `ep_dt` writer - Endpoint Data Toggle Clear"]
56pub type EP_DT_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 6>;
57#[doc = "Field `ep_stall` reader - Endpoint Stall"]
58pub type EP_STALL_R = crate::BitReader<bool>;
59#[doc = "Field `ep_stall` writer - Endpoint Stall"]
60pub type EP_STALL_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 8>;
61#[doc = "Field `ep_st_stall` reader - Endpoint Stall Status Stage of Control Transfer"]
62pub type EP_ST_STALL_R = crate::BitReader<bool>;
63#[doc = "Field `ep_st_stall` writer - Endpoint Stall Status Stage of Control Transfer"]
64pub type EP_ST_STALL_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 9>;
65#[doc = "Field `ep_st_ack` reader - Endpoint Acknowledge Status Stage of Control Transfer"]
66pub type EP_ST_ACK_R = crate::BitReader<bool>;
67#[doc = "Field `ep_st_ack` writer - Endpoint Acknowledge Status Stage of Control Transfer"]
68pub type EP_ST_ACK_W<'a> = crate::BitWriter<'a, u32, EP1_SPEC, bool, 10>;
69impl R {
70    #[doc = "Bits 0:1 - Endpoint Direction"]
71    #[inline(always)]
72    pub fn ep_dir(&self) -> EP_DIR_R {
73        EP_DIR_R::new((self.bits & 3) as u8)
74    }
75    #[doc = "Bit 3 - Endpoint Double Buffered Enable"]
76    #[inline(always)]
77    pub fn ep_buf2(&self) -> EP_BUF2_R {
78        EP_BUF2_R::new(((self.bits >> 3) & 1) != 0)
79    }
80    #[doc = "Bit 4 - Endpoint Transfer Complete Interrupt Enable"]
81    #[inline(always)]
82    pub fn ep_int_en(&self) -> EP_INT_EN_R {
83        EP_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
84    }
85    #[doc = "Bit 5 - Endpoint NAK Interrupt Enable"]
86    #[inline(always)]
87    pub fn ep_nak_en(&self) -> EP_NAK_EN_R {
88        EP_NAK_EN_R::new(((self.bits >> 5) & 1) != 0)
89    }
90    #[doc = "Bit 6 - Endpoint Data Toggle Clear"]
91    #[inline(always)]
92    pub fn ep_dt(&self) -> EP_DT_R {
93        EP_DT_R::new(((self.bits >> 6) & 1) != 0)
94    }
95    #[doc = "Bit 8 - Endpoint Stall"]
96    #[inline(always)]
97    pub fn ep_stall(&self) -> EP_STALL_R {
98        EP_STALL_R::new(((self.bits >> 8) & 1) != 0)
99    }
100    #[doc = "Bit 9 - Endpoint Stall Status Stage of Control Transfer"]
101    #[inline(always)]
102    pub fn ep_st_stall(&self) -> EP_ST_STALL_R {
103        EP_ST_STALL_R::new(((self.bits >> 9) & 1) != 0)
104    }
105    #[doc = "Bit 10 - Endpoint Acknowledge Status Stage of Control Transfer"]
106    #[inline(always)]
107    pub fn ep_st_ack(&self) -> EP_ST_ACK_R {
108        EP_ST_ACK_R::new(((self.bits >> 10) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bits 0:1 - Endpoint Direction"]
113    #[inline(always)]
114    pub fn ep_dir(&mut self) -> EP_DIR_W {
115        EP_DIR_W::new(self)
116    }
117    #[doc = "Bit 3 - Endpoint Double Buffered Enable"]
118    #[inline(always)]
119    pub fn ep_buf2(&mut self) -> EP_BUF2_W {
120        EP_BUF2_W::new(self)
121    }
122    #[doc = "Bit 4 - Endpoint Transfer Complete Interrupt Enable"]
123    #[inline(always)]
124    pub fn ep_int_en(&mut self) -> EP_INT_EN_W {
125        EP_INT_EN_W::new(self)
126    }
127    #[doc = "Bit 5 - Endpoint NAK Interrupt Enable"]
128    #[inline(always)]
129    pub fn ep_nak_en(&mut self) -> EP_NAK_EN_W {
130        EP_NAK_EN_W::new(self)
131    }
132    #[doc = "Bit 6 - Endpoint Data Toggle Clear"]
133    #[inline(always)]
134    pub fn ep_dt(&mut self) -> EP_DT_W {
135        EP_DT_W::new(self)
136    }
137    #[doc = "Bit 8 - Endpoint Stall"]
138    #[inline(always)]
139    pub fn ep_stall(&mut self) -> EP_STALL_W {
140        EP_STALL_W::new(self)
141    }
142    #[doc = "Bit 9 - Endpoint Stall Status Stage of Control Transfer"]
143    #[inline(always)]
144    pub fn ep_st_stall(&mut self) -> EP_ST_STALL_W {
145        EP_ST_STALL_W::new(self)
146    }
147    #[doc = "Bit 10 - Endpoint Acknowledge Status Stage of Control Transfer"]
148    #[inline(always)]
149    pub fn ep_st_ack(&mut self) -> EP_ST_ACK_W {
150        EP_ST_ACK_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "USB Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ep1](index.html) module"]
160pub struct EP1_SPEC;
161impl crate::RegisterSpec for EP1_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [ep1::R](R) reader structure"]
165impl crate::Readable for EP1_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [ep1::W](W) writer structure"]
169impl crate::Writable for EP1_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets EP1 to value 0"]
173impl crate::Resettable for EP1_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0
177    }
178}