max3263x/pwrseq/
reg3.rs

1#[doc = "Register `REG3` reader"]
2pub struct R(crate::R<REG3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<REG3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<REG3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<REG3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `REG3` writer"]
17pub struct W(crate::W<REG3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<REG3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<REG3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<REG3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `pwr_rosel` reader - Relaxation Oscillator Stable Timeout"]
38pub type PWR_ROSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `pwr_rosel` writer - Relaxation Oscillator Stable Timeout"]
40pub type PWR_ROSEL_W<'a> = crate::FieldWriter<'a, u32, REG3_SPEC, u8, u8, 3, 0>;
41#[doc = "Field `pwr_fltrrosel` reader - Window of time power must be valid before entering Run mode."]
42pub type PWR_FLTRROSEL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `pwr_fltrrosel` writer - Window of time power must be valid before entering Run mode."]
44pub type PWR_FLTRROSEL_W<'a> = crate::FieldWriter<'a, u32, REG3_SPEC, u8, u8, 3, 3>;
45#[doc = "Field `pwr_svm_clk_mux` reader - SVM Clock Mux"]
46pub type PWR_SVM_CLK_MUX_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `pwr_svm_clk_mux` writer - SVM Clock Mux"]
48pub type PWR_SVM_CLK_MUX_W<'a> = crate::FieldWriter<'a, u32, REG3_SPEC, u8, u8, 2, 6>;
49#[doc = "Field `pwr_ro_clk_mux` reader - Relaxation Clock Mux"]
50pub type PWR_RO_CLK_MUX_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `pwr_ro_clk_mux` writer - Relaxation Clock Mux"]
52pub type PWR_RO_CLK_MUX_W<'a> = crate::FieldWriter<'a, u32, REG3_SPEC, u8, u8, 2, 8>;
53#[doc = "Field `pwr_failsel` reader - Timeout before rebooting during PowerFail/BootFail events."]
54pub type PWR_FAILSEL_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `pwr_failsel` writer - Timeout before rebooting during PowerFail/BootFail events."]
56pub type PWR_FAILSEL_W<'a> = crate::FieldWriter<'a, u32, REG3_SPEC, u8, u8, 3, 10>;
57impl R {
58    #[doc = "Bits 0:2 - Relaxation Oscillator Stable Timeout"]
59    #[inline(always)]
60    pub fn pwr_rosel(&self) -> PWR_ROSEL_R {
61        PWR_ROSEL_R::new((self.bits & 7) as u8)
62    }
63    #[doc = "Bits 3:5 - Window of time power must be valid before entering Run mode."]
64    #[inline(always)]
65    pub fn pwr_fltrrosel(&self) -> PWR_FLTRROSEL_R {
66        PWR_FLTRROSEL_R::new(((self.bits >> 3) & 7) as u8)
67    }
68    #[doc = "Bits 6:7 - SVM Clock Mux"]
69    #[inline(always)]
70    pub fn pwr_svm_clk_mux(&self) -> PWR_SVM_CLK_MUX_R {
71        PWR_SVM_CLK_MUX_R::new(((self.bits >> 6) & 3) as u8)
72    }
73    #[doc = "Bits 8:9 - Relaxation Clock Mux"]
74    #[inline(always)]
75    pub fn pwr_ro_clk_mux(&self) -> PWR_RO_CLK_MUX_R {
76        PWR_RO_CLK_MUX_R::new(((self.bits >> 8) & 3) as u8)
77    }
78    #[doc = "Bits 10:12 - Timeout before rebooting during PowerFail/BootFail events."]
79    #[inline(always)]
80    pub fn pwr_failsel(&self) -> PWR_FAILSEL_R {
81        PWR_FAILSEL_R::new(((self.bits >> 10) & 7) as u8)
82    }
83}
84impl W {
85    #[doc = "Bits 0:2 - Relaxation Oscillator Stable Timeout"]
86    #[inline(always)]
87    pub fn pwr_rosel(&mut self) -> PWR_ROSEL_W {
88        PWR_ROSEL_W::new(self)
89    }
90    #[doc = "Bits 3:5 - Window of time power must be valid before entering Run mode."]
91    #[inline(always)]
92    pub fn pwr_fltrrosel(&mut self) -> PWR_FLTRROSEL_W {
93        PWR_FLTRROSEL_W::new(self)
94    }
95    #[doc = "Bits 6:7 - SVM Clock Mux"]
96    #[inline(always)]
97    pub fn pwr_svm_clk_mux(&mut self) -> PWR_SVM_CLK_MUX_W {
98        PWR_SVM_CLK_MUX_W::new(self)
99    }
100    #[doc = "Bits 8:9 - Relaxation Clock Mux"]
101    #[inline(always)]
102    pub fn pwr_ro_clk_mux(&mut self) -> PWR_RO_CLK_MUX_W {
103        PWR_RO_CLK_MUX_W::new(self)
104    }
105    #[doc = "Bits 10:12 - Timeout before rebooting during PowerFail/BootFail events."]
106    #[inline(always)]
107    pub fn pwr_failsel(&mut self) -> PWR_FAILSEL_W {
108        PWR_FAILSEL_W::new(self)
109    }
110    #[doc = "Writes raw bits to the register."]
111    #[inline(always)]
112    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
113        self.0.bits(bits);
114        self
115    }
116}
117#[doc = "Power Sequencer Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reg3](index.html) module"]
118pub struct REG3_SPEC;
119impl crate::RegisterSpec for REG3_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [reg3::R](R) reader structure"]
123impl crate::Readable for REG3_SPEC {
124    type Reader = R;
125}
126#[doc = "`write(|w| ..)` method takes [reg3::W](W) writer structure"]
127impl crate::Writable for REG3_SPEC {
128    type Writer = W;
129}
130#[doc = "`reset()` method sets REG3 to value 0"]
131impl crate::Resettable for REG3_SPEC {
132    #[inline(always)]
133    fn reset_value() -> Self::Ux {
134        0
135    }
136}
max3263x/pwrseq/reg3.rs

max3263x/pwrseq/
reg3.rs
