1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Port P0 Default (Power-On Reset) Output Drive Mode"]
5 pub rst_mode_p0: crate::Reg<rst_mode_p0::RST_MODE_P0_SPEC>,
6 #[doc = "0x04 - Port P1 Default (Power-On Reset) Output Drive Mode"]
7 pub rst_mode_p1: crate::Reg<rst_mode_p1::RST_MODE_P1_SPEC>,
8 #[doc = "0x08 - Port P2 Default (Power-On Reset) Output Drive Mode"]
9 pub rst_mode_p2: crate::Reg<rst_mode_p2::RST_MODE_P2_SPEC>,
10 #[doc = "0x0c - Port P3 Default (Power-On Reset) Output Drive Mode"]
11 pub rst_mode_p3: crate::Reg<rst_mode_p3::RST_MODE_P3_SPEC>,
12 #[doc = "0x10 - Port P4 Default (Power-On Reset) Output Drive Mode"]
13 pub rst_mode_p4: crate::Reg<rst_mode_p4::RST_MODE_P4_SPEC>,
14 #[doc = "0x14 - Port P5 Default (Power-On Reset) Output Drive Mode"]
15 pub rst_mode_p5: crate::Reg<rst_mode_p5::RST_MODE_P5_SPEC>,
16 #[doc = "0x18 - Port P6 Default (Power-On Reset) Output Drive Mode"]
17 pub rst_mode_p6: crate::Reg<rst_mode_p6::RST_MODE_P6_SPEC>,
18 #[doc = "0x1c - Port P7 Default (Power-On Reset) Output Drive Mode"]
19 pub rst_mode_p7: crate::Reg<rst_mode_p7::RST_MODE_P7_SPEC>,
20 #[doc = "0x20 - Port P8 Default (Power-On Reset) Output Drive Mode"]
21 pub rst_mode_p8: crate::Reg<rst_mode_p8::RST_MODE_P8_SPEC>,
22 _reserved9: [u8; 0x1c],
23 #[doc = "0x40 - Port P0 Free for GPIO Operation Flags"]
24 pub free_p0: crate::Reg<free_p0::FREE_P0_SPEC>,
25 #[doc = "0x44 - Port P1 Free for GPIO Operation Flags"]
26 pub free_p1: crate::Reg<free_p1::FREE_P1_SPEC>,
27 #[doc = "0x48 - Port P2 Free for GPIO Operation Flags"]
28 pub free_p2: crate::Reg<free_p2::FREE_P2_SPEC>,
29 #[doc = "0x4c - Port P3 Free for GPIO Operation Flags"]
30 pub free_p3: crate::Reg<free_p3::FREE_P3_SPEC>,
31 #[doc = "0x50 - Port P4 Free for GPIO Operation Flags"]
32 pub free_p4: crate::Reg<free_p4::FREE_P4_SPEC>,
33 #[doc = "0x54 - Port P5 Free for GPIO Operation Flags"]
34 pub free_p5: crate::Reg<free_p5::FREE_P5_SPEC>,
35 #[doc = "0x58 - Port P6 Free for GPIO Operation Flags"]
36 pub free_p6: crate::Reg<free_p6::FREE_P6_SPEC>,
37 #[doc = "0x5c - Port P7 Free for GPIO Operation Flags"]
38 pub free_p7: crate::Reg<free_p7::FREE_P7_SPEC>,
39 #[doc = "0x60 - Port P8 Free for GPIO Operation Flags"]
40 pub free_p8: crate::Reg<free_p8::FREE_P8_SPEC>,
41 _reserved18: [u8; 0x1c],
42 #[doc = "0x80 - Port P0 GPIO Output Drive Mode"]
43 pub out_mode_p0: crate::Reg<out_mode_p0::OUT_MODE_P0_SPEC>,
44 #[doc = "0x84 - Port P1 GPIO Output Drive Mode"]
45 pub out_mode_p1: crate::Reg<out_mode_p1::OUT_MODE_P1_SPEC>,
46 #[doc = "0x88 - Port P2 GPIO Output Drive Mode"]
47 pub out_mode_p2: crate::Reg<out_mode_p2::OUT_MODE_P2_SPEC>,
48 #[doc = "0x8c - Port P3 GPIO Output Drive Mode"]
49 pub out_mode_p3: crate::Reg<out_mode_p3::OUT_MODE_P3_SPEC>,
50 #[doc = "0x90 - Port P4 GPIO Output Drive Mode"]
51 pub out_mode_p4: crate::Reg<out_mode_p4::OUT_MODE_P4_SPEC>,
52 #[doc = "0x94 - Port P5 GPIO Output Drive Mode"]
53 pub out_mode_p5: crate::Reg<out_mode_p5::OUT_MODE_P5_SPEC>,
54 #[doc = "0x98 - Port P6 GPIO Output Drive Mode"]
55 pub out_mode_p6: crate::Reg<out_mode_p6::OUT_MODE_P6_SPEC>,
56 #[doc = "0x9c - Port P7 GPIO Output Drive Mode"]
57 pub out_mode_p7: crate::Reg<out_mode_p7::OUT_MODE_P7_SPEC>,
58 #[doc = "0xa0 - Port P8 GPIO Output Drive Mode"]
59 pub out_mode_p8: crate::Reg<out_mode_p8::OUT_MODE_P8_SPEC>,
60 _reserved27: [u8; 0x1c],
61 #[doc = "0xc0 - Port P0 GPIO Output Value"]
62 pub out_val_p0: crate::Reg<out_val_p0::OUT_VAL_P0_SPEC>,
63 #[doc = "0xc4 - Port P1 GPIO Output Value"]
64 pub out_val_p1: crate::Reg<out_val_p1::OUT_VAL_P1_SPEC>,
65 #[doc = "0xc8 - Port P2 GPIO Output Value"]
66 pub out_val_p2: crate::Reg<out_val_p2::OUT_VAL_P2_SPEC>,
67 #[doc = "0xcc - Port P3 GPIO Output Value"]
68 pub out_val_p3: crate::Reg<out_val_p3::OUT_VAL_P3_SPEC>,
69 #[doc = "0xd0 - Port P4 GPIO Output Value"]
70 pub out_val_p4: crate::Reg<out_val_p4::OUT_VAL_P4_SPEC>,
71 #[doc = "0xd4 - Port P5 GPIO Output Value"]
72 pub out_val_p5: crate::Reg<out_val_p5::OUT_VAL_P5_SPEC>,
73 #[doc = "0xd8 - Port P6 GPIO Output Value"]
74 pub out_val_p6: crate::Reg<out_val_p6::OUT_VAL_P6_SPEC>,
75 #[doc = "0xdc - Port P7 GPIO Output Value"]
76 pub out_val_p7: crate::Reg<out_val_p7::OUT_VAL_P7_SPEC>,
77 #[doc = "0xe0 - Port P8 GPIO Output Value"]
78 pub out_val_p8: crate::Reg<out_val_p8::OUT_VAL_P8_SPEC>,
79 _reserved36: [u8; 0x1c],
80 #[doc = "0x100 - Port P0 GPIO Function Select"]
81 pub func_sel_p0: crate::Reg<func_sel_p0::FUNC_SEL_P0_SPEC>,
82 #[doc = "0x104 - Port P1 GPIO Function Select"]
83 pub func_sel_p1: crate::Reg<func_sel_p1::FUNC_SEL_P1_SPEC>,
84 #[doc = "0x108 - Port P2 GPIO Function Select"]
85 pub func_sel_p2: crate::Reg<func_sel_p2::FUNC_SEL_P2_SPEC>,
86 #[doc = "0x10c - Port P3 GPIO Function Select"]
87 pub func_sel_p3: crate::Reg<func_sel_p3::FUNC_SEL_P3_SPEC>,
88 #[doc = "0x110 - Port P4 GPIO Function Select"]
89 pub func_sel_p4: crate::Reg<func_sel_p4::FUNC_SEL_P4_SPEC>,
90 #[doc = "0x114 - Port P5 GPIO Function Select"]
91 pub func_sel_p5: crate::Reg<func_sel_p5::FUNC_SEL_P5_SPEC>,
92 #[doc = "0x118 - Port P6 GPIO Function Select"]
93 pub func_sel_p6: crate::Reg<func_sel_p6::FUNC_SEL_P6_SPEC>,
94 #[doc = "0x11c - Port P7 GPIO Function Select"]
95 pub func_sel_p7: crate::Reg<func_sel_p7::FUNC_SEL_P7_SPEC>,
96 #[doc = "0x120 - Port P8 GPIO Function Select"]
97 pub func_sel_p8: crate::Reg<func_sel_p8::FUNC_SEL_P8_SPEC>,
98 _reserved45: [u8; 0x1c],
99 #[doc = "0x140 - Port P0 GPIO Input Monitoring Mode"]
100 pub in_mode_p0: crate::Reg<in_mode_p0::IN_MODE_P0_SPEC>,
101 #[doc = "0x144 - Port P1 GPIO Input Monitoring Mode"]
102 pub in_mode_p1: crate::Reg<in_mode_p1::IN_MODE_P1_SPEC>,
103 #[doc = "0x148 - Port P2 GPIO Input Monitoring Mode"]
104 pub in_mode_p2: crate::Reg<in_mode_p2::IN_MODE_P2_SPEC>,
105 #[doc = "0x14c - Port P3 GPIO Input Monitoring Mode"]
106 pub in_mode_p3: crate::Reg<in_mode_p3::IN_MODE_P3_SPEC>,
107 #[doc = "0x150 - Port P4 GPIO Input Monitoring Mode"]
108 pub in_mode_p4: crate::Reg<in_mode_p4::IN_MODE_P4_SPEC>,
109 #[doc = "0x154 - Port P5 GPIO Input Monitoring Mode"]
110 pub in_mode_p5: crate::Reg<in_mode_p5::IN_MODE_P5_SPEC>,
111 #[doc = "0x158 - Port P6 GPIO Input Monitoring Mode"]
112 pub in_mode_p6: crate::Reg<in_mode_p6::IN_MODE_P6_SPEC>,
113 #[doc = "0x15c - Port P7 GPIO Input Monitoring Mode"]
114 pub in_mode_p7: crate::Reg<in_mode_p7::IN_MODE_P7_SPEC>,
115 #[doc = "0x160 - Port P8 GPIO Input Monitoring Mode"]
116 pub in_mode_p8: crate::Reg<in_mode_p8::IN_MODE_P8_SPEC>,
117 _reserved54: [u8; 0x1c],
118 #[doc = "0x180 - Port P0 GPIO Input Value"]
119 pub in_val_p0: crate::Reg<in_val_p0::IN_VAL_P0_SPEC>,
120 #[doc = "0x184 - Port P1 GPIO Input Value"]
121 pub in_val_p1: crate::Reg<in_val_p1::IN_VAL_P1_SPEC>,
122 #[doc = "0x188 - Port P2 GPIO Input Value"]
123 pub in_val_p2: crate::Reg<in_val_p2::IN_VAL_P2_SPEC>,
124 #[doc = "0x18c - Port P3 GPIO Input Value"]
125 pub in_val_p3: crate::Reg<in_val_p3::IN_VAL_P3_SPEC>,
126 #[doc = "0x190 - Port P4 GPIO Input Value"]
127 pub in_val_p4: crate::Reg<in_val_p4::IN_VAL_P4_SPEC>,
128 #[doc = "0x194 - Port P5 GPIO Input Value"]
129 pub in_val_p5: crate::Reg<in_val_p5::IN_VAL_P5_SPEC>,
130 #[doc = "0x198 - Port P6 GPIO Input Value"]
131 pub in_val_p6: crate::Reg<in_val_p6::IN_VAL_P6_SPEC>,
132 #[doc = "0x19c - Port P7 GPIO Input Value"]
133 pub in_val_p7: crate::Reg<in_val_p7::IN_VAL_P7_SPEC>,
134 #[doc = "0x1a0 - Port P8 GPIO Input Value"]
135 pub in_val_p8: crate::Reg<in_val_p8::IN_VAL_P8_SPEC>,
136 _reserved63: [u8; 0x1c],
137 #[doc = "0x1c0 - Port P0 Interrupt Detection Mode"]
138 pub int_mode_p0: crate::Reg<int_mode_p0::INT_MODE_P0_SPEC>,
139 #[doc = "0x1c4 - Port P1 Interrupt Detection Mode"]
140 pub int_mode_p1: crate::Reg<int_mode_p1::INT_MODE_P1_SPEC>,
141 #[doc = "0x1c8 - Port P2 Interrupt Detection Mode"]
142 pub int_mode_p2: crate::Reg<int_mode_p2::INT_MODE_P2_SPEC>,
143 #[doc = "0x1cc - Port P3 Interrupt Detection Mode"]
144 pub int_mode_p3: crate::Reg<int_mode_p3::INT_MODE_P3_SPEC>,
145 #[doc = "0x1d0 - Port P4 Interrupt Detection Mode"]
146 pub int_mode_p4: crate::Reg<int_mode_p4::INT_MODE_P4_SPEC>,
147 #[doc = "0x1d4 - Port P5 Interrupt Detection Mode"]
148 pub int_mode_p5: crate::Reg<int_mode_p5::INT_MODE_P5_SPEC>,
149 #[doc = "0x1d8 - Port P6 Interrupt Detection Mode"]
150 pub int_mode_p6: crate::Reg<int_mode_p6::INT_MODE_P6_SPEC>,
151 #[doc = "0x1dc - Port P7 Interrupt Detection Mode"]
152 pub int_mode_p7: crate::Reg<int_mode_p7::INT_MODE_P7_SPEC>,
153 #[doc = "0x1e0 - Port P8 Interrupt Detection Mode"]
154 pub int_mode_p8: crate::Reg<int_mode_p8::INT_MODE_P8_SPEC>,
155 _reserved72: [u8; 0x1c],
156 #[doc = "0x200 - Port P0 Interrupt Flags"]
157 pub intfl_p0: crate::Reg<intfl_p0::INTFL_P0_SPEC>,
158 #[doc = "0x204 - Port P1 Interrupt Flags"]
159 pub intfl_p1: crate::Reg<intfl_p1::INTFL_P1_SPEC>,
160 #[doc = "0x208 - Port P2 Interrupt Flags"]
161 pub intfl_p2: crate::Reg<intfl_p2::INTFL_P2_SPEC>,
162 #[doc = "0x20c - Port P3 Interrupt Flags"]
163 pub intfl_p3: crate::Reg<intfl_p3::INTFL_P3_SPEC>,
164 #[doc = "0x210 - Port P4 Interrupt Flags"]
165 pub intfl_p4: crate::Reg<intfl_p4::INTFL_P4_SPEC>,
166 #[doc = "0x214 - Port P5 Interrupt Flags"]
167 pub intfl_p5: crate::Reg<intfl_p5::INTFL_P5_SPEC>,
168 #[doc = "0x218 - Port P6 Interrupt Flags"]
169 pub intfl_p6: crate::Reg<intfl_p6::INTFL_P6_SPEC>,
170 #[doc = "0x21c - Port P7 Interrupt Flags"]
171 pub intfl_p7: crate::Reg<intfl_p7::INTFL_P7_SPEC>,
172 #[doc = "0x220 - Port P8 Interrupt Flags"]
173 pub intfl_p8: crate::Reg<intfl_p8::INTFL_P8_SPEC>,
174 _reserved81: [u8; 0x1c],
175 #[doc = "0x240 - Port P0 Interrupt Enables"]
176 pub inten_p0: crate::Reg<inten_p0::INTEN_P0_SPEC>,
177 #[doc = "0x244 - Port P1 Interrupt Enables"]
178 pub inten_p1: crate::Reg<inten_p1::INTEN_P1_SPEC>,
179 #[doc = "0x248 - Port P2 Interrupt Enables"]
180 pub inten_p2: crate::Reg<inten_p2::INTEN_P2_SPEC>,
181 #[doc = "0x24c - Port P3 Interrupt Enables"]
182 pub inten_p3: crate::Reg<inten_p3::INTEN_P3_SPEC>,
183 #[doc = "0x250 - Port P4 Interrupt Enables"]
184 pub inten_p4: crate::Reg<inten_p4::INTEN_P4_SPEC>,
185 #[doc = "0x254 - Port P5 Interrupt Enables"]
186 pub inten_p5: crate::Reg<inten_p5::INTEN_P5_SPEC>,
187 #[doc = "0x258 - Port P6 Interrupt Enables"]
188 pub inten_p6: crate::Reg<inten_p6::INTEN_P6_SPEC>,
189 #[doc = "0x25c - Port P7 Interrupt Enables"]
190 pub inten_p7: crate::Reg<inten_p7::INTEN_P7_SPEC>,
191 #[doc = "0x260 - Port P8 Interrupt Enables"]
192 pub inten_p8: crate::Reg<inten_p8::INTEN_P8_SPEC>,
193}
194#[doc = "RST_MODE_P0 register accessor: an alias for `Reg<RST_MODE_P0_SPEC>`"]
195pub type RST_MODE_P0 = crate::Reg<rst_mode_p0::RST_MODE_P0_SPEC>;
196#[doc = "Port P0 Default (Power-On Reset) Output Drive Mode"]
197pub mod rst_mode_p0;
198#[doc = "RST_MODE_P1 register accessor: an alias for `Reg<RST_MODE_P1_SPEC>`"]
199pub type RST_MODE_P1 = crate::Reg<rst_mode_p1::RST_MODE_P1_SPEC>;
200#[doc = "Port P1 Default (Power-On Reset) Output Drive Mode"]
201pub mod rst_mode_p1;
202#[doc = "RST_MODE_P2 register accessor: an alias for `Reg<RST_MODE_P2_SPEC>`"]
203pub type RST_MODE_P2 = crate::Reg<rst_mode_p2::RST_MODE_P2_SPEC>;
204#[doc = "Port P2 Default (Power-On Reset) Output Drive Mode"]
205pub mod rst_mode_p2;
206#[doc = "RST_MODE_P3 register accessor: an alias for `Reg<RST_MODE_P3_SPEC>`"]
207pub type RST_MODE_P3 = crate::Reg<rst_mode_p3::RST_MODE_P3_SPEC>;
208#[doc = "Port P3 Default (Power-On Reset) Output Drive Mode"]
209pub mod rst_mode_p3;
210#[doc = "RST_MODE_P4 register accessor: an alias for `Reg<RST_MODE_P4_SPEC>`"]
211pub type RST_MODE_P4 = crate::Reg<rst_mode_p4::RST_MODE_P4_SPEC>;
212#[doc = "Port P4 Default (Power-On Reset) Output Drive Mode"]
213pub mod rst_mode_p4;
214#[doc = "RST_MODE_P5 register accessor: an alias for `Reg<RST_MODE_P5_SPEC>`"]
215pub type RST_MODE_P5 = crate::Reg<rst_mode_p5::RST_MODE_P5_SPEC>;
216#[doc = "Port P5 Default (Power-On Reset) Output Drive Mode"]
217pub mod rst_mode_p5;
218#[doc = "RST_MODE_P6 register accessor: an alias for `Reg<RST_MODE_P6_SPEC>`"]
219pub type RST_MODE_P6 = crate::Reg<rst_mode_p6::RST_MODE_P6_SPEC>;
220#[doc = "Port P6 Default (Power-On Reset) Output Drive Mode"]
221pub mod rst_mode_p6;
222#[doc = "RST_MODE_P7 register accessor: an alias for `Reg<RST_MODE_P7_SPEC>`"]
223pub type RST_MODE_P7 = crate::Reg<rst_mode_p7::RST_MODE_P7_SPEC>;
224#[doc = "Port P7 Default (Power-On Reset) Output Drive Mode"]
225pub mod rst_mode_p7;
226#[doc = "RST_MODE_P8 register accessor: an alias for `Reg<RST_MODE_P8_SPEC>`"]
227pub type RST_MODE_P8 = crate::Reg<rst_mode_p8::RST_MODE_P8_SPEC>;
228#[doc = "Port P8 Default (Power-On Reset) Output Drive Mode"]
229pub mod rst_mode_p8;
230#[doc = "FREE_P0 register accessor: an alias for `Reg<FREE_P0_SPEC>`"]
231pub type FREE_P0 = crate::Reg<free_p0::FREE_P0_SPEC>;
232#[doc = "Port P0 Free for GPIO Operation Flags"]
233pub mod free_p0;
234#[doc = "FREE_P1 register accessor: an alias for `Reg<FREE_P1_SPEC>`"]
235pub type FREE_P1 = crate::Reg<free_p1::FREE_P1_SPEC>;
236#[doc = "Port P1 Free for GPIO Operation Flags"]
237pub mod free_p1;
238#[doc = "FREE_P2 register accessor: an alias for `Reg<FREE_P2_SPEC>`"]
239pub type FREE_P2 = crate::Reg<free_p2::FREE_P2_SPEC>;
240#[doc = "Port P2 Free for GPIO Operation Flags"]
241pub mod free_p2;
242#[doc = "FREE_P3 register accessor: an alias for `Reg<FREE_P3_SPEC>`"]
243pub type FREE_P3 = crate::Reg<free_p3::FREE_P3_SPEC>;
244#[doc = "Port P3 Free for GPIO Operation Flags"]
245pub mod free_p3;
246#[doc = "FREE_P4 register accessor: an alias for `Reg<FREE_P4_SPEC>`"]
247pub type FREE_P4 = crate::Reg<free_p4::FREE_P4_SPEC>;
248#[doc = "Port P4 Free for GPIO Operation Flags"]
249pub mod free_p4;
250#[doc = "FREE_P5 register accessor: an alias for `Reg<FREE_P5_SPEC>`"]
251pub type FREE_P5 = crate::Reg<free_p5::FREE_P5_SPEC>;
252#[doc = "Port P5 Free for GPIO Operation Flags"]
253pub mod free_p5;
254#[doc = "FREE_P6 register accessor: an alias for `Reg<FREE_P6_SPEC>`"]
255pub type FREE_P6 = crate::Reg<free_p6::FREE_P6_SPEC>;
256#[doc = "Port P6 Free for GPIO Operation Flags"]
257pub mod free_p6;
258#[doc = "FREE_P7 register accessor: an alias for `Reg<FREE_P7_SPEC>`"]
259pub type FREE_P7 = crate::Reg<free_p7::FREE_P7_SPEC>;
260#[doc = "Port P7 Free for GPIO Operation Flags"]
261pub mod free_p7;
262#[doc = "FREE_P8 register accessor: an alias for `Reg<FREE_P8_SPEC>`"]
263pub type FREE_P8 = crate::Reg<free_p8::FREE_P8_SPEC>;
264#[doc = "Port P8 Free for GPIO Operation Flags"]
265pub mod free_p8;
266#[doc = "OUT_MODE_P0 register accessor: an alias for `Reg<OUT_MODE_P0_SPEC>`"]
267pub type OUT_MODE_P0 = crate::Reg<out_mode_p0::OUT_MODE_P0_SPEC>;
268#[doc = "Port P0 GPIO Output Drive Mode"]
269pub mod out_mode_p0;
270#[doc = "OUT_MODE_P1 register accessor: an alias for `Reg<OUT_MODE_P1_SPEC>`"]
271pub type OUT_MODE_P1 = crate::Reg<out_mode_p1::OUT_MODE_P1_SPEC>;
272#[doc = "Port P1 GPIO Output Drive Mode"]
273pub mod out_mode_p1;
274#[doc = "OUT_MODE_P2 register accessor: an alias for `Reg<OUT_MODE_P2_SPEC>`"]
275pub type OUT_MODE_P2 = crate::Reg<out_mode_p2::OUT_MODE_P2_SPEC>;
276#[doc = "Port P2 GPIO Output Drive Mode"]
277pub mod out_mode_p2;
278#[doc = "OUT_MODE_P3 register accessor: an alias for `Reg<OUT_MODE_P3_SPEC>`"]
279pub type OUT_MODE_P3 = crate::Reg<out_mode_p3::OUT_MODE_P3_SPEC>;
280#[doc = "Port P3 GPIO Output Drive Mode"]
281pub mod out_mode_p3;
282#[doc = "OUT_MODE_P4 register accessor: an alias for `Reg<OUT_MODE_P4_SPEC>`"]
283pub type OUT_MODE_P4 = crate::Reg<out_mode_p4::OUT_MODE_P4_SPEC>;
284#[doc = "Port P4 GPIO Output Drive Mode"]
285pub mod out_mode_p4;
286#[doc = "OUT_MODE_P5 register accessor: an alias for `Reg<OUT_MODE_P5_SPEC>`"]
287pub type OUT_MODE_P5 = crate::Reg<out_mode_p5::OUT_MODE_P5_SPEC>;
288#[doc = "Port P5 GPIO Output Drive Mode"]
289pub mod out_mode_p5;
290#[doc = "OUT_MODE_P6 register accessor: an alias for `Reg<OUT_MODE_P6_SPEC>`"]
291pub type OUT_MODE_P6 = crate::Reg<out_mode_p6::OUT_MODE_P6_SPEC>;
292#[doc = "Port P6 GPIO Output Drive Mode"]
293pub mod out_mode_p6;
294#[doc = "OUT_MODE_P7 register accessor: an alias for `Reg<OUT_MODE_P7_SPEC>`"]
295pub type OUT_MODE_P7 = crate::Reg<out_mode_p7::OUT_MODE_P7_SPEC>;
296#[doc = "Port P7 GPIO Output Drive Mode"]
297pub mod out_mode_p7;
298#[doc = "OUT_MODE_P8 register accessor: an alias for `Reg<OUT_MODE_P8_SPEC>`"]
299pub type OUT_MODE_P8 = crate::Reg<out_mode_p8::OUT_MODE_P8_SPEC>;
300#[doc = "Port P8 GPIO Output Drive Mode"]
301pub mod out_mode_p8;
302#[doc = "OUT_VAL_P0 register accessor: an alias for `Reg<OUT_VAL_P0_SPEC>`"]
303pub type OUT_VAL_P0 = crate::Reg<out_val_p0::OUT_VAL_P0_SPEC>;
304#[doc = "Port P0 GPIO Output Value"]
305pub mod out_val_p0;
306#[doc = "OUT_VAL_P1 register accessor: an alias for `Reg<OUT_VAL_P1_SPEC>`"]
307pub type OUT_VAL_P1 = crate::Reg<out_val_p1::OUT_VAL_P1_SPEC>;
308#[doc = "Port P1 GPIO Output Value"]
309pub mod out_val_p1;
310#[doc = "OUT_VAL_P2 register accessor: an alias for `Reg<OUT_VAL_P2_SPEC>`"]
311pub type OUT_VAL_P2 = crate::Reg<out_val_p2::OUT_VAL_P2_SPEC>;
312#[doc = "Port P2 GPIO Output Value"]
313pub mod out_val_p2;
314#[doc = "OUT_VAL_P3 register accessor: an alias for `Reg<OUT_VAL_P3_SPEC>`"]
315pub type OUT_VAL_P3 = crate::Reg<out_val_p3::OUT_VAL_P3_SPEC>;
316#[doc = "Port P3 GPIO Output Value"]
317pub mod out_val_p3;
318#[doc = "OUT_VAL_P4 register accessor: an alias for `Reg<OUT_VAL_P4_SPEC>`"]
319pub type OUT_VAL_P4 = crate::Reg<out_val_p4::OUT_VAL_P4_SPEC>;
320#[doc = "Port P4 GPIO Output Value"]
321pub mod out_val_p4;
322#[doc = "OUT_VAL_P5 register accessor: an alias for `Reg<OUT_VAL_P5_SPEC>`"]
323pub type OUT_VAL_P5 = crate::Reg<out_val_p5::OUT_VAL_P5_SPEC>;
324#[doc = "Port P5 GPIO Output Value"]
325pub mod out_val_p5;
326#[doc = "OUT_VAL_P6 register accessor: an alias for `Reg<OUT_VAL_P6_SPEC>`"]
327pub type OUT_VAL_P6 = crate::Reg<out_val_p6::OUT_VAL_P6_SPEC>;
328#[doc = "Port P6 GPIO Output Value"]
329pub mod out_val_p6;
330#[doc = "OUT_VAL_P7 register accessor: an alias for `Reg<OUT_VAL_P7_SPEC>`"]
331pub type OUT_VAL_P7 = crate::Reg<out_val_p7::OUT_VAL_P7_SPEC>;
332#[doc = "Port P7 GPIO Output Value"]
333pub mod out_val_p7;
334#[doc = "OUT_VAL_P8 register accessor: an alias for `Reg<OUT_VAL_P8_SPEC>`"]
335pub type OUT_VAL_P8 = crate::Reg<out_val_p8::OUT_VAL_P8_SPEC>;
336#[doc = "Port P8 GPIO Output Value"]
337pub mod out_val_p8;
338#[doc = "FUNC_SEL_P0 register accessor: an alias for `Reg<FUNC_SEL_P0_SPEC>`"]
339pub type FUNC_SEL_P0 = crate::Reg<func_sel_p0::FUNC_SEL_P0_SPEC>;
340#[doc = "Port P0 GPIO Function Select"]
341pub mod func_sel_p0;
342#[doc = "FUNC_SEL_P1 register accessor: an alias for `Reg<FUNC_SEL_P1_SPEC>`"]
343pub type FUNC_SEL_P1 = crate::Reg<func_sel_p1::FUNC_SEL_P1_SPEC>;
344#[doc = "Port P1 GPIO Function Select"]
345pub mod func_sel_p1;
346#[doc = "FUNC_SEL_P2 register accessor: an alias for `Reg<FUNC_SEL_P2_SPEC>`"]
347pub type FUNC_SEL_P2 = crate::Reg<func_sel_p2::FUNC_SEL_P2_SPEC>;
348#[doc = "Port P2 GPIO Function Select"]
349pub mod func_sel_p2;
350#[doc = "FUNC_SEL_P3 register accessor: an alias for `Reg<FUNC_SEL_P3_SPEC>`"]
351pub type FUNC_SEL_P3 = crate::Reg<func_sel_p3::FUNC_SEL_P3_SPEC>;
352#[doc = "Port P3 GPIO Function Select"]
353pub mod func_sel_p3;
354#[doc = "FUNC_SEL_P4 register accessor: an alias for `Reg<FUNC_SEL_P4_SPEC>`"]
355pub type FUNC_SEL_P4 = crate::Reg<func_sel_p4::FUNC_SEL_P4_SPEC>;
356#[doc = "Port P4 GPIO Function Select"]
357pub mod func_sel_p4;
358#[doc = "FUNC_SEL_P5 register accessor: an alias for `Reg<FUNC_SEL_P5_SPEC>`"]
359pub type FUNC_SEL_P5 = crate::Reg<func_sel_p5::FUNC_SEL_P5_SPEC>;
360#[doc = "Port P5 GPIO Function Select"]
361pub mod func_sel_p5;
362#[doc = "FUNC_SEL_P6 register accessor: an alias for `Reg<FUNC_SEL_P6_SPEC>`"]
363pub type FUNC_SEL_P6 = crate::Reg<func_sel_p6::FUNC_SEL_P6_SPEC>;
364#[doc = "Port P6 GPIO Function Select"]
365pub mod func_sel_p6;
366#[doc = "FUNC_SEL_P7 register accessor: an alias for `Reg<FUNC_SEL_P7_SPEC>`"]
367pub type FUNC_SEL_P7 = crate::Reg<func_sel_p7::FUNC_SEL_P7_SPEC>;
368#[doc = "Port P7 GPIO Function Select"]
369pub mod func_sel_p7;
370#[doc = "FUNC_SEL_P8 register accessor: an alias for `Reg<FUNC_SEL_P8_SPEC>`"]
371pub type FUNC_SEL_P8 = crate::Reg<func_sel_p8::FUNC_SEL_P8_SPEC>;
372#[doc = "Port P8 GPIO Function Select"]
373pub mod func_sel_p8;
374#[doc = "IN_MODE_P0 register accessor: an alias for `Reg<IN_MODE_P0_SPEC>`"]
375pub type IN_MODE_P0 = crate::Reg<in_mode_p0::IN_MODE_P0_SPEC>;
376#[doc = "Port P0 GPIO Input Monitoring Mode"]
377pub mod in_mode_p0;
378#[doc = "IN_MODE_P1 register accessor: an alias for `Reg<IN_MODE_P1_SPEC>`"]
379pub type IN_MODE_P1 = crate::Reg<in_mode_p1::IN_MODE_P1_SPEC>;
380#[doc = "Port P1 GPIO Input Monitoring Mode"]
381pub mod in_mode_p1;
382#[doc = "IN_MODE_P2 register accessor: an alias for `Reg<IN_MODE_P2_SPEC>`"]
383pub type IN_MODE_P2 = crate::Reg<in_mode_p2::IN_MODE_P2_SPEC>;
384#[doc = "Port P2 GPIO Input Monitoring Mode"]
385pub mod in_mode_p2;
386#[doc = "IN_MODE_P3 register accessor: an alias for `Reg<IN_MODE_P3_SPEC>`"]
387pub type IN_MODE_P3 = crate::Reg<in_mode_p3::IN_MODE_P3_SPEC>;
388#[doc = "Port P3 GPIO Input Monitoring Mode"]
389pub mod in_mode_p3;
390#[doc = "IN_MODE_P4 register accessor: an alias for `Reg<IN_MODE_P4_SPEC>`"]
391pub type IN_MODE_P4 = crate::Reg<in_mode_p4::IN_MODE_P4_SPEC>;
392#[doc = "Port P4 GPIO Input Monitoring Mode"]
393pub mod in_mode_p4;
394#[doc = "IN_MODE_P5 register accessor: an alias for `Reg<IN_MODE_P5_SPEC>`"]
395pub type IN_MODE_P5 = crate::Reg<in_mode_p5::IN_MODE_P5_SPEC>;
396#[doc = "Port P5 GPIO Input Monitoring Mode"]
397pub mod in_mode_p5;
398#[doc = "IN_MODE_P6 register accessor: an alias for `Reg<IN_MODE_P6_SPEC>`"]
399pub type IN_MODE_P6 = crate::Reg<in_mode_p6::IN_MODE_P6_SPEC>;
400#[doc = "Port P6 GPIO Input Monitoring Mode"]
401pub mod in_mode_p6;
402#[doc = "IN_MODE_P7 register accessor: an alias for `Reg<IN_MODE_P7_SPEC>`"]
403pub type IN_MODE_P7 = crate::Reg<in_mode_p7::IN_MODE_P7_SPEC>;
404#[doc = "Port P7 GPIO Input Monitoring Mode"]
405pub mod in_mode_p7;
406#[doc = "IN_MODE_P8 register accessor: an alias for `Reg<IN_MODE_P8_SPEC>`"]
407pub type IN_MODE_P8 = crate::Reg<in_mode_p8::IN_MODE_P8_SPEC>;
408#[doc = "Port P8 GPIO Input Monitoring Mode"]
409pub mod in_mode_p8;
410#[doc = "IN_VAL_P0 register accessor: an alias for `Reg<IN_VAL_P0_SPEC>`"]
411pub type IN_VAL_P0 = crate::Reg<in_val_p0::IN_VAL_P0_SPEC>;
412#[doc = "Port P0 GPIO Input Value"]
413pub mod in_val_p0;
414#[doc = "IN_VAL_P1 register accessor: an alias for `Reg<IN_VAL_P1_SPEC>`"]
415pub type IN_VAL_P1 = crate::Reg<in_val_p1::IN_VAL_P1_SPEC>;
416#[doc = "Port P1 GPIO Input Value"]
417pub mod in_val_p1;
418#[doc = "IN_VAL_P2 register accessor: an alias for `Reg<IN_VAL_P2_SPEC>`"]
419pub type IN_VAL_P2 = crate::Reg<in_val_p2::IN_VAL_P2_SPEC>;
420#[doc = "Port P2 GPIO Input Value"]
421pub mod in_val_p2;
422#[doc = "IN_VAL_P3 register accessor: an alias for `Reg<IN_VAL_P3_SPEC>`"]
423pub type IN_VAL_P3 = crate::Reg<in_val_p3::IN_VAL_P3_SPEC>;
424#[doc = "Port P3 GPIO Input Value"]
425pub mod in_val_p3;
426#[doc = "IN_VAL_P4 register accessor: an alias for `Reg<IN_VAL_P4_SPEC>`"]
427pub type IN_VAL_P4 = crate::Reg<in_val_p4::IN_VAL_P4_SPEC>;
428#[doc = "Port P4 GPIO Input Value"]
429pub mod in_val_p4;
430#[doc = "IN_VAL_P5 register accessor: an alias for `Reg<IN_VAL_P5_SPEC>`"]
431pub type IN_VAL_P5 = crate::Reg<in_val_p5::IN_VAL_P5_SPEC>;
432#[doc = "Port P5 GPIO Input Value"]
433pub mod in_val_p5;
434#[doc = "IN_VAL_P6 register accessor: an alias for `Reg<IN_VAL_P6_SPEC>`"]
435pub type IN_VAL_P6 = crate::Reg<in_val_p6::IN_VAL_P6_SPEC>;
436#[doc = "Port P6 GPIO Input Value"]
437pub mod in_val_p6;
438#[doc = "IN_VAL_P7 register accessor: an alias for `Reg<IN_VAL_P7_SPEC>`"]
439pub type IN_VAL_P7 = crate::Reg<in_val_p7::IN_VAL_P7_SPEC>;
440#[doc = "Port P7 GPIO Input Value"]
441pub mod in_val_p7;
442#[doc = "IN_VAL_P8 register accessor: an alias for `Reg<IN_VAL_P8_SPEC>`"]
443pub type IN_VAL_P8 = crate::Reg<in_val_p8::IN_VAL_P8_SPEC>;
444#[doc = "Port P8 GPIO Input Value"]
445pub mod in_val_p8;
446#[doc = "INT_MODE_P0 register accessor: an alias for `Reg<INT_MODE_P0_SPEC>`"]
447pub type INT_MODE_P0 = crate::Reg<int_mode_p0::INT_MODE_P0_SPEC>;
448#[doc = "Port P0 Interrupt Detection Mode"]
449pub mod int_mode_p0;
450#[doc = "INT_MODE_P1 register accessor: an alias for `Reg<INT_MODE_P1_SPEC>`"]
451pub type INT_MODE_P1 = crate::Reg<int_mode_p1::INT_MODE_P1_SPEC>;
452#[doc = "Port P1 Interrupt Detection Mode"]
453pub mod int_mode_p1;
454#[doc = "INT_MODE_P2 register accessor: an alias for `Reg<INT_MODE_P2_SPEC>`"]
455pub type INT_MODE_P2 = crate::Reg<int_mode_p2::INT_MODE_P2_SPEC>;
456#[doc = "Port P2 Interrupt Detection Mode"]
457pub mod int_mode_p2;
458#[doc = "INT_MODE_P3 register accessor: an alias for `Reg<INT_MODE_P3_SPEC>`"]
459pub type INT_MODE_P3 = crate::Reg<int_mode_p3::INT_MODE_P3_SPEC>;
460#[doc = "Port P3 Interrupt Detection Mode"]
461pub mod int_mode_p3;
462#[doc = "INT_MODE_P4 register accessor: an alias for `Reg<INT_MODE_P4_SPEC>`"]
463pub type INT_MODE_P4 = crate::Reg<int_mode_p4::INT_MODE_P4_SPEC>;
464#[doc = "Port P4 Interrupt Detection Mode"]
465pub mod int_mode_p4;
466#[doc = "INT_MODE_P5 register accessor: an alias for `Reg<INT_MODE_P5_SPEC>`"]
467pub type INT_MODE_P5 = crate::Reg<int_mode_p5::INT_MODE_P5_SPEC>;
468#[doc = "Port P5 Interrupt Detection Mode"]
469pub mod int_mode_p5;
470#[doc = "INT_MODE_P6 register accessor: an alias for `Reg<INT_MODE_P6_SPEC>`"]
471pub type INT_MODE_P6 = crate::Reg<int_mode_p6::INT_MODE_P6_SPEC>;
472#[doc = "Port P6 Interrupt Detection Mode"]
473pub mod int_mode_p6;
474#[doc = "INT_MODE_P7 register accessor: an alias for `Reg<INT_MODE_P7_SPEC>`"]
475pub type INT_MODE_P7 = crate::Reg<int_mode_p7::INT_MODE_P7_SPEC>;
476#[doc = "Port P7 Interrupt Detection Mode"]
477pub mod int_mode_p7;
478#[doc = "INT_MODE_P8 register accessor: an alias for `Reg<INT_MODE_P8_SPEC>`"]
479pub type INT_MODE_P8 = crate::Reg<int_mode_p8::INT_MODE_P8_SPEC>;
480#[doc = "Port P8 Interrupt Detection Mode"]
481pub mod int_mode_p8;
482#[doc = "INTFL_P0 register accessor: an alias for `Reg<INTFL_P0_SPEC>`"]
483pub type INTFL_P0 = crate::Reg<intfl_p0::INTFL_P0_SPEC>;
484#[doc = "Port P0 Interrupt Flags"]
485pub mod intfl_p0;
486#[doc = "INTFL_P1 register accessor: an alias for `Reg<INTFL_P1_SPEC>`"]
487pub type INTFL_P1 = crate::Reg<intfl_p1::INTFL_P1_SPEC>;
488#[doc = "Port P1 Interrupt Flags"]
489pub mod intfl_p1;
490#[doc = "INTFL_P2 register accessor: an alias for `Reg<INTFL_P2_SPEC>`"]
491pub type INTFL_P2 = crate::Reg<intfl_p2::INTFL_P2_SPEC>;
492#[doc = "Port P2 Interrupt Flags"]
493pub mod intfl_p2;
494#[doc = "INTFL_P3 register accessor: an alias for `Reg<INTFL_P3_SPEC>`"]
495pub type INTFL_P3 = crate::Reg<intfl_p3::INTFL_P3_SPEC>;
496#[doc = "Port P3 Interrupt Flags"]
497pub mod intfl_p3;
498#[doc = "INTFL_P4 register accessor: an alias for `Reg<INTFL_P4_SPEC>`"]
499pub type INTFL_P4 = crate::Reg<intfl_p4::INTFL_P4_SPEC>;
500#[doc = "Port P4 Interrupt Flags"]
501pub mod intfl_p4;
502#[doc = "INTFL_P5 register accessor: an alias for `Reg<INTFL_P5_SPEC>`"]
503pub type INTFL_P5 = crate::Reg<intfl_p5::INTFL_P5_SPEC>;
504#[doc = "Port P5 Interrupt Flags"]
505pub mod intfl_p5;
506#[doc = "INTFL_P6 register accessor: an alias for `Reg<INTFL_P6_SPEC>`"]
507pub type INTFL_P6 = crate::Reg<intfl_p6::INTFL_P6_SPEC>;
508#[doc = "Port P6 Interrupt Flags"]
509pub mod intfl_p6;
510#[doc = "INTFL_P7 register accessor: an alias for `Reg<INTFL_P7_SPEC>`"]
511pub type INTFL_P7 = crate::Reg<intfl_p7::INTFL_P7_SPEC>;
512#[doc = "Port P7 Interrupt Flags"]
513pub mod intfl_p7;
514#[doc = "INTFL_P8 register accessor: an alias for `Reg<INTFL_P8_SPEC>`"]
515pub type INTFL_P8 = crate::Reg<intfl_p8::INTFL_P8_SPEC>;
516#[doc = "Port P8 Interrupt Flags"]
517pub mod intfl_p8;
518#[doc = "INTEN_P0 register accessor: an alias for `Reg<INTEN_P0_SPEC>`"]
519pub type INTEN_P0 = crate::Reg<inten_p0::INTEN_P0_SPEC>;
520#[doc = "Port P0 Interrupt Enables"]
521pub mod inten_p0;
522#[doc = "INTEN_P1 register accessor: an alias for `Reg<INTEN_P1_SPEC>`"]
523pub type INTEN_P1 = crate::Reg<inten_p1::INTEN_P1_SPEC>;
524#[doc = "Port P1 Interrupt Enables"]
525pub mod inten_p1;
526#[doc = "INTEN_P2 register accessor: an alias for `Reg<INTEN_P2_SPEC>`"]
527pub type INTEN_P2 = crate::Reg<inten_p2::INTEN_P2_SPEC>;
528#[doc = "Port P2 Interrupt Enables"]
529pub mod inten_p2;
530#[doc = "INTEN_P3 register accessor: an alias for `Reg<INTEN_P3_SPEC>`"]
531pub type INTEN_P3 = crate::Reg<inten_p3::INTEN_P3_SPEC>;
532#[doc = "Port P3 Interrupt Enables"]
533pub mod inten_p3;
534#[doc = "INTEN_P4 register accessor: an alias for `Reg<INTEN_P4_SPEC>`"]
535pub type INTEN_P4 = crate::Reg<inten_p4::INTEN_P4_SPEC>;
536#[doc = "Port P4 Interrupt Enables"]
537pub mod inten_p4;
538#[doc = "INTEN_P5 register accessor: an alias for `Reg<INTEN_P5_SPEC>`"]
539pub type INTEN_P5 = crate::Reg<inten_p5::INTEN_P5_SPEC>;
540#[doc = "Port P5 Interrupt Enables"]
541pub mod inten_p5;
542#[doc = "INTEN_P6 register accessor: an alias for `Reg<INTEN_P6_SPEC>`"]
543pub type INTEN_P6 = crate::Reg<inten_p6::INTEN_P6_SPEC>;
544#[doc = "Port P6 Interrupt Enables"]
545pub mod inten_p6;
546#[doc = "INTEN_P7 register accessor: an alias for `Reg<INTEN_P7_SPEC>`"]
547pub type INTEN_P7 = crate::Reg<inten_p7::INTEN_P7_SPEC>;
548#[doc = "Port P7 Interrupt Enables"]
549pub mod inten_p7;
550#[doc = "INTEN_P8 register accessor: an alias for `Reg<INTEN_P8_SPEC>`"]
551pub type INTEN_P8 = crate::Reg<inten_p8::INTEN_P8_SPEC>;
552#[doc = "Port P8 Interrupt Enables"]
553pub mod inten_p8;