max3263x 0.5.0

svd2rust generated peripheral crate for the max3263x
Documentation 
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#[doc = "Register `REG1` reader"]
pub struct R(crate::R<REG1_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<REG1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<REG1_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<REG1_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `REG1` writer"]
pub struct W(crate::W<REG1_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<REG1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<REG1_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<REG1_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `pwr_clr_io_event_latch` reader - Clear all GPIO Event Seen Latches"]
pub type PWR_CLR_IO_EVENT_LATCH_R = crate::BitReader<bool>;
#[doc = "Field `pwr_clr_io_event_latch` writer - Clear all GPIO Event Seen Latches"]
pub type PWR_CLR_IO_EVENT_LATCH_W<'a> = crate::BitWriter<'a, u32, REG1_SPEC, bool, 0>;
#[doc = "Field `pwr_clr_io_cfg_latch` reader - Clear all GPIO Configuration Latches"]
pub type PWR_CLR_IO_CFG_LATCH_R = crate::BitReader<bool>;
#[doc = "Field `pwr_clr_io_cfg_latch` writer - Clear all GPIO Configuration Latches"]
pub type PWR_CLR_IO_CFG_LATCH_W<'a> = crate::BitWriter<'a, u32, REG1_SPEC, bool, 1>;
#[doc = "Field `pwr_mbus_gate` reader - Freeze GPIO MBus State"]
pub type PWR_MBUS_GATE_R = crate::BitReader<bool>;
#[doc = "Field `pwr_mbus_gate` writer - Freeze GPIO MBus State"]
pub type PWR_MBUS_GATE_W<'a> = crate::BitWriter<'a, u32, REG1_SPEC, bool, 2>;
#[doc = "Field `pwr_discharge_en` reader - Enable Flash Discharge During Powerfail Event"]
pub type PWR_DISCHARGE_EN_R = crate::BitReader<bool>;
#[doc = "Field `pwr_discharge_en` writer - Enable Flash Discharge During Powerfail Event"]
pub type PWR_DISCHARGE_EN_W<'a> = crate::BitWriter<'a, u32, REG1_SPEC, bool, 3>;
#[doc = "Field `pwr_tvdd12_well` reader - TVDD12 Well Switch"]
pub type PWR_TVDD12_WELL_R = crate::BitReader<bool>;
#[doc = "Field `pwr_tvdd12_well` writer - TVDD12 Well Switch"]
pub type PWR_TVDD12_WELL_W<'a> = crate::BitWriter<'a, u32, REG1_SPEC, bool, 4>;
impl R {
    #[doc = "Bit 0 - Clear all GPIO Event Seen Latches"]
    #[inline(always)]
    pub fn pwr_clr_io_event_latch(&self) -> PWR_CLR_IO_EVENT_LATCH_R {
        PWR_CLR_IO_EVENT_LATCH_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Clear all GPIO Configuration Latches"]
    #[inline(always)]
    pub fn pwr_clr_io_cfg_latch(&self) -> PWR_CLR_IO_CFG_LATCH_R {
        PWR_CLR_IO_CFG_LATCH_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Freeze GPIO MBus State"]
    #[inline(always)]
    pub fn pwr_mbus_gate(&self) -> PWR_MBUS_GATE_R {
        PWR_MBUS_GATE_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Enable Flash Discharge During Powerfail Event"]
    #[inline(always)]
    pub fn pwr_discharge_en(&self) -> PWR_DISCHARGE_EN_R {
        PWR_DISCHARGE_EN_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - TVDD12 Well Switch"]
    #[inline(always)]
    pub fn pwr_tvdd12_well(&self) -> PWR_TVDD12_WELL_R {
        PWR_TVDD12_WELL_R::new(((self.bits >> 4) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Clear all GPIO Event Seen Latches"]
    #[inline(always)]
    pub fn pwr_clr_io_event_latch(&mut self) -> PWR_CLR_IO_EVENT_LATCH_W {
        PWR_CLR_IO_EVENT_LATCH_W::new(self)
    }
    #[doc = "Bit 1 - Clear all GPIO Configuration Latches"]
    #[inline(always)]
    pub fn pwr_clr_io_cfg_latch(&mut self) -> PWR_CLR_IO_CFG_LATCH_W {
        PWR_CLR_IO_CFG_LATCH_W::new(self)
    }
    #[doc = "Bit 2 - Freeze GPIO MBus State"]
    #[inline(always)]
    pub fn pwr_mbus_gate(&mut self) -> PWR_MBUS_GATE_W {
        PWR_MBUS_GATE_W::new(self)
    }
    #[doc = "Bit 3 - Enable Flash Discharge During Powerfail Event"]
    #[inline(always)]
    pub fn pwr_discharge_en(&mut self) -> PWR_DISCHARGE_EN_W {
        PWR_DISCHARGE_EN_W::new(self)
    }
    #[doc = "Bit 4 - TVDD12 Well Switch"]
    #[inline(always)]
    pub fn pwr_tvdd12_well(&mut self) -> PWR_TVDD12_WELL_W {
        PWR_TVDD12_WELL_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Power Sequencer Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reg1](index.html) module"]
pub struct REG1_SPEC;
impl crate::RegisterSpec for REG1_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [reg1::R](R) reader structure"]
impl crate::Readable for REG1_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [reg1::W](W) writer structure"]
impl crate::Writable for REG1_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets REG1 to value 0"]
impl crate::Resettable for REG1_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}