1#[doc = "Register `INTEN` reader"]
2pub struct R(crate::R<INTEN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<INTEN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<INTEN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<INTEN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `INTEN` writer"]
17pub struct W(crate::W<INTEN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<INTEN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<INTEN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<INTEN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `tx_done` reader - Transaction Done Int Enable"]
38pub type TX_DONE_R = crate::BitReader<bool>;
39#[doc = "Field `tx_done` writer - Transaction Done Int Enable"]
40pub type TX_DONE_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 0>;
41#[doc = "Field `tx_nacked` reader - Transaction NACKed Int Enable"]
42pub type TX_NACKED_R = crate::BitReader<bool>;
43#[doc = "Field `tx_nacked` writer - Transaction NACKed Int Enable"]
44pub type TX_NACKED_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 1>;
45#[doc = "Field `tx_lost_arbitr` reader - Transaction Lost Arbitration IntEnable"]
46pub type TX_LOST_ARBITR_R = crate::BitReader<bool>;
47#[doc = "Field `tx_lost_arbitr` writer - Transaction Lost Arbitration IntEnable"]
48pub type TX_LOST_ARBITR_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 2>;
49#[doc = "Field `tx_timeout` reader - Transaction Timed Out Int Enable"]
50pub type TX_TIMEOUT_R = crate::BitReader<bool>;
51#[doc = "Field `tx_timeout` writer - Transaction Timed Out Int Enable"]
52pub type TX_TIMEOUT_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 3>;
53#[doc = "Field `tx_fifo_empty` reader - Transaction FIFO Empty Int Enable"]
54pub type TX_FIFO_EMPTY_R = crate::BitReader<bool>;
55#[doc = "Field `tx_fifo_empty` writer - Transaction FIFO Empty Int Enable"]
56pub type TX_FIFO_EMPTY_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 4>;
57#[doc = "Field `tx_fifo_3q_empty` reader - Transaction FIFO 3Q Empty Int Enable"]
58pub type TX_FIFO_3Q_EMPTY_R = crate::BitReader<bool>;
59#[doc = "Field `tx_fifo_3q_empty` writer - Transaction FIFO 3Q Empty Int Enable"]
60pub type TX_FIFO_3Q_EMPTY_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 5>;
61#[doc = "Field `rx_fifo_not_empty` reader - Results FIFO Not Empty Int Enable"]
62pub type RX_FIFO_NOT_EMPTY_R = crate::BitReader<bool>;
63#[doc = "Field `rx_fifo_not_empty` writer - Results FIFO Not Empty Int Enable"]
64pub type RX_FIFO_NOT_EMPTY_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 6>;
65#[doc = "Field `rx_fifo_2q_full` reader - Results FIFO 2Q Full Int Enable"]
66pub type RX_FIFO_2Q_FULL_R = crate::BitReader<bool>;
67#[doc = "Field `rx_fifo_2q_full` writer - Results FIFO 2Q Full Int Enable"]
68pub type RX_FIFO_2Q_FULL_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 7>;
69#[doc = "Field `rx_fifo_3q_full` reader - Results FIFO 3Q Full Int Enable"]
70pub type RX_FIFO_3Q_FULL_R = crate::BitReader<bool>;
71#[doc = "Field `rx_fifo_3q_full` writer - Results FIFO 3Q Full Int Enable"]
72pub type RX_FIFO_3Q_FULL_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 8>;
73#[doc = "Field `rx_fifo_full` reader - Results FIFO Full Int Enable"]
74pub type RX_FIFO_FULL_R = crate::BitReader<bool>;
75#[doc = "Field `rx_fifo_full` writer - Results FIFO Full Int Enable"]
76pub type RX_FIFO_FULL_W<'a> = crate::BitWriter<'a, u32, INTEN_SPEC, bool, 9>;
77impl R {
78 #[doc = "Bit 0 - Transaction Done Int Enable"]
79 #[inline(always)]
80 pub fn tx_done(&self) -> TX_DONE_R {
81 TX_DONE_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Transaction NACKed Int Enable"]
84 #[inline(always)]
85 pub fn tx_nacked(&self) -> TX_NACKED_R {
86 TX_NACKED_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - Transaction Lost Arbitration IntEnable"]
89 #[inline(always)]
90 pub fn tx_lost_arbitr(&self) -> TX_LOST_ARBITR_R {
91 TX_LOST_ARBITR_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - Transaction Timed Out Int Enable"]
94 #[inline(always)]
95 pub fn tx_timeout(&self) -> TX_TIMEOUT_R {
96 TX_TIMEOUT_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - Transaction FIFO Empty Int Enable"]
99 #[inline(always)]
100 pub fn tx_fifo_empty(&self) -> TX_FIFO_EMPTY_R {
101 TX_FIFO_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - Transaction FIFO 3Q Empty Int Enable"]
104 #[inline(always)]
105 pub fn tx_fifo_3q_empty(&self) -> TX_FIFO_3Q_EMPTY_R {
106 TX_FIFO_3Q_EMPTY_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 6 - Results FIFO Not Empty Int Enable"]
109 #[inline(always)]
110 pub fn rx_fifo_not_empty(&self) -> RX_FIFO_NOT_EMPTY_R {
111 RX_FIFO_NOT_EMPTY_R::new(((self.bits >> 6) & 1) != 0)
112 }
113 #[doc = "Bit 7 - Results FIFO 2Q Full Int Enable"]
114 #[inline(always)]
115 pub fn rx_fifo_2q_full(&self) -> RX_FIFO_2Q_FULL_R {
116 RX_FIFO_2Q_FULL_R::new(((self.bits >> 7) & 1) != 0)
117 }
118 #[doc = "Bit 8 - Results FIFO 3Q Full Int Enable"]
119 #[inline(always)]
120 pub fn rx_fifo_3q_full(&self) -> RX_FIFO_3Q_FULL_R {
121 RX_FIFO_3Q_FULL_R::new(((self.bits >> 8) & 1) != 0)
122 }
123 #[doc = "Bit 9 - Results FIFO Full Int Enable"]
124 #[inline(always)]
125 pub fn rx_fifo_full(&self) -> RX_FIFO_FULL_R {
126 RX_FIFO_FULL_R::new(((self.bits >> 9) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Transaction Done Int Enable"]
131 #[inline(always)]
132 pub fn tx_done(&mut self) -> TX_DONE_W {
133 TX_DONE_W::new(self)
134 }
135 #[doc = "Bit 1 - Transaction NACKed Int Enable"]
136 #[inline(always)]
137 pub fn tx_nacked(&mut self) -> TX_NACKED_W {
138 TX_NACKED_W::new(self)
139 }
140 #[doc = "Bit 2 - Transaction Lost Arbitration IntEnable"]
141 #[inline(always)]
142 pub fn tx_lost_arbitr(&mut self) -> TX_LOST_ARBITR_W {
143 TX_LOST_ARBITR_W::new(self)
144 }
145 #[doc = "Bit 3 - Transaction Timed Out Int Enable"]
146 #[inline(always)]
147 pub fn tx_timeout(&mut self) -> TX_TIMEOUT_W {
148 TX_TIMEOUT_W::new(self)
149 }
150 #[doc = "Bit 4 - Transaction FIFO Empty Int Enable"]
151 #[inline(always)]
152 pub fn tx_fifo_empty(&mut self) -> TX_FIFO_EMPTY_W {
153 TX_FIFO_EMPTY_W::new(self)
154 }
155 #[doc = "Bit 5 - Transaction FIFO 3Q Empty Int Enable"]
156 #[inline(always)]
157 pub fn tx_fifo_3q_empty(&mut self) -> TX_FIFO_3Q_EMPTY_W {
158 TX_FIFO_3Q_EMPTY_W::new(self)
159 }
160 #[doc = "Bit 6 - Results FIFO Not Empty Int Enable"]
161 #[inline(always)]
162 pub fn rx_fifo_not_empty(&mut self) -> RX_FIFO_NOT_EMPTY_W {
163 RX_FIFO_NOT_EMPTY_W::new(self)
164 }
165 #[doc = "Bit 7 - Results FIFO 2Q Full Int Enable"]
166 #[inline(always)]
167 pub fn rx_fifo_2q_full(&mut self) -> RX_FIFO_2Q_FULL_W {
168 RX_FIFO_2Q_FULL_W::new(self)
169 }
170 #[doc = "Bit 8 - Results FIFO 3Q Full Int Enable"]
171 #[inline(always)]
172 pub fn rx_fifo_3q_full(&mut self) -> RX_FIFO_3Q_FULL_W {
173 RX_FIFO_3Q_FULL_W::new(self)
174 }
175 #[doc = "Bit 9 - Results FIFO Full Int Enable"]
176 #[inline(always)]
177 pub fn rx_fifo_full(&mut self) -> RX_FIFO_FULL_W {
178 RX_FIFO_FULL_W::new(self)
179 }
180 #[doc = "Writes raw bits to the register."]
181 #[inline(always)]
182 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183 self.0.bits(bits);
184 self
185 }
186}
187#[doc = "Interrupt Enable/Disable Controls\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
188pub struct INTEN_SPEC;
189impl crate::RegisterSpec for INTEN_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [inten::R](R) reader structure"]
193impl crate::Readable for INTEN_SPEC {
194 type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
197impl crate::Writable for INTEN_SPEC {
198 type Writer = W;
199}
200#[doc = "`reset()` method sets INTEN to value 0"]
201impl crate::Resettable for INTEN_SPEC {
202 #[inline(always)]
203 fn reset_value() -> Self::Ux {
204 0
205 }
206}