1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `cpu_adc_start` reader - Start ADC Conversion"]
38pub type CPU_ADC_START_R = crate::BitReader<bool>;
39#[doc = "Field `cpu_adc_start` writer - Start ADC Conversion"]
40pub type CPU_ADC_START_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `adc_pu` reader - ADC Power Up"]
42pub type ADC_PU_R = crate::BitReader<bool>;
43#[doc = "Field `adc_pu` writer - ADC Power Up"]
44pub type ADC_PU_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `buf_pu` reader - ADC Input Buffer Power Up"]
46pub type BUF_PU_R = crate::BitReader<bool>;
47#[doc = "Field `buf_pu` writer - ADC Input Buffer Power Up"]
48pub type BUF_PU_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `adc_refbuf_pu` reader - ADC Reference Buffer Power Up"]
50pub type ADC_REFBUF_PU_R = crate::BitReader<bool>;
51#[doc = "Field `adc_refbuf_pu` writer - ADC Reference Buffer Power Up"]
52pub type ADC_REFBUF_PU_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `adc_chgpump_pu` reader - ADC Charge Pump Power Up"]
54pub type ADC_CHGPUMP_PU_R = crate::BitReader<bool>;
55#[doc = "Field `adc_chgpump_pu` writer - ADC Charge Pump Power Up"]
56pub type ADC_CHGPUMP_PU_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57#[doc = "Field `buf_chop_dis` reader - ADC Input Buffer Chop Disable (INTERNAL ONLY)"]
58pub type BUF_CHOP_DIS_R = crate::BitReader<bool>;
59#[doc = "Field `buf_chop_dis` writer - ADC Input Buffer Chop Disable (INTERNAL ONLY)"]
60pub type BUF_CHOP_DIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 5>;
61#[doc = "Field `buf_pump_dis` reader - Disable Use of Charge Pump Output by Input Buffer (INTERNAL)"]
62pub type BUF_PUMP_DIS_R = crate::BitReader<bool>;
63#[doc = "Field `buf_pump_dis` writer - Disable Use of Charge Pump Output by Input Buffer (INTERNAL)"]
64pub type BUF_PUMP_DIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 6>;
65#[doc = "Field `buf_bypass` reader - Bypass Input Buffer"]
66pub type BUF_BYPASS_R = crate::BitReader<bool>;
67#[doc = "Field `buf_bypass` writer - Bypass Input Buffer"]
68pub type BUF_BYPASS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 7>;
69#[doc = "Field `adc_refscl` reader - ADC Reference Scale"]
70pub type ADC_REFSCL_R = crate::BitReader<bool>;
71#[doc = "Field `adc_refscl` writer - ADC Reference Scale"]
72pub type ADC_REFSCL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
73#[doc = "Field `adc_scale` reader - ADC Scale"]
74pub type ADC_SCALE_R = crate::BitReader<bool>;
75#[doc = "Field `adc_scale` writer - ADC Scale"]
76pub type ADC_SCALE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
77#[doc = "Field `adc_refsel` reader - ADC Reference (VRef) Select (INTERNAL ONLY)"]
78pub type ADC_REFSEL_R = crate::BitReader<bool>;
79#[doc = "Field `adc_refsel` writer - ADC Reference (VRef) Select (INTERNAL ONLY)"]
80pub type ADC_REFSEL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
81#[doc = "Field `adc_clk_en` reader - ADC Clock Enable"]
82pub type ADC_CLK_EN_R = crate::BitReader<bool>;
83#[doc = "Field `adc_clk_en` writer - ADC Clock Enable"]
84pub type ADC_CLK_EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 11>;
85#[doc = "Field `adc_chsel` reader - ADC Channel Select"]
86pub type ADC_CHSEL_R = crate::FieldReader<u8, u8>;
87#[doc = "Field `adc_chsel` writer - ADC Channel Select"]
88pub type ADC_CHSEL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 4, 12>;
89#[doc = "Field `adc_xref` reader - Enable Use of ADC External Reference"]
90pub type ADC_XREF_R = crate::BitReader<bool>;
91#[doc = "Field `adc_xref` writer - Enable Use of ADC External Reference"]
92pub type ADC_XREF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
93#[doc = "Field `adc_dataalign` reader - ADC Data Alignment Select"]
94pub type ADC_DATAALIGN_R = crate::BitReader<bool>;
95#[doc = "Field `adc_dataalign` writer - ADC Data Alignment Select"]
96pub type ADC_DATAALIGN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
97#[doc = "Field `afe_pwr_up_dly` reader - Delay from ADC Powerup Until ADC Ready Asserted"]
98pub type AFE_PWR_UP_DLY_R = crate::FieldReader<u8, u8>;
99#[doc = "Field `afe_pwr_up_dly` writer - Delay from ADC Powerup Until ADC Ready Asserted"]
100pub type AFE_PWR_UP_DLY_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 8, 24>;
101impl R {
102 #[doc = "Bit 0 - Start ADC Conversion"]
103 #[inline(always)]
104 pub fn cpu_adc_start(&self) -> CPU_ADC_START_R {
105 CPU_ADC_START_R::new((self.bits & 1) != 0)
106 }
107 #[doc = "Bit 1 - ADC Power Up"]
108 #[inline(always)]
109 pub fn adc_pu(&self) -> ADC_PU_R {
110 ADC_PU_R::new(((self.bits >> 1) & 1) != 0)
111 }
112 #[doc = "Bit 2 - ADC Input Buffer Power Up"]
113 #[inline(always)]
114 pub fn buf_pu(&self) -> BUF_PU_R {
115 BUF_PU_R::new(((self.bits >> 2) & 1) != 0)
116 }
117 #[doc = "Bit 3 - ADC Reference Buffer Power Up"]
118 #[inline(always)]
119 pub fn adc_refbuf_pu(&self) -> ADC_REFBUF_PU_R {
120 ADC_REFBUF_PU_R::new(((self.bits >> 3) & 1) != 0)
121 }
122 #[doc = "Bit 4 - ADC Charge Pump Power Up"]
123 #[inline(always)]
124 pub fn adc_chgpump_pu(&self) -> ADC_CHGPUMP_PU_R {
125 ADC_CHGPUMP_PU_R::new(((self.bits >> 4) & 1) != 0)
126 }
127 #[doc = "Bit 5 - ADC Input Buffer Chop Disable (INTERNAL ONLY)"]
128 #[inline(always)]
129 pub fn buf_chop_dis(&self) -> BUF_CHOP_DIS_R {
130 BUF_CHOP_DIS_R::new(((self.bits >> 5) & 1) != 0)
131 }
132 #[doc = "Bit 6 - Disable Use of Charge Pump Output by Input Buffer (INTERNAL)"]
133 #[inline(always)]
134 pub fn buf_pump_dis(&self) -> BUF_PUMP_DIS_R {
135 BUF_PUMP_DIS_R::new(((self.bits >> 6) & 1) != 0)
136 }
137 #[doc = "Bit 7 - Bypass Input Buffer"]
138 #[inline(always)]
139 pub fn buf_bypass(&self) -> BUF_BYPASS_R {
140 BUF_BYPASS_R::new(((self.bits >> 7) & 1) != 0)
141 }
142 #[doc = "Bit 8 - ADC Reference Scale"]
143 #[inline(always)]
144 pub fn adc_refscl(&self) -> ADC_REFSCL_R {
145 ADC_REFSCL_R::new(((self.bits >> 8) & 1) != 0)
146 }
147 #[doc = "Bit 9 - ADC Scale"]
148 #[inline(always)]
149 pub fn adc_scale(&self) -> ADC_SCALE_R {
150 ADC_SCALE_R::new(((self.bits >> 9) & 1) != 0)
151 }
152 #[doc = "Bit 10 - ADC Reference (VRef) Select (INTERNAL ONLY)"]
153 #[inline(always)]
154 pub fn adc_refsel(&self) -> ADC_REFSEL_R {
155 ADC_REFSEL_R::new(((self.bits >> 10) & 1) != 0)
156 }
157 #[doc = "Bit 11 - ADC Clock Enable"]
158 #[inline(always)]
159 pub fn adc_clk_en(&self) -> ADC_CLK_EN_R {
160 ADC_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
161 }
162 #[doc = "Bits 12:15 - ADC Channel Select"]
163 #[inline(always)]
164 pub fn adc_chsel(&self) -> ADC_CHSEL_R {
165 ADC_CHSEL_R::new(((self.bits >> 12) & 0x0f) as u8)
166 }
167 #[doc = "Bit 16 - Enable Use of ADC External Reference"]
168 #[inline(always)]
169 pub fn adc_xref(&self) -> ADC_XREF_R {
170 ADC_XREF_R::new(((self.bits >> 16) & 1) != 0)
171 }
172 #[doc = "Bit 17 - ADC Data Alignment Select"]
173 #[inline(always)]
174 pub fn adc_dataalign(&self) -> ADC_DATAALIGN_R {
175 ADC_DATAALIGN_R::new(((self.bits >> 17) & 1) != 0)
176 }
177 #[doc = "Bits 24:31 - Delay from ADC Powerup Until ADC Ready Asserted"]
178 #[inline(always)]
179 pub fn afe_pwr_up_dly(&self) -> AFE_PWR_UP_DLY_R {
180 AFE_PWR_UP_DLY_R::new(((self.bits >> 24) & 0xff) as u8)
181 }
182}
183impl W {
184 #[doc = "Bit 0 - Start ADC Conversion"]
185 #[inline(always)]
186 pub fn cpu_adc_start(&mut self) -> CPU_ADC_START_W {
187 CPU_ADC_START_W::new(self)
188 }
189 #[doc = "Bit 1 - ADC Power Up"]
190 #[inline(always)]
191 pub fn adc_pu(&mut self) -> ADC_PU_W {
192 ADC_PU_W::new(self)
193 }
194 #[doc = "Bit 2 - ADC Input Buffer Power Up"]
195 #[inline(always)]
196 pub fn buf_pu(&mut self) -> BUF_PU_W {
197 BUF_PU_W::new(self)
198 }
199 #[doc = "Bit 3 - ADC Reference Buffer Power Up"]
200 #[inline(always)]
201 pub fn adc_refbuf_pu(&mut self) -> ADC_REFBUF_PU_W {
202 ADC_REFBUF_PU_W::new(self)
203 }
204 #[doc = "Bit 4 - ADC Charge Pump Power Up"]
205 #[inline(always)]
206 pub fn adc_chgpump_pu(&mut self) -> ADC_CHGPUMP_PU_W {
207 ADC_CHGPUMP_PU_W::new(self)
208 }
209 #[doc = "Bit 5 - ADC Input Buffer Chop Disable (INTERNAL ONLY)"]
210 #[inline(always)]
211 pub fn buf_chop_dis(&mut self) -> BUF_CHOP_DIS_W {
212 BUF_CHOP_DIS_W::new(self)
213 }
214 #[doc = "Bit 6 - Disable Use of Charge Pump Output by Input Buffer (INTERNAL)"]
215 #[inline(always)]
216 pub fn buf_pump_dis(&mut self) -> BUF_PUMP_DIS_W {
217 BUF_PUMP_DIS_W::new(self)
218 }
219 #[doc = "Bit 7 - Bypass Input Buffer"]
220 #[inline(always)]
221 pub fn buf_bypass(&mut self) -> BUF_BYPASS_W {
222 BUF_BYPASS_W::new(self)
223 }
224 #[doc = "Bit 8 - ADC Reference Scale"]
225 #[inline(always)]
226 pub fn adc_refscl(&mut self) -> ADC_REFSCL_W {
227 ADC_REFSCL_W::new(self)
228 }
229 #[doc = "Bit 9 - ADC Scale"]
230 #[inline(always)]
231 pub fn adc_scale(&mut self) -> ADC_SCALE_W {
232 ADC_SCALE_W::new(self)
233 }
234 #[doc = "Bit 10 - ADC Reference (VRef) Select (INTERNAL ONLY)"]
235 #[inline(always)]
236 pub fn adc_refsel(&mut self) -> ADC_REFSEL_W {
237 ADC_REFSEL_W::new(self)
238 }
239 #[doc = "Bit 11 - ADC Clock Enable"]
240 #[inline(always)]
241 pub fn adc_clk_en(&mut self) -> ADC_CLK_EN_W {
242 ADC_CLK_EN_W::new(self)
243 }
244 #[doc = "Bits 12:15 - ADC Channel Select"]
245 #[inline(always)]
246 pub fn adc_chsel(&mut self) -> ADC_CHSEL_W {
247 ADC_CHSEL_W::new(self)
248 }
249 #[doc = "Bit 16 - Enable Use of ADC External Reference"]
250 #[inline(always)]
251 pub fn adc_xref(&mut self) -> ADC_XREF_W {
252 ADC_XREF_W::new(self)
253 }
254 #[doc = "Bit 17 - ADC Data Alignment Select"]
255 #[inline(always)]
256 pub fn adc_dataalign(&mut self) -> ADC_DATAALIGN_W {
257 ADC_DATAALIGN_W::new(self)
258 }
259 #[doc = "Bits 24:31 - Delay from ADC Powerup Until ADC Ready Asserted"]
260 #[inline(always)]
261 pub fn afe_pwr_up_dly(&mut self) -> AFE_PWR_UP_DLY_W {
262 AFE_PWR_UP_DLY_W::new(self)
263 }
264 #[doc = "Writes raw bits to the register."]
265 #[inline(always)]
266 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
267 self.0.bits(bits);
268 self
269 }
270}
271#[doc = "ADC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
272pub struct CTRL_SPEC;
273impl crate::RegisterSpec for CTRL_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
277impl crate::Readable for CTRL_SPEC {
278 type Reader = R;
279}
280#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
281impl crate::Writable for CTRL_SPEC {
282 type Writer = W;
283}
284#[doc = "`reset()` method sets CTRL to value 0"]
285impl crate::Resettable for CTRL_SPEC {
286 #[inline(always)]
287 fn reset_value() -> Self::Ux {
288 0
289 }
290}