max3263x/usb/
dma_err_int.rs

1#[doc = "Register `DMA_ERR_INT` reader"]
2pub struct R(crate::R<DMA_ERR_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA_ERR_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA_ERR_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA_ERR_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA_ERR_INT` writer"]
17pub struct W(crate::W<DMA_ERR_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA_ERR_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA_ERR_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA_ERR_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `dma_err0` reader - Endpoint 0 DMA Error Interrupt Flag"]
38pub type DMA_ERR0_R = crate::BitReader<bool>;
39#[doc = "Field `dma_err0` writer - Endpoint 0 DMA Error Interrupt Flag"]
40pub type DMA_ERR0_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 0>;
41#[doc = "Field `dma_err1` reader - Endpoint 1 DMA Error Interrupt Flag"]
42pub type DMA_ERR1_R = crate::BitReader<bool>;
43#[doc = "Field `dma_err1` writer - Endpoint 1 DMA Error Interrupt Flag"]
44pub type DMA_ERR1_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 1>;
45#[doc = "Field `dma_err2` reader - Endpoint 2 DMA Error Interrupt Flag"]
46pub type DMA_ERR2_R = crate::BitReader<bool>;
47#[doc = "Field `dma_err2` writer - Endpoint 2 DMA Error Interrupt Flag"]
48pub type DMA_ERR2_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 2>;
49#[doc = "Field `dma_err3` reader - Endpoint 3 DMA Error Interrupt Flag"]
50pub type DMA_ERR3_R = crate::BitReader<bool>;
51#[doc = "Field `dma_err3` writer - Endpoint 3 DMA Error Interrupt Flag"]
52pub type DMA_ERR3_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 3>;
53#[doc = "Field `dma_err4` reader - Endpoint 4 DMA Error Interrupt Flag"]
54pub type DMA_ERR4_R = crate::BitReader<bool>;
55#[doc = "Field `dma_err4` writer - Endpoint 4 DMA Error Interrupt Flag"]
56pub type DMA_ERR4_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 4>;
57#[doc = "Field `dma_err5` reader - Endpoint 5 DMA Error Interrupt Flag"]
58pub type DMA_ERR5_R = crate::BitReader<bool>;
59#[doc = "Field `dma_err5` writer - Endpoint 5 DMA Error Interrupt Flag"]
60pub type DMA_ERR5_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 5>;
61#[doc = "Field `dma_err6` reader - Endpoint 6 DMA Error Interrupt Flag"]
62pub type DMA_ERR6_R = crate::BitReader<bool>;
63#[doc = "Field `dma_err6` writer - Endpoint 6 DMA Error Interrupt Flag"]
64pub type DMA_ERR6_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 6>;
65#[doc = "Field `dma_err7` reader - Endpoint 7 DMA Error Interrupt Flag"]
66pub type DMA_ERR7_R = crate::BitReader<bool>;
67#[doc = "Field `dma_err7` writer - Endpoint 7 DMA Error Interrupt Flag"]
68pub type DMA_ERR7_W<'a> = crate::BitWriter1C<'a, u32, DMA_ERR_INT_SPEC, bool, 7>;
69impl R {
70    #[doc = "Bit 0 - Endpoint 0 DMA Error Interrupt Flag"]
71    #[inline(always)]
72    pub fn dma_err0(&self) -> DMA_ERR0_R {
73        DMA_ERR0_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Endpoint 1 DMA Error Interrupt Flag"]
76    #[inline(always)]
77    pub fn dma_err1(&self) -> DMA_ERR1_R {
78        DMA_ERR1_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Endpoint 2 DMA Error Interrupt Flag"]
81    #[inline(always)]
82    pub fn dma_err2(&self) -> DMA_ERR2_R {
83        DMA_ERR2_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - Endpoint 3 DMA Error Interrupt Flag"]
86    #[inline(always)]
87    pub fn dma_err3(&self) -> DMA_ERR3_R {
88        DMA_ERR3_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - Endpoint 4 DMA Error Interrupt Flag"]
91    #[inline(always)]
92    pub fn dma_err4(&self) -> DMA_ERR4_R {
93        DMA_ERR4_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - Endpoint 5 DMA Error Interrupt Flag"]
96    #[inline(always)]
97    pub fn dma_err5(&self) -> DMA_ERR5_R {
98        DMA_ERR5_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - Endpoint 6 DMA Error Interrupt Flag"]
101    #[inline(always)]
102    pub fn dma_err6(&self) -> DMA_ERR6_R {
103        DMA_ERR6_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7 - Endpoint 7 DMA Error Interrupt Flag"]
106    #[inline(always)]
107    pub fn dma_err7(&self) -> DMA_ERR7_R {
108        DMA_ERR7_R::new(((self.bits >> 7) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Endpoint 0 DMA Error Interrupt Flag"]
113    #[inline(always)]
114    pub fn dma_err0(&mut self) -> DMA_ERR0_W {
115        DMA_ERR0_W::new(self)
116    }
117    #[doc = "Bit 1 - Endpoint 1 DMA Error Interrupt Flag"]
118    #[inline(always)]
119    pub fn dma_err1(&mut self) -> DMA_ERR1_W {
120        DMA_ERR1_W::new(self)
121    }
122    #[doc = "Bit 2 - Endpoint 2 DMA Error Interrupt Flag"]
123    #[inline(always)]
124    pub fn dma_err2(&mut self) -> DMA_ERR2_W {
125        DMA_ERR2_W::new(self)
126    }
127    #[doc = "Bit 3 - Endpoint 3 DMA Error Interrupt Flag"]
128    #[inline(always)]
129    pub fn dma_err3(&mut self) -> DMA_ERR3_W {
130        DMA_ERR3_W::new(self)
131    }
132    #[doc = "Bit 4 - Endpoint 4 DMA Error Interrupt Flag"]
133    #[inline(always)]
134    pub fn dma_err4(&mut self) -> DMA_ERR4_W {
135        DMA_ERR4_W::new(self)
136    }
137    #[doc = "Bit 5 - Endpoint 5 DMA Error Interrupt Flag"]
138    #[inline(always)]
139    pub fn dma_err5(&mut self) -> DMA_ERR5_W {
140        DMA_ERR5_W::new(self)
141    }
142    #[doc = "Bit 6 - Endpoint 6 DMA Error Interrupt Flag"]
143    #[inline(always)]
144    pub fn dma_err6(&mut self) -> DMA_ERR6_W {
145        DMA_ERR6_W::new(self)
146    }
147    #[doc = "Bit 7 - Endpoint 7 DMA Error Interrupt Flag"]
148    #[inline(always)]
149    pub fn dma_err7(&mut self) -> DMA_ERR7_W {
150        DMA_ERR7_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "USB DMA Error Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_err_int](index.html) module"]
160pub struct DMA_ERR_INT_SPEC;
161impl crate::RegisterSpec for DMA_ERR_INT_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [dma_err_int::R](R) reader structure"]
165impl crate::Readable for DMA_ERR_INT_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [dma_err_int::W](W) writer structure"]
169impl crate::Writable for DMA_ERR_INT_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets DMA_ERR_INT to value 0"]
173impl crate::Resettable for DMA_ERR_INT_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0
177    }
178}
max3263x/usb/dma_err_int.rs

max3263x/usb/
dma_err_int.rs
