use bitfield_struct::bitfield;
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroDataRate {
#[default]
Hz95 = 0b00,
Hz190 = 0b01,
Hz380 = 0b10,
Hz760 = 0b11,
}
impl GyroDataRate {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Hz95,
0b01 => Self::Hz190,
0b10 => Self::Hz380,
_ => Self::Hz760,
}
}
pub const fn hz(self) -> f32 {
match self {
Self::Hz95 => 95.0,
Self::Hz190 => 190.0,
Self::Hz380 => 380.0,
Self::Hz760 => 760.0,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroBandwidth {
#[default]
Bw0 = 0b00,
Bw1 = 0b01,
Bw2 = 0b10,
Bw3 = 0b11,
}
impl GyroBandwidth {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Bw0,
0b01 => Self::Bw1,
0b10 => Self::Bw2,
_ => Self::Bw3,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroScale {
#[default]
Dps245 = 0b00,
Dps500 = 0b01,
Dps2000 = 0b10,
}
impl GyroScale {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Dps245,
0b01 => Self::Dps500,
_ => Self::Dps2000,
}
}
pub const fn sensitivity(self) -> f32 {
match self {
Self::Dps245 => 8.75,
Self::Dps500 => 17.5,
Self::Dps2000 => 70.0,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroHpfMode {
#[default]
NormalReset = 0b00,
Reference = 0b01,
Normal = 0b10,
AutoReset = 0b11,
}
impl GyroHpfMode {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::NormalReset,
0b01 => Self::Reference,
0b10 => Self::Normal,
_ => Self::AutoReset,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroHpfCutoff {
#[default]
Cutoff0 = 0b0000,
Cutoff1 = 0b0001,
Cutoff2 = 0b0010,
Cutoff3 = 0b0011,
Cutoff4 = 0b0100,
Cutoff5 = 0b0101,
Cutoff6 = 0b0110,
Cutoff7 = 0b0111,
Cutoff8 = 0b1000,
Cutoff9 = 0b1001,
}
impl GyroHpfCutoff {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1111 {
0b0000 => Self::Cutoff0,
0b0001 => Self::Cutoff1,
0b0010 => Self::Cutoff2,
0b0011 => Self::Cutoff3,
0b0100 => Self::Cutoff4,
0b0101 => Self::Cutoff5,
0b0110 => Self::Cutoff6,
0b0111 => Self::Cutoff7,
0b1000 => Self::Cutoff8,
_ => Self::Cutoff9,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroSelfTest {
#[default]
Disabled = 0b00,
Mode0 = 0b01,
Mode1 = 0b11,
}
impl GyroSelfTest {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Disabled,
0b01 => Self::Mode0,
_ => Self::Mode1,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroOutputSel {
#[default]
LpfOnly = 0b00,
LpfAndHpf = 0b01,
LpfHpfAndLpf2 = 0b10,
}
impl GyroOutputSel {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::LpfOnly,
0b01 => Self::LpfAndHpf,
_ => Self::LpfHpfAndLpf2,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum FifoMode {
#[default]
Bypass = 0b000,
Fifo = 0b001,
Stream = 0b010,
StreamToFifo = 0b011,
BypassToStream = 0b100,
}
impl FifoMode {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b111 {
0b000 => Self::Bypass,
0b001 => Self::Fifo,
0b010 => Self::Stream,
0b011 => Self::StreamToFifo,
0b100 => Self::BypassToStream,
_ => Self::Bypass,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum AccelDataRate {
#[default]
PowerDown = 0b0000,
Hz3_125 = 0b0001,
Hz6_25 = 0b0010,
Hz12_5 = 0b0011,
Hz25 = 0b0100,
Hz50 = 0b0101,
Hz100 = 0b0110,
Hz200 = 0b0111,
Hz400 = 0b1000,
Hz800 = 0b1001,
Hz1600 = 0b1010,
}
impl AccelDataRate {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1111 {
0b0000 => Self::PowerDown,
0b0001 => Self::Hz3_125,
0b0010 => Self::Hz6_25,
0b0011 => Self::Hz12_5,
0b0100 => Self::Hz25,
0b0101 => Self::Hz50,
0b0110 => Self::Hz100,
0b0111 => Self::Hz200,
0b1000 => Self::Hz400,
0b1001 => Self::Hz800,
0b1010 => Self::Hz1600,
_ => Self::PowerDown,
}
}
pub const fn hz(self) -> f32 {
match self {
Self::PowerDown => 0.0,
Self::Hz3_125 => 3.125,
Self::Hz6_25 => 6.25,
Self::Hz12_5 => 12.5,
Self::Hz25 => 25.0,
Self::Hz50 => 50.0,
Self::Hz100 => 100.0,
Self::Hz200 => 200.0,
Self::Hz400 => 400.0,
Self::Hz800 => 800.0,
Self::Hz1600 => 1600.0,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum AccelScale {
#[default]
G2 = 0b000,
G4 = 0b001,
G6 = 0b010,
G8 = 0b011,
G16 = 0b100,
}
impl AccelScale {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b111 {
0b000 => Self::G2,
0b001 => Self::G4,
0b010 => Self::G6,
0b011 => Self::G8,
_ => Self::G16,
}
}
pub const fn sensitivity(self) -> f32 {
match self {
Self::G2 => 0.061,
Self::G4 => 0.122,
Self::G6 => 0.183,
Self::G8 => 0.244,
Self::G16 => 0.732,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum AccelBandwidth {
#[default]
Hz773 = 0b00,
Hz194 = 0b01,
Hz362 = 0b10,
Hz50 = 0b11,
}
impl AccelBandwidth {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Hz773,
0b01 => Self::Hz194,
0b10 => Self::Hz362,
_ => Self::Hz50,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum AccelSelfTest {
#[default]
Normal = 0b00,
PositiveSign = 0b01,
NegativeSign = 0b10,
}
impl AccelSelfTest {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Normal,
0b01 => Self::PositiveSign,
_ => Self::NegativeSign,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum AccelHpfMode {
#[default]
NormalReset = 0b00,
Reference = 0b01,
Normal = 0b10,
AutoReset = 0b11,
}
impl AccelHpfMode {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::NormalReset,
0b01 => Self::Reference,
0b10 => Self::Normal,
_ => Self::AutoReset,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum MagDataRate {
Hz3_125 = 0b000,
Hz6_25 = 0b001,
Hz12_5 = 0b010,
Hz25 = 0b011,
#[default]
Hz50 = 0b100,
Hz100 = 0b101,
}
impl MagDataRate {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b111 {
0b000 => Self::Hz3_125,
0b001 => Self::Hz6_25,
0b010 => Self::Hz12_5,
0b011 => Self::Hz25,
0b100 => Self::Hz50,
0b101 => Self::Hz100,
_ => Self::Hz50,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum MagScale {
Gauss2 = 0b00,
#[default]
Gauss4 = 0b01,
Gauss8 = 0b10,
Gauss12 = 0b11,
}
impl MagScale {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Gauss2,
0b01 => Self::Gauss4,
0b10 => Self::Gauss8,
_ => Self::Gauss12,
}
}
pub const fn sensitivity(self) -> f32 {
match self {
Self::Gauss2 => 0.08,
Self::Gauss4 => 0.16,
Self::Gauss8 => 0.32,
Self::Gauss12 => 0.48,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum MagResolution {
#[default]
Low = 0b00,
High = 0b11,
}
impl MagResolution {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::Low,
_ => Self::High,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum MagMode {
ContinuousConversion = 0b00,
SingleConversion = 0b01,
#[default]
PowerDown = 0b10,
}
impl MagMode {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b11 {
0b00 => Self::ContinuousConversion,
0b01 => Self::SingleConversion,
_ => Self::PowerDown,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Enable {
#[default]
Disabled = 0,
Enabled = 1,
}
impl Enable {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::Disabled,
_ => Self::Enabled,
}
}
}
impl From<bool> for Enable {
fn from(value: bool) -> Self {
if value { Self::Enabled } else { Self::Disabled }
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum PowerMode {
#[default]
PowerDown = 0,
Normal = 1,
}
impl PowerMode {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::PowerDown,
_ => Self::Normal,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum GyroPowerMode {
#[default]
PowerDown = 0,
Sleep = 1,
Normal = 2,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum BlockDataUpdate {
#[default]
Continuous = 0,
WaitForRead = 1,
}
impl BlockDataUpdate {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::Continuous,
_ => Self::WaitForRead,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum OutputType {
#[default]
PushPull = 0,
OpenDrain = 1,
}
impl OutputType {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::PushPull,
_ => Self::OpenDrain,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum ActiveLevel {
#[default]
ActiveHigh = 0,
ActiveLow = 1,
}
impl ActiveLevel {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::ActiveHigh,
_ => Self::ActiveLow,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum ActiveLevelInverted {
#[default]
ActiveLow = 0,
ActiveHigh = 1,
}
impl ActiveLevelInverted {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::ActiveLow,
_ => Self::ActiveHigh,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Endianness {
#[default]
Little = 0,
Big = 1,
}
impl Endianness {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::Little,
_ => Self::Big,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum SpiMode {
#[default]
FourWire = 0,
ThreeWire = 1,
}
impl SpiMode {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::FourWire,
_ => Self::ThreeWire,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum LatchInterrupt {
#[default]
NotLatched = 0,
Latched = 1,
}
impl LatchInterrupt {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::NotLatched,
_ => Self::Latched,
}
}
}
impl From<bool> for LatchInterrupt {
fn from(value: bool) -> Self {
if value {
Self::Latched
} else {
Self::NotLatched
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum InterruptCombination {
#[default]
Or = 0,
And = 1,
}
impl InterruptCombination {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::Or,
_ => Self::And,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum MagLowPower {
#[default]
Normal = 0,
LowPower = 1,
}
impl MagLowPower {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::Normal,
_ => Self::LowPower,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum ClickSign {
#[default]
Positive = 0,
Negative = 1,
}
impl ClickSign {
const fn into_bits(self) -> u8 {
self as u8
}
const fn from_bits(value: u8) -> Self {
match value & 0b1 {
0 => Self::Positive,
_ => Self::Negative,
}
}
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg1G {
#[bits(1)]
pub xen: Enable,
#[bits(1)]
pub yen: Enable,
#[bits(1)]
pub zen: Enable,
#[bits(1)]
pub pd: PowerMode,
#[bits(2)]
pub bw: GyroBandwidth,
#[bits(2)]
pub dr: GyroDataRate,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg2G {
#[bits(4)]
pub hpcf: GyroHpfCutoff,
#[bits(2)]
pub hpm: GyroHpfMode,
#[bits(2)]
__reserved: u8,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg3G {
#[bits(1)]
pub i2_empty: Enable,
#[bits(1)]
pub i2_orun: Enable,
#[bits(1)]
pub i2_wtm: Enable,
#[bits(1)]
pub i2_drdy: Enable,
#[bits(1)]
pub pp_od: OutputType,
#[bits(1)]
pub h_lactive: ActiveLevel,
#[bits(1)]
pub i1_boot: Enable,
#[bits(1)]
pub i1_int1: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg4G {
#[bits(1)]
pub sim: SpiMode,
#[bits(2)]
pub st: GyroSelfTest,
#[bits(1)]
__reserved: u8,
#[bits(2)]
pub fs: GyroScale,
#[bits(1)]
pub ble: Endianness,
#[bits(1)]
pub bdu: BlockDataUpdate,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg5G {
#[bits(2)]
pub out_sel: GyroOutputSel,
#[bits(2)]
pub int1_sel: GyroOutputSel,
#[bits(1)]
pub hpen: Enable,
#[bits(1)]
__reserved: u8,
#[bits(1)]
pub fifo_en: Enable,
#[bits(1)]
pub boot: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct StatusRegG {
pub xda: bool,
pub yda: bool,
pub zda: bool,
pub zyxda: bool,
pub xor: bool,
pub yor: bool,
pub zor: bool,
pub zyxor: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct FifoCtrlRegG {
#[bits(5)]
pub wtm: u8,
#[bits(3)]
pub fm: FifoMode,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct FifoSrcRegG {
#[bits(5)]
pub fss: u8,
pub empty: bool,
pub ovrn: bool,
pub wtm: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct Int1CfgG {
#[bits(1)]
pub xlie: Enable,
#[bits(1)]
pub xhie: Enable,
#[bits(1)]
pub ylie: Enable,
#[bits(1)]
pub yhie: Enable,
#[bits(1)]
pub zlie: Enable,
#[bits(1)]
pub zhie: Enable,
#[bits(1)]
pub lir: LatchInterrupt,
#[bits(1)]
pub and_or: InterruptCombination,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct Int1SrcG {
pub xl: bool,
pub xh: bool,
pub yl: bool,
pub yh: bool,
pub zl: bool,
pub zh: bool,
pub ia: bool,
#[bits(1)]
__reserved: u8,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct Int1DurationG {
#[bits(7)]
pub duration: u8,
pub wait: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct StatusRegM {
pub xmda: bool,
pub ymda: bool,
pub zmda: bool,
pub zyxmda: bool,
pub xmor: bool,
pub ymor: bool,
pub zmor: bool,
pub zyxmor: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct IntCtrlRegM {
#[bits(1)]
pub mien: Enable,
#[bits(1)]
pub fourd: Enable,
#[bits(1)]
pub iel: LatchInterrupt,
#[bits(1)]
pub iea: ActiveLevelInverted,
#[bits(1)]
pub pp_od: OutputType,
#[bits(1)]
pub zmien: Enable,
#[bits(1)]
pub ymien: Enable,
#[bits(1)]
pub xmien: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct IntSrcRegM {
pub mint: bool,
pub mroi: bool,
pub m_nth_z: bool,
pub m_nth_y: bool,
pub m_nth_x: bool,
pub m_pth_z: bool,
pub m_pth_y: bool,
pub m_pth_x: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg0Xm {
#[bits(1)]
pub hpis2: Enable,
#[bits(1)]
pub hpis1: Enable,
#[bits(1)]
pub hp_click: Enable,
#[bits(2)]
__reserved: u8,
#[bits(1)]
pub wtm_en: Enable,
#[bits(1)]
pub fifo_en: Enable,
#[bits(1)]
pub boot: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg1Xm {
#[bits(1)]
pub axen: Enable,
#[bits(1)]
pub ayen: Enable,
#[bits(1)]
pub azen: Enable,
#[bits(1)]
pub bdu: BlockDataUpdate,
#[bits(4)]
pub aodr: AccelDataRate,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg2Xm {
#[bits(1)]
pub sim: SpiMode,
#[bits(2)]
pub ast: AccelSelfTest,
#[bits(3)]
pub afs: AccelScale,
#[bits(2)]
pub abw: AccelBandwidth,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg3Xm {
#[bits(1)]
pub p1_empty: Enable,
#[bits(1)]
pub p1_drdym: Enable,
#[bits(1)]
pub p1_drdya: Enable,
#[bits(1)]
pub p1_intm: Enable,
#[bits(1)]
pub p1_int2: Enable,
#[bits(1)]
pub p1_int1: Enable,
#[bits(1)]
pub p1_tap: Enable,
#[bits(1)]
pub p1_boot: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg4Xm {
#[bits(1)]
pub p2_wtm: Enable,
#[bits(1)]
pub p2_overrun: Enable,
#[bits(1)]
pub p2_drdym: Enable,
#[bits(1)]
pub p2_drdya: Enable,
#[bits(1)]
pub p2_intm: Enable,
#[bits(1)]
pub p2_int2: Enable,
#[bits(1)]
pub p2_int1: Enable,
#[bits(1)]
pub p2_tap: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg5Xm {
#[bits(1)]
pub lir1: LatchInterrupt,
#[bits(1)]
pub lir2: LatchInterrupt,
#[bits(3)]
pub m_odr: MagDataRate,
#[bits(2)]
pub m_res: MagResolution,
#[bits(1)]
pub temp_en: Enable,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg6Xm {
#[bits(5)]
__reserved: u8,
#[bits(2)]
pub mfs: MagScale,
#[bits(1)]
__reserved2: u8,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct CtrlReg7Xm {
#[bits(2)]
pub md: MagMode,
#[bits(1)]
pub mlp: MagLowPower,
#[bits(2)]
__reserved: u8,
#[bits(1)]
pub afds: Enable,
#[bits(2)]
pub ahpm: AccelHpfMode,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct StatusRegA {
pub xada: bool,
pub yada: bool,
pub zada: bool,
pub zyxada: bool,
pub xaor: bool,
pub yaor: bool,
pub zaor: bool,
pub zyxaor: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct FifoCtrlReg {
#[bits(5)]
pub fth: u8,
#[bits(3)]
pub fm: FifoMode,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct FifoSrcReg {
#[bits(5)]
pub fss: u8,
pub empty: bool,
pub ovrn: bool,
pub wtm: bool,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct IntGenReg {
#[bits(1)]
pub xlie: Enable,
#[bits(1)]
pub xhie: Enable,
#[bits(1)]
pub ylie: Enable,
#[bits(1)]
pub yhie: Enable,
#[bits(1)]
pub zlie: Enable,
#[bits(1)]
pub zhie: Enable,
#[bits(1)]
pub six_d: Enable,
#[bits(1)]
pub aoi: InterruptCombination,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct IntGenSrc {
pub xl: bool,
pub xh: bool,
pub yl: bool,
pub yh: bool,
pub zl: bool,
pub zh: bool,
pub ia: bool,
#[bits(1)]
__reserved: u8,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct ClickCfg {
#[bits(1)]
pub xs: Enable,
#[bits(1)]
pub xd: Enable,
#[bits(1)]
pub ys: Enable,
#[bits(1)]
pub yd: Enable,
#[bits(1)]
pub zs: Enable,
#[bits(1)]
pub zd: Enable,
#[bits(2)]
__reserved: u8,
}
#[bitfield(u8, defmt = cfg(feature = "defmt"))]
pub struct ClickSrc {
pub x: bool,
pub y: bool,
pub z: bool,
#[bits(1)]
pub sign: ClickSign,
pub sclick: bool,
pub dclick: bool,
pub ia: bool,
#[bits(1)]
__reserved: u8,
}
#[allow(non_camel_case_types)]
#[repr(u8)]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum GyroRegisters {
WHO_AM_I_G = 0x0F,
CTRL_REG1_G = 0x20,
CTRL_REG2_G = 0x21,
CTRL_REG3_G = 0x22,
CTRL_REG4_G = 0x23,
CTRL_REG5_G = 0x24,
REFERENCE_G = 0x25,
STATUS_REG_G = 0x27,
OUT_X_L_G = 0x28,
OUT_X_H_G = 0x29,
OUT_Y_L_G = 0x2A,
OUT_Y_H_G = 0x2B,
OUT_Z_L_G = 0x2C,
OUT_Z_H_G = 0x2D,
FIFO_CTRL_REG_G = 0x2E,
FIFO_SRC_REG_G = 0x2F,
INT1_CFG_G = 0x30,
INT1_SRC_G = 0x31,
INT1_THS_XH_G = 0x32,
INT1_THS_XL_G = 0x33,
INT1_THS_YH_G = 0x34,
INT1_THS_YL_G = 0x35,
INT1_THS_ZH_G = 0x36,
INT1_THS_ZL_G = 0x37,
INT1_DURATION_G = 0x38,
}
impl GyroRegisters {
pub const fn addr(self) -> u8 {
self as u8
}
}
#[allow(non_camel_case_types)]
#[repr(u8)]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum AccelMagRegisters {
OUT_TEMP_L_XM = 0x05,
OUT_TEMP_H_XM = 0x06,
STATUS_REG_M = 0x07,
OUT_X_L_M = 0x08,
OUT_X_H_M = 0x09,
OUT_Y_L_M = 0x0A,
OUT_Y_H_M = 0x0B,
OUT_Z_L_M = 0x0C,
OUT_Z_H_M = 0x0D,
WHO_AM_I_XM = 0x0F,
INT_CTRL_REG_M = 0x12,
INT_SRC_REG_M = 0x13,
INT_THS_L_M = 0x14,
INT_THS_H_M = 0x15,
OFFSET_X_L_M = 0x16,
OFFSET_X_H_M = 0x17,
OFFSET_Y_L_M = 0x18,
OFFSET_Y_H_M = 0x19,
OFFSET_Z_L_M = 0x1A,
OFFSET_Z_H_M = 0x1B,
REFERENCE_X = 0x1C,
REFERENCE_Y = 0x1D,
REFERENCE_Z = 0x1E,
CTRL_REG0_XM = 0x1F,
CTRL_REG1_XM = 0x20,
CTRL_REG2_XM = 0x21,
CTRL_REG3_XM = 0x22,
CTRL_REG4_XM = 0x23,
CTRL_REG5_XM = 0x24,
CTRL_REG6_XM = 0x25,
CTRL_REG7_XM = 0x26,
STATUS_REG_A = 0x27,
OUT_X_L_A = 0x28,
OUT_X_H_A = 0x29,
OUT_Y_L_A = 0x2A,
OUT_Y_H_A = 0x2B,
OUT_Z_L_A = 0x2C,
OUT_Z_H_A = 0x2D,
FIFO_CTRL_REG = 0x2E,
FIFO_SRC_REG = 0x2F,
INT_GEN_1_REG = 0x30,
INT_GEN_1_SRC = 0x31,
INT_GEN_1_THS = 0x32,
INT_GEN_1_DURATION = 0x33,
INT_GEN_2_REG = 0x34,
INT_GEN_2_SRC = 0x35,
INT_GEN_2_THS = 0x36,
INT_GEN_2_DURATION = 0x37,
CLICK_CFG = 0x38,
CLICK_SRC = 0x39,
CLICK_THS = 0x3A,
TIME_LIMIT = 0x3B,
TIME_LATENCY = 0x3C,
TIME_WINDOW = 0x3D,
ACT_THS = 0x3E,
ACT_DUR = 0x3F,
}
impl AccelMagRegisters {
pub const fn addr(self) -> u8 {
self as u8
}
}
pub mod device_constants {
pub mod gyro {
pub const I2C_ADDR_0: u8 = 0x6A;
pub const I2C_ADDR_1: u8 = 0x6B;
pub const DEVICE_ID: u8 = 0xD4;
}
pub mod xm {
pub const I2C_ADDR_0: u8 = 0x1E;
pub const I2C_ADDR_1: u8 = 0x1D;
pub const DEVICE_ID: u8 = 0x49;
}
}