Module ls7366::mdr0

Primary configuration

Public representation is via the Mdr0 struct.

Exposes configurations for

• Quadrature count mode: Controls the interpretation of the input encoder signals
• Index pin behavior: Controls the behavior of the Index pin.
• Count cycle mode: Controls the behavior of the counter.
• Filter clock division factor: Controls the rate of the Filter clock, for validating Index inputs.

Structs

Mdr0	Representation of the Mdr0 register.

Enums

CycleCountMode	Enum representing cycle count modes.
FilterClockDivisionFactor	Controls Filter clock frequency, used to validate Index inputs.
IndexMode	controls the behavior of the Index pin on the chip.
QuadCountMode	Possible quadrature count modes