Struct lpc845_pac::syscon::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 50 fields
pub sysmemremap: Reg<SYSMEMREMAP_SPEC>,
pub syspllctrl: Reg<SYSPLLCTRL_SPEC>,
pub syspllstat: Reg<SYSPLLSTAT_SPEC>,
pub sysoscctrl: Reg<SYSOSCCTRL_SPEC>,
pub wdtoscctrl: Reg<WDTOSCCTRL_SPEC>,
pub frooscctrl: Reg<FROOSCCTRL_SPEC>,
pub frodirectclkuen: Reg<FRODIRECTCLKUEN_SPEC>,
pub sysrststat: Reg<SYSRSTSTAT_SPEC>,
pub syspllclksel: Reg<SYSPLLCLKSEL_SPEC>,
pub syspllclkuen: Reg<SYSPLLCLKUEN_SPEC>,
pub mainclkpllsel: Reg<MAINCLKPLLSEL_SPEC>,
pub mainclkplluen: Reg<MAINCLKPLLUEN_SPEC>,
pub mainclksel: Reg<MAINCLKSEL_SPEC>,
pub mainclkuen: Reg<MAINCLKUEN_SPEC>,
pub sysahbclkdiv: Reg<SYSAHBCLKDIV_SPEC>,
pub captclksel: Reg<CAPTCLKSEL_SPEC>,
pub adcclksel: Reg<ADCCLKSEL_SPEC>,
pub adcclkdiv: Reg<ADCCLKDIV_SPEC>,
pub sctclksel: Reg<SCTCLKSEL_SPEC>,
pub sctclkdiv: Reg<SCTCLKDIV_SPEC>,
pub extclksel: Reg<EXTCLKSEL_SPEC>,
pub sysahbclkctrl0: Reg<SYSAHBCLKCTRL0_SPEC>,
pub sysahbclkctrl1: Reg<SYSAHBCLKCTRL1_SPEC>,
pub presetctrl0: Reg<PRESETCTRL0_SPEC>,
pub presetctrl1: Reg<PRESETCTRL1_SPEC>,
pub fclksel: [Reg<FCLKSEL_SPEC>; 11],
pub frg0: FRG,
pub frg1: FRG,
pub clkoutsel: Reg<CLKOUTSEL_SPEC>,
pub clkoutdiv: Reg<CLKOUTDIV_SPEC>,
pub exttracecmd: Reg<EXTTRACECMD_SPEC>,
pub pioporcap: [Reg<PIOPORCAP_SPEC>; 2],
pub ioconclkdiv6: Reg<IOCONCLKDIV6_SPEC>,
pub ioconclkdiv5: Reg<IOCONCLKDIV5_SPEC>,
pub ioconclkdiv4: Reg<IOCONCLKDIV4_SPEC>,
pub ioconclkdiv3: Reg<IOCONCLKDIV3_SPEC>,
pub ioconclkdiv2: Reg<IOCONCLKDIV2_SPEC>,
pub ioconclkdiv1: Reg<IOCONCLKDIV1_SPEC>,
pub ioconclkdiv0: Reg<IOCONCLKDIV0_SPEC>,
pub bodctrl: Reg<BODCTRL_SPEC>,
pub systckcal: Reg<SYSTCKCAL_SPEC>,
pub irqlatency: Reg<IRQLATENCY_SPEC>,
pub nmisrc: Reg<NMISRC_SPEC>,
pub pintsel: [Reg<PINTSEL_SPEC>; 8],
pub starterp0: Reg<STARTERP0_SPEC>,
pub starterp1: Reg<STARTERP1_SPEC>,
pub pdsleepcfg: Reg<PDSLEEPCFG_SPEC>,
pub pdawakecfg: Reg<PDAWAKECFG_SPEC>,
pub pdruncfg: Reg<PDRUNCFG_SPEC>,
pub device_id: Reg<DEVICE_ID_SPEC>,
// some fields omitted
}
Expand description
Register block
Fields
sysmemremap: Reg<SYSMEMREMAP_SPEC>
0x00 - System Remap register
syspllctrl: Reg<SYSPLLCTRL_SPEC>
0x08 - PLL control
syspllstat: Reg<SYSPLLSTAT_SPEC>
0x0c - PLL status
sysoscctrl: Reg<SYSOSCCTRL_SPEC>
0x20 - system oscillator control
wdtoscctrl: Reg<WDTOSCCTRL_SPEC>
0x24 - Watchdog oscillator control
frooscctrl: Reg<FROOSCCTRL_SPEC>
0x28 - FRO oscillator control
frodirectclkuen: Reg<FRODIRECTCLKUEN_SPEC>
0x30 - FRO direct clock source update enable register
sysrststat: Reg<SYSRSTSTAT_SPEC>
0x38 - System reset status register
syspllclksel: Reg<SYSPLLCLKSEL_SPEC>
0x40 - System PLL clock source select register
syspllclkuen: Reg<SYSPLLCLKUEN_SPEC>
0x44 - System PLL clock source update enable register
mainclkpllsel: Reg<MAINCLKPLLSEL_SPEC>
0x48 - Main clock source select register
mainclkplluen: Reg<MAINCLKPLLUEN_SPEC>
0x4c - Main clock source update enable register
mainclksel: Reg<MAINCLKSEL_SPEC>
0x50 - Main clock source select register
mainclkuen: Reg<MAINCLKUEN_SPEC>
0x54 - Main clock source update enable register
sysahbclkdiv: Reg<SYSAHBCLKDIV_SPEC>
0x58 - System clock divider register
captclksel: Reg<CAPTCLKSEL_SPEC>
0x60 - CAPT clock source select register
adcclksel: Reg<ADCCLKSEL_SPEC>
0x64 - ADC clock source select register
adcclkdiv: Reg<ADCCLKDIV_SPEC>
0x68 - ADC clock divider register
sctclksel: Reg<SCTCLKSEL_SPEC>
0x6c - SCT clock source select register
sctclkdiv: Reg<SCTCLKDIV_SPEC>
0x70 - SCT clock divider register
extclksel: Reg<EXTCLKSEL_SPEC>
0x74 - external clock source select register
sysahbclkctrl0: Reg<SYSAHBCLKCTRL0_SPEC>
0x80 - System clock group 0 control register
sysahbclkctrl1: Reg<SYSAHBCLKCTRL1_SPEC>
0x84 - System clock group 1 control register
presetctrl0: Reg<PRESETCTRL0_SPEC>
0x88 - Peripheral reset group 0 control register
presetctrl1: Reg<PRESETCTRL1_SPEC>
0x8c - Peripheral reset group 1 control register
fclksel: [Reg<FCLKSEL_SPEC>; 11]
0x90..0xbc - peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register.
frg0: FRG
0xd0..0xdc - no description available
frg1: FRG
0xe0..0xec - no description available
clkoutsel: Reg<CLKOUTSEL_SPEC>
0xf0 - CLKOUT clock source select register
clkoutdiv: Reg<CLKOUTDIV_SPEC>
0xf4 - CLKOUT clock divider registers
exttracecmd: Reg<EXTTRACECMD_SPEC>
0xfc - External trace buffer command register
pioporcap: [Reg<PIOPORCAP_SPEC>; 2]
0x100..0x108 - POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs)
ioconclkdiv6: Reg<IOCONCLKDIV6_SPEC>
0x134 - Peripheral clock 6 to the IOCON block for programmable glitch filter
ioconclkdiv5: Reg<IOCONCLKDIV5_SPEC>
0x138 - Peripheral clock 6 to the IOCON block for programmable glitch filter
ioconclkdiv4: Reg<IOCONCLKDIV4_SPEC>
0x13c - Peripheral clock 4 to the IOCON block for programmable glitch filter
ioconclkdiv3: Reg<IOCONCLKDIV3_SPEC>
0x140 - Peripheral clock 3 to the IOCON block for programmable glitch filter
ioconclkdiv2: Reg<IOCONCLKDIV2_SPEC>
0x144 - Peripheral clock 2 to the IOCON block for programmable glitch filter
ioconclkdiv1: Reg<IOCONCLKDIV1_SPEC>
0x148 - Peripheral clock 1 to the IOCON block for programmable glitch filter
ioconclkdiv0: Reg<IOCONCLKDIV0_SPEC>
0x14c - Peripheral clock 0 to the IOCON block for programmable glitch filter
bodctrl: Reg<BODCTRL_SPEC>
0x150 - BOD control register
systckcal: Reg<SYSTCKCAL_SPEC>
0x154 - System tick timer calibration register
irqlatency: Reg<IRQLATENCY_SPEC>
0x170 - IRQ latency register
nmisrc: Reg<NMISRC_SPEC>
0x174 - NMI source selection register
pintsel: [Reg<PINTSEL_SPEC>; 8]
0x178..0x198 - Pin interrupt select registers N
starterp0: Reg<STARTERP0_SPEC>
0x204 - Start logic 0 pin wake-up enable register 0
starterp1: Reg<STARTERP1_SPEC>
0x214 - Start logic 0 pin wake-up enable register 1
pdsleepcfg: Reg<PDSLEEPCFG_SPEC>
0x230 - Deep-sleep configuration register
pdawakecfg: Reg<PDAWAKECFG_SPEC>
0x234 - Wake-up configuration register
pdruncfg: Reg<PDRUNCFG_SPEC>
0x238 - Power configuration register
device_id: Reg<DEVICE_ID_SPEC>
0x3f8 - Part ID register