Struct lpc845_pac::adc0::ctrl::CLKDIV_W

pub struct CLKDIV_W<'a> { /* fields omitted */ }

Field CLKDIV writer - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.

Implementations

impl<'a> CLKDIV_W<'a>

pub unsafe fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field