1#[doc = "Register `CTCR` reader"]
2pub struct R(crate::R<CTCR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTCR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTCR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTCR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTCR` writer"]
17pub struct W(crate::W<CTCR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTCR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTCR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTCR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum CTMODE_A {
41 #[doc = "0: Timer Mode. Incremented every rising APB bus clock edge."]
42 TIMER = 0,
43 #[doc = "1: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2."]
44 COUNTER_RISING_EDGE = 1,
45 #[doc = "2: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2."]
46 COUNTER_FALLING_EDGE = 2,
47 #[doc = "3: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2."]
48 COUNTER_DUAL_EDGE = 3,
49}
50impl From<CTMODE_A> for u8 {
51 #[inline(always)]
52 fn from(variant: CTMODE_A) -> Self {
53 variant as _
54 }
55}
56#[doc = "Field `CTMODE` reader - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
57pub struct CTMODE_R(crate::FieldReader<u8, CTMODE_A>);
58impl CTMODE_R {
59 pub(crate) fn new(bits: u8) -> Self {
60 CTMODE_R(crate::FieldReader::new(bits))
61 }
62 #[doc = r"Get enumerated values variant"]
63 #[inline(always)]
64 pub fn variant(&self) -> CTMODE_A {
65 match self.bits {
66 0 => CTMODE_A::TIMER,
67 1 => CTMODE_A::COUNTER_RISING_EDGE,
68 2 => CTMODE_A::COUNTER_FALLING_EDGE,
69 3 => CTMODE_A::COUNTER_DUAL_EDGE,
70 _ => unreachable!(),
71 }
72 }
73 #[doc = "Checks if the value of the field is `TIMER`"]
74 #[inline(always)]
75 pub fn is_timer(&self) -> bool {
76 **self == CTMODE_A::TIMER
77 }
78 #[doc = "Checks if the value of the field is `COUNTER_RISING_EDGE`"]
79 #[inline(always)]
80 pub fn is_counter_rising_edge(&self) -> bool {
81 **self == CTMODE_A::COUNTER_RISING_EDGE
82 }
83 #[doc = "Checks if the value of the field is `COUNTER_FALLING_EDGE`"]
84 #[inline(always)]
85 pub fn is_counter_falling_edge(&self) -> bool {
86 **self == CTMODE_A::COUNTER_FALLING_EDGE
87 }
88 #[doc = "Checks if the value of the field is `COUNTER_DUAL_EDGE`"]
89 #[inline(always)]
90 pub fn is_counter_dual_edge(&self) -> bool {
91 **self == CTMODE_A::COUNTER_DUAL_EDGE
92 }
93}
94impl core::ops::Deref for CTMODE_R {
95 type Target = crate::FieldReader<u8, CTMODE_A>;
96 #[inline(always)]
97 fn deref(&self) -> &Self::Target {
98 &self.0
99 }
100}
101#[doc = "Field `CTMODE` writer - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
102pub struct CTMODE_W<'a> {
103 w: &'a mut W,
104}
105impl<'a> CTMODE_W<'a> {
106 #[doc = r"Writes `variant` to the field"]
107 #[inline(always)]
108 pub fn variant(self, variant: CTMODE_A) -> &'a mut W {
109 self.bits(variant.into())
110 }
111 #[doc = "Timer Mode. Incremented every rising APB bus clock edge."]
112 #[inline(always)]
113 pub fn timer(self) -> &'a mut W {
114 self.variant(CTMODE_A::TIMER)
115 }
116 #[doc = "Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2."]
117 #[inline(always)]
118 pub fn counter_rising_edge(self) -> &'a mut W {
119 self.variant(CTMODE_A::COUNTER_RISING_EDGE)
120 }
121 #[doc = "Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2."]
122 #[inline(always)]
123 pub fn counter_falling_edge(self) -> &'a mut W {
124 self.variant(CTMODE_A::COUNTER_FALLING_EDGE)
125 }
126 #[doc = "Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2."]
127 #[inline(always)]
128 pub fn counter_dual_edge(self) -> &'a mut W {
129 self.variant(CTMODE_A::COUNTER_DUAL_EDGE)
130 }
131 #[doc = r"Writes raw bits to the field"]
132 #[inline(always)]
133 pub fn bits(self, value: u8) -> &'a mut W {
134 self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
135 self.w
136 }
137}
138#[doc = "Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.\n\nValue on reset: 0"]
139#[derive(Clone, Copy, Debug, PartialEq)]
140#[repr(u8)]
141pub enum CINSEL_A {
142 #[doc = "0: Channel 0. CAPn.0 for CTIMERn"]
143 CHANNEL_0 = 0,
144 #[doc = "1: Channel 1. CAPn.1 for CTIMERn"]
145 CHANNEL_1 = 1,
146 #[doc = "2: Channel 2. CAPn.2 for CTIMERn"]
147 CHANNEL_2 = 2,
148 #[doc = "3: Channel 3. CAPn.3 for CTIMERn"]
149 CHANNEL_3 = 3,
150}
151impl From<CINSEL_A> for u8 {
152 #[inline(always)]
153 fn from(variant: CINSEL_A) -> Self {
154 variant as _
155 }
156}
157#[doc = "Field `CINSEL` reader - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
158pub struct CINSEL_R(crate::FieldReader<u8, CINSEL_A>);
159impl CINSEL_R {
160 pub(crate) fn new(bits: u8) -> Self {
161 CINSEL_R(crate::FieldReader::new(bits))
162 }
163 #[doc = r"Get enumerated values variant"]
164 #[inline(always)]
165 pub fn variant(&self) -> CINSEL_A {
166 match self.bits {
167 0 => CINSEL_A::CHANNEL_0,
168 1 => CINSEL_A::CHANNEL_1,
169 2 => CINSEL_A::CHANNEL_2,
170 3 => CINSEL_A::CHANNEL_3,
171 _ => unreachable!(),
172 }
173 }
174 #[doc = "Checks if the value of the field is `CHANNEL_0`"]
175 #[inline(always)]
176 pub fn is_channel_0(&self) -> bool {
177 **self == CINSEL_A::CHANNEL_0
178 }
179 #[doc = "Checks if the value of the field is `CHANNEL_1`"]
180 #[inline(always)]
181 pub fn is_channel_1(&self) -> bool {
182 **self == CINSEL_A::CHANNEL_1
183 }
184 #[doc = "Checks if the value of the field is `CHANNEL_2`"]
185 #[inline(always)]
186 pub fn is_channel_2(&self) -> bool {
187 **self == CINSEL_A::CHANNEL_2
188 }
189 #[doc = "Checks if the value of the field is `CHANNEL_3`"]
190 #[inline(always)]
191 pub fn is_channel_3(&self) -> bool {
192 **self == CINSEL_A::CHANNEL_3
193 }
194}
195impl core::ops::Deref for CINSEL_R {
196 type Target = crate::FieldReader<u8, CINSEL_A>;
197 #[inline(always)]
198 fn deref(&self) -> &Self::Target {
199 &self.0
200 }
201}
202#[doc = "Field `CINSEL` writer - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
203pub struct CINSEL_W<'a> {
204 w: &'a mut W,
205}
206impl<'a> CINSEL_W<'a> {
207 #[doc = r"Writes `variant` to the field"]
208 #[inline(always)]
209 pub fn variant(self, variant: CINSEL_A) -> &'a mut W {
210 self.bits(variant.into())
211 }
212 #[doc = "Channel 0. CAPn.0 for CTIMERn"]
213 #[inline(always)]
214 pub fn channel_0(self) -> &'a mut W {
215 self.variant(CINSEL_A::CHANNEL_0)
216 }
217 #[doc = "Channel 1. CAPn.1 for CTIMERn"]
218 #[inline(always)]
219 pub fn channel_1(self) -> &'a mut W {
220 self.variant(CINSEL_A::CHANNEL_1)
221 }
222 #[doc = "Channel 2. CAPn.2 for CTIMERn"]
223 #[inline(always)]
224 pub fn channel_2(self) -> &'a mut W {
225 self.variant(CINSEL_A::CHANNEL_2)
226 }
227 #[doc = "Channel 3. CAPn.3 for CTIMERn"]
228 #[inline(always)]
229 pub fn channel_3(self) -> &'a mut W {
230 self.variant(CINSEL_A::CHANNEL_3)
231 }
232 #[doc = r"Writes raw bits to the field"]
233 #[inline(always)]
234 pub fn bits(self, value: u8) -> &'a mut W {
235 self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
236 self.w
237 }
238}
239#[doc = "Field `ENCC` reader - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
240pub struct ENCC_R(crate::FieldReader<bool, bool>);
241impl ENCC_R {
242 pub(crate) fn new(bits: bool) -> Self {
243 ENCC_R(crate::FieldReader::new(bits))
244 }
245}
246impl core::ops::Deref for ENCC_R {
247 type Target = crate::FieldReader<bool, bool>;
248 #[inline(always)]
249 fn deref(&self) -> &Self::Target {
250 &self.0
251 }
252}
253#[doc = "Field `ENCC` writer - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
254pub struct ENCC_W<'a> {
255 w: &'a mut W,
256}
257impl<'a> ENCC_W<'a> {
258 #[doc = r"Sets the field bit"]
259 #[inline(always)]
260 pub fn set_bit(self) -> &'a mut W {
261 self.bit(true)
262 }
263 #[doc = r"Clears the field bit"]
264 #[inline(always)]
265 pub fn clear_bit(self) -> &'a mut W {
266 self.bit(false)
267 }
268 #[doc = r"Writes raw bits to the field"]
269 #[inline(always)]
270 pub fn bit(self, value: bool) -> &'a mut W {
271 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
272 self.w
273 }
274}
275#[doc = "Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.\n\nValue on reset: 0"]
276#[derive(Clone, Copy, Debug, PartialEq)]
277#[repr(u8)]
278pub enum SELCC_A {
279 #[doc = "0: Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set)."]
280 CHANNEL_0_RISING = 0,
281 #[doc = "1: Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set)."]
282 CHANNEL_0_FALLING = 1,
283 #[doc = "2: Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set)."]
284 CHANNEL_1_RISING = 2,
285 #[doc = "3: Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set)."]
286 CHANNEL_1_FALLING = 3,
287 #[doc = "4: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
288 CHANNEL_2_RISING = 4,
289 #[doc = "5: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
290 CHANNEL_2_FALLING = 5,
291 #[doc = "6: Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
292 CHANNEL_3_RISING = 6,
293 #[doc = "7: Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
294 CHANNEL_3_FALLING = 7,
295}
296impl From<SELCC_A> for u8 {
297 #[inline(always)]
298 fn from(variant: SELCC_A) -> Self {
299 variant as _
300 }
301}
302#[doc = "Field `SELCC` reader - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."]
303pub struct SELCC_R(crate::FieldReader<u8, SELCC_A>);
304impl SELCC_R {
305 pub(crate) fn new(bits: u8) -> Self {
306 SELCC_R(crate::FieldReader::new(bits))
307 }
308 #[doc = r"Get enumerated values variant"]
309 #[inline(always)]
310 pub fn variant(&self) -> SELCC_A {
311 match self.bits {
312 0 => SELCC_A::CHANNEL_0_RISING,
313 1 => SELCC_A::CHANNEL_0_FALLING,
314 2 => SELCC_A::CHANNEL_1_RISING,
315 3 => SELCC_A::CHANNEL_1_FALLING,
316 4 => SELCC_A::CHANNEL_2_RISING,
317 5 => SELCC_A::CHANNEL_2_FALLING,
318 6 => SELCC_A::CHANNEL_3_RISING,
319 7 => SELCC_A::CHANNEL_3_FALLING,
320 _ => unreachable!(),
321 }
322 }
323 #[doc = "Checks if the value of the field is `CHANNEL_0_RISING`"]
324 #[inline(always)]
325 pub fn is_channel_0_rising(&self) -> bool {
326 **self == SELCC_A::CHANNEL_0_RISING
327 }
328 #[doc = "Checks if the value of the field is `CHANNEL_0_FALLING`"]
329 #[inline(always)]
330 pub fn is_channel_0_falling(&self) -> bool {
331 **self == SELCC_A::CHANNEL_0_FALLING
332 }
333 #[doc = "Checks if the value of the field is `CHANNEL_1_RISING`"]
334 #[inline(always)]
335 pub fn is_channel_1_rising(&self) -> bool {
336 **self == SELCC_A::CHANNEL_1_RISING
337 }
338 #[doc = "Checks if the value of the field is `CHANNEL_1_FALLING`"]
339 #[inline(always)]
340 pub fn is_channel_1_falling(&self) -> bool {
341 **self == SELCC_A::CHANNEL_1_FALLING
342 }
343 #[doc = "Checks if the value of the field is `CHANNEL_2_RISING`"]
344 #[inline(always)]
345 pub fn is_channel_2_rising(&self) -> bool {
346 **self == SELCC_A::CHANNEL_2_RISING
347 }
348 #[doc = "Checks if the value of the field is `CHANNEL_2_FALLING`"]
349 #[inline(always)]
350 pub fn is_channel_2_falling(&self) -> bool {
351 **self == SELCC_A::CHANNEL_2_FALLING
352 }
353 #[doc = "Checks if the value of the field is `CHANNEL_3_RISING`"]
354 #[inline(always)]
355 pub fn is_channel_3_rising(&self) -> bool {
356 **self == SELCC_A::CHANNEL_3_RISING
357 }
358 #[doc = "Checks if the value of the field is `CHANNEL_3_FALLING`"]
359 #[inline(always)]
360 pub fn is_channel_3_falling(&self) -> bool {
361 **self == SELCC_A::CHANNEL_3_FALLING
362 }
363}
364impl core::ops::Deref for SELCC_R {
365 type Target = crate::FieldReader<u8, SELCC_A>;
366 #[inline(always)]
367 fn deref(&self) -> &Self::Target {
368 &self.0
369 }
370}
371#[doc = "Field `SELCC` writer - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."]
372pub struct SELCC_W<'a> {
373 w: &'a mut W,
374}
375impl<'a> SELCC_W<'a> {
376 #[doc = r"Writes `variant` to the field"]
377 #[inline(always)]
378 pub fn variant(self, variant: SELCC_A) -> &'a mut W {
379 self.bits(variant.into())
380 }
381 #[doc = "Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set)."]
382 #[inline(always)]
383 pub fn channel_0_rising(self) -> &'a mut W {
384 self.variant(SELCC_A::CHANNEL_0_RISING)
385 }
386 #[doc = "Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set)."]
387 #[inline(always)]
388 pub fn channel_0_falling(self) -> &'a mut W {
389 self.variant(SELCC_A::CHANNEL_0_FALLING)
390 }
391 #[doc = "Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set)."]
392 #[inline(always)]
393 pub fn channel_1_rising(self) -> &'a mut W {
394 self.variant(SELCC_A::CHANNEL_1_RISING)
395 }
396 #[doc = "Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set)."]
397 #[inline(always)]
398 pub fn channel_1_falling(self) -> &'a mut W {
399 self.variant(SELCC_A::CHANNEL_1_FALLING)
400 }
401 #[doc = "Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
402 #[inline(always)]
403 pub fn channel_2_rising(self) -> &'a mut W {
404 self.variant(SELCC_A::CHANNEL_2_RISING)
405 }
406 #[doc = "Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
407 #[inline(always)]
408 pub fn channel_2_falling(self) -> &'a mut W {
409 self.variant(SELCC_A::CHANNEL_2_FALLING)
410 }
411 #[doc = "Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
412 #[inline(always)]
413 pub fn channel_3_rising(self) -> &'a mut W {
414 self.variant(SELCC_A::CHANNEL_3_RISING)
415 }
416 #[doc = "Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set)."]
417 #[inline(always)]
418 pub fn channel_3_falling(self) -> &'a mut W {
419 self.variant(SELCC_A::CHANNEL_3_FALLING)
420 }
421 #[doc = r"Writes raw bits to the field"]
422 #[inline(always)]
423 pub fn bits(self, value: u8) -> &'a mut W {
424 self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5);
425 self.w
426 }
427}
428impl R {
429 #[doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
430 #[inline(always)]
431 pub fn ctmode(&self) -> CTMODE_R {
432 CTMODE_R::new((self.bits & 0x03) as u8)
433 }
434 #[doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
435 #[inline(always)]
436 pub fn cinsel(&self) -> CINSEL_R {
437 CINSEL_R::new(((self.bits >> 2) & 0x03) as u8)
438 }
439 #[doc = "Bit 4 - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
440 #[inline(always)]
441 pub fn encc(&self) -> ENCC_R {
442 ENCC_R::new(((self.bits >> 4) & 0x01) != 0)
443 }
444 #[doc = "Bits 5:7 - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."]
445 #[inline(always)]
446 pub fn selcc(&self) -> SELCC_R {
447 SELCC_R::new(((self.bits >> 5) & 0x07) as u8)
448 }
449}
450impl W {
451 #[doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
452 #[inline(always)]
453 pub fn ctmode(&mut self) -> CTMODE_W {
454 CTMODE_W { w: self }
455 }
456 #[doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
457 #[inline(always)]
458 pub fn cinsel(&mut self) -> CINSEL_W {
459 CINSEL_W { w: self }
460 }
461 #[doc = "Bit 4 - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
462 #[inline(always)]
463 pub fn encc(&mut self) -> ENCC_W {
464 ENCC_W { w: self }
465 }
466 #[doc = "Bits 5:7 - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."]
467 #[inline(always)]
468 pub fn selcc(&mut self) -> SELCC_W {
469 SELCC_W { w: self }
470 }
471 #[doc = "Writes raw bits to the register."]
472 #[inline(always)]
473 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
474 self.0.bits(bits);
475 self
476 }
477}
478#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctcr](index.html) module"]
479pub struct CTCR_SPEC;
480impl crate::RegisterSpec for CTCR_SPEC {
481 type Ux = u32;
482}
483#[doc = "`read()` method returns [ctcr::R](R) reader structure"]
484impl crate::Readable for CTCR_SPEC {
485 type Reader = R;
486}
487#[doc = "`write(|w| ..)` method takes [ctcr::W](W) writer structure"]
488impl crate::Writable for CTCR_SPEC {
489 type Writer = W;
490}
491#[doc = "`reset()` method sets CTCR to value 0"]
492impl crate::Resettable for CTCR_SPEC {
493 #[inline(always)]
494 fn reset_value() -> Self::Ux {
495 0
496 }
497}