1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CLKDIV` reader - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
38pub struct CLKDIV_R(crate::FieldReader<u8, u8>);
39impl CLKDIV_R {
40 pub(crate) fn new(bits: u8) -> Self {
41 CLKDIV_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for CLKDIV_R {
45 type Target = crate::FieldReader<u8, u8>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `CLKDIV` writer - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
52pub struct CLKDIV_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> CLKDIV_W<'a> {
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub unsafe fn bits(self, value: u8) -> &'a mut W {
59 self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
60 self.w
61 }
62}
63#[doc = "Select clock mode.\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq)]
65pub enum ASYNMODE_A {
66 #[doc = "0: Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse."]
67 SYNCHRONOUS_MODE = 0,
68 #[doc = "1: Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block."]
69 ASYNCHRONOUS_MODE = 1,
70}
71impl From<ASYNMODE_A> for bool {
72 #[inline(always)]
73 fn from(variant: ASYNMODE_A) -> Self {
74 variant as u8 != 0
75 }
76}
77#[doc = "Field `ASYNMODE` reader - Select clock mode."]
78pub struct ASYNMODE_R(crate::FieldReader<bool, ASYNMODE_A>);
79impl ASYNMODE_R {
80 pub(crate) fn new(bits: bool) -> Self {
81 ASYNMODE_R(crate::FieldReader::new(bits))
82 }
83 #[doc = r"Get enumerated values variant"]
84 #[inline(always)]
85 pub fn variant(&self) -> ASYNMODE_A {
86 match self.bits {
87 false => ASYNMODE_A::SYNCHRONOUS_MODE,
88 true => ASYNMODE_A::ASYNCHRONOUS_MODE,
89 }
90 }
91 #[doc = "Checks if the value of the field is `SYNCHRONOUS_MODE`"]
92 #[inline(always)]
93 pub fn is_synchronous_mode(&self) -> bool {
94 **self == ASYNMODE_A::SYNCHRONOUS_MODE
95 }
96 #[doc = "Checks if the value of the field is `ASYNCHRONOUS_MODE`"]
97 #[inline(always)]
98 pub fn is_asynchronous_mode(&self) -> bool {
99 **self == ASYNMODE_A::ASYNCHRONOUS_MODE
100 }
101}
102impl core::ops::Deref for ASYNMODE_R {
103 type Target = crate::FieldReader<bool, ASYNMODE_A>;
104 #[inline(always)]
105 fn deref(&self) -> &Self::Target {
106 &self.0
107 }
108}
109#[doc = "Field `ASYNMODE` writer - Select clock mode."]
110pub struct ASYNMODE_W<'a> {
111 w: &'a mut W,
112}
113impl<'a> ASYNMODE_W<'a> {
114 #[doc = r"Writes `variant` to the field"]
115 #[inline(always)]
116 pub fn variant(self, variant: ASYNMODE_A) -> &'a mut W {
117 self.bit(variant.into())
118 }
119 #[doc = "Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse."]
120 #[inline(always)]
121 pub fn synchronous_mode(self) -> &'a mut W {
122 self.variant(ASYNMODE_A::SYNCHRONOUS_MODE)
123 }
124 #[doc = "Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block."]
125 #[inline(always)]
126 pub fn asynchronous_mode(self) -> &'a mut W {
127 self.variant(ASYNMODE_A::ASYNCHRONOUS_MODE)
128 }
129 #[doc = r"Sets the field bit"]
130 #[inline(always)]
131 pub fn set_bit(self) -> &'a mut W {
132 self.bit(true)
133 }
134 #[doc = r"Clears the field bit"]
135 #[inline(always)]
136 pub fn clear_bit(self) -> &'a mut W {
137 self.bit(false)
138 }
139 #[doc = r"Writes raw bits to the field"]
140 #[inline(always)]
141 pub fn bit(self, value: bool) -> &'a mut W {
142 self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
143 self.w
144 }
145}
146#[doc = "The low-power ADC mode\n\nValue on reset: 0"]
147#[derive(Clone, Copy, Debug, PartialEq)]
148pub enum LPWRMODE_A {
149 #[doc = "0: The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested."]
150 LPWRMODE_0 = 0,
151 #[doc = "1: The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low."]
152 LPWRMODE_1 = 1,
153}
154impl From<LPWRMODE_A> for bool {
155 #[inline(always)]
156 fn from(variant: LPWRMODE_A) -> Self {
157 variant as u8 != 0
158 }
159}
160#[doc = "Field `LPWRMODE` reader - The low-power ADC mode"]
161pub struct LPWRMODE_R(crate::FieldReader<bool, LPWRMODE_A>);
162impl LPWRMODE_R {
163 pub(crate) fn new(bits: bool) -> Self {
164 LPWRMODE_R(crate::FieldReader::new(bits))
165 }
166 #[doc = r"Get enumerated values variant"]
167 #[inline(always)]
168 pub fn variant(&self) -> LPWRMODE_A {
169 match self.bits {
170 false => LPWRMODE_A::LPWRMODE_0,
171 true => LPWRMODE_A::LPWRMODE_1,
172 }
173 }
174 #[doc = "Checks if the value of the field is `LPWRMODE_0`"]
175 #[inline(always)]
176 pub fn is_lpwrmode_0(&self) -> bool {
177 **self == LPWRMODE_A::LPWRMODE_0
178 }
179 #[doc = "Checks if the value of the field is `LPWRMODE_1`"]
180 #[inline(always)]
181 pub fn is_lpwrmode_1(&self) -> bool {
182 **self == LPWRMODE_A::LPWRMODE_1
183 }
184}
185impl core::ops::Deref for LPWRMODE_R {
186 type Target = crate::FieldReader<bool, LPWRMODE_A>;
187 #[inline(always)]
188 fn deref(&self) -> &Self::Target {
189 &self.0
190 }
191}
192#[doc = "Field `LPWRMODE` writer - The low-power ADC mode"]
193pub struct LPWRMODE_W<'a> {
194 w: &'a mut W,
195}
196impl<'a> LPWRMODE_W<'a> {
197 #[doc = r"Writes `variant` to the field"]
198 #[inline(always)]
199 pub fn variant(self, variant: LPWRMODE_A) -> &'a mut W {
200 self.bit(variant.into())
201 }
202 #[doc = "The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested."]
203 #[inline(always)]
204 pub fn lpwrmode_0(self) -> &'a mut W {
205 self.variant(LPWRMODE_A::LPWRMODE_0)
206 }
207 #[doc = "The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low."]
208 #[inline(always)]
209 pub fn lpwrmode_1(self) -> &'a mut W {
210 self.variant(LPWRMODE_A::LPWRMODE_1)
211 }
212 #[doc = r"Sets the field bit"]
213 #[inline(always)]
214 pub fn set_bit(self) -> &'a mut W {
215 self.bit(true)
216 }
217 #[doc = r"Clears the field bit"]
218 #[inline(always)]
219 pub fn clear_bit(self) -> &'a mut W {
220 self.bit(false)
221 }
222 #[doc = r"Writes raw bits to the field"]
223 #[inline(always)]
224 pub fn bit(self, value: bool) -> &'a mut W {
225 self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
226 self.w
227 }
228}
229#[doc = "Field `CALMODE` reader - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
230pub struct CALMODE_R(crate::FieldReader<bool, bool>);
231impl CALMODE_R {
232 pub(crate) fn new(bits: bool) -> Self {
233 CALMODE_R(crate::FieldReader::new(bits))
234 }
235}
236impl core::ops::Deref for CALMODE_R {
237 type Target = crate::FieldReader<bool, bool>;
238 #[inline(always)]
239 fn deref(&self) -> &Self::Target {
240 &self.0
241 }
242}
243#[doc = "Field `CALMODE` writer - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
244pub struct CALMODE_W<'a> {
245 w: &'a mut W,
246}
247impl<'a> CALMODE_W<'a> {
248 #[doc = r"Sets the field bit"]
249 #[inline(always)]
250 pub fn set_bit(self) -> &'a mut W {
251 self.bit(true)
252 }
253 #[doc = r"Clears the field bit"]
254 #[inline(always)]
255 pub fn clear_bit(self) -> &'a mut W {
256 self.bit(false)
257 }
258 #[doc = r"Writes raw bits to the field"]
259 #[inline(always)]
260 pub fn bit(self, value: bool) -> &'a mut W {
261 self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
262 self.w
263 }
264}
265impl R {
266 #[doc = "Bits 0:7 - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
267 #[inline(always)]
268 pub fn clkdiv(&self) -> CLKDIV_R {
269 CLKDIV_R::new((self.bits & 0xff) as u8)
270 }
271 #[doc = "Bit 8 - Select clock mode."]
272 #[inline(always)]
273 pub fn asynmode(&self) -> ASYNMODE_R {
274 ASYNMODE_R::new(((self.bits >> 8) & 0x01) != 0)
275 }
276 #[doc = "Bit 10 - The low-power ADC mode"]
277 #[inline(always)]
278 pub fn lpwrmode(&self) -> LPWRMODE_R {
279 LPWRMODE_R::new(((self.bits >> 10) & 0x01) != 0)
280 }
281 #[doc = "Bit 30 - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
282 #[inline(always)]
283 pub fn calmode(&self) -> CALMODE_R {
284 CALMODE_R::new(((self.bits >> 30) & 0x01) != 0)
285 }
286}
287impl W {
288 #[doc = "Bits 0:7 - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
289 #[inline(always)]
290 pub fn clkdiv(&mut self) -> CLKDIV_W {
291 CLKDIV_W { w: self }
292 }
293 #[doc = "Bit 8 - Select clock mode."]
294 #[inline(always)]
295 pub fn asynmode(&mut self) -> ASYNMODE_W {
296 ASYNMODE_W { w: self }
297 }
298 #[doc = "Bit 10 - The low-power ADC mode"]
299 #[inline(always)]
300 pub fn lpwrmode(&mut self) -> LPWRMODE_W {
301 LPWRMODE_W { w: self }
302 }
303 #[doc = "Bit 30 - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
304 #[inline(always)]
305 pub fn calmode(&mut self) -> CALMODE_W {
306 CALMODE_W { w: self }
307 }
308 #[doc = "Writes raw bits to the register."]
309 #[inline(always)]
310 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
311 self.0.bits(bits);
312 self
313 }
314}
315#[doc = "ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
316pub struct CTRL_SPEC;
317impl crate::RegisterSpec for CTRL_SPEC {
318 type Ux = u32;
319}
320#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
321impl crate::Readable for CTRL_SPEC {
322 type Reader = R;
323}
324#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
325impl crate::Writable for CTRL_SPEC {
326 type Writer = W;
327}
328#[doc = "`reset()` method sets CTRL to value 0"]
329impl crate::Resettable for CTRL_SPEC {
330 #[inline(always)]
331 fn reset_value() -> Self::Ux {
332 0
333 }
334}