lpc845_pac/gpio/
dir.rs

1#[doc = "Register `DIR[%s]` reader"]
2pub struct R(crate::R<DIR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIR[%s]` writer"]
17pub struct W(crate::W<DIR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DIRP` reader - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."]
38pub struct DIRP_R(crate::FieldReader<u32, u32>);
39impl DIRP_R {
40    pub(crate) fn new(bits: u32) -> Self {
41        DIRP_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for DIRP_R {
45    type Target = crate::FieldReader<u32, u32>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `DIRP` writer - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."]
52pub struct DIRP_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> DIRP_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u32) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff);
60        self.w
61    }
62}
63impl R {
64    #[doc = "Bits 0:31 - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."]
65    #[inline(always)]
66    pub fn dirp(&self) -> DIRP_R {
67        DIRP_R::new((self.bits & 0xffff_ffff) as u32)
68    }
69}
70impl W {
71    #[doc = "Bits 0:31 - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output."]
72    #[inline(always)]
73    pub fn dirp(&mut self) -> DIRP_W {
74        DIRP_W { w: self }
75    }
76    #[doc = "Writes raw bits to the register."]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.0.bits(bits);
80        self
81    }
82}
83#[doc = "Direction registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"]
84pub struct DIR_SPEC;
85impl crate::RegisterSpec for DIR_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [dir::R](R) reader structure"]
89impl crate::Readable for DIR_SPEC {
90    type Reader = R;
91}
92#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"]
93impl crate::Writable for DIR_SPEC {
94    type Writer = W;
95}
96#[doc = "`reset()` method sets DIR[%s]
97to value 0"]
98impl crate::Resettable for DIR_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
lpc845_pac/gpio/dir.rs

lpc845_pac/gpio/
dir.rs
