1#[doc = "Register `TXDATCTL` reader"]
2pub struct R(crate::R<TXDATCTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<TXDATCTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<TXDATCTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<TXDATCTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `TXDATCTL` writer"]
17pub struct W(crate::W<TXDATCTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<TXDATCTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<TXDATCTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<TXDATCTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TXDAT` reader - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."]
38pub struct TXDAT_R(crate::FieldReader<u16, u16>);
39impl TXDAT_R {
40 pub(crate) fn new(bits: u16) -> Self {
41 TXDAT_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for TXDAT_R {
45 type Target = crate::FieldReader<u16, u16>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `TXDAT` writer - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."]
52pub struct TXDAT_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> TXDAT_W<'a> {
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub unsafe fn bits(self, value: u16) -> &'a mut W {
59 self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
60 self.w
61 }
62}
63#[doc = "Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq)]
65pub enum TXSSEL0_N_A {
66 #[doc = "0: SSEL0 asserted."]
67 TXSSEL0_N_0 = 0,
68 #[doc = "1: SSEL0 not asserted."]
69 TXSSEL0_N_1 = 1,
70}
71impl From<TXSSEL0_N_A> for bool {
72 #[inline(always)]
73 fn from(variant: TXSSEL0_N_A) -> Self {
74 variant as u8 != 0
75 }
76}
77#[doc = "Field `TXSSEL0_N` reader - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register."]
78pub struct TXSSEL0_N_R(crate::FieldReader<bool, TXSSEL0_N_A>);
79impl TXSSEL0_N_R {
80 pub(crate) fn new(bits: bool) -> Self {
81 TXSSEL0_N_R(crate::FieldReader::new(bits))
82 }
83 #[doc = r"Get enumerated values variant"]
84 #[inline(always)]
85 pub fn variant(&self) -> TXSSEL0_N_A {
86 match self.bits {
87 false => TXSSEL0_N_A::TXSSEL0_N_0,
88 true => TXSSEL0_N_A::TXSSEL0_N_1,
89 }
90 }
91 #[doc = "Checks if the value of the field is `TXSSEL0_N_0`"]
92 #[inline(always)]
93 pub fn is_txssel0_n_0(&self) -> bool {
94 **self == TXSSEL0_N_A::TXSSEL0_N_0
95 }
96 #[doc = "Checks if the value of the field is `TXSSEL0_N_1`"]
97 #[inline(always)]
98 pub fn is_txssel0_n_1(&self) -> bool {
99 **self == TXSSEL0_N_A::TXSSEL0_N_1
100 }
101}
102impl core::ops::Deref for TXSSEL0_N_R {
103 type Target = crate::FieldReader<bool, TXSSEL0_N_A>;
104 #[inline(always)]
105 fn deref(&self) -> &Self::Target {
106 &self.0
107 }
108}
109#[doc = "Field `TXSSEL0_N` writer - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register."]
110pub struct TXSSEL0_N_W<'a> {
111 w: &'a mut W,
112}
113impl<'a> TXSSEL0_N_W<'a> {
114 #[doc = r"Writes `variant` to the field"]
115 #[inline(always)]
116 pub fn variant(self, variant: TXSSEL0_N_A) -> &'a mut W {
117 self.bit(variant.into())
118 }
119 #[doc = "SSEL0 asserted."]
120 #[inline(always)]
121 pub fn txssel0_n_0(self) -> &'a mut W {
122 self.variant(TXSSEL0_N_A::TXSSEL0_N_0)
123 }
124 #[doc = "SSEL0 not asserted."]
125 #[inline(always)]
126 pub fn txssel0_n_1(self) -> &'a mut W {
127 self.variant(TXSSEL0_N_A::TXSSEL0_N_1)
128 }
129 #[doc = r"Sets the field bit"]
130 #[inline(always)]
131 pub fn set_bit(self) -> &'a mut W {
132 self.bit(true)
133 }
134 #[doc = r"Clears the field bit"]
135 #[inline(always)]
136 pub fn clear_bit(self) -> &'a mut W {
137 self.bit(false)
138 }
139 #[doc = r"Writes raw bits to the field"]
140 #[inline(always)]
141 pub fn bit(self, value: bool) -> &'a mut W {
142 self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
143 self.w
144 }
145}
146#[doc = "Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.\n\nValue on reset: 0"]
147#[derive(Clone, Copy, Debug, PartialEq)]
148pub enum TXSSEL1_N_A {
149 #[doc = "0: SSEL1 asserted."]
150 TXSSEL1_N_0 = 0,
151 #[doc = "1: SSEL1 not asserted."]
152 TXSSEL1_N_1 = 1,
153}
154impl From<TXSSEL1_N_A> for bool {
155 #[inline(always)]
156 fn from(variant: TXSSEL1_N_A) -> Self {
157 variant as u8 != 0
158 }
159}
160#[doc = "Field `TXSSEL1_N` reader - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register."]
161pub struct TXSSEL1_N_R(crate::FieldReader<bool, TXSSEL1_N_A>);
162impl TXSSEL1_N_R {
163 pub(crate) fn new(bits: bool) -> Self {
164 TXSSEL1_N_R(crate::FieldReader::new(bits))
165 }
166 #[doc = r"Get enumerated values variant"]
167 #[inline(always)]
168 pub fn variant(&self) -> TXSSEL1_N_A {
169 match self.bits {
170 false => TXSSEL1_N_A::TXSSEL1_N_0,
171 true => TXSSEL1_N_A::TXSSEL1_N_1,
172 }
173 }
174 #[doc = "Checks if the value of the field is `TXSSEL1_N_0`"]
175 #[inline(always)]
176 pub fn is_txssel1_n_0(&self) -> bool {
177 **self == TXSSEL1_N_A::TXSSEL1_N_0
178 }
179 #[doc = "Checks if the value of the field is `TXSSEL1_N_1`"]
180 #[inline(always)]
181 pub fn is_txssel1_n_1(&self) -> bool {
182 **self == TXSSEL1_N_A::TXSSEL1_N_1
183 }
184}
185impl core::ops::Deref for TXSSEL1_N_R {
186 type Target = crate::FieldReader<bool, TXSSEL1_N_A>;
187 #[inline(always)]
188 fn deref(&self) -> &Self::Target {
189 &self.0
190 }
191}
192#[doc = "Field `TXSSEL1_N` writer - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register."]
193pub struct TXSSEL1_N_W<'a> {
194 w: &'a mut W,
195}
196impl<'a> TXSSEL1_N_W<'a> {
197 #[doc = r"Writes `variant` to the field"]
198 #[inline(always)]
199 pub fn variant(self, variant: TXSSEL1_N_A) -> &'a mut W {
200 self.bit(variant.into())
201 }
202 #[doc = "SSEL1 asserted."]
203 #[inline(always)]
204 pub fn txssel1_n_0(self) -> &'a mut W {
205 self.variant(TXSSEL1_N_A::TXSSEL1_N_0)
206 }
207 #[doc = "SSEL1 not asserted."]
208 #[inline(always)]
209 pub fn txssel1_n_1(self) -> &'a mut W {
210 self.variant(TXSSEL1_N_A::TXSSEL1_N_1)
211 }
212 #[doc = r"Sets the field bit"]
213 #[inline(always)]
214 pub fn set_bit(self) -> &'a mut W {
215 self.bit(true)
216 }
217 #[doc = r"Clears the field bit"]
218 #[inline(always)]
219 pub fn clear_bit(self) -> &'a mut W {
220 self.bit(false)
221 }
222 #[doc = r"Writes raw bits to the field"]
223 #[inline(always)]
224 pub fn bit(self, value: bool) -> &'a mut W {
225 self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
226 self.w
227 }
228}
229#[doc = "Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register.\n\nValue on reset: 0"]
230#[derive(Clone, Copy, Debug, PartialEq)]
231pub enum TXSSEL2_N_A {
232 #[doc = "0: SSEL2 asserted."]
233 TXSSEL2_N_0 = 0,
234 #[doc = "1: SSEL2 not asserted."]
235 TXSSEL2_N_1 = 1,
236}
237impl From<TXSSEL2_N_A> for bool {
238 #[inline(always)]
239 fn from(variant: TXSSEL2_N_A) -> Self {
240 variant as u8 != 0
241 }
242}
243#[doc = "Field `TXSSEL2_N` reader - Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register."]
244pub struct TXSSEL2_N_R(crate::FieldReader<bool, TXSSEL2_N_A>);
245impl TXSSEL2_N_R {
246 pub(crate) fn new(bits: bool) -> Self {
247 TXSSEL2_N_R(crate::FieldReader::new(bits))
248 }
249 #[doc = r"Get enumerated values variant"]
250 #[inline(always)]
251 pub fn variant(&self) -> TXSSEL2_N_A {
252 match self.bits {
253 false => TXSSEL2_N_A::TXSSEL2_N_0,
254 true => TXSSEL2_N_A::TXSSEL2_N_1,
255 }
256 }
257 #[doc = "Checks if the value of the field is `TXSSEL2_N_0`"]
258 #[inline(always)]
259 pub fn is_txssel2_n_0(&self) -> bool {
260 **self == TXSSEL2_N_A::TXSSEL2_N_0
261 }
262 #[doc = "Checks if the value of the field is `TXSSEL2_N_1`"]
263 #[inline(always)]
264 pub fn is_txssel2_n_1(&self) -> bool {
265 **self == TXSSEL2_N_A::TXSSEL2_N_1
266 }
267}
268impl core::ops::Deref for TXSSEL2_N_R {
269 type Target = crate::FieldReader<bool, TXSSEL2_N_A>;
270 #[inline(always)]
271 fn deref(&self) -> &Self::Target {
272 &self.0
273 }
274}
275#[doc = "Field `TXSSEL2_N` writer - Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register."]
276pub struct TXSSEL2_N_W<'a> {
277 w: &'a mut W,
278}
279impl<'a> TXSSEL2_N_W<'a> {
280 #[doc = r"Writes `variant` to the field"]
281 #[inline(always)]
282 pub fn variant(self, variant: TXSSEL2_N_A) -> &'a mut W {
283 self.bit(variant.into())
284 }
285 #[doc = "SSEL2 asserted."]
286 #[inline(always)]
287 pub fn txssel2_n_0(self) -> &'a mut W {
288 self.variant(TXSSEL2_N_A::TXSSEL2_N_0)
289 }
290 #[doc = "SSEL2 not asserted."]
291 #[inline(always)]
292 pub fn txssel2_n_1(self) -> &'a mut W {
293 self.variant(TXSSEL2_N_A::TXSSEL2_N_1)
294 }
295 #[doc = r"Sets the field bit"]
296 #[inline(always)]
297 pub fn set_bit(self) -> &'a mut W {
298 self.bit(true)
299 }
300 #[doc = r"Clears the field bit"]
301 #[inline(always)]
302 pub fn clear_bit(self) -> &'a mut W {
303 self.bit(false)
304 }
305 #[doc = r"Writes raw bits to the field"]
306 #[inline(always)]
307 pub fn bit(self, value: bool) -> &'a mut W {
308 self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
309 self.w
310 }
311}
312#[doc = "Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register.\n\nValue on reset: 0"]
313#[derive(Clone, Copy, Debug, PartialEq)]
314pub enum TXSSEL3_N_A {
315 #[doc = "0: SSEL3 asserted."]
316 TXSSEL3_N_0 = 0,
317 #[doc = "1: SSEL3 not asserted."]
318 TXSSEL3_N_1 = 1,
319}
320impl From<TXSSEL3_N_A> for bool {
321 #[inline(always)]
322 fn from(variant: TXSSEL3_N_A) -> Self {
323 variant as u8 != 0
324 }
325}
326#[doc = "Field `TXSSEL3_N` reader - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register."]
327pub struct TXSSEL3_N_R(crate::FieldReader<bool, TXSSEL3_N_A>);
328impl TXSSEL3_N_R {
329 pub(crate) fn new(bits: bool) -> Self {
330 TXSSEL3_N_R(crate::FieldReader::new(bits))
331 }
332 #[doc = r"Get enumerated values variant"]
333 #[inline(always)]
334 pub fn variant(&self) -> TXSSEL3_N_A {
335 match self.bits {
336 false => TXSSEL3_N_A::TXSSEL3_N_0,
337 true => TXSSEL3_N_A::TXSSEL3_N_1,
338 }
339 }
340 #[doc = "Checks if the value of the field is `TXSSEL3_N_0`"]
341 #[inline(always)]
342 pub fn is_txssel3_n_0(&self) -> bool {
343 **self == TXSSEL3_N_A::TXSSEL3_N_0
344 }
345 #[doc = "Checks if the value of the field is `TXSSEL3_N_1`"]
346 #[inline(always)]
347 pub fn is_txssel3_n_1(&self) -> bool {
348 **self == TXSSEL3_N_A::TXSSEL3_N_1
349 }
350}
351impl core::ops::Deref for TXSSEL3_N_R {
352 type Target = crate::FieldReader<bool, TXSSEL3_N_A>;
353 #[inline(always)]
354 fn deref(&self) -> &Self::Target {
355 &self.0
356 }
357}
358#[doc = "Field `TXSSEL3_N` writer - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register."]
359pub struct TXSSEL3_N_W<'a> {
360 w: &'a mut W,
361}
362impl<'a> TXSSEL3_N_W<'a> {
363 #[doc = r"Writes `variant` to the field"]
364 #[inline(always)]
365 pub fn variant(self, variant: TXSSEL3_N_A) -> &'a mut W {
366 self.bit(variant.into())
367 }
368 #[doc = "SSEL3 asserted."]
369 #[inline(always)]
370 pub fn txssel3_n_0(self) -> &'a mut W {
371 self.variant(TXSSEL3_N_A::TXSSEL3_N_0)
372 }
373 #[doc = "SSEL3 not asserted."]
374 #[inline(always)]
375 pub fn txssel3_n_1(self) -> &'a mut W {
376 self.variant(TXSSEL3_N_A::TXSSEL3_N_1)
377 }
378 #[doc = r"Sets the field bit"]
379 #[inline(always)]
380 pub fn set_bit(self) -> &'a mut W {
381 self.bit(true)
382 }
383 #[doc = r"Clears the field bit"]
384 #[inline(always)]
385 pub fn clear_bit(self) -> &'a mut W {
386 self.bit(false)
387 }
388 #[doc = r"Writes raw bits to the field"]
389 #[inline(always)]
390 pub fn bit(self, value: bool) -> &'a mut W {
391 self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
392 self.w
393 }
394}
395#[doc = "End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.\n\nValue on reset: 0"]
396#[derive(Clone, Copy, Debug, PartialEq)]
397pub enum EOT_A {
398 #[doc = "0: This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data."]
399 SSEL_DEASSERTED = 0,
400 #[doc = "1: This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data."]
401 SSEL_NOT_DEASSERTED = 1,
402}
403impl From<EOT_A> for bool {
404 #[inline(always)]
405 fn from(variant: EOT_A) -> Self {
406 variant as u8 != 0
407 }
408}
409#[doc = "Field `EOT` reader - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register."]
410pub struct EOT_R(crate::FieldReader<bool, EOT_A>);
411impl EOT_R {
412 pub(crate) fn new(bits: bool) -> Self {
413 EOT_R(crate::FieldReader::new(bits))
414 }
415 #[doc = r"Get enumerated values variant"]
416 #[inline(always)]
417 pub fn variant(&self) -> EOT_A {
418 match self.bits {
419 false => EOT_A::SSEL_DEASSERTED,
420 true => EOT_A::SSEL_NOT_DEASSERTED,
421 }
422 }
423 #[doc = "Checks if the value of the field is `SSEL_DEASSERTED`"]
424 #[inline(always)]
425 pub fn is_ssel_deasserted(&self) -> bool {
426 **self == EOT_A::SSEL_DEASSERTED
427 }
428 #[doc = "Checks if the value of the field is `SSEL_NOT_DEASSERTED`"]
429 #[inline(always)]
430 pub fn is_ssel_not_deasserted(&self) -> bool {
431 **self == EOT_A::SSEL_NOT_DEASSERTED
432 }
433}
434impl core::ops::Deref for EOT_R {
435 type Target = crate::FieldReader<bool, EOT_A>;
436 #[inline(always)]
437 fn deref(&self) -> &Self::Target {
438 &self.0
439 }
440}
441#[doc = "Field `EOT` writer - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register."]
442pub struct EOT_W<'a> {
443 w: &'a mut W,
444}
445impl<'a> EOT_W<'a> {
446 #[doc = r"Writes `variant` to the field"]
447 #[inline(always)]
448 pub fn variant(self, variant: EOT_A) -> &'a mut W {
449 self.bit(variant.into())
450 }
451 #[doc = "This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data."]
452 #[inline(always)]
453 pub fn ssel_deasserted(self) -> &'a mut W {
454 self.variant(EOT_A::SSEL_DEASSERTED)
455 }
456 #[doc = "This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data."]
457 #[inline(always)]
458 pub fn ssel_not_deasserted(self) -> &'a mut W {
459 self.variant(EOT_A::SSEL_NOT_DEASSERTED)
460 }
461 #[doc = r"Sets the field bit"]
462 #[inline(always)]
463 pub fn set_bit(self) -> &'a mut W {
464 self.bit(true)
465 }
466 #[doc = r"Clears the field bit"]
467 #[inline(always)]
468 pub fn clear_bit(self) -> &'a mut W {
469 self.bit(false)
470 }
471 #[doc = r"Writes raw bits to the field"]
472 #[inline(always)]
473 pub fn bit(self, value: bool) -> &'a mut W {
474 self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
475 self.w
476 }
477}
478#[doc = "End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.\n\nValue on reset: 0"]
479#[derive(Clone, Copy, Debug, PartialEq)]
480pub enum EOF_A {
481 #[doc = "0: This piece of data transmitted is not treated as the end of a frame."]
482 DATA_NOT_EOF = 0,
483 #[doc = "1: This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted."]
484 DATA_EOF = 1,
485}
486impl From<EOF_A> for bool {
487 #[inline(always)]
488 fn from(variant: EOF_A) -> Self {
489 variant as u8 != 0
490 }
491}
492#[doc = "Field `EOF` reader - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits."]
493pub struct EOF_R(crate::FieldReader<bool, EOF_A>);
494impl EOF_R {
495 pub(crate) fn new(bits: bool) -> Self {
496 EOF_R(crate::FieldReader::new(bits))
497 }
498 #[doc = r"Get enumerated values variant"]
499 #[inline(always)]
500 pub fn variant(&self) -> EOF_A {
501 match self.bits {
502 false => EOF_A::DATA_NOT_EOF,
503 true => EOF_A::DATA_EOF,
504 }
505 }
506 #[doc = "Checks if the value of the field is `DATA_NOT_EOF`"]
507 #[inline(always)]
508 pub fn is_data_not_eof(&self) -> bool {
509 **self == EOF_A::DATA_NOT_EOF
510 }
511 #[doc = "Checks if the value of the field is `DATA_EOF`"]
512 #[inline(always)]
513 pub fn is_data_eof(&self) -> bool {
514 **self == EOF_A::DATA_EOF
515 }
516}
517impl core::ops::Deref for EOF_R {
518 type Target = crate::FieldReader<bool, EOF_A>;
519 #[inline(always)]
520 fn deref(&self) -> &Self::Target {
521 &self.0
522 }
523}
524#[doc = "Field `EOF` writer - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits."]
525pub struct EOF_W<'a> {
526 w: &'a mut W,
527}
528impl<'a> EOF_W<'a> {
529 #[doc = r"Writes `variant` to the field"]
530 #[inline(always)]
531 pub fn variant(self, variant: EOF_A) -> &'a mut W {
532 self.bit(variant.into())
533 }
534 #[doc = "This piece of data transmitted is not treated as the end of a frame."]
535 #[inline(always)]
536 pub fn data_not_eof(self) -> &'a mut W {
537 self.variant(EOF_A::DATA_NOT_EOF)
538 }
539 #[doc = "This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted."]
540 #[inline(always)]
541 pub fn data_eof(self) -> &'a mut W {
542 self.variant(EOF_A::DATA_EOF)
543 }
544 #[doc = r"Sets the field bit"]
545 #[inline(always)]
546 pub fn set_bit(self) -> &'a mut W {
547 self.bit(true)
548 }
549 #[doc = r"Clears the field bit"]
550 #[inline(always)]
551 pub fn clear_bit(self) -> &'a mut W {
552 self.bit(false)
553 }
554 #[doc = r"Writes raw bits to the field"]
555 #[inline(always)]
556 pub fn bit(self, value: bool) -> &'a mut W {
557 self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
558 self.w
559 }
560}
561#[doc = "Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.\n\nValue on reset: 0"]
562#[derive(Clone, Copy, Debug, PartialEq)]
563pub enum RXIGNORE_A {
564 #[doc = "0: Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received."]
565 READ_RECEIVED_DATA = 0,
566 #[doc = "1: Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated."]
567 IGNORE_RECEIVED_DATA = 1,
568}
569impl From<RXIGNORE_A> for bool {
570 #[inline(always)]
571 fn from(variant: RXIGNORE_A) -> Self {
572 variant as u8 != 0
573 }
574}
575#[doc = "Field `RXIGNORE` reader - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA."]
576pub struct RXIGNORE_R(crate::FieldReader<bool, RXIGNORE_A>);
577impl RXIGNORE_R {
578 pub(crate) fn new(bits: bool) -> Self {
579 RXIGNORE_R(crate::FieldReader::new(bits))
580 }
581 #[doc = r"Get enumerated values variant"]
582 #[inline(always)]
583 pub fn variant(&self) -> RXIGNORE_A {
584 match self.bits {
585 false => RXIGNORE_A::READ_RECEIVED_DATA,
586 true => RXIGNORE_A::IGNORE_RECEIVED_DATA,
587 }
588 }
589 #[doc = "Checks if the value of the field is `READ_RECEIVED_DATA`"]
590 #[inline(always)]
591 pub fn is_read_received_data(&self) -> bool {
592 **self == RXIGNORE_A::READ_RECEIVED_DATA
593 }
594 #[doc = "Checks if the value of the field is `IGNORE_RECEIVED_DATA`"]
595 #[inline(always)]
596 pub fn is_ignore_received_data(&self) -> bool {
597 **self == RXIGNORE_A::IGNORE_RECEIVED_DATA
598 }
599}
600impl core::ops::Deref for RXIGNORE_R {
601 type Target = crate::FieldReader<bool, RXIGNORE_A>;
602 #[inline(always)]
603 fn deref(&self) -> &Self::Target {
604 &self.0
605 }
606}
607#[doc = "Field `RXIGNORE` writer - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA."]
608pub struct RXIGNORE_W<'a> {
609 w: &'a mut W,
610}
611impl<'a> RXIGNORE_W<'a> {
612 #[doc = r"Writes `variant` to the field"]
613 #[inline(always)]
614 pub fn variant(self, variant: RXIGNORE_A) -> &'a mut W {
615 self.bit(variant.into())
616 }
617 #[doc = "Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received."]
618 #[inline(always)]
619 pub fn read_received_data(self) -> &'a mut W {
620 self.variant(RXIGNORE_A::READ_RECEIVED_DATA)
621 }
622 #[doc = "Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated."]
623 #[inline(always)]
624 pub fn ignore_received_data(self) -> &'a mut W {
625 self.variant(RXIGNORE_A::IGNORE_RECEIVED_DATA)
626 }
627 #[doc = r"Sets the field bit"]
628 #[inline(always)]
629 pub fn set_bit(self) -> &'a mut W {
630 self.bit(true)
631 }
632 #[doc = r"Clears the field bit"]
633 #[inline(always)]
634 pub fn clear_bit(self) -> &'a mut W {
635 self.bit(false)
636 }
637 #[doc = r"Writes raw bits to the field"]
638 #[inline(always)]
639 pub fn bit(self, value: bool) -> &'a mut W {
640 self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
641 self.w
642 }
643}
644#[doc = "Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.\n\nValue on reset: 0"]
645#[derive(Clone, Copy, Debug, PartialEq)]
646#[repr(u8)]
647pub enum LEN_A {
648 #[doc = "0: no description available"]
649 LEN_0 = 0,
650 #[doc = "1: Data transfer is 1 bit in length."]
651 LEN_1 = 1,
652 #[doc = "2: Data transfer is 2 bit in length."]
653 LEN_2 = 2,
654 #[doc = "3: Data transfer is 3 bit in length."]
655 LEN_3 = 3,
656 #[doc = "4: Data transfer is 4 bit in length."]
657 LEN_4 = 4,
658 #[doc = "5: Data transfer is 5 bit in length."]
659 LEN_5 = 5,
660 #[doc = "6: Data transfer is 6 bit in length."]
661 LEN_6 = 6,
662 #[doc = "7: Data transfer is 7 bit in length."]
663 LEN_7 = 7,
664 #[doc = "8: Data transfer is 8 bit in length."]
665 LEN_8 = 8,
666 #[doc = "9: Data transfer is 9 bit in length."]
667 LEN_9 = 9,
668 #[doc = "10: Data transfer is 10 bit in length."]
669 LEN_10 = 10,
670 #[doc = "11: Data transfer is 11 bit in length."]
671 LEN_11 = 11,
672 #[doc = "12: Data transfer is 12 bit in length."]
673 LEN_12 = 12,
674 #[doc = "13: Data transfer is 13 bit in length."]
675 LEN_13 = 13,
676 #[doc = "14: Data transfer is 14 bit in length."]
677 LEN_14 = 14,
678 #[doc = "15: Data transfer is 15 bit in length."]
679 LEN_15 = 15,
680}
681impl From<LEN_A> for u8 {
682 #[inline(always)]
683 fn from(variant: LEN_A) -> Self {
684 variant as _
685 }
686}
687#[doc = "Field `LEN` reader - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length."]
688pub struct LEN_R(crate::FieldReader<u8, LEN_A>);
689impl LEN_R {
690 pub(crate) fn new(bits: u8) -> Self {
691 LEN_R(crate::FieldReader::new(bits))
692 }
693 #[doc = r"Get enumerated values variant"]
694 #[inline(always)]
695 pub fn variant(&self) -> LEN_A {
696 match self.bits {
697 0 => LEN_A::LEN_0,
698 1 => LEN_A::LEN_1,
699 2 => LEN_A::LEN_2,
700 3 => LEN_A::LEN_3,
701 4 => LEN_A::LEN_4,
702 5 => LEN_A::LEN_5,
703 6 => LEN_A::LEN_6,
704 7 => LEN_A::LEN_7,
705 8 => LEN_A::LEN_8,
706 9 => LEN_A::LEN_9,
707 10 => LEN_A::LEN_10,
708 11 => LEN_A::LEN_11,
709 12 => LEN_A::LEN_12,
710 13 => LEN_A::LEN_13,
711 14 => LEN_A::LEN_14,
712 15 => LEN_A::LEN_15,
713 _ => unreachable!(),
714 }
715 }
716 #[doc = "Checks if the value of the field is `LEN_0`"]
717 #[inline(always)]
718 pub fn is_len_0(&self) -> bool {
719 **self == LEN_A::LEN_0
720 }
721 #[doc = "Checks if the value of the field is `LEN_1`"]
722 #[inline(always)]
723 pub fn is_len_1(&self) -> bool {
724 **self == LEN_A::LEN_1
725 }
726 #[doc = "Checks if the value of the field is `LEN_2`"]
727 #[inline(always)]
728 pub fn is_len_2(&self) -> bool {
729 **self == LEN_A::LEN_2
730 }
731 #[doc = "Checks if the value of the field is `LEN_3`"]
732 #[inline(always)]
733 pub fn is_len_3(&self) -> bool {
734 **self == LEN_A::LEN_3
735 }
736 #[doc = "Checks if the value of the field is `LEN_4`"]
737 #[inline(always)]
738 pub fn is_len_4(&self) -> bool {
739 **self == LEN_A::LEN_4
740 }
741 #[doc = "Checks if the value of the field is `LEN_5`"]
742 #[inline(always)]
743 pub fn is_len_5(&self) -> bool {
744 **self == LEN_A::LEN_5
745 }
746 #[doc = "Checks if the value of the field is `LEN_6`"]
747 #[inline(always)]
748 pub fn is_len_6(&self) -> bool {
749 **self == LEN_A::LEN_6
750 }
751 #[doc = "Checks if the value of the field is `LEN_7`"]
752 #[inline(always)]
753 pub fn is_len_7(&self) -> bool {
754 **self == LEN_A::LEN_7
755 }
756 #[doc = "Checks if the value of the field is `LEN_8`"]
757 #[inline(always)]
758 pub fn is_len_8(&self) -> bool {
759 **self == LEN_A::LEN_8
760 }
761 #[doc = "Checks if the value of the field is `LEN_9`"]
762 #[inline(always)]
763 pub fn is_len_9(&self) -> bool {
764 **self == LEN_A::LEN_9
765 }
766 #[doc = "Checks if the value of the field is `LEN_10`"]
767 #[inline(always)]
768 pub fn is_len_10(&self) -> bool {
769 **self == LEN_A::LEN_10
770 }
771 #[doc = "Checks if the value of the field is `LEN_11`"]
772 #[inline(always)]
773 pub fn is_len_11(&self) -> bool {
774 **self == LEN_A::LEN_11
775 }
776 #[doc = "Checks if the value of the field is `LEN_12`"]
777 #[inline(always)]
778 pub fn is_len_12(&self) -> bool {
779 **self == LEN_A::LEN_12
780 }
781 #[doc = "Checks if the value of the field is `LEN_13`"]
782 #[inline(always)]
783 pub fn is_len_13(&self) -> bool {
784 **self == LEN_A::LEN_13
785 }
786 #[doc = "Checks if the value of the field is `LEN_14`"]
787 #[inline(always)]
788 pub fn is_len_14(&self) -> bool {
789 **self == LEN_A::LEN_14
790 }
791 #[doc = "Checks if the value of the field is `LEN_15`"]
792 #[inline(always)]
793 pub fn is_len_15(&self) -> bool {
794 **self == LEN_A::LEN_15
795 }
796}
797impl core::ops::Deref for LEN_R {
798 type Target = crate::FieldReader<u8, LEN_A>;
799 #[inline(always)]
800 fn deref(&self) -> &Self::Target {
801 &self.0
802 }
803}
804#[doc = "Field `LEN` writer - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length."]
805pub struct LEN_W<'a> {
806 w: &'a mut W,
807}
808impl<'a> LEN_W<'a> {
809 #[doc = r"Writes `variant` to the field"]
810 #[inline(always)]
811 pub fn variant(self, variant: LEN_A) -> &'a mut W {
812 self.bits(variant.into())
813 }
814 #[doc = "no description available"]
815 #[inline(always)]
816 pub fn len_0(self) -> &'a mut W {
817 self.variant(LEN_A::LEN_0)
818 }
819 #[doc = "Data transfer is 1 bit in length."]
820 #[inline(always)]
821 pub fn len_1(self) -> &'a mut W {
822 self.variant(LEN_A::LEN_1)
823 }
824 #[doc = "Data transfer is 2 bit in length."]
825 #[inline(always)]
826 pub fn len_2(self) -> &'a mut W {
827 self.variant(LEN_A::LEN_2)
828 }
829 #[doc = "Data transfer is 3 bit in length."]
830 #[inline(always)]
831 pub fn len_3(self) -> &'a mut W {
832 self.variant(LEN_A::LEN_3)
833 }
834 #[doc = "Data transfer is 4 bit in length."]
835 #[inline(always)]
836 pub fn len_4(self) -> &'a mut W {
837 self.variant(LEN_A::LEN_4)
838 }
839 #[doc = "Data transfer is 5 bit in length."]
840 #[inline(always)]
841 pub fn len_5(self) -> &'a mut W {
842 self.variant(LEN_A::LEN_5)
843 }
844 #[doc = "Data transfer is 6 bit in length."]
845 #[inline(always)]
846 pub fn len_6(self) -> &'a mut W {
847 self.variant(LEN_A::LEN_6)
848 }
849 #[doc = "Data transfer is 7 bit in length."]
850 #[inline(always)]
851 pub fn len_7(self) -> &'a mut W {
852 self.variant(LEN_A::LEN_7)
853 }
854 #[doc = "Data transfer is 8 bit in length."]
855 #[inline(always)]
856 pub fn len_8(self) -> &'a mut W {
857 self.variant(LEN_A::LEN_8)
858 }
859 #[doc = "Data transfer is 9 bit in length."]
860 #[inline(always)]
861 pub fn len_9(self) -> &'a mut W {
862 self.variant(LEN_A::LEN_9)
863 }
864 #[doc = "Data transfer is 10 bit in length."]
865 #[inline(always)]
866 pub fn len_10(self) -> &'a mut W {
867 self.variant(LEN_A::LEN_10)
868 }
869 #[doc = "Data transfer is 11 bit in length."]
870 #[inline(always)]
871 pub fn len_11(self) -> &'a mut W {
872 self.variant(LEN_A::LEN_11)
873 }
874 #[doc = "Data transfer is 12 bit in length."]
875 #[inline(always)]
876 pub fn len_12(self) -> &'a mut W {
877 self.variant(LEN_A::LEN_12)
878 }
879 #[doc = "Data transfer is 13 bit in length."]
880 #[inline(always)]
881 pub fn len_13(self) -> &'a mut W {
882 self.variant(LEN_A::LEN_13)
883 }
884 #[doc = "Data transfer is 14 bit in length."]
885 #[inline(always)]
886 pub fn len_14(self) -> &'a mut W {
887 self.variant(LEN_A::LEN_14)
888 }
889 #[doc = "Data transfer is 15 bit in length."]
890 #[inline(always)]
891 pub fn len_15(self) -> &'a mut W {
892 self.variant(LEN_A::LEN_15)
893 }
894 #[doc = r"Writes raw bits to the field"]
895 #[inline(always)]
896 pub fn bits(self, value: u8) -> &'a mut W {
897 self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24);
898 self.w
899 }
900}
901impl R {
902 #[doc = "Bits 0:15 - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."]
903 #[inline(always)]
904 pub fn txdat(&self) -> TXDAT_R {
905 TXDAT_R::new((self.bits & 0xffff) as u16)
906 }
907 #[doc = "Bit 16 - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register."]
908 #[inline(always)]
909 pub fn txssel0_n(&self) -> TXSSEL0_N_R {
910 TXSSEL0_N_R::new(((self.bits >> 16) & 0x01) != 0)
911 }
912 #[doc = "Bit 17 - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register."]
913 #[inline(always)]
914 pub fn txssel1_n(&self) -> TXSSEL1_N_R {
915 TXSSEL1_N_R::new(((self.bits >> 17) & 0x01) != 0)
916 }
917 #[doc = "Bit 18 - Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register."]
918 #[inline(always)]
919 pub fn txssel2_n(&self) -> TXSSEL2_N_R {
920 TXSSEL2_N_R::new(((self.bits >> 18) & 0x01) != 0)
921 }
922 #[doc = "Bit 19 - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register."]
923 #[inline(always)]
924 pub fn txssel3_n(&self) -> TXSSEL3_N_R {
925 TXSSEL3_N_R::new(((self.bits >> 19) & 0x01) != 0)
926 }
927 #[doc = "Bit 20 - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register."]
928 #[inline(always)]
929 pub fn eot(&self) -> EOT_R {
930 EOT_R::new(((self.bits >> 20) & 0x01) != 0)
931 }
932 #[doc = "Bit 21 - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits."]
933 #[inline(always)]
934 pub fn eof(&self) -> EOF_R {
935 EOF_R::new(((self.bits >> 21) & 0x01) != 0)
936 }
937 #[doc = "Bit 22 - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA."]
938 #[inline(always)]
939 pub fn rxignore(&self) -> RXIGNORE_R {
940 RXIGNORE_R::new(((self.bits >> 22) & 0x01) != 0)
941 }
942 #[doc = "Bits 24:27 - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length."]
943 #[inline(always)]
944 pub fn len(&self) -> LEN_R {
945 LEN_R::new(((self.bits >> 24) & 0x0f) as u8)
946 }
947}
948impl W {
949 #[doc = "Bits 0:15 - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted."]
950 #[inline(always)]
951 pub fn txdat(&mut self) -> TXDAT_W {
952 TXDAT_W { w: self }
953 }
954 #[doc = "Bit 16 - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register."]
955 #[inline(always)]
956 pub fn txssel0_n(&mut self) -> TXSSEL0_N_W {
957 TXSSEL0_N_W { w: self }
958 }
959 #[doc = "Bit 17 - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register."]
960 #[inline(always)]
961 pub fn txssel1_n(&mut self) -> TXSSEL1_N_W {
962 TXSSEL1_N_W { w: self }
963 }
964 #[doc = "Bit 18 - Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register."]
965 #[inline(always)]
966 pub fn txssel2_n(&mut self) -> TXSSEL2_N_W {
967 TXSSEL2_N_W { w: self }
968 }
969 #[doc = "Bit 19 - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register."]
970 #[inline(always)]
971 pub fn txssel3_n(&mut self) -> TXSSEL3_N_W {
972 TXSSEL3_N_W { w: self }
973 }
974 #[doc = "Bit 20 - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register."]
975 #[inline(always)]
976 pub fn eot(&mut self) -> EOT_W {
977 EOT_W { w: self }
978 }
979 #[doc = "Bit 21 - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits."]
980 #[inline(always)]
981 pub fn eof(&mut self) -> EOF_W {
982 EOF_W { w: self }
983 }
984 #[doc = "Bit 22 - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA."]
985 #[inline(always)]
986 pub fn rxignore(&mut self) -> RXIGNORE_W {
987 RXIGNORE_W { w: self }
988 }
989 #[doc = "Bits 24:27 - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length."]
990 #[inline(always)]
991 pub fn len(&mut self) -> LEN_W {
992 LEN_W { w: self }
993 }
994 #[doc = "Writes raw bits to the register."]
995 #[inline(always)]
996 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
997 self.0.bits(bits);
998 self
999 }
1000}
1001#[doc = "SPI Transmit Data with Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdatctl](index.html) module"]
1002pub struct TXDATCTL_SPEC;
1003impl crate::RegisterSpec for TXDATCTL_SPEC {
1004 type Ux = u32;
1005}
1006#[doc = "`read()` method returns [txdatctl::R](R) reader structure"]
1007impl crate::Readable for TXDATCTL_SPEC {
1008 type Reader = R;
1009}
1010#[doc = "`write(|w| ..)` method takes [txdatctl::W](W) writer structure"]
1011impl crate::Writable for TXDATCTL_SPEC {
1012 type Writer = W;
1013}
1014#[doc = "`reset()` method sets TXDATCTL to value 0"]
1015impl crate::Resettable for TXDATCTL_SPEC {
1016 #[inline(always)]
1017 fn reset_value() -> Self::Ux {
1018 0
1019 }
1020}