lpc82x_pac/i2c0/
msttime.rs

1#[doc = "Register `MSTTIME` reader"]
2pub struct R(crate::R<MSTTIME_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MSTTIME_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MSTTIME_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MSTTIME_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MSTTIME` writer"]
17pub struct W(crate::W<MSTTIME_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MSTTIME_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MSTTIME_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MSTTIME_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.\n\nValue on reset: 7"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MSTSCLLOW_A {
41    #[doc = "0: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
42    CLOCKS_2 = 0,
43    #[doc = "1: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
44    CLOCKS_3 = 1,
45    #[doc = "2: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
46    CLOCKS_4 = 2,
47    #[doc = "3: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
48    CLOCKS_5 = 3,
49    #[doc = "4: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
50    CLOCKS_6 = 4,
51    #[doc = "5: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
52    CLOCKS_7 = 5,
53    #[doc = "6: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
54    CLOCKS_8 = 6,
55    #[doc = "7: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
56    CLOCKS_9 = 7,
57}
58impl From<MSTSCLLOW_A> for u8 {
59    #[inline(always)]
60    fn from(variant: MSTSCLLOW_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `MSTSCLLOW` reader - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
65pub struct MSTSCLLOW_R(crate::FieldReader<u8, MSTSCLLOW_A>);
66impl MSTSCLLOW_R {
67    pub(crate) fn new(bits: u8) -> Self {
68        MSTSCLLOW_R(crate::FieldReader::new(bits))
69    }
70    #[doc = r"Get enumerated values variant"]
71    #[inline(always)]
72    pub fn variant(&self) -> MSTSCLLOW_A {
73        match self.bits {
74            0 => MSTSCLLOW_A::CLOCKS_2,
75            1 => MSTSCLLOW_A::CLOCKS_3,
76            2 => MSTSCLLOW_A::CLOCKS_4,
77            3 => MSTSCLLOW_A::CLOCKS_5,
78            4 => MSTSCLLOW_A::CLOCKS_6,
79            5 => MSTSCLLOW_A::CLOCKS_7,
80            6 => MSTSCLLOW_A::CLOCKS_8,
81            7 => MSTSCLLOW_A::CLOCKS_9,
82            _ => unreachable!(),
83        }
84    }
85    #[doc = "Checks if the value of the field is `CLOCKS_2`"]
86    #[inline(always)]
87    pub fn is_clocks_2(&self) -> bool {
88        **self == MSTSCLLOW_A::CLOCKS_2
89    }
90    #[doc = "Checks if the value of the field is `CLOCKS_3`"]
91    #[inline(always)]
92    pub fn is_clocks_3(&self) -> bool {
93        **self == MSTSCLLOW_A::CLOCKS_3
94    }
95    #[doc = "Checks if the value of the field is `CLOCKS_4`"]
96    #[inline(always)]
97    pub fn is_clocks_4(&self) -> bool {
98        **self == MSTSCLLOW_A::CLOCKS_4
99    }
100    #[doc = "Checks if the value of the field is `CLOCKS_5`"]
101    #[inline(always)]
102    pub fn is_clocks_5(&self) -> bool {
103        **self == MSTSCLLOW_A::CLOCKS_5
104    }
105    #[doc = "Checks if the value of the field is `CLOCKS_6`"]
106    #[inline(always)]
107    pub fn is_clocks_6(&self) -> bool {
108        **self == MSTSCLLOW_A::CLOCKS_6
109    }
110    #[doc = "Checks if the value of the field is `CLOCKS_7`"]
111    #[inline(always)]
112    pub fn is_clocks_7(&self) -> bool {
113        **self == MSTSCLLOW_A::CLOCKS_7
114    }
115    #[doc = "Checks if the value of the field is `CLOCKS_8`"]
116    #[inline(always)]
117    pub fn is_clocks_8(&self) -> bool {
118        **self == MSTSCLLOW_A::CLOCKS_8
119    }
120    #[doc = "Checks if the value of the field is `CLOCKS_9`"]
121    #[inline(always)]
122    pub fn is_clocks_9(&self) -> bool {
123        **self == MSTSCLLOW_A::CLOCKS_9
124    }
125}
126impl core::ops::Deref for MSTSCLLOW_R {
127    type Target = crate::FieldReader<u8, MSTSCLLOW_A>;
128    #[inline(always)]
129    fn deref(&self) -> &Self::Target {
130        &self.0
131    }
132}
133#[doc = "Field `MSTSCLLOW` writer - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
134pub struct MSTSCLLOW_W<'a> {
135    w: &'a mut W,
136}
137impl<'a> MSTSCLLOW_W<'a> {
138    #[doc = r"Writes `variant` to the field"]
139    #[inline(always)]
140    pub fn variant(self, variant: MSTSCLLOW_A) -> &'a mut W {
141        self.bits(variant.into())
142    }
143    #[doc = "2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
144    #[inline(always)]
145    pub fn clocks_2(self) -> &'a mut W {
146        self.variant(MSTSCLLOW_A::CLOCKS_2)
147    }
148    #[doc = "3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
149    #[inline(always)]
150    pub fn clocks_3(self) -> &'a mut W {
151        self.variant(MSTSCLLOW_A::CLOCKS_3)
152    }
153    #[doc = "4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
154    #[inline(always)]
155    pub fn clocks_4(self) -> &'a mut W {
156        self.variant(MSTSCLLOW_A::CLOCKS_4)
157    }
158    #[doc = "5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
159    #[inline(always)]
160    pub fn clocks_5(self) -> &'a mut W {
161        self.variant(MSTSCLLOW_A::CLOCKS_5)
162    }
163    #[doc = "6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
164    #[inline(always)]
165    pub fn clocks_6(self) -> &'a mut W {
166        self.variant(MSTSCLLOW_A::CLOCKS_6)
167    }
168    #[doc = "7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
169    #[inline(always)]
170    pub fn clocks_7(self) -> &'a mut W {
171        self.variant(MSTSCLLOW_A::CLOCKS_7)
172    }
173    #[doc = "8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
174    #[inline(always)]
175    pub fn clocks_8(self) -> &'a mut W {
176        self.variant(MSTSCLLOW_A::CLOCKS_8)
177    }
178    #[doc = "9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
179    #[inline(always)]
180    pub fn clocks_9(self) -> &'a mut W {
181        self.variant(MSTSCLLOW_A::CLOCKS_9)
182    }
183    #[doc = r"Writes raw bits to the field"]
184    #[inline(always)]
185    pub fn bits(self, value: u8) -> &'a mut W {
186        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
187        self.w
188    }
189}
190#[doc = "Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.\n\nValue on reset: 7"]
191#[derive(Clone, Copy, Debug, PartialEq)]
192#[repr(u8)]
193pub enum MSTSCLHIGH_A {
194    #[doc = "0: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
195    CLOCKS_2 = 0,
196    #[doc = "1: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
197    CLOCKS_3 = 1,
198    #[doc = "2: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
199    CLOCKS_4 = 2,
200    #[doc = "3: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
201    CLOCKS_5 = 3,
202    #[doc = "4: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
203    CLOCKS_6 = 4,
204    #[doc = "5: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
205    CLOCKS_7 = 5,
206    #[doc = "6: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
207    CLOCKS_8 = 6,
208    #[doc = "7: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
209    CLOCKS_9 = 7,
210}
211impl From<MSTSCLHIGH_A> for u8 {
212    #[inline(always)]
213    fn from(variant: MSTSCLHIGH_A) -> Self {
214        variant as _
215    }
216}
217#[doc = "Field `MSTSCLHIGH` reader - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
218pub struct MSTSCLHIGH_R(crate::FieldReader<u8, MSTSCLHIGH_A>);
219impl MSTSCLHIGH_R {
220    pub(crate) fn new(bits: u8) -> Self {
221        MSTSCLHIGH_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> MSTSCLHIGH_A {
226        match self.bits {
227            0 => MSTSCLHIGH_A::CLOCKS_2,
228            1 => MSTSCLHIGH_A::CLOCKS_3,
229            2 => MSTSCLHIGH_A::CLOCKS_4,
230            3 => MSTSCLHIGH_A::CLOCKS_5,
231            4 => MSTSCLHIGH_A::CLOCKS_6,
232            5 => MSTSCLHIGH_A::CLOCKS_7,
233            6 => MSTSCLHIGH_A::CLOCKS_8,
234            7 => MSTSCLHIGH_A::CLOCKS_9,
235            _ => unreachable!(),
236        }
237    }
238    #[doc = "Checks if the value of the field is `CLOCKS_2`"]
239    #[inline(always)]
240    pub fn is_clocks_2(&self) -> bool {
241        **self == MSTSCLHIGH_A::CLOCKS_2
242    }
243    #[doc = "Checks if the value of the field is `CLOCKS_3`"]
244    #[inline(always)]
245    pub fn is_clocks_3(&self) -> bool {
246        **self == MSTSCLHIGH_A::CLOCKS_3
247    }
248    #[doc = "Checks if the value of the field is `CLOCKS_4`"]
249    #[inline(always)]
250    pub fn is_clocks_4(&self) -> bool {
251        **self == MSTSCLHIGH_A::CLOCKS_4
252    }
253    #[doc = "Checks if the value of the field is `CLOCKS_5`"]
254    #[inline(always)]
255    pub fn is_clocks_5(&self) -> bool {
256        **self == MSTSCLHIGH_A::CLOCKS_5
257    }
258    #[doc = "Checks if the value of the field is `CLOCKS_6`"]
259    #[inline(always)]
260    pub fn is_clocks_6(&self) -> bool {
261        **self == MSTSCLHIGH_A::CLOCKS_6
262    }
263    #[doc = "Checks if the value of the field is `CLOCKS_7`"]
264    #[inline(always)]
265    pub fn is_clocks_7(&self) -> bool {
266        **self == MSTSCLHIGH_A::CLOCKS_7
267    }
268    #[doc = "Checks if the value of the field is `CLOCKS_8`"]
269    #[inline(always)]
270    pub fn is_clocks_8(&self) -> bool {
271        **self == MSTSCLHIGH_A::CLOCKS_8
272    }
273    #[doc = "Checks if the value of the field is `CLOCKS_9`"]
274    #[inline(always)]
275    pub fn is_clocks_9(&self) -> bool {
276        **self == MSTSCLHIGH_A::CLOCKS_9
277    }
278}
279impl core::ops::Deref for MSTSCLHIGH_R {
280    type Target = crate::FieldReader<u8, MSTSCLHIGH_A>;
281    #[inline(always)]
282    fn deref(&self) -> &Self::Target {
283        &self.0
284    }
285}
286#[doc = "Field `MSTSCLHIGH` writer - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
287pub struct MSTSCLHIGH_W<'a> {
288    w: &'a mut W,
289}
290impl<'a> MSTSCLHIGH_W<'a> {
291    #[doc = r"Writes `variant` to the field"]
292    #[inline(always)]
293    pub fn variant(self, variant: MSTSCLHIGH_A) -> &'a mut W {
294        self.bits(variant.into())
295    }
296    #[doc = "2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
297    #[inline(always)]
298    pub fn clocks_2(self) -> &'a mut W {
299        self.variant(MSTSCLHIGH_A::CLOCKS_2)
300    }
301    #[doc = "3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
302    #[inline(always)]
303    pub fn clocks_3(self) -> &'a mut W {
304        self.variant(MSTSCLHIGH_A::CLOCKS_3)
305    }
306    #[doc = "4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
307    #[inline(always)]
308    pub fn clocks_4(self) -> &'a mut W {
309        self.variant(MSTSCLHIGH_A::CLOCKS_4)
310    }
311    #[doc = "5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
312    #[inline(always)]
313    pub fn clocks_5(self) -> &'a mut W {
314        self.variant(MSTSCLHIGH_A::CLOCKS_5)
315    }
316    #[doc = "6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
317    #[inline(always)]
318    pub fn clocks_6(self) -> &'a mut W {
319        self.variant(MSTSCLHIGH_A::CLOCKS_6)
320    }
321    #[doc = "7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
322    #[inline(always)]
323    pub fn clocks_7(self) -> &'a mut W {
324        self.variant(MSTSCLHIGH_A::CLOCKS_7)
325    }
326    #[doc = "8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
327    #[inline(always)]
328    pub fn clocks_8(self) -> &'a mut W {
329        self.variant(MSTSCLHIGH_A::CLOCKS_8)
330    }
331    #[doc = "9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
332    #[inline(always)]
333    pub fn clocks_9(self) -> &'a mut W {
334        self.variant(MSTSCLHIGH_A::CLOCKS_9)
335    }
336    #[doc = r"Writes raw bits to the field"]
337    #[inline(always)]
338    pub fn bits(self, value: u8) -> &'a mut W {
339        self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
340        self.w
341    }
342}
343impl R {
344    #[doc = "Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
345    #[inline(always)]
346    pub fn mstscllow(&self) -> MSTSCLLOW_R {
347        MSTSCLLOW_R::new((self.bits & 0x07) as u8)
348    }
349    #[doc = "Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
350    #[inline(always)]
351    pub fn mstsclhigh(&self) -> MSTSCLHIGH_R {
352        MSTSCLHIGH_R::new(((self.bits >> 4) & 0x07) as u8)
353    }
354}
355impl W {
356    #[doc = "Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
357    #[inline(always)]
358    pub fn mstscllow(&mut self) -> MSTSCLLOW_W {
359        MSTSCLLOW_W { w: self }
360    }
361    #[doc = "Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
362    #[inline(always)]
363    pub fn mstsclhigh(&mut self) -> MSTSCLHIGH_W {
364        MSTSCLHIGH_W { w: self }
365    }
366    #[doc = "Writes raw bits to the register."]
367    #[inline(always)]
368    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
369        self.0.bits(bits);
370        self
371    }
372}
373#[doc = "Master timing configuration.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msttime](index.html) module"]
374pub struct MSTTIME_SPEC;
375impl crate::RegisterSpec for MSTTIME_SPEC {
376    type Ux = u32;
377}
378#[doc = "`read()` method returns [msttime::R](R) reader structure"]
379impl crate::Readable for MSTTIME_SPEC {
380    type Reader = R;
381}
382#[doc = "`write(|w| ..)` method takes [msttime::W](W) writer structure"]
383impl crate::Writable for MSTTIME_SPEC {
384    type Writer = W;
385}
386#[doc = "`reset()` method sets MSTTIME to value 0x77"]
387impl crate::Resettable for MSTTIME_SPEC {
388    #[inline(always)]
389    fn reset_value() -> Self::Ux {
390        0x77
391    }
392}
lpc82x_pac/i2c0/msttime.rs

lpc82x_pac/i2c0/
msttime.rs
