1#[doc = "Reader of register DLY"]
2pub type R = crate::R<u32, super::DLY>;
3#[doc = "Writer for register DLY"]
4pub type W = crate::W<u32, super::DLY>;
5#[doc = "Register DLY `reset()`'s with value 0"]
6impl crate::ResetValue for super::DLY {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `PRE_DELAY`"]
14pub type PRE_DELAY_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `PRE_DELAY`"]
16pub struct PRE_DELAY_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> PRE_DELAY_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
24 self.w
25 }
26}
27#[doc = "Reader of field `POST_DELAY`"]
28pub type POST_DELAY_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `POST_DELAY`"]
30pub struct POST_DELAY_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> POST_DELAY_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
38 self.w
39 }
40}
41#[doc = "Reader of field `FRAME_DELAY`"]
42pub type FRAME_DELAY_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `FRAME_DELAY`"]
44pub struct FRAME_DELAY_W<'a> {
45 w: &'a mut W,
46}
47impl<'a> FRAME_DELAY_W<'a> {
48 #[doc = r"Writes raw bits to the field"]
49 #[inline(always)]
50 pub unsafe fn bits(self, value: u8) -> &'a mut W {
51 self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
52 self.w
53 }
54}
55#[doc = "Reader of field `TRANSFER_DELAY`"]
56pub type TRANSFER_DELAY_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `TRANSFER_DELAY`"]
58pub struct TRANSFER_DELAY_W<'a> {
59 w: &'a mut W,
60}
61impl<'a> TRANSFER_DELAY_W<'a> {
62 #[doc = r"Writes raw bits to the field"]
63 #[inline(always)]
64 pub unsafe fn bits(self, value: u8) -> &'a mut W {
65 self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
66 self.w
67 }
68}
69impl R {
70 #[doc = "Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
71 #[inline(always)]
72 pub fn pre_delay(&self) -> PRE_DELAY_R {
73 PRE_DELAY_R::new((self.bits & 0x0f) as u8)
74 }
75 #[doc = "Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
76 #[inline(always)]
77 pub fn post_delay(&self) -> POST_DELAY_R {
78 POST_DELAY_R::new(((self.bits >> 4) & 0x0f) as u8)
79 }
80 #[doc = "Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
81 #[inline(always)]
82 pub fn frame_delay(&self) -> FRAME_DELAY_R {
83 FRAME_DELAY_R::new(((self.bits >> 8) & 0x0f) as u8)
84 }
85 #[doc = "Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."]
86 #[inline(always)]
87 pub fn transfer_delay(&self) -> TRANSFER_DELAY_R {
88 TRANSFER_DELAY_R::new(((self.bits >> 12) & 0x0f) as u8)
89 }
90}
91impl W {
92 #[doc = "Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
93 #[inline(always)]
94 pub fn pre_delay(&mut self) -> PRE_DELAY_W {
95 PRE_DELAY_W { w: self }
96 }
97 #[doc = "Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
98 #[inline(always)]
99 pub fn post_delay(&mut self) -> POST_DELAY_W {
100 POST_DELAY_W { w: self }
101 }
102 #[doc = "Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
103 #[inline(always)]
104 pub fn frame_delay(&mut self) -> FRAME_DELAY_W {
105 FRAME_DELAY_W { w: self }
106 }
107 #[doc = "Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."]
108 #[inline(always)]
109 pub fn transfer_delay(&mut self) -> TRANSFER_DELAY_W {
110 TRANSFER_DELAY_W { w: self }
111 }
112}