lpc55s6x_pac/syscon/
clockgenupdatelockout.rs

1#[doc = "Reader of register CLOCKGENUPDATELOCKOUT"]
2pub type R = crate::R<u32, super::CLOCKGENUPDATELOCKOUT>;
3#[doc = "Writer for register CLOCKGENUPDATELOCKOUT"]
4pub type W = crate::W<u32, super::CLOCKGENUPDATELOCKOUT>;
5#[doc = "Register CLOCKGENUPDATELOCKOUT `reset()`'s with value 0"]
6impl crate::ResetValue for super::CLOCKGENUPDATELOCKOUT {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL).\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u32)]
16pub enum CLOCKGENUPDATELOCKOUT_A {
17    #[doc = "0: all hardware clock configruration are freeze."]
18    FREEZE = 0,
19    #[doc = "1: update all clock configuration."]
20    ENABLE = 1,
21}
22impl From<CLOCKGENUPDATELOCKOUT_A> for u32 {
23    #[inline(always)]
24    fn from(variant: CLOCKGENUPDATELOCKOUT_A) -> Self {
25        variant as _
26    }
27}
28#[doc = "Reader of field `CLOCKGENUPDATELOCKOUT`"]
29pub type CLOCKGENUPDATELOCKOUT_R = crate::R<u32, CLOCKGENUPDATELOCKOUT_A>;
30impl CLOCKGENUPDATELOCKOUT_R {
31    #[doc = r"Get enumerated values variant"]
32    #[inline(always)]
33    pub fn variant(&self) -> crate::Variant<u32, CLOCKGENUPDATELOCKOUT_A> {
34        use crate::Variant::*;
35        match self.bits {
36            0 => Val(CLOCKGENUPDATELOCKOUT_A::FREEZE),
37            1 => Val(CLOCKGENUPDATELOCKOUT_A::ENABLE),
38            i => Res(i),
39        }
40    }
41    #[doc = "Checks if the value of the field is `FREEZE`"]
42    #[inline(always)]
43    pub fn is_freeze(&self) -> bool {
44        *self == CLOCKGENUPDATELOCKOUT_A::FREEZE
45    }
46    #[doc = "Checks if the value of the field is `ENABLE`"]
47    #[inline(always)]
48    pub fn is_enable(&self) -> bool {
49        *self == CLOCKGENUPDATELOCKOUT_A::ENABLE
50    }
51}
52#[doc = "Write proxy for field `CLOCKGENUPDATELOCKOUT`"]
53pub struct CLOCKGENUPDATELOCKOUT_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> CLOCKGENUPDATELOCKOUT_W<'a> {
57    #[doc = r"Writes `variant` to the field"]
58    #[inline(always)]
59    pub fn variant(self, variant: CLOCKGENUPDATELOCKOUT_A) -> &'a mut W {
60        unsafe { self.bits(variant.into()) }
61    }
62    #[doc = "all hardware clock configruration are freeze."]
63    #[inline(always)]
64    pub fn freeze(self) -> &'a mut W {
65        self.variant(CLOCKGENUPDATELOCKOUT_A::FREEZE)
66    }
67    #[doc = "update all clock configuration."]
68    #[inline(always)]
69    pub fn enable(self) -> &'a mut W {
70        self.variant(CLOCKGENUPDATELOCKOUT_A::ENABLE)
71    }
72    #[doc = r"Writes raw bits to the field"]
73    #[inline(always)]
74    pub unsafe fn bits(self, value: u32) -> &'a mut W {
75        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
76        self.w
77    }
78}
79impl R {
80    #[doc = "Bits 0:31 - Control clock configuration registers access (like xxxDIV, xxxSEL)."]
81    #[inline(always)]
82    pub fn clockgenupdatelockout(&self) -> CLOCKGENUPDATELOCKOUT_R {
83        CLOCKGENUPDATELOCKOUT_R::new((self.bits & 0xffff_ffff) as u32)
84    }
85}
86impl W {
87    #[doc = "Bits 0:31 - Control clock configuration registers access (like xxxDIV, xxxSEL)."]
88    #[inline(always)]
89    pub fn clockgenupdatelockout(&mut self) -> CLOCKGENUPDATELOCKOUT_W {
90        CLOCKGENUPDATELOCKOUT_W { w: self }
91    }
92}
lpc55s6x_pac/syscon/clockgenupdatelockout.rs

lpc55s6x_pac/syscon/
clockgenupdatelockout.rs
