#[doc = "Reader of register PORTSC1"]
pub type R = crate::R<u32, super::PORTSC1>;
#[doc = "Writer for register PORTSC1"]
pub type W = crate::W<u32, super::PORTSC1>;
#[doc = "Register PORTSC1 `reset()`'s with value 0"]
impl crate::ResetValue for super::PORTSC1 {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `CCS`"]
pub type CCS_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CCS`"]
pub struct CCS_W<'a> {
w: &'a mut W,
}
impl<'a> CCS_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w
}
}
#[doc = "Reader of field `CSC`"]
pub type CSC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CSC`"]
pub struct CSC_W<'a> {
w: &'a mut W,
}
impl<'a> CSC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
self.w
}
}
#[doc = "Reader of field `PED`"]
pub type PED_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PED`"]
pub struct PED_W<'a> {
w: &'a mut W,
}
impl<'a> PED_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
self.w
}
}
#[doc = "Reader of field `PEDC`"]
pub type PEDC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PEDC`"]
pub struct PEDC_W<'a> {
w: &'a mut W,
}
impl<'a> PEDC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.w
}
}
#[doc = "Reader of field `OCA`"]
pub type OCA_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `OCA`"]
pub struct OCA_W<'a> {
w: &'a mut W,
}
impl<'a> OCA_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
self.w
}
}
#[doc = "Reader of field `OCC`"]
pub type OCC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `OCC`"]
pub struct OCC_W<'a> {
w: &'a mut W,
}
impl<'a> OCC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
self.w
}
}
#[doc = "Reader of field `FPR`"]
pub type FPR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `FPR`"]
pub struct FPR_W<'a> {
w: &'a mut W,
}
impl<'a> FPR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
self.w
}
}
#[doc = "Reader of field `SUSP`"]
pub type SUSP_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `SUSP`"]
pub struct SUSP_W<'a> {
w: &'a mut W,
}
impl<'a> SUSP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "Reader of field `PR`"]
pub type PR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PR`"]
pub struct PR_W<'a> {
w: &'a mut W,
}
impl<'a> PR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
self.w
}
}
#[doc = "Reader of field `LS`"]
pub type LS_R = crate::R<u8, u8>;
#[doc = "Reader of field `PP`"]
pub type PP_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PP`"]
pub struct PP_W<'a> {
w: &'a mut W,
}
impl<'a> PP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
self.w
}
}
#[doc = "Reader of field `PIC`"]
pub type PIC_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `PIC`"]
pub struct PIC_W<'a> {
w: &'a mut W,
}
impl<'a> PIC_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
self.w
}
}
#[doc = "Reader of field `PTC`"]
pub type PTC_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `PTC`"]
pub struct PTC_W<'a> {
w: &'a mut W,
}
impl<'a> PTC_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
self.w
}
}
#[doc = "Reader of field `PSPD`"]
pub type PSPD_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `PSPD`"]
pub struct PSPD_W<'a> {
w: &'a mut W,
}
impl<'a> PSPD_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
self.w
}
}
#[doc = "Reader of field `WOO`"]
pub type WOO_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `WOO`"]
pub struct WOO_W<'a> {
w: &'a mut W,
}
impl<'a> WOO_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
self.w
}
}
impl R {
#[doc = "Bit 0 - Current Connect Status: Logic 1 indicates a device is present on the port."]
#[inline(always)]
pub fn ccs(&self) -> CCS_R {
CCS_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - Connect Status Change: Logic 1 means that the value of CCS has changed."]
#[inline(always)]
pub fn csc(&self) -> CSC_R {
CSC_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 2 - Port Enabled/Disabled."]
#[inline(always)]
pub fn ped(&self) -> PED_R {
PED_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 3 - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed."]
#[inline(always)]
pub fn pedc(&self) -> PEDC_R {
PEDC_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 4 - Over-current active: Logic 1 means that this port has an over-current condition."]
#[inline(always)]
pub fn oca(&self) -> OCA_R {
OCA_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 5 - Over-current change: Logic 1 means that the value of OCA has changed."]
#[inline(always)]
pub fn occ(&self) -> OCC_R {
OCC_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 6 - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port."]
#[inline(always)]
pub fn fpr(&self) -> FPR_R {
FPR_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - Suspend: Logic 1 means port is in the suspend state."]
#[inline(always)]
pub fn susp(&self) -> SUSP_R {
SUSP_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 8 - Port Reset: Logic 1 means the port is in the reset state."]
#[inline(always)]
pub fn pr(&self) -> PR_R {
PR_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bits 10:11 - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines."]
#[inline(always)]
pub fn ls(&self) -> LS_R {
LS_R::new(((self.bits >> 10) & 0x03) as u8)
}
#[doc = "Bit 12 - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register."]
#[inline(always)]
pub fn pp(&self) -> PP_R {
PP_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bits 14:15 - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0."]
#[inline(always)]
pub fn pic(&self) -> PIC_R {
PIC_R::new(((self.bits >> 14) & 0x03) as u8)
}
#[doc = "Bits 16:19 - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value."]
#[inline(always)]
pub fn ptc(&self) -> PTC_R {
PTC_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:21 - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved."]
#[inline(always)]
pub fn pspd(&self) -> PSPD_R {
PSPD_R::new(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bit 22 - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events."]
#[inline(always)]
pub fn woo(&self) -> WOO_R {
WOO_R::new(((self.bits >> 22) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Current Connect Status: Logic 1 indicates a device is present on the port."]
#[inline(always)]
pub fn ccs(&mut self) -> CCS_W {
CCS_W { w: self }
}
#[doc = "Bit 1 - Connect Status Change: Logic 1 means that the value of CCS has changed."]
#[inline(always)]
pub fn csc(&mut self) -> CSC_W {
CSC_W { w: self }
}
#[doc = "Bit 2 - Port Enabled/Disabled."]
#[inline(always)]
pub fn ped(&mut self) -> PED_W {
PED_W { w: self }
}
#[doc = "Bit 3 - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed."]
#[inline(always)]
pub fn pedc(&mut self) -> PEDC_W {
PEDC_W { w: self }
}
#[doc = "Bit 4 - Over-current active: Logic 1 means that this port has an over-current condition."]
#[inline(always)]
pub fn oca(&mut self) -> OCA_W {
OCA_W { w: self }
}
#[doc = "Bit 5 - Over-current change: Logic 1 means that the value of OCA has changed."]
#[inline(always)]
pub fn occ(&mut self) -> OCC_W {
OCC_W { w: self }
}
#[doc = "Bit 6 - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port."]
#[inline(always)]
pub fn fpr(&mut self) -> FPR_W {
FPR_W { w: self }
}
#[doc = "Bit 7 - Suspend: Logic 1 means port is in the suspend state."]
#[inline(always)]
pub fn susp(&mut self) -> SUSP_W {
SUSP_W { w: self }
}
#[doc = "Bit 8 - Port Reset: Logic 1 means the port is in the reset state."]
#[inline(always)]
pub fn pr(&mut self) -> PR_W {
PR_W { w: self }
}
#[doc = "Bit 12 - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register."]
#[inline(always)]
pub fn pp(&mut self) -> PP_W {
PP_W { w: self }
}
#[doc = "Bits 14:15 - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0."]
#[inline(always)]
pub fn pic(&mut self) -> PIC_W {
PIC_W { w: self }
}
#[doc = "Bits 16:19 - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value."]
#[inline(always)]
pub fn ptc(&mut self) -> PTC_W {
PTC_W { w: self }
}
#[doc = "Bits 20:21 - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved."]
#[inline(always)]
pub fn pspd(&mut self) -> PSPD_W {
PSPD_W { w: self }
}
#[doc = "Bit 22 - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events."]
#[inline(always)]
pub fn woo(&mut self) -> WOO_W {
WOO_W { w: self }
}
}