lpc55s6x_pac/sysctl/
fcctrlsel.rs1#[doc = "Reader of register FCCTRLSEL%s"]
2pub type R = crate::R<u32, super::FCCTRLSEL>;
3#[doc = "Writer for register FCCTRLSEL%s"]
4pub type W = crate::W<u32, super::FCCTRLSEL>;
5#[doc = "Register FCCTRLSEL%s `reset()`'s with value 0"]
6impl crate::ResetValue for super::FCCTRLSEL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Selects the source for SCK going into this Flexcomm.\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum SCKINSEL_A {
17 #[doc = "0: Selects the dedicated FCn_SCK function for this Flexcomm."]
18 ORIG_FLEX_I2S_SIGNALS = 0,
19 #[doc = "1: SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
20 SHARED_SET0_I2S_SIGNALS = 1,
21 #[doc = "2: SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
22 SHARED_SET1_I2S_SIGNALS = 2,
23}
24impl From<SCKINSEL_A> for u8 {
25 #[inline(always)]
26 fn from(variant: SCKINSEL_A) -> Self {
27 variant as _
28 }
29}
30#[doc = "Reader of field `SCKINSEL`"]
31pub type SCKINSEL_R = crate::R<u8, SCKINSEL_A>;
32impl SCKINSEL_R {
33 #[doc = r"Get enumerated values variant"]
34 #[inline(always)]
35 pub fn variant(&self) -> crate::Variant<u8, SCKINSEL_A> {
36 use crate::Variant::*;
37 match self.bits {
38 0 => Val(SCKINSEL_A::ORIG_FLEX_I2S_SIGNALS),
39 1 => Val(SCKINSEL_A::SHARED_SET0_I2S_SIGNALS),
40 2 => Val(SCKINSEL_A::SHARED_SET1_I2S_SIGNALS),
41 i => Res(i),
42 }
43 }
44 #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
45 #[inline(always)]
46 pub fn is_orig_flex_i2s_signals(&self) -> bool {
47 *self == SCKINSEL_A::ORIG_FLEX_I2S_SIGNALS
48 }
49 #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
50 #[inline(always)]
51 pub fn is_shared_set0_i2s_signals(&self) -> bool {
52 *self == SCKINSEL_A::SHARED_SET0_I2S_SIGNALS
53 }
54 #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
55 #[inline(always)]
56 pub fn is_shared_set1_i2s_signals(&self) -> bool {
57 *self == SCKINSEL_A::SHARED_SET1_I2S_SIGNALS
58 }
59}
60#[doc = "Write proxy for field `SCKINSEL`"]
61pub struct SCKINSEL_W<'a> {
62 w: &'a mut W,
63}
64impl<'a> SCKINSEL_W<'a> {
65 #[doc = r"Writes `variant` to the field"]
66 #[inline(always)]
67 pub fn variant(self, variant: SCKINSEL_A) -> &'a mut W {
68 unsafe { self.bits(variant.into()) }
69 }
70 #[doc = "Selects the dedicated FCn_SCK function for this Flexcomm."]
71 #[inline(always)]
72 pub fn orig_flex_i2s_signals(self) -> &'a mut W {
73 self.variant(SCKINSEL_A::ORIG_FLEX_I2S_SIGNALS)
74 }
75 #[doc = "SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
76 #[inline(always)]
77 pub fn shared_set0_i2s_signals(self) -> &'a mut W {
78 self.variant(SCKINSEL_A::SHARED_SET0_I2S_SIGNALS)
79 }
80 #[doc = "SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
81 #[inline(always)]
82 pub fn shared_set1_i2s_signals(self) -> &'a mut W {
83 self.variant(SCKINSEL_A::SHARED_SET1_I2S_SIGNALS)
84 }
85 #[doc = r"Writes raw bits to the field"]
86 #[inline(always)]
87 pub unsafe fn bits(self, value: u8) -> &'a mut W {
88 self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
89 self.w
90 }
91}
92#[doc = "Selects the source for WS going into this Flexcomm.\n\nValue on reset: 0"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94#[repr(u8)]
95pub enum WSINSEL_A {
96 #[doc = "0: Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm."]
97 ORIG_FLEX_I2S_SIGNALS = 0,
98 #[doc = "1: WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
99 SHARED_SET0_I2S_SIGNALS = 1,
100 #[doc = "2: WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
101 SHARED_SET1_I2S_SIGNALS = 2,
102}
103impl From<WSINSEL_A> for u8 {
104 #[inline(always)]
105 fn from(variant: WSINSEL_A) -> Self {
106 variant as _
107 }
108}
109#[doc = "Reader of field `WSINSEL`"]
110pub type WSINSEL_R = crate::R<u8, WSINSEL_A>;
111impl WSINSEL_R {
112 #[doc = r"Get enumerated values variant"]
113 #[inline(always)]
114 pub fn variant(&self) -> crate::Variant<u8, WSINSEL_A> {
115 use crate::Variant::*;
116 match self.bits {
117 0 => Val(WSINSEL_A::ORIG_FLEX_I2S_SIGNALS),
118 1 => Val(WSINSEL_A::SHARED_SET0_I2S_SIGNALS),
119 2 => Val(WSINSEL_A::SHARED_SET1_I2S_SIGNALS),
120 i => Res(i),
121 }
122 }
123 #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
124 #[inline(always)]
125 pub fn is_orig_flex_i2s_signals(&self) -> bool {
126 *self == WSINSEL_A::ORIG_FLEX_I2S_SIGNALS
127 }
128 #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
129 #[inline(always)]
130 pub fn is_shared_set0_i2s_signals(&self) -> bool {
131 *self == WSINSEL_A::SHARED_SET0_I2S_SIGNALS
132 }
133 #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
134 #[inline(always)]
135 pub fn is_shared_set1_i2s_signals(&self) -> bool {
136 *self == WSINSEL_A::SHARED_SET1_I2S_SIGNALS
137 }
138}
139#[doc = "Write proxy for field `WSINSEL`"]
140pub struct WSINSEL_W<'a> {
141 w: &'a mut W,
142}
143impl<'a> WSINSEL_W<'a> {
144 #[doc = r"Writes `variant` to the field"]
145 #[inline(always)]
146 pub fn variant(self, variant: WSINSEL_A) -> &'a mut W {
147 unsafe { self.bits(variant.into()) }
148 }
149 #[doc = "Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm."]
150 #[inline(always)]
151 pub fn orig_flex_i2s_signals(self) -> &'a mut W {
152 self.variant(WSINSEL_A::ORIG_FLEX_I2S_SIGNALS)
153 }
154 #[doc = "WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
155 #[inline(always)]
156 pub fn shared_set0_i2s_signals(self) -> &'a mut W {
157 self.variant(WSINSEL_A::SHARED_SET0_I2S_SIGNALS)
158 }
159 #[doc = "WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
160 #[inline(always)]
161 pub fn shared_set1_i2s_signals(self) -> &'a mut W {
162 self.variant(WSINSEL_A::SHARED_SET1_I2S_SIGNALS)
163 }
164 #[doc = r"Writes raw bits to the field"]
165 #[inline(always)]
166 pub unsafe fn bits(self, value: u8) -> &'a mut W {
167 self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
168 self.w
169 }
170}
171#[doc = "Selects the source for DATA input to this Flexcomm.\n\nValue on reset: 0"]
172#[derive(Clone, Copy, Debug, PartialEq)]
173#[repr(u8)]
174pub enum DATAINSEL_A {
175 #[doc = "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm."]
176 ORIG_FLEX_I2S_SIGNALS = 0,
177 #[doc = "1: Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
178 SHARED_SET0_I2S_SIGNALS = 1,
179 #[doc = "2: Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
180 SHARED_SET1_I2S_SIGNALS = 2,
181}
182impl From<DATAINSEL_A> for u8 {
183 #[inline(always)]
184 fn from(variant: DATAINSEL_A) -> Self {
185 variant as _
186 }
187}
188#[doc = "Reader of field `DATAINSEL`"]
189pub type DATAINSEL_R = crate::R<u8, DATAINSEL_A>;
190impl DATAINSEL_R {
191 #[doc = r"Get enumerated values variant"]
192 #[inline(always)]
193 pub fn variant(&self) -> crate::Variant<u8, DATAINSEL_A> {
194 use crate::Variant::*;
195 match self.bits {
196 0 => Val(DATAINSEL_A::ORIG_FLEX_I2S_SIGNALS),
197 1 => Val(DATAINSEL_A::SHARED_SET0_I2S_SIGNALS),
198 2 => Val(DATAINSEL_A::SHARED_SET1_I2S_SIGNALS),
199 i => Res(i),
200 }
201 }
202 #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
203 #[inline(always)]
204 pub fn is_orig_flex_i2s_signals(&self) -> bool {
205 *self == DATAINSEL_A::ORIG_FLEX_I2S_SIGNALS
206 }
207 #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
208 #[inline(always)]
209 pub fn is_shared_set0_i2s_signals(&self) -> bool {
210 *self == DATAINSEL_A::SHARED_SET0_I2S_SIGNALS
211 }
212 #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
213 #[inline(always)]
214 pub fn is_shared_set1_i2s_signals(&self) -> bool {
215 *self == DATAINSEL_A::SHARED_SET1_I2S_SIGNALS
216 }
217}
218#[doc = "Write proxy for field `DATAINSEL`"]
219pub struct DATAINSEL_W<'a> {
220 w: &'a mut W,
221}
222impl<'a> DATAINSEL_W<'a> {
223 #[doc = r"Writes `variant` to the field"]
224 #[inline(always)]
225 pub fn variant(self, variant: DATAINSEL_A) -> &'a mut W {
226 unsafe { self.bits(variant.into()) }
227 }
228 #[doc = "Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm."]
229 #[inline(always)]
230 pub fn orig_flex_i2s_signals(self) -> &'a mut W {
231 self.variant(DATAINSEL_A::ORIG_FLEX_I2S_SIGNALS)
232 }
233 #[doc = "Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
234 #[inline(always)]
235 pub fn shared_set0_i2s_signals(self) -> &'a mut W {
236 self.variant(DATAINSEL_A::SHARED_SET0_I2S_SIGNALS)
237 }
238 #[doc = "Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
239 #[inline(always)]
240 pub fn shared_set1_i2s_signals(self) -> &'a mut W {
241 self.variant(DATAINSEL_A::SHARED_SET1_I2S_SIGNALS)
242 }
243 #[doc = r"Writes raw bits to the field"]
244 #[inline(always)]
245 pub unsafe fn bits(self, value: u8) -> &'a mut W {
246 self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
247 self.w
248 }
249}
250#[doc = "Selects the source for DATA output from this Flexcomm.\n\nValue on reset: 0"]
251#[derive(Clone, Copy, Debug, PartialEq)]
252#[repr(u8)]
253pub enum DATAOUTSEL_A {
254 #[doc = "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm."]
255 ORIG_FLEX_I2S_SIGNALS = 0,
256 #[doc = "1: Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
257 SHARED_SET0_I2S_SIGNALS = 1,
258 #[doc = "2: Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
259 SHARED_SET1_I2S_SIGNALS = 2,
260}
261impl From<DATAOUTSEL_A> for u8 {
262 #[inline(always)]
263 fn from(variant: DATAOUTSEL_A) -> Self {
264 variant as _
265 }
266}
267#[doc = "Reader of field `DATAOUTSEL`"]
268pub type DATAOUTSEL_R = crate::R<u8, DATAOUTSEL_A>;
269impl DATAOUTSEL_R {
270 #[doc = r"Get enumerated values variant"]
271 #[inline(always)]
272 pub fn variant(&self) -> crate::Variant<u8, DATAOUTSEL_A> {
273 use crate::Variant::*;
274 match self.bits {
275 0 => Val(DATAOUTSEL_A::ORIG_FLEX_I2S_SIGNALS),
276 1 => Val(DATAOUTSEL_A::SHARED_SET0_I2S_SIGNALS),
277 2 => Val(DATAOUTSEL_A::SHARED_SET1_I2S_SIGNALS),
278 i => Res(i),
279 }
280 }
281 #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
282 #[inline(always)]
283 pub fn is_orig_flex_i2s_signals(&self) -> bool {
284 *self == DATAOUTSEL_A::ORIG_FLEX_I2S_SIGNALS
285 }
286 #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
287 #[inline(always)]
288 pub fn is_shared_set0_i2s_signals(&self) -> bool {
289 *self == DATAOUTSEL_A::SHARED_SET0_I2S_SIGNALS
290 }
291 #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
292 #[inline(always)]
293 pub fn is_shared_set1_i2s_signals(&self) -> bool {
294 *self == DATAOUTSEL_A::SHARED_SET1_I2S_SIGNALS
295 }
296}
297#[doc = "Write proxy for field `DATAOUTSEL`"]
298pub struct DATAOUTSEL_W<'a> {
299 w: &'a mut W,
300}
301impl<'a> DATAOUTSEL_W<'a> {
302 #[doc = r"Writes `variant` to the field"]
303 #[inline(always)]
304 pub fn variant(self, variant: DATAOUTSEL_A) -> &'a mut W {
305 unsafe { self.bits(variant.into()) }
306 }
307 #[doc = "Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm."]
308 #[inline(always)]
309 pub fn orig_flex_i2s_signals(self) -> &'a mut W {
310 self.variant(DATAOUTSEL_A::ORIG_FLEX_I2S_SIGNALS)
311 }
312 #[doc = "Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
313 #[inline(always)]
314 pub fn shared_set0_i2s_signals(self) -> &'a mut W {
315 self.variant(DATAOUTSEL_A::SHARED_SET0_I2S_SIGNALS)
316 }
317 #[doc = "Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
318 #[inline(always)]
319 pub fn shared_set1_i2s_signals(self) -> &'a mut W {
320 self.variant(DATAOUTSEL_A::SHARED_SET1_I2S_SIGNALS)
321 }
322 #[doc = r"Writes raw bits to the field"]
323 #[inline(always)]
324 pub unsafe fn bits(self, value: u8) -> &'a mut W {
325 self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
326 self.w
327 }
328}
329impl R {
330 #[doc = "Bits 0:1 - Selects the source for SCK going into this Flexcomm."]
331 #[inline(always)]
332 pub fn sckinsel(&self) -> SCKINSEL_R {
333 SCKINSEL_R::new((self.bits & 0x03) as u8)
334 }
335 #[doc = "Bits 8:9 - Selects the source for WS going into this Flexcomm."]
336 #[inline(always)]
337 pub fn wsinsel(&self) -> WSINSEL_R {
338 WSINSEL_R::new(((self.bits >> 8) & 0x03) as u8)
339 }
340 #[doc = "Bits 16:17 - Selects the source for DATA input to this Flexcomm."]
341 #[inline(always)]
342 pub fn datainsel(&self) -> DATAINSEL_R {
343 DATAINSEL_R::new(((self.bits >> 16) & 0x03) as u8)
344 }
345 #[doc = "Bits 24:25 - Selects the source for DATA output from this Flexcomm."]
346 #[inline(always)]
347 pub fn dataoutsel(&self) -> DATAOUTSEL_R {
348 DATAOUTSEL_R::new(((self.bits >> 24) & 0x03) as u8)
349 }
350}
351impl W {
352 #[doc = "Bits 0:1 - Selects the source for SCK going into this Flexcomm."]
353 #[inline(always)]
354 pub fn sckinsel(&mut self) -> SCKINSEL_W {
355 SCKINSEL_W { w: self }
356 }
357 #[doc = "Bits 8:9 - Selects the source for WS going into this Flexcomm."]
358 #[inline(always)]
359 pub fn wsinsel(&mut self) -> WSINSEL_W {
360 WSINSEL_W { w: self }
361 }
362 #[doc = "Bits 16:17 - Selects the source for DATA input to this Flexcomm."]
363 #[inline(always)]
364 pub fn datainsel(&mut self) -> DATAINSEL_W {
365 DATAINSEL_W { w: self }
366 }
367 #[doc = "Bits 24:25 - Selects the source for DATA output from this Flexcomm."]
368 #[inline(always)]
369 pub fn dataoutsel(&mut self) -> DATAOUTSEL_W {
370 DATAOUTSEL_W { w: self }
371 }
372}