[−][src]Type Definition lpc55s6x_pac::syscon::pll1ctrl::W
type W = W<u32, PLL1CTRL>;
Writer for register PLL1CTRL
Methods
impl W[src]
pub fn selr(&mut self) -> SELR_W[src]
Bits 0:3 - Bandwidth select R value.
pub fn seli(&mut self) -> SELI_W[src]
Bits 4:9 - Bandwidth select I value.
pub fn selp(&mut self) -> SELP_W[src]
Bits 10:14 - Bandwidth select P value.
pub fn bypasspll(&mut self) -> BYPASSPLL_W[src]
Bit 15 - Bypass PLL input clock is sent directly to the PLL output (default).
pub fn bypasspostdiv2(&mut self) -> BYPASSPOSTDIV2_W[src]
Bit 16 - bypass of the divide-by-2 divider in the post-divider.
pub fn limupoff(&mut self) -> LIMUPOFF_W[src]
Bit 17 - limup_off = 1 in spread spectrum and fractional PLL applications.
pub fn bwdirect(&mut self) -> BWDIRECT_W[src]
Bit 18 - control of the bandwidth of the PLL.
pub fn bypassprediv(&mut self) -> BYPASSPREDIV_W[src]
Bit 19 - bypass of the pre-divider.
pub fn bypasspostdiv(&mut self) -> BYPASSPOSTDIV_W[src]
Bit 20 - bypass of the post-divider.
pub fn clken(&mut self) -> CLKEN_W[src]
Bit 21 - enable the output clock.
pub fn frmen(&mut self) -> FRMEN_W[src]
Bit 22 - 1: free running mode.
pub fn frmclkstable(&mut self) -> FRMCLKSTABLE_W[src]
Bit 23 - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.
pub fn skewen(&mut self) -> SKEWEN_W[src]
Bit 24 - Skew mode.