1#[doc = "Register `FIFOCFG` reader"]
2pub struct R(crate::R<FIFOCFG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<FIFOCFG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<FIFOCFG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<FIFOCFG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `FIFOCFG` writer"]
17pub struct W(crate::W<FIFOCFG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<FIFOCFG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<FIFOCFG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<FIFOCFG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ENABLETX` reader - Enable the transmit FIFO."]
38pub type ENABLETX_R = crate::BitReader<ENABLETX_A>;
39#[doc = "Enable the transmit FIFO.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum ENABLETX_A {
42 #[doc = "0: The transmit FIFO is not enabled."]
43 DISABLED = 0,
44 #[doc = "1: The transmit FIFO is enabled."]
45 ENABLED = 1,
46}
47impl From<ENABLETX_A> for bool {
48 #[inline(always)]
49 fn from(variant: ENABLETX_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl ENABLETX_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> ENABLETX_A {
57 match self.bits {
58 false => ENABLETX_A::DISABLED,
59 true => ENABLETX_A::ENABLED,
60 }
61 }
62 #[doc = "Checks if the value of the field is `DISABLED`"]
63 #[inline(always)]
64 pub fn is_disabled(&self) -> bool {
65 *self == ENABLETX_A::DISABLED
66 }
67 #[doc = "Checks if the value of the field is `ENABLED`"]
68 #[inline(always)]
69 pub fn is_enabled(&self) -> bool {
70 *self == ENABLETX_A::ENABLED
71 }
72}
73#[doc = "Field `ENABLETX` writer - Enable the transmit FIFO."]
74pub type ENABLETX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, ENABLETX_A, O>;
75impl<'a, const O: u8> ENABLETX_W<'a, O> {
76 #[doc = "The transmit FIFO is not enabled."]
77 #[inline(always)]
78 pub fn disabled(self) -> &'a mut W {
79 self.variant(ENABLETX_A::DISABLED)
80 }
81 #[doc = "The transmit FIFO is enabled."]
82 #[inline(always)]
83 pub fn enabled(self) -> &'a mut W {
84 self.variant(ENABLETX_A::ENABLED)
85 }
86}
87#[doc = "Field `ENABLERX` reader - Enable the receive FIFO."]
88pub type ENABLERX_R = crate::BitReader<ENABLERX_A>;
89#[doc = "Enable the receive FIFO.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum ENABLERX_A {
92 #[doc = "0: The receive FIFO is not enabled."]
93 DISABLED = 0,
94 #[doc = "1: The receive FIFO is enabled."]
95 ENABLED = 1,
96}
97impl From<ENABLERX_A> for bool {
98 #[inline(always)]
99 fn from(variant: ENABLERX_A) -> Self {
100 variant as u8 != 0
101 }
102}
103impl ENABLERX_R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub fn variant(&self) -> ENABLERX_A {
107 match self.bits {
108 false => ENABLERX_A::DISABLED,
109 true => ENABLERX_A::ENABLED,
110 }
111 }
112 #[doc = "Checks if the value of the field is `DISABLED`"]
113 #[inline(always)]
114 pub fn is_disabled(&self) -> bool {
115 *self == ENABLERX_A::DISABLED
116 }
117 #[doc = "Checks if the value of the field is `ENABLED`"]
118 #[inline(always)]
119 pub fn is_enabled(&self) -> bool {
120 *self == ENABLERX_A::ENABLED
121 }
122}
123#[doc = "Field `ENABLERX` writer - Enable the receive FIFO."]
124pub type ENABLERX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, ENABLERX_A, O>;
125impl<'a, const O: u8> ENABLERX_W<'a, O> {
126 #[doc = "The receive FIFO is not enabled."]
127 #[inline(always)]
128 pub fn disabled(self) -> &'a mut W {
129 self.variant(ENABLERX_A::DISABLED)
130 }
131 #[doc = "The receive FIFO is enabled."]
132 #[inline(always)]
133 pub fn enabled(self) -> &'a mut W {
134 self.variant(ENABLERX_A::ENABLED)
135 }
136}
137#[doc = "Field `SIZE` reader - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART."]
138pub type SIZE_R = crate::FieldReader<u8, u8>;
139#[doc = "Field `DMATX` reader - DMA configuration for transmit."]
140pub type DMATX_R = crate::BitReader<DMATX_A>;
141#[doc = "DMA configuration for transmit.\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum DMATX_A {
144 #[doc = "0: DMA is not used for the transmit function."]
145 DISABLED = 0,
146 #[doc = "1: Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled."]
147 ENABLED = 1,
148}
149impl From<DMATX_A> for bool {
150 #[inline(always)]
151 fn from(variant: DMATX_A) -> Self {
152 variant as u8 != 0
153 }
154}
155impl DMATX_R {
156 #[doc = "Get enumerated values variant"]
157 #[inline(always)]
158 pub fn variant(&self) -> DMATX_A {
159 match self.bits {
160 false => DMATX_A::DISABLED,
161 true => DMATX_A::ENABLED,
162 }
163 }
164 #[doc = "Checks if the value of the field is `DISABLED`"]
165 #[inline(always)]
166 pub fn is_disabled(&self) -> bool {
167 *self == DMATX_A::DISABLED
168 }
169 #[doc = "Checks if the value of the field is `ENABLED`"]
170 #[inline(always)]
171 pub fn is_enabled(&self) -> bool {
172 *self == DMATX_A::ENABLED
173 }
174}
175#[doc = "Field `DMATX` writer - DMA configuration for transmit."]
176pub type DMATX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, DMATX_A, O>;
177impl<'a, const O: u8> DMATX_W<'a, O> {
178 #[doc = "DMA is not used for the transmit function."]
179 #[inline(always)]
180 pub fn disabled(self) -> &'a mut W {
181 self.variant(DMATX_A::DISABLED)
182 }
183 #[doc = "Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled."]
184 #[inline(always)]
185 pub fn enabled(self) -> &'a mut W {
186 self.variant(DMATX_A::ENABLED)
187 }
188}
189#[doc = "Field `DMARX` reader - DMA configuration for receive."]
190pub type DMARX_R = crate::BitReader<DMARX_A>;
191#[doc = "DMA configuration for receive.\n\nValue on reset: 0"]
192#[derive(Clone, Copy, Debug, PartialEq, Eq)]
193pub enum DMARX_A {
194 #[doc = "0: DMA is not used for the receive function."]
195 DISABLED = 0,
196 #[doc = "1: Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled."]
197 ENABLED = 1,
198}
199impl From<DMARX_A> for bool {
200 #[inline(always)]
201 fn from(variant: DMARX_A) -> Self {
202 variant as u8 != 0
203 }
204}
205impl DMARX_R {
206 #[doc = "Get enumerated values variant"]
207 #[inline(always)]
208 pub fn variant(&self) -> DMARX_A {
209 match self.bits {
210 false => DMARX_A::DISABLED,
211 true => DMARX_A::ENABLED,
212 }
213 }
214 #[doc = "Checks if the value of the field is `DISABLED`"]
215 #[inline(always)]
216 pub fn is_disabled(&self) -> bool {
217 *self == DMARX_A::DISABLED
218 }
219 #[doc = "Checks if the value of the field is `ENABLED`"]
220 #[inline(always)]
221 pub fn is_enabled(&self) -> bool {
222 *self == DMARX_A::ENABLED
223 }
224}
225#[doc = "Field `DMARX` writer - DMA configuration for receive."]
226pub type DMARX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, DMARX_A, O>;
227impl<'a, const O: u8> DMARX_W<'a, O> {
228 #[doc = "DMA is not used for the receive function."]
229 #[inline(always)]
230 pub fn disabled(self) -> &'a mut W {
231 self.variant(DMARX_A::DISABLED)
232 }
233 #[doc = "Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled."]
234 #[inline(always)]
235 pub fn enabled(self) -> &'a mut W {
236 self.variant(DMARX_A::ENABLED)
237 }
238}
239#[doc = "Field `WAKETX` reader - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
240pub type WAKETX_R = crate::BitReader<WAKETX_A>;
241#[doc = "Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq, Eq)]
243pub enum WAKETX_A {
244 #[doc = "0: Only enabled interrupts will wake up the device form reduced power modes."]
245 DISABLED = 0,
246 #[doc = "1: A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled."]
247 ENABLED = 1,
248}
249impl From<WAKETX_A> for bool {
250 #[inline(always)]
251 fn from(variant: WAKETX_A) -> Self {
252 variant as u8 != 0
253 }
254}
255impl WAKETX_R {
256 #[doc = "Get enumerated values variant"]
257 #[inline(always)]
258 pub fn variant(&self) -> WAKETX_A {
259 match self.bits {
260 false => WAKETX_A::DISABLED,
261 true => WAKETX_A::ENABLED,
262 }
263 }
264 #[doc = "Checks if the value of the field is `DISABLED`"]
265 #[inline(always)]
266 pub fn is_disabled(&self) -> bool {
267 *self == WAKETX_A::DISABLED
268 }
269 #[doc = "Checks if the value of the field is `ENABLED`"]
270 #[inline(always)]
271 pub fn is_enabled(&self) -> bool {
272 *self == WAKETX_A::ENABLED
273 }
274}
275#[doc = "Field `WAKETX` writer - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
276pub type WAKETX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, WAKETX_A, O>;
277impl<'a, const O: u8> WAKETX_W<'a, O> {
278 #[doc = "Only enabled interrupts will wake up the device form reduced power modes."]
279 #[inline(always)]
280 pub fn disabled(self) -> &'a mut W {
281 self.variant(WAKETX_A::DISABLED)
282 }
283 #[doc = "A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled."]
284 #[inline(always)]
285 pub fn enabled(self) -> &'a mut W {
286 self.variant(WAKETX_A::ENABLED)
287 }
288}
289#[doc = "Field `WAKERX` reader - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
290pub type WAKERX_R = crate::BitReader<WAKERX_A>;
291#[doc = "Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum WAKERX_A {
294 #[doc = "0: Only enabled interrupts will wake up the device form reduced power modes."]
295 DISABLED = 0,
296 #[doc = "1: A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled."]
297 ENABLED = 1,
298}
299impl From<WAKERX_A> for bool {
300 #[inline(always)]
301 fn from(variant: WAKERX_A) -> Self {
302 variant as u8 != 0
303 }
304}
305impl WAKERX_R {
306 #[doc = "Get enumerated values variant"]
307 #[inline(always)]
308 pub fn variant(&self) -> WAKERX_A {
309 match self.bits {
310 false => WAKERX_A::DISABLED,
311 true => WAKERX_A::ENABLED,
312 }
313 }
314 #[doc = "Checks if the value of the field is `DISABLED`"]
315 #[inline(always)]
316 pub fn is_disabled(&self) -> bool {
317 *self == WAKERX_A::DISABLED
318 }
319 #[doc = "Checks if the value of the field is `ENABLED`"]
320 #[inline(always)]
321 pub fn is_enabled(&self) -> bool {
322 *self == WAKERX_A::ENABLED
323 }
324}
325#[doc = "Field `WAKERX` writer - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
326pub type WAKERX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, WAKERX_A, O>;
327impl<'a, const O: u8> WAKERX_W<'a, O> {
328 #[doc = "Only enabled interrupts will wake up the device form reduced power modes."]
329 #[inline(always)]
330 pub fn disabled(self) -> &'a mut W {
331 self.variant(WAKERX_A::DISABLED)
332 }
333 #[doc = "A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled."]
334 #[inline(always)]
335 pub fn enabled(self) -> &'a mut W {
336 self.variant(WAKERX_A::ENABLED)
337 }
338}
339#[doc = "Field `EMPTYTX` reader - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied."]
340pub type EMPTYTX_R = crate::BitReader<bool>;
341#[doc = "Field `EMPTYTX` writer - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied."]
342pub type EMPTYTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, bool, O>;
343#[doc = "Field `EMPTYRX` reader - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied."]
344pub type EMPTYRX_R = crate::BitReader<bool>;
345#[doc = "Field `EMPTYRX` writer - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied."]
346pub type EMPTYRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOCFG_SPEC, bool, O>;
347impl R {
348 #[doc = "Bit 0 - Enable the transmit FIFO."]
349 #[inline(always)]
350 pub fn enabletx(&self) -> ENABLETX_R {
351 ENABLETX_R::new((self.bits & 1) != 0)
352 }
353 #[doc = "Bit 1 - Enable the receive FIFO."]
354 #[inline(always)]
355 pub fn enablerx(&self) -> ENABLERX_R {
356 ENABLERX_R::new(((self.bits >> 1) & 1) != 0)
357 }
358 #[doc = "Bits 4:5 - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART."]
359 #[inline(always)]
360 pub fn size(&self) -> SIZE_R {
361 SIZE_R::new(((self.bits >> 4) & 3) as u8)
362 }
363 #[doc = "Bit 12 - DMA configuration for transmit."]
364 #[inline(always)]
365 pub fn dmatx(&self) -> DMATX_R {
366 DMATX_R::new(((self.bits >> 12) & 1) != 0)
367 }
368 #[doc = "Bit 13 - DMA configuration for receive."]
369 #[inline(always)]
370 pub fn dmarx(&self) -> DMARX_R {
371 DMARX_R::new(((self.bits >> 13) & 1) != 0)
372 }
373 #[doc = "Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
374 #[inline(always)]
375 pub fn waketx(&self) -> WAKETX_R {
376 WAKETX_R::new(((self.bits >> 14) & 1) != 0)
377 }
378 #[doc = "Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
379 #[inline(always)]
380 pub fn wakerx(&self) -> WAKERX_R {
381 WAKERX_R::new(((self.bits >> 15) & 1) != 0)
382 }
383 #[doc = "Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied."]
384 #[inline(always)]
385 pub fn emptytx(&self) -> EMPTYTX_R {
386 EMPTYTX_R::new(((self.bits >> 16) & 1) != 0)
387 }
388 #[doc = "Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied."]
389 #[inline(always)]
390 pub fn emptyrx(&self) -> EMPTYRX_R {
391 EMPTYRX_R::new(((self.bits >> 17) & 1) != 0)
392 }
393}
394impl W {
395 #[doc = "Bit 0 - Enable the transmit FIFO."]
396 #[inline(always)]
397 pub fn enabletx(&mut self) -> ENABLETX_W<0> {
398 ENABLETX_W::new(self)
399 }
400 #[doc = "Bit 1 - Enable the receive FIFO."]
401 #[inline(always)]
402 pub fn enablerx(&mut self) -> ENABLERX_W<1> {
403 ENABLERX_W::new(self)
404 }
405 #[doc = "Bit 12 - DMA configuration for transmit."]
406 #[inline(always)]
407 pub fn dmatx(&mut self) -> DMATX_W<12> {
408 DMATX_W::new(self)
409 }
410 #[doc = "Bit 13 - DMA configuration for receive."]
411 #[inline(always)]
412 pub fn dmarx(&mut self) -> DMARX_W<13> {
413 DMARX_W::new(self)
414 }
415 #[doc = "Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
416 #[inline(always)]
417 pub fn waketx(&mut self) -> WAKETX_W<14> {
418 WAKETX_W::new(self)
419 }
420 #[doc = "Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register."]
421 #[inline(always)]
422 pub fn wakerx(&mut self) -> WAKERX_W<15> {
423 WAKERX_W::new(self)
424 }
425 #[doc = "Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied."]
426 #[inline(always)]
427 pub fn emptytx(&mut self) -> EMPTYTX_W<16> {
428 EMPTYTX_W::new(self)
429 }
430 #[doc = "Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied."]
431 #[inline(always)]
432 pub fn emptyrx(&mut self) -> EMPTYRX_W<17> {
433 EMPTYRX_W::new(self)
434 }
435 #[doc = "Writes raw bits to the register."]
436 #[inline(always)]
437 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
438 self.0.bits(bits);
439 self
440 }
441}
442#[doc = "FIFO configuration and enable register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifocfg](index.html) module"]
443pub struct FIFOCFG_SPEC;
444impl crate::RegisterSpec for FIFOCFG_SPEC {
445 type Ux = u32;
446}
447#[doc = "`read()` method returns [fifocfg::R](R) reader structure"]
448impl crate::Readable for FIFOCFG_SPEC {
449 type Reader = R;
450}
451#[doc = "`write(|w| ..)` method takes [fifocfg::W](W) writer structure"]
452impl crate::Writable for FIFOCFG_SPEC {
453 type Writer = W;
454}
455#[doc = "`reset()` method sets FIFOCFG to value 0"]
456impl crate::Resettable for FIFOCFG_SPEC {
457 #[inline(always)]
458 fn reset_value() -> Self::Ux {
459 0
460 }
461}