lpc550x/syscon/
clockgenupdatelockout.rs

1#[doc = "Register `CLOCKGENUPDATELOCKOUT` reader"]
2pub struct R(crate::R<CLOCKGENUPDATELOCKOUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLOCKGENUPDATELOCKOUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLOCKGENUPDATELOCKOUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLOCKGENUPDATELOCKOUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLOCKGENUPDATELOCKOUT` writer"]
17pub struct W(crate::W<CLOCKGENUPDATELOCKOUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLOCKGENUPDATELOCKOUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLOCKGENUPDATELOCKOUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLOCKGENUPDATELOCKOUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLOCKGENUPDATELOCKOUT` reader - Control clock configuration registers access (for example, xxxDIV, xxxSEL)."]
38pub type CLOCKGENUPDATELOCKOUT_R = crate::FieldReader<u32, CLOCKGENUPDATELOCKOUT_A>;
39#[doc = "Control clock configuration registers access (for example, xxxDIV, xxxSEL).\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u32)]
42pub enum CLOCKGENUPDATELOCKOUT_A {
43    #[doc = "0: all hardware clock configruration are freeze."]
44    FREEZE = 0,
45    #[doc = "1: update all clock configuration."]
46    ENABLE = 1,
47}
48impl From<CLOCKGENUPDATELOCKOUT_A> for u32 {
49    #[inline(always)]
50    fn from(variant: CLOCKGENUPDATELOCKOUT_A) -> Self {
51        variant as _
52    }
53}
54impl CLOCKGENUPDATELOCKOUT_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<CLOCKGENUPDATELOCKOUT_A> {
58        match self.bits {
59            0 => Some(CLOCKGENUPDATELOCKOUT_A::FREEZE),
60            1 => Some(CLOCKGENUPDATELOCKOUT_A::ENABLE),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `FREEZE`"]
65    #[inline(always)]
66    pub fn is_freeze(&self) -> bool {
67        *self == CLOCKGENUPDATELOCKOUT_A::FREEZE
68    }
69    #[doc = "Checks if the value of the field is `ENABLE`"]
70    #[inline(always)]
71    pub fn is_enable(&self) -> bool {
72        *self == CLOCKGENUPDATELOCKOUT_A::ENABLE
73    }
74}
75#[doc = "Field `CLOCKGENUPDATELOCKOUT` writer - Control clock configuration registers access (for example, xxxDIV, xxxSEL)."]
76pub type CLOCKGENUPDATELOCKOUT_W<'a, const O: u8> =
77    crate::FieldWriter<'a, u32, CLOCKGENUPDATELOCKOUT_SPEC, u32, CLOCKGENUPDATELOCKOUT_A, 32, O>;
78impl<'a, const O: u8> CLOCKGENUPDATELOCKOUT_W<'a, O> {
79    #[doc = "all hardware clock configruration are freeze."]
80    #[inline(always)]
81    pub fn freeze(self) -> &'a mut W {
82        self.variant(CLOCKGENUPDATELOCKOUT_A::FREEZE)
83    }
84    #[doc = "update all clock configuration."]
85    #[inline(always)]
86    pub fn enable(self) -> &'a mut W {
87        self.variant(CLOCKGENUPDATELOCKOUT_A::ENABLE)
88    }
89}
90impl R {
91    #[doc = "Bits 0:31 - Control clock configuration registers access (for example, xxxDIV, xxxSEL)."]
92    #[inline(always)]
93    pub fn clockgenupdatelockout(&self) -> CLOCKGENUPDATELOCKOUT_R {
94        CLOCKGENUPDATELOCKOUT_R::new(self.bits)
95    }
96}
97impl W {
98    #[doc = "Bits 0:31 - Control clock configuration registers access (for example, xxxDIV, xxxSEL)."]
99    #[inline(always)]
100    pub fn clockgenupdatelockout(&mut self) -> CLOCKGENUPDATELOCKOUT_W<0> {
101        CLOCKGENUPDATELOCKOUT_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clockgenupdatelockout](index.html) module"]
111pub struct CLOCKGENUPDATELOCKOUT_SPEC;
112impl crate::RegisterSpec for CLOCKGENUPDATELOCKOUT_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [clockgenupdatelockout::R](R) reader structure"]
116impl crate::Readable for CLOCKGENUPDATELOCKOUT_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [clockgenupdatelockout::W](W) writer structure"]
120impl crate::Writable for CLOCKGENUPDATELOCKOUT_SPEC {
121    type Writer = W;
122}
123#[doc = "`reset()` method sets CLOCKGENUPDATELOCKOUT to value 0"]
124impl crate::Resettable for CLOCKGENUPDATELOCKOUT_SPEC {
125    #[inline(always)]
126    fn reset_value() -> Self::Ux {
127        0
128    }
129}
lpc550x/syscon/clockgenupdatelockout.rs

lpc550x/syscon/
clockgenupdatelockout.rs
