lpc550x/syscon/
cpu0nstckcal.rs

1#[doc = "Register `CPU0NSTCKCAL` reader"]
2pub struct R(crate::R<CPU0NSTCKCAL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CPU0NSTCKCAL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CPU0NSTCKCAL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CPU0NSTCKCAL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CPU0NSTCKCAL` writer"]
17pub struct W(crate::W<CPU0NSTCKCAL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CPU0NSTCKCAL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CPU0NSTCKCAL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CPU0NSTCKCAL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TENMS` reader - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."]
38pub type TENMS_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `TENMS` writer - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."]
40pub type TENMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CPU0NSTCKCAL_SPEC, u32, u32, 24, O>;
41#[doc = "Field `SKEW` reader - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given."]
42pub type SKEW_R = crate::BitReader<bool>;
43#[doc = "Field `SKEW` writer - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given."]
44pub type SKEW_W<'a, const O: u8> = crate::BitWriter<'a, u32, CPU0NSTCKCAL_SPEC, bool, O>;
45#[doc = "Field `NOREF` reader - Initial value for the Systick timer."]
46pub type NOREF_R = crate::BitReader<bool>;
47#[doc = "Field `NOREF` writer - Initial value for the Systick timer."]
48pub type NOREF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CPU0NSTCKCAL_SPEC, bool, O>;
49impl R {
50    #[doc = "Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."]
51    #[inline(always)]
52    pub fn tenms(&self) -> TENMS_R {
53        TENMS_R::new((self.bits & 0x00ff_ffff) as u32)
54    }
55    #[doc = "Bit 24 - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given."]
56    #[inline(always)]
57    pub fn skew(&self) -> SKEW_R {
58        SKEW_R::new(((self.bits >> 24) & 1) != 0)
59    }
60    #[doc = "Bit 25 - Initial value for the Systick timer."]
61    #[inline(always)]
62    pub fn noref(&self) -> NOREF_R {
63        NOREF_R::new(((self.bits >> 25) & 1) != 0)
64    }
65}
66impl W {
67    #[doc = "Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known."]
68    #[inline(always)]
69    pub fn tenms(&mut self) -> TENMS_W<0> {
70        TENMS_W::new(self)
71    }
72    #[doc = "Bit 24 - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given."]
73    #[inline(always)]
74    pub fn skew(&mut self) -> SKEW_W<24> {
75        SKEW_W::new(self)
76    }
77    #[doc = "Bit 25 - Initial value for the Systick timer."]
78    #[inline(always)]
79    pub fn noref(&mut self) -> NOREF_W<25> {
80        NOREF_W::new(self)
81    }
82    #[doc = "Writes raw bits to the register."]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.0.bits(bits);
86        self
87    }
88}
89#[doc = "System tick calibration for non-secure part of CPU0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpu0nstckcal](index.html) module"]
90pub struct CPU0NSTCKCAL_SPEC;
91impl crate::RegisterSpec for CPU0NSTCKCAL_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [cpu0nstckcal::R](R) reader structure"]
95impl crate::Readable for CPU0NSTCKCAL_SPEC {
96    type Reader = R;
97}
98#[doc = "`write(|w| ..)` method takes [cpu0nstckcal::W](W) writer structure"]
99impl crate::Writable for CPU0NSTCKCAL_SPEC {
100    type Writer = W;
101}
102#[doc = "`reset()` method sets CPU0NSTCKCAL to value 0"]
103impl crate::Resettable for CPU0NSTCKCAL_SPEC {
104    #[inline(always)]
105    fn reset_value() -> Self::Ux {
106        0
107    }
108}
lpc550x/syscon/cpu0nstckcal.rs

lpc550x/syscon/
cpu0nstckcal.rs
