1#[doc = "Register `FIFOTRIG` reader"]
2pub struct R(crate::R<FIFOTRIG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<FIFOTRIG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<FIFOTRIG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<FIFOTRIG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `FIFOTRIG` writer"]
17pub struct W(crate::W<FIFOTRIG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<FIFOTRIG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<FIFOTRIG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<FIFOTRIG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TXLVLENA` reader - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set."]
38pub type TXLVLENA_R = crate::BitReader<TXLVLENA_A>;
39#[doc = "Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum TXLVLENA_A {
42 #[doc = "0: Transmit FIFO level does not generate a FIFO level trigger."]
43 DISABLED = 0,
44 #[doc = "1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register."]
45 ENABLED = 1,
46}
47impl From<TXLVLENA_A> for bool {
48 #[inline(always)]
49 fn from(variant: TXLVLENA_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl TXLVLENA_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> TXLVLENA_A {
57 match self.bits {
58 false => TXLVLENA_A::DISABLED,
59 true => TXLVLENA_A::ENABLED,
60 }
61 }
62 #[doc = "Checks if the value of the field is `DISABLED`"]
63 #[inline(always)]
64 pub fn is_disabled(&self) -> bool {
65 *self == TXLVLENA_A::DISABLED
66 }
67 #[doc = "Checks if the value of the field is `ENABLED`"]
68 #[inline(always)]
69 pub fn is_enabled(&self) -> bool {
70 *self == TXLVLENA_A::ENABLED
71 }
72}
73#[doc = "Field `TXLVLENA` writer - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set."]
74pub type TXLVLENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOTRIG_SPEC, TXLVLENA_A, O>;
75impl<'a, const O: u8> TXLVLENA_W<'a, O> {
76 #[doc = "Transmit FIFO level does not generate a FIFO level trigger."]
77 #[inline(always)]
78 pub fn disabled(self) -> &'a mut W {
79 self.variant(TXLVLENA_A::DISABLED)
80 }
81 #[doc = "An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register."]
82 #[inline(always)]
83 pub fn enabled(self) -> &'a mut W {
84 self.variant(TXLVLENA_A::ENABLED)
85 }
86}
87#[doc = "Field `RXLVLENA` reader - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set."]
88pub type RXLVLENA_R = crate::BitReader<RXLVLENA_A>;
89#[doc = "Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum RXLVLENA_A {
92 #[doc = "0: Receive FIFO level does not generate a FIFO level trigger."]
93 DISABLED = 0,
94 #[doc = "1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register."]
95 ENABLED = 1,
96}
97impl From<RXLVLENA_A> for bool {
98 #[inline(always)]
99 fn from(variant: RXLVLENA_A) -> Self {
100 variant as u8 != 0
101 }
102}
103impl RXLVLENA_R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub fn variant(&self) -> RXLVLENA_A {
107 match self.bits {
108 false => RXLVLENA_A::DISABLED,
109 true => RXLVLENA_A::ENABLED,
110 }
111 }
112 #[doc = "Checks if the value of the field is `DISABLED`"]
113 #[inline(always)]
114 pub fn is_disabled(&self) -> bool {
115 *self == RXLVLENA_A::DISABLED
116 }
117 #[doc = "Checks if the value of the field is `ENABLED`"]
118 #[inline(always)]
119 pub fn is_enabled(&self) -> bool {
120 *self == RXLVLENA_A::ENABLED
121 }
122}
123#[doc = "Field `RXLVLENA` writer - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set."]
124pub type RXLVLENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFOTRIG_SPEC, RXLVLENA_A, O>;
125impl<'a, const O: u8> RXLVLENA_W<'a, O> {
126 #[doc = "Receive FIFO level does not generate a FIFO level trigger."]
127 #[inline(always)]
128 pub fn disabled(self) -> &'a mut W {
129 self.variant(RXLVLENA_A::DISABLED)
130 }
131 #[doc = "An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register."]
132 #[inline(always)]
133 pub fn enabled(self) -> &'a mut W {
134 self.variant(RXLVLENA_A::ENABLED)
135 }
136}
137#[doc = "Field `TXLVL` reader - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)."]
138pub type TXLVL_R = crate::FieldReader<u8, u8>;
139#[doc = "Field `TXLVL` writer - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)."]
140pub type TXLVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOTRIG_SPEC, u8, u8, 4, O>;
141#[doc = "Field `RXLVL` reader - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)."]
142pub type RXLVL_R = crate::FieldReader<u8, u8>;
143#[doc = "Field `RXLVL` writer - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)."]
144pub type RXLVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFOTRIG_SPEC, u8, u8, 4, O>;
145impl R {
146 #[doc = "Bit 0 - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set."]
147 #[inline(always)]
148 pub fn txlvlena(&self) -> TXLVLENA_R {
149 TXLVLENA_R::new((self.bits & 1) != 0)
150 }
151 #[doc = "Bit 1 - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set."]
152 #[inline(always)]
153 pub fn rxlvlena(&self) -> RXLVLENA_R {
154 RXLVLENA_R::new(((self.bits >> 1) & 1) != 0)
155 }
156 #[doc = "Bits 8:11 - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)."]
157 #[inline(always)]
158 pub fn txlvl(&self) -> TXLVL_R {
159 TXLVL_R::new(((self.bits >> 8) & 0x0f) as u8)
160 }
161 #[doc = "Bits 16:19 - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)."]
162 #[inline(always)]
163 pub fn rxlvl(&self) -> RXLVL_R {
164 RXLVL_R::new(((self.bits >> 16) & 0x0f) as u8)
165 }
166}
167impl W {
168 #[doc = "Bit 0 - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set."]
169 #[inline(always)]
170 pub fn txlvlena(&mut self) -> TXLVLENA_W<0> {
171 TXLVLENA_W::new(self)
172 }
173 #[doc = "Bit 1 - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set."]
174 #[inline(always)]
175 pub fn rxlvlena(&mut self) -> RXLVLENA_W<1> {
176 RXLVLENA_W::new(self)
177 }
178 #[doc = "Bits 8:11 - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full)."]
179 #[inline(always)]
180 pub fn txlvl(&mut self) -> TXLVL_W<8> {
181 TXLVL_W::new(self)
182 }
183 #[doc = "Bits 16:19 - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full)."]
184 #[inline(always)]
185 pub fn rxlvl(&mut self) -> RXLVL_W<16> {
186 RXLVL_W::new(self)
187 }
188 #[doc = "Writes raw bits to the register."]
189 #[inline(always)]
190 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
191 self.0.bits(bits);
192 self
193 }
194}
195#[doc = "FIFO trigger settings for interrupt and DMA request.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifotrig](index.html) module"]
196pub struct FIFOTRIG_SPEC;
197impl crate::RegisterSpec for FIFOTRIG_SPEC {
198 type Ux = u32;
199}
200#[doc = "`read()` method returns [fifotrig::R](R) reader structure"]
201impl crate::Readable for FIFOTRIG_SPEC {
202 type Reader = R;
203}
204#[doc = "`write(|w| ..)` method takes [fifotrig::W](W) writer structure"]
205impl crate::Writable for FIFOTRIG_SPEC {
206 type Writer = W;
207}
208#[doc = "`reset()` method sets FIFOTRIG to value 0"]
209impl crate::Resettable for FIFOTRIG_SPEC {
210 #[inline(always)]
211 fn reset_value() -> Self::Ux {
212 0
213 }
214}