lpc550x/
ahb_secure_ctrl.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - Security access rules for Flash and ROM slaves."]
5    pub sec_ctrl_flash_rom_slave_rule: SEC_CTRL_FLASH_ROM_SLAVE_RULE,
6    _reserved1: [u8; 0x0c],
7    #[doc = "0x10 - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total."]
8    pub sec_ctrl_flash_mem_rule0: SEC_CTRL_FLASH_MEM_RULE0,
9    _reserved2: [u8; 0x0c],
10    #[doc = "0x20 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
11    pub sec_ctrl_rom_mem_rule0: SEC_CTRL_ROM_MEM_RULE0,
12    #[doc = "0x24 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
13    pub sec_ctrl_rom_mem_rule1: SEC_CTRL_ROM_MEM_RULE1,
14    #[doc = "0x28 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
15    pub sec_ctrl_rom_mem_rule2: SEC_CTRL_ROM_MEM_RULE2,
16    #[doc = "0x2c - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
17    pub sec_ctrl_rom_mem_rule3: SEC_CTRL_ROM_MEM_RULE3,
18    #[doc = "0x30 - Security access rules for RAMX slaves."]
19    pub sec_ctrl_ramx_slave_rule: SEC_CTRL_RAMX_SLAVE_RULE,
20    _reserved7: [u8; 0x0c],
21    #[doc = "0x40 - Security access rules for RAMX slaves."]
22    pub sec_ctrl_ramx_mem_rule0: SEC_CTRL_RAMX_MEM_RULE0,
23    _reserved8: [u8; 0x0c],
24    #[doc = "0x50 - Security access rules for RAM0 slaves."]
25    pub sec_ctrl_ram0_slave_rule: SEC_CTRL_RAM0_SLAVE_RULE,
26    _reserved9: [u8; 0x0c],
27    #[doc = "0x60 - Security access rules for RAM0 slaves."]
28    pub sec_ctrl_ram0_mem_rule0: SEC_CTRL_RAM0_MEM_RULE0,
29    _reserved10: [u8; 0x0c],
30    #[doc = "0x70 - Security access rules for RAM1 slaves."]
31    pub sec_ctrl_ram1_slave_rule: SEC_CTRL_RAM1_SLAVE_RULE,
32    _reserved11: [u8; 0x0c],
33    #[doc = "0x80 - Security access rules for RAM1 slaves."]
34    pub sec_ctrl_ram1_mem_rule0: SEC_CTRL_RAM1_MEM_RULE0,
35    _reserved12: [u8; 0x0c],
36    #[doc = "0x90 - Security access rules for RAM2 slaves."]
37    pub sec_ctrl_ram2_slave_rule: SEC_CTRL_RAM2_SLAVE_RULE,
38    _reserved13: [u8; 0x0c],
39    #[doc = "0xa0 - Security access rules for RAM2 slaves."]
40    pub sec_ctrl_ram2_mem_rule0: SEC_CTRL_RAM2_MEM_RULE0,
41    _reserved14: [u8; 0x0c],
42    #[doc = "0xb0 - Security access rules for RAM3 slaves."]
43    pub sec_ctrl_ram3_slave_rule: SEC_CTRL_RAM3_SLAVE_RULE,
44    _reserved15: [u8; 0x0c],
45    #[doc = "0xc0 - Security access rules for RAM3."]
46    pub sec_ctrl_ram3_mem_rule0: SEC_CTRL_RAM3_MEM_RULE0,
47    _reserved16: [u8; 0x0c],
48    #[doc = "0xd0 - Security access rules for both APB Bridges slaves."]
49    pub sec_ctrl_apb_bridge_slave_rule: SEC_CTRL_APB_BRIDGE_SLAVE_RULE,
50    _reserved17: [u8; 0x0c],
51    #[doc = "0xe0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
52    pub sec_ctrl_apb_bridge0_mem_ctrl0: SEC_CTRL_APB_BRIDGE0_MEM_CTRL0,
53    #[doc = "0xe4 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
54    pub sec_ctrl_apb_bridge0_mem_ctrl1: SEC_CTRL_APB_BRIDGE0_MEM_CTRL1,
55    #[doc = "0xe8 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
56    pub sec_ctrl_apb_bridge0_mem_ctrl2: SEC_CTRL_APB_BRIDGE0_MEM_CTRL2,
57    _reserved20: [u8; 0x04],
58    #[doc = "0xf0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
59    pub sec_ctrl_apb_bridge1_mem_ctrl0: SEC_CTRL_APB_BRIDGE1_MEM_CTRL0,
60    #[doc = "0xf4 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
61    pub sec_ctrl_apb_bridge1_mem_ctrl1: SEC_CTRL_APB_BRIDGE1_MEM_CTRL1,
62    #[doc = "0xf8 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
63    pub sec_ctrl_apb_bridge1_mem_ctrl2: SEC_CTRL_APB_BRIDGE1_MEM_CTRL2,
64    #[doc = "0xfc - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
65    pub sec_ctrl_apb_bridge1_mem_ctrl3: SEC_CTRL_APB_BRIDGE1_MEM_CTRL3,
66    #[doc = "0x100 - Security access rules for AHB peripherals."]
67    pub sec_ctrl_ahb_port7_slave0_rule: SEC_CTRL_AHB_PORT7_SLAVE0_RULE,
68    #[doc = "0x104 - Security access rules for AHB peripherals."]
69    pub sec_ctrl_ahb_port7_slave1_rule: SEC_CTRL_AHB_PORT7_SLAVE1_RULE,
70    _reserved26: [u8; 0x08],
71    #[doc = "0x110 - Security access rules for AHB peripherals."]
72    pub sec_ctrl_ahb_port8_slave0_rule: SEC_CTRL_AHB_PORT8_SLAVE0_RULE,
73    #[doc = "0x114 - Security access rules for AHB peripherals."]
74    pub sec_ctrl_ahb_port8_slave1_rule: SEC_CTRL_AHB_PORT8_SLAVE1_RULE,
75    _reserved28: [u8; 0x08],
76    #[doc = "0x120 - Security access rules for AHB peripherals."]
77    pub sec_ctrl_ahb_port9_slave0_rule: SEC_CTRL_AHB_PORT9_SLAVE0_RULE,
78    #[doc = "0x124 - Security access rules for AHB peripherals."]
79    pub sec_ctrl_ahb_port9_slave1_rule: SEC_CTRL_AHB_PORT9_SLAVE1_RULE,
80    _reserved30: [u8; 0x08],
81    #[doc = "0x130 - Security access rules for AHB_SEC_CTRL_AHB."]
82    pub sec_ctrl_ahb_sec_ctrl_mem_rule: SEC_CTRL_AHB_SEC_CTRL_MEM_RULE,
83    _reserved31: [u8; 0x0ccc],
84    #[doc = "0xe00..0xe28 - most recent security violation address for AHB layer n."]
85    pub sec_vio_addr: [SEC_VIO_ADDR; 10],
86    _reserved32: [u8; 0x58],
87    #[doc = "0xe80..0xea8 - most recent security violation miscellaneous information for AHB layer n."]
88    pub sec_vio_misc_info: [SEC_VIO_MISC_INFO; 10],
89    _reserved33: [u8; 0x58],
90    #[doc = "0xf00 - security violation address/information registers valid flags."]
91    pub sec_vio_info_valid: SEC_VIO_INFO_VALID,
92    _reserved34: [u8; 0x7c],
93    #[doc = "0xf80 - Secure GPIO mask for port 0 pins."]
94    pub sec_gpio_mask0: SEC_GPIO_MASK0,
95    #[doc = "0xf84 - Secure GPIO mask for port 1 pins."]
96    pub sec_gpio_mask1: SEC_GPIO_MASK1,
97    _reserved36: [u8; 0x34],
98    #[doc = "0xfbc - Security General Purpose register access control."]
99    pub sec_mask_lock: SEC_MASK_LOCK,
100    _reserved37: [u8; 0x10],
101    #[doc = "0xfd0 - master secure level register."]
102    pub master_sec_level: MASTER_SEC_LEVEL,
103    #[doc = "0xfd4 - master secure level anti-pole register."]
104    pub master_sec_anti_pol_reg: MASTER_SEC_ANTI_POL_REG,
105    _reserved39: [u8; 0x14],
106    #[doc = "0xfec - Miscalleneous control signals for in Cortex M33 (CPU0)"]
107    pub cpu0_lock_reg: CPU0_LOCK_REG,
108    _reserved40: [u8; 0x08],
109    #[doc = "0xff8 - secure control duplicate register."]
110    pub misc_ctrl_dp_reg: MISC_CTRL_DP_REG,
111    #[doc = "0xffc - secure control register."]
112    pub misc_ctrl_reg: MISC_CTRL_REG,
113}
114#[doc = "SEC_CTRL_FLASH_ROM_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_FLASH_ROM_SLAVE_RULE_SPEC>`"]
115pub type SEC_CTRL_FLASH_ROM_SLAVE_RULE =
116    crate::Reg<sec_ctrl_flash_rom_slave_rule::SEC_CTRL_FLASH_ROM_SLAVE_RULE_SPEC>;
117#[doc = "Security access rules for Flash and ROM slaves."]
118pub mod sec_ctrl_flash_rom_slave_rule;
119#[doc = "SEC_CTRL_FLASH_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_FLASH_MEM_RULE0_SPEC>`"]
120pub type SEC_CTRL_FLASH_MEM_RULE0 =
121    crate::Reg<sec_ctrl_flash_mem_rule0::SEC_CTRL_FLASH_MEM_RULE0_SPEC>;
122#[doc = "Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total."]
123pub mod sec_ctrl_flash_mem_rule0;
124#[doc = "SEC_CTRL_ROM_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE0_SPEC>`"]
125pub type SEC_CTRL_ROM_MEM_RULE0 = crate::Reg<sec_ctrl_rom_mem_rule0::SEC_CTRL_ROM_MEM_RULE0_SPEC>;
126#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
127pub mod sec_ctrl_rom_mem_rule0;
128#[doc = "SEC_CTRL_ROM_MEM_RULE1 (rw) register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE1_SPEC>`"]
129pub type SEC_CTRL_ROM_MEM_RULE1 = crate::Reg<sec_ctrl_rom_mem_rule1::SEC_CTRL_ROM_MEM_RULE1_SPEC>;
130#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
131pub mod sec_ctrl_rom_mem_rule1;
132#[doc = "SEC_CTRL_ROM_MEM_RULE2 (rw) register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE2_SPEC>`"]
133pub type SEC_CTRL_ROM_MEM_RULE2 = crate::Reg<sec_ctrl_rom_mem_rule2::SEC_CTRL_ROM_MEM_RULE2_SPEC>;
134#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
135pub mod sec_ctrl_rom_mem_rule2;
136#[doc = "SEC_CTRL_ROM_MEM_RULE3 (rw) register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE3_SPEC>`"]
137pub type SEC_CTRL_ROM_MEM_RULE3 = crate::Reg<sec_ctrl_rom_mem_rule3::SEC_CTRL_ROM_MEM_RULE3_SPEC>;
138#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
139pub mod sec_ctrl_rom_mem_rule3;
140#[doc = "SEC_CTRL_RAMX_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_RAMX_SLAVE_RULE_SPEC>`"]
141pub type SEC_CTRL_RAMX_SLAVE_RULE =
142    crate::Reg<sec_ctrl_ramx_slave_rule::SEC_CTRL_RAMX_SLAVE_RULE_SPEC>;
143#[doc = "Security access rules for RAMX slaves."]
144pub mod sec_ctrl_ramx_slave_rule;
145#[doc = "SEC_CTRL_RAMX_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_RAMX_MEM_RULE0_SPEC>`"]
146pub type SEC_CTRL_RAMX_MEM_RULE0 =
147    crate::Reg<sec_ctrl_ramx_mem_rule0::SEC_CTRL_RAMX_MEM_RULE0_SPEC>;
148#[doc = "Security access rules for RAMX slaves."]
149pub mod sec_ctrl_ramx_mem_rule0;
150#[doc = "SEC_CTRL_RAM0_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM0_SLAVE_RULE_SPEC>`"]
151pub type SEC_CTRL_RAM0_SLAVE_RULE =
152    crate::Reg<sec_ctrl_ram0_slave_rule::SEC_CTRL_RAM0_SLAVE_RULE_SPEC>;
153#[doc = "Security access rules for RAM0 slaves."]
154pub mod sec_ctrl_ram0_slave_rule;
155#[doc = "SEC_CTRL_RAM0_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM0_MEM_RULE0_SPEC>`"]
156pub type SEC_CTRL_RAM0_MEM_RULE0 =
157    crate::Reg<sec_ctrl_ram0_mem_rule0::SEC_CTRL_RAM0_MEM_RULE0_SPEC>;
158#[doc = "Security access rules for RAM0 slaves."]
159pub mod sec_ctrl_ram0_mem_rule0;
160#[doc = "SEC_CTRL_RAM1_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM1_SLAVE_RULE_SPEC>`"]
161pub type SEC_CTRL_RAM1_SLAVE_RULE =
162    crate::Reg<sec_ctrl_ram1_slave_rule::SEC_CTRL_RAM1_SLAVE_RULE_SPEC>;
163#[doc = "Security access rules for RAM1 slaves."]
164pub mod sec_ctrl_ram1_slave_rule;
165#[doc = "SEC_CTRL_RAM1_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM1_MEM_RULE0_SPEC>`"]
166pub type SEC_CTRL_RAM1_MEM_RULE0 =
167    crate::Reg<sec_ctrl_ram1_mem_rule0::SEC_CTRL_RAM1_MEM_RULE0_SPEC>;
168#[doc = "Security access rules for RAM1 slaves."]
169pub mod sec_ctrl_ram1_mem_rule0;
170#[doc = "SEC_CTRL_RAM2_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM2_SLAVE_RULE_SPEC>`"]
171pub type SEC_CTRL_RAM2_SLAVE_RULE =
172    crate::Reg<sec_ctrl_ram2_slave_rule::SEC_CTRL_RAM2_SLAVE_RULE_SPEC>;
173#[doc = "Security access rules for RAM2 slaves."]
174pub mod sec_ctrl_ram2_slave_rule;
175#[doc = "SEC_CTRL_RAM2_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM2_MEM_RULE0_SPEC>`"]
176pub type SEC_CTRL_RAM2_MEM_RULE0 =
177    crate::Reg<sec_ctrl_ram2_mem_rule0::SEC_CTRL_RAM2_MEM_RULE0_SPEC>;
178#[doc = "Security access rules for RAM2 slaves."]
179pub mod sec_ctrl_ram2_mem_rule0;
180#[doc = "SEC_CTRL_RAM3_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM3_SLAVE_RULE_SPEC>`"]
181pub type SEC_CTRL_RAM3_SLAVE_RULE =
182    crate::Reg<sec_ctrl_ram3_slave_rule::SEC_CTRL_RAM3_SLAVE_RULE_SPEC>;
183#[doc = "Security access rules for RAM3 slaves."]
184pub mod sec_ctrl_ram3_slave_rule;
185#[doc = "SEC_CTRL_RAM3_MEM_RULE0 (rw) register accessor: an alias for `Reg<SEC_CTRL_RAM3_MEM_RULE0_SPEC>`"]
186pub type SEC_CTRL_RAM3_MEM_RULE0 =
187    crate::Reg<sec_ctrl_ram3_mem_rule0::SEC_CTRL_RAM3_MEM_RULE0_SPEC>;
188#[doc = "Security access rules for RAM3."]
189pub mod sec_ctrl_ram3_mem_rule0;
190#[doc = "SEC_CTRL_APB_BRIDGE_SLAVE_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE_SLAVE_RULE_SPEC>`"]
191pub type SEC_CTRL_APB_BRIDGE_SLAVE_RULE =
192    crate::Reg<sec_ctrl_apb_bridge_slave_rule::SEC_CTRL_APB_BRIDGE_SLAVE_RULE_SPEC>;
193#[doc = "Security access rules for both APB Bridges slaves."]
194pub mod sec_ctrl_apb_bridge_slave_rule;
195#[doc = "SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SPEC>`"]
196pub type SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 =
197    crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl0::SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SPEC>;
198#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
199pub mod sec_ctrl_apb_bridge0_mem_ctrl0;
200#[doc = "SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_SPEC>`"]
201pub type SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 =
202    crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl1::SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_SPEC>;
203#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
204pub mod sec_ctrl_apb_bridge0_mem_ctrl1;
205#[doc = "SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_SPEC>`"]
206pub type SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 =
207    crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl2::SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_SPEC>;
208#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
209pub mod sec_ctrl_apb_bridge0_mem_ctrl2;
210#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPEC>`"]
211pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 =
212    crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl0::SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPEC>;
213#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
214pub mod sec_ctrl_apb_bridge1_mem_ctrl0;
215#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_SPEC>`"]
216pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 =
217    crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl1::SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_SPEC>;
218#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
219pub mod sec_ctrl_apb_bridge1_mem_ctrl1;
220#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_SPEC>`"]
221pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 =
222    crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl2::SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_SPEC>;
223#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
224pub mod sec_ctrl_apb_bridge1_mem_ctrl2;
225#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 (rw) register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_SPEC>`"]
226pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 =
227    crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl3::SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_SPEC>;
228#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
229pub mod sec_ctrl_apb_bridge1_mem_ctrl3;
230#[doc = "SEC_CTRL_AHB_PORT7_SLAVE0_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SPEC>`"]
231pub type SEC_CTRL_AHB_PORT7_SLAVE0_RULE =
232    crate::Reg<sec_ctrl_ahb_port7_slave0_rule::SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SPEC>;
233#[doc = "Security access rules for AHB peripherals."]
234pub mod sec_ctrl_ahb_port7_slave0_rule;
235#[doc = "SEC_CTRL_AHB_PORT7_SLAVE1_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT7_SLAVE1_RULE_SPEC>`"]
236pub type SEC_CTRL_AHB_PORT7_SLAVE1_RULE =
237    crate::Reg<sec_ctrl_ahb_port7_slave1_rule::SEC_CTRL_AHB_PORT7_SLAVE1_RULE_SPEC>;
238#[doc = "Security access rules for AHB peripherals."]
239pub mod sec_ctrl_ahb_port7_slave1_rule;
240#[doc = "SEC_CTRL_AHB_PORT8_SLAVE0_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SPEC>`"]
241pub type SEC_CTRL_AHB_PORT8_SLAVE0_RULE =
242    crate::Reg<sec_ctrl_ahb_port8_slave0_rule::SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SPEC>;
243#[doc = "Security access rules for AHB peripherals."]
244pub mod sec_ctrl_ahb_port8_slave0_rule;
245#[doc = "SEC_CTRL_AHB_PORT8_SLAVE1_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>`"]
246pub type SEC_CTRL_AHB_PORT8_SLAVE1_RULE =
247    crate::Reg<sec_ctrl_ahb_port8_slave1_rule::SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>;
248#[doc = "Security access rules for AHB peripherals."]
249pub mod sec_ctrl_ahb_port8_slave1_rule;
250#[doc = "SEC_CTRL_AHB_PORT9_SLAVE0_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT9_SLAVE0_RULE_SPEC>`"]
251pub type SEC_CTRL_AHB_PORT9_SLAVE0_RULE =
252    crate::Reg<sec_ctrl_ahb_port9_slave0_rule::SEC_CTRL_AHB_PORT9_SLAVE0_RULE_SPEC>;
253#[doc = "Security access rules for AHB peripherals."]
254pub mod sec_ctrl_ahb_port9_slave0_rule;
255#[doc = "SEC_CTRL_AHB_PORT9_SLAVE1_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SPEC>`"]
256pub type SEC_CTRL_AHB_PORT9_SLAVE1_RULE =
257    crate::Reg<sec_ctrl_ahb_port9_slave1_rule::SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SPEC>;
258#[doc = "Security access rules for AHB peripherals."]
259pub mod sec_ctrl_ahb_port9_slave1_rule;
260#[doc = "SEC_CTRL_AHB_SEC_CTRL_MEM_RULE (rw) register accessor: an alias for `Reg<SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_SPEC>`"]
261pub type SEC_CTRL_AHB_SEC_CTRL_MEM_RULE =
262    crate::Reg<sec_ctrl_ahb_sec_ctrl_mem_rule::SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_SPEC>;
263#[doc = "Security access rules for AHB_SEC_CTRL_AHB."]
264pub mod sec_ctrl_ahb_sec_ctrl_mem_rule;
265#[doc = "sec_vio_addr (r) register accessor: an alias for `Reg<SEC_VIO_ADDR_SPEC>`"]
266pub type SEC_VIO_ADDR = crate::Reg<sec_vio_addr::SEC_VIO_ADDR_SPEC>;
267#[doc = "most recent security violation address for AHB layer n."]
268pub mod sec_vio_addr;
269#[doc = "sec_vio_misc_info (r) register accessor: an alias for `Reg<SEC_VIO_MISC_INFO_SPEC>`"]
270pub type SEC_VIO_MISC_INFO = crate::Reg<sec_vio_misc_info::SEC_VIO_MISC_INFO_SPEC>;
271#[doc = "most recent security violation miscellaneous information for AHB layer n."]
272pub mod sec_vio_misc_info;
273#[doc = "SEC_VIO_INFO_VALID (rw) register accessor: an alias for `Reg<SEC_VIO_INFO_VALID_SPEC>`"]
274pub type SEC_VIO_INFO_VALID = crate::Reg<sec_vio_info_valid::SEC_VIO_INFO_VALID_SPEC>;
275#[doc = "security violation address/information registers valid flags."]
276pub mod sec_vio_info_valid;
277#[doc = "SEC_GPIO_MASK0 (rw) register accessor: an alias for `Reg<SEC_GPIO_MASK0_SPEC>`"]
278pub type SEC_GPIO_MASK0 = crate::Reg<sec_gpio_mask0::SEC_GPIO_MASK0_SPEC>;
279#[doc = "Secure GPIO mask for port 0 pins."]
280pub mod sec_gpio_mask0;
281#[doc = "SEC_GPIO_MASK1 (rw) register accessor: an alias for `Reg<SEC_GPIO_MASK1_SPEC>`"]
282pub type SEC_GPIO_MASK1 = crate::Reg<sec_gpio_mask1::SEC_GPIO_MASK1_SPEC>;
283#[doc = "Secure GPIO mask for port 1 pins."]
284pub mod sec_gpio_mask1;
285#[doc = "SEC_MASK_LOCK (rw) register accessor: an alias for `Reg<SEC_MASK_LOCK_SPEC>`"]
286pub type SEC_MASK_LOCK = crate::Reg<sec_mask_lock::SEC_MASK_LOCK_SPEC>;
287#[doc = "Security General Purpose register access control."]
288pub mod sec_mask_lock;
289#[doc = "MASTER_SEC_LEVEL (rw) register accessor: an alias for `Reg<MASTER_SEC_LEVEL_SPEC>`"]
290pub type MASTER_SEC_LEVEL = crate::Reg<master_sec_level::MASTER_SEC_LEVEL_SPEC>;
291#[doc = "master secure level register."]
292pub mod master_sec_level;
293#[doc = "MASTER_SEC_ANTI_POL_REG (rw) register accessor: an alias for `Reg<MASTER_SEC_ANTI_POL_REG_SPEC>`"]
294pub type MASTER_SEC_ANTI_POL_REG =
295    crate::Reg<master_sec_anti_pol_reg::MASTER_SEC_ANTI_POL_REG_SPEC>;
296#[doc = "master secure level anti-pole register."]
297pub mod master_sec_anti_pol_reg;
298#[doc = "CPU0_LOCK_REG (rw) register accessor: an alias for `Reg<CPU0_LOCK_REG_SPEC>`"]
299pub type CPU0_LOCK_REG = crate::Reg<cpu0_lock_reg::CPU0_LOCK_REG_SPEC>;
300#[doc = "Miscalleneous control signals for in Cortex M33 (CPU0)"]
301pub mod cpu0_lock_reg;
302#[doc = "MISC_CTRL_DP_REG (rw) register accessor: an alias for `Reg<MISC_CTRL_DP_REG_SPEC>`"]
303pub type MISC_CTRL_DP_REG = crate::Reg<misc_ctrl_dp_reg::MISC_CTRL_DP_REG_SPEC>;
304#[doc = "secure control duplicate register."]
305pub mod misc_ctrl_dp_reg;
306#[doc = "MISC_CTRL_REG (rw) register accessor: an alias for `Reg<MISC_CTRL_REG_SPEC>`"]
307pub type MISC_CTRL_REG = crate::Reg<misc_ctrl_reg::MISC_CTRL_REG_SPEC>;
308#[doc = "secure control register."]
309pub mod misc_ctrl_reg;
lpc550x/ahb_secure_ctrl.rs

lpc550x/
ahb_secure_ctrl.rs
