lpc550x/syscon/
ctimerclksel3.rs1#[doc = "Register `CTIMERCLKSEL3` reader"]
2pub struct R(crate::R<CTIMERCLKSEL3_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTIMERCLKSEL3_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTIMERCLKSEL3_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTIMERCLKSEL3_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTIMERCLKSEL3` writer"]
17pub struct W(crate::W<CTIMERCLKSEL3_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTIMERCLKSEL3_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTIMERCLKSEL3_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTIMERCLKSEL3_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SEL` reader - CTimer 3 clock source select."]
38pub type SEL_R = crate::FieldReader<u8, SEL_A>;
39#[doc = "CTimer 3 clock source select.\n\nValue on reset: 7"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SEL_A {
43 #[doc = "0: Main clock."]
44 MAIN_CLK = 0,
45 #[doc = "1: PLL0 clock."]
46 PLL0 = 1,
47 #[doc = "3: FRO 96 MHz clock."]
48 FRO_96MHZ = 3,
49 #[doc = "4: FRO 1MHz clock."]
50 FRO_1MHZ = 4,
51 #[doc = "5: MCLK clock."]
52 MCLK = 5,
53 #[doc = "6: Oscillator 32kHz clock."]
54 OSC_32KHZ = 6,
55 #[doc = "7: No clock."]
56 NONE = 7,
57}
58impl From<SEL_A> for u8 {
59 #[inline(always)]
60 fn from(variant: SEL_A) -> Self {
61 variant as _
62 }
63}
64impl SEL_R {
65 #[doc = "Get enumerated values variant"]
66 #[inline(always)]
67 pub fn variant(&self) -> Option<SEL_A> {
68 match self.bits {
69 0 => Some(SEL_A::MAIN_CLK),
70 1 => Some(SEL_A::PLL0),
71 3 => Some(SEL_A::FRO_96MHZ),
72 4 => Some(SEL_A::FRO_1MHZ),
73 5 => Some(SEL_A::MCLK),
74 6 => Some(SEL_A::OSC_32KHZ),
75 7 => Some(SEL_A::NONE),
76 _ => None,
77 }
78 }
79 #[doc = "Checks if the value of the field is `MAIN_CLK`"]
80 #[inline(always)]
81 pub fn is_main_clk(&self) -> bool {
82 *self == SEL_A::MAIN_CLK
83 }
84 #[doc = "Checks if the value of the field is `PLL0`"]
85 #[inline(always)]
86 pub fn is_pll0(&self) -> bool {
87 *self == SEL_A::PLL0
88 }
89 #[doc = "Checks if the value of the field is `FRO_96MHZ`"]
90 #[inline(always)]
91 pub fn is_fro_96mhz(&self) -> bool {
92 *self == SEL_A::FRO_96MHZ
93 }
94 #[doc = "Checks if the value of the field is `FRO_1MHZ`"]
95 #[inline(always)]
96 pub fn is_fro_1mhz(&self) -> bool {
97 *self == SEL_A::FRO_1MHZ
98 }
99 #[doc = "Checks if the value of the field is `MCLK`"]
100 #[inline(always)]
101 pub fn is_mclk(&self) -> bool {
102 *self == SEL_A::MCLK
103 }
104 #[doc = "Checks if the value of the field is `OSC_32KHZ`"]
105 #[inline(always)]
106 pub fn is_osc_32khz(&self) -> bool {
107 *self == SEL_A::OSC_32KHZ
108 }
109 #[doc = "Checks if the value of the field is `NONE`"]
110 #[inline(always)]
111 pub fn is_none(&self) -> bool {
112 *self == SEL_A::NONE
113 }
114}
115#[doc = "Field `SEL` writer - CTimer 3 clock source select."]
116pub type SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTIMERCLKSEL3_SPEC, u8, SEL_A, 3, O>;
117impl<'a, const O: u8> SEL_W<'a, O> {
118 #[doc = "Main clock."]
119 #[inline(always)]
120 pub fn main_clk(self) -> &'a mut W {
121 self.variant(SEL_A::MAIN_CLK)
122 }
123 #[doc = "PLL0 clock."]
124 #[inline(always)]
125 pub fn pll0(self) -> &'a mut W {
126 self.variant(SEL_A::PLL0)
127 }
128 #[doc = "FRO 96 MHz clock."]
129 #[inline(always)]
130 pub fn fro_96mhz(self) -> &'a mut W {
131 self.variant(SEL_A::FRO_96MHZ)
132 }
133 #[doc = "FRO 1MHz clock."]
134 #[inline(always)]
135 pub fn fro_1mhz(self) -> &'a mut W {
136 self.variant(SEL_A::FRO_1MHZ)
137 }
138 #[doc = "MCLK clock."]
139 #[inline(always)]
140 pub fn mclk(self) -> &'a mut W {
141 self.variant(SEL_A::MCLK)
142 }
143 #[doc = "Oscillator 32kHz clock."]
144 #[inline(always)]
145 pub fn osc_32khz(self) -> &'a mut W {
146 self.variant(SEL_A::OSC_32KHZ)
147 }
148 #[doc = "No clock."]
149 #[inline(always)]
150 pub fn none(self) -> &'a mut W {
151 self.variant(SEL_A::NONE)
152 }
153}
154impl R {
155 #[doc = "Bits 0:2 - CTimer 3 clock source select."]
156 #[inline(always)]
157 pub fn sel(&self) -> SEL_R {
158 SEL_R::new((self.bits & 7) as u8)
159 }
160}
161impl W {
162 #[doc = "Bits 0:2 - CTimer 3 clock source select."]
163 #[inline(always)]
164 pub fn sel(&mut self) -> SEL_W<0> {
165 SEL_W::new(self)
166 }
167 #[doc = "Writes raw bits to the register."]
168 #[inline(always)]
169 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
170 self.0.bits(bits);
171 self
172 }
173}
174#[doc = "CTimer 3 clock source select.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclksel3](index.html) module"]
175pub struct CTIMERCLKSEL3_SPEC;
176impl crate::RegisterSpec for CTIMERCLKSEL3_SPEC {
177 type Ux = u32;
178}
179#[doc = "`read()` method returns [ctimerclksel3::R](R) reader structure"]
180impl crate::Readable for CTIMERCLKSEL3_SPEC {
181 type Reader = R;
182}
183#[doc = "`write(|w| ..)` method takes [ctimerclksel3::W](W) writer structure"]
184impl crate::Writable for CTIMERCLKSEL3_SPEC {
185 type Writer = W;
186}
187#[doc = "`reset()` method sets CTIMERCLKSEL3 to value 0x07"]
188impl crate::Resettable for CTIMERCLKSEL3_SPEC {
189 #[inline(always)]
190 fn reset_value() -> Self::Ux {
191 0x07
192 }
193}