lpc550x/syscon/
fcclksel1.rs

1#[doc = "Register `FCCLKSEL1` reader"]
2pub struct R(crate::R<FCCLKSEL1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FCCLKSEL1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FCCLKSEL1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FCCLKSEL1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FCCLKSEL1` writer"]
17pub struct W(crate::W<FCCLKSEL1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FCCLKSEL1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FCCLKSEL1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FCCLKSEL1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SEL` reader - Flexcomm Interface 1 clock source select for Fractional Rate Divider."]
38pub type SEL_R = crate::FieldReader<u8, SEL_A>;
39#[doc = "Flexcomm Interface 1 clock source select for Fractional Rate Divider.\n\nValue on reset: 7"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SEL_A {
43    #[doc = "0: Main clock."]
44    MAIN_CLK = 0,
45    #[doc = "1: PLL0 divided clock."]
46    PLL0_DIV = 1,
47    #[doc = "2: FRO 12 MHz clock."]
48    FRO_12MHZ = 2,
49    #[doc = "3: FRO HF divided clock."]
50    FRO_HF_DIV = 3,
51    #[doc = "4: FRO 1MHz clock."]
52    FRO_1MHZ = 4,
53    #[doc = "5: MCLK clock."]
54    MCLK = 5,
55    #[doc = "6: Oscillator 32 kHz clock."]
56    OSC_32KHZ = 6,
57    #[doc = "7: No clock."]
58    NONE = 7,
59}
60impl From<SEL_A> for u8 {
61    #[inline(always)]
62    fn from(variant: SEL_A) -> Self {
63        variant as _
64    }
65}
66impl SEL_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> SEL_A {
70        match self.bits {
71            0 => SEL_A::MAIN_CLK,
72            1 => SEL_A::PLL0_DIV,
73            2 => SEL_A::FRO_12MHZ,
74            3 => SEL_A::FRO_HF_DIV,
75            4 => SEL_A::FRO_1MHZ,
76            5 => SEL_A::MCLK,
77            6 => SEL_A::OSC_32KHZ,
78            7 => SEL_A::NONE,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `MAIN_CLK`"]
83    #[inline(always)]
84    pub fn is_main_clk(&self) -> bool {
85        *self == SEL_A::MAIN_CLK
86    }
87    #[doc = "Checks if the value of the field is `PLL0_DIV`"]
88    #[inline(always)]
89    pub fn is_pll0_div(&self) -> bool {
90        *self == SEL_A::PLL0_DIV
91    }
92    #[doc = "Checks if the value of the field is `FRO_12MHZ`"]
93    #[inline(always)]
94    pub fn is_fro_12mhz(&self) -> bool {
95        *self == SEL_A::FRO_12MHZ
96    }
97    #[doc = "Checks if the value of the field is `FRO_HF_DIV`"]
98    #[inline(always)]
99    pub fn is_fro_hf_div(&self) -> bool {
100        *self == SEL_A::FRO_HF_DIV
101    }
102    #[doc = "Checks if the value of the field is `FRO_1MHZ`"]
103    #[inline(always)]
104    pub fn is_fro_1mhz(&self) -> bool {
105        *self == SEL_A::FRO_1MHZ
106    }
107    #[doc = "Checks if the value of the field is `MCLK`"]
108    #[inline(always)]
109    pub fn is_mclk(&self) -> bool {
110        *self == SEL_A::MCLK
111    }
112    #[doc = "Checks if the value of the field is `OSC_32KHZ`"]
113    #[inline(always)]
114    pub fn is_osc_32khz(&self) -> bool {
115        *self == SEL_A::OSC_32KHZ
116    }
117    #[doc = "Checks if the value of the field is `NONE`"]
118    #[inline(always)]
119    pub fn is_none(&self) -> bool {
120        *self == SEL_A::NONE
121    }
122}
123#[doc = "Field `SEL` writer - Flexcomm Interface 1 clock source select for Fractional Rate Divider."]
124pub type SEL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, FCCLKSEL1_SPEC, u8, SEL_A, 3, O>;
125impl<'a, const O: u8> SEL_W<'a, O> {
126    #[doc = "Main clock."]
127    #[inline(always)]
128    pub fn main_clk(self) -> &'a mut W {
129        self.variant(SEL_A::MAIN_CLK)
130    }
131    #[doc = "PLL0 divided clock."]
132    #[inline(always)]
133    pub fn pll0_div(self) -> &'a mut W {
134        self.variant(SEL_A::PLL0_DIV)
135    }
136    #[doc = "FRO 12 MHz clock."]
137    #[inline(always)]
138    pub fn fro_12mhz(self) -> &'a mut W {
139        self.variant(SEL_A::FRO_12MHZ)
140    }
141    #[doc = "FRO HF divided clock."]
142    #[inline(always)]
143    pub fn fro_hf_div(self) -> &'a mut W {
144        self.variant(SEL_A::FRO_HF_DIV)
145    }
146    #[doc = "FRO 1MHz clock."]
147    #[inline(always)]
148    pub fn fro_1mhz(self) -> &'a mut W {
149        self.variant(SEL_A::FRO_1MHZ)
150    }
151    #[doc = "MCLK clock."]
152    #[inline(always)]
153    pub fn mclk(self) -> &'a mut W {
154        self.variant(SEL_A::MCLK)
155    }
156    #[doc = "Oscillator 32 kHz clock."]
157    #[inline(always)]
158    pub fn osc_32khz(self) -> &'a mut W {
159        self.variant(SEL_A::OSC_32KHZ)
160    }
161    #[doc = "No clock."]
162    #[inline(always)]
163    pub fn none(self) -> &'a mut W {
164        self.variant(SEL_A::NONE)
165    }
166}
167impl R {
168    #[doc = "Bits 0:2 - Flexcomm Interface 1 clock source select for Fractional Rate Divider."]
169    #[inline(always)]
170    pub fn sel(&self) -> SEL_R {
171        SEL_R::new((self.bits & 7) as u8)
172    }
173}
174impl W {
175    #[doc = "Bits 0:2 - Flexcomm Interface 1 clock source select for Fractional Rate Divider."]
176    #[inline(always)]
177    pub fn sel(&mut self) -> SEL_W<0> {
178        SEL_W::new(self)
179    }
180    #[doc = "Writes raw bits to the register."]
181    #[inline(always)]
182    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183        self.0.bits(bits);
184        self
185    }
186}
187#[doc = "Flexcomm Interface 1 clock source select for Fractional Rate Divider.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel1](index.html) module"]
188pub struct FCCLKSEL1_SPEC;
189impl crate::RegisterSpec for FCCLKSEL1_SPEC {
190    type Ux = u32;
191}
192#[doc = "`read()` method returns [fcclksel1::R](R) reader structure"]
193impl crate::Readable for FCCLKSEL1_SPEC {
194    type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [fcclksel1::W](W) writer structure"]
197impl crate::Writable for FCCLKSEL1_SPEC {
198    type Writer = W;
199}
200#[doc = "`reset()` method sets FCCLKSEL1 to value 0x07"]
201impl crate::Resettable for FCCLKSEL1_SPEC {
202    #[inline(always)]
203    fn reset_value() -> Self::Ux {
204        0x07
205    }
206}
lpc550x/syscon/fcclksel1.rs

lpc550x/syscon/
fcclksel1.rs
