lpc550x/sysctl/
fcctrlsel.rs

1#[doc = "Register `FCCTRLSEL%s` reader"]
2pub struct R(crate::R<FCCTRLSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FCCTRLSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FCCTRLSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FCCTRLSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FCCTRLSEL%s` writer"]
17pub struct W(crate::W<FCCTRLSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FCCTRLSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FCCTRLSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FCCTRLSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SCKINSEL` reader - Selects the source for SCK going into this Flexcomm."]
38pub type SCKINSEL_R = crate::FieldReader<u8, SCKINSEL_A>;
39#[doc = "Selects the source for SCK going into this Flexcomm.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SCKINSEL_A {
43    #[doc = "0: Selects the dedicated FCn_SCK function for this Flexcomm."]
44    ORIG_FLEX_I2S_SIGNALS = 0,
45    #[doc = "1: SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
46    SHARED_SET0_I2S_SIGNALS = 1,
47    #[doc = "2: SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
48    SHARED_SET1_I2S_SIGNALS = 2,
49}
50impl From<SCKINSEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: SCKINSEL_A) -> Self {
53        variant as _
54    }
55}
56impl SCKINSEL_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<SCKINSEL_A> {
60        match self.bits {
61            0 => Some(SCKINSEL_A::ORIG_FLEX_I2S_SIGNALS),
62            1 => Some(SCKINSEL_A::SHARED_SET0_I2S_SIGNALS),
63            2 => Some(SCKINSEL_A::SHARED_SET1_I2S_SIGNALS),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
68    #[inline(always)]
69    pub fn is_orig_flex_i2s_signals(&self) -> bool {
70        *self == SCKINSEL_A::ORIG_FLEX_I2S_SIGNALS
71    }
72    #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
73    #[inline(always)]
74    pub fn is_shared_set0_i2s_signals(&self) -> bool {
75        *self == SCKINSEL_A::SHARED_SET0_I2S_SIGNALS
76    }
77    #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
78    #[inline(always)]
79    pub fn is_shared_set1_i2s_signals(&self) -> bool {
80        *self == SCKINSEL_A::SHARED_SET1_I2S_SIGNALS
81    }
82}
83#[doc = "Field `SCKINSEL` writer - Selects the source for SCK going into this Flexcomm."]
84pub type SCKINSEL_W<'a, const O: u8> =
85    crate::FieldWriter<'a, u32, FCCTRLSEL_SPEC, u8, SCKINSEL_A, 2, O>;
86impl<'a, const O: u8> SCKINSEL_W<'a, O> {
87    #[doc = "Selects the dedicated FCn_SCK function for this Flexcomm."]
88    #[inline(always)]
89    pub fn orig_flex_i2s_signals(self) -> &'a mut W {
90        self.variant(SCKINSEL_A::ORIG_FLEX_I2S_SIGNALS)
91    }
92    #[doc = "SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
93    #[inline(always)]
94    pub fn shared_set0_i2s_signals(self) -> &'a mut W {
95        self.variant(SCKINSEL_A::SHARED_SET0_I2S_SIGNALS)
96    }
97    #[doc = "SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
98    #[inline(always)]
99    pub fn shared_set1_i2s_signals(self) -> &'a mut W {
100        self.variant(SCKINSEL_A::SHARED_SET1_I2S_SIGNALS)
101    }
102}
103#[doc = "Field `WSINSEL` reader - Selects the source for WS going into this Flexcomm."]
104pub type WSINSEL_R = crate::FieldReader<u8, WSINSEL_A>;
105#[doc = "Selects the source for WS going into this Flexcomm.\n\nValue on reset: 0"]
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107#[repr(u8)]
108pub enum WSINSEL_A {
109    #[doc = "0: Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm."]
110    ORIG_FLEX_I2S_SIGNALS = 0,
111    #[doc = "1: WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
112    SHARED_SET0_I2S_SIGNALS = 1,
113    #[doc = "2: WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
114    SHARED_SET1_I2S_SIGNALS = 2,
115}
116impl From<WSINSEL_A> for u8 {
117    #[inline(always)]
118    fn from(variant: WSINSEL_A) -> Self {
119        variant as _
120    }
121}
122impl WSINSEL_R {
123    #[doc = "Get enumerated values variant"]
124    #[inline(always)]
125    pub fn variant(&self) -> Option<WSINSEL_A> {
126        match self.bits {
127            0 => Some(WSINSEL_A::ORIG_FLEX_I2S_SIGNALS),
128            1 => Some(WSINSEL_A::SHARED_SET0_I2S_SIGNALS),
129            2 => Some(WSINSEL_A::SHARED_SET1_I2S_SIGNALS),
130            _ => None,
131        }
132    }
133    #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
134    #[inline(always)]
135    pub fn is_orig_flex_i2s_signals(&self) -> bool {
136        *self == WSINSEL_A::ORIG_FLEX_I2S_SIGNALS
137    }
138    #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
139    #[inline(always)]
140    pub fn is_shared_set0_i2s_signals(&self) -> bool {
141        *self == WSINSEL_A::SHARED_SET0_I2S_SIGNALS
142    }
143    #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
144    #[inline(always)]
145    pub fn is_shared_set1_i2s_signals(&self) -> bool {
146        *self == WSINSEL_A::SHARED_SET1_I2S_SIGNALS
147    }
148}
149#[doc = "Field `WSINSEL` writer - Selects the source for WS going into this Flexcomm."]
150pub type WSINSEL_W<'a, const O: u8> =
151    crate::FieldWriter<'a, u32, FCCTRLSEL_SPEC, u8, WSINSEL_A, 2, O>;
152impl<'a, const O: u8> WSINSEL_W<'a, O> {
153    #[doc = "Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm."]
154    #[inline(always)]
155    pub fn orig_flex_i2s_signals(self) -> &'a mut W {
156        self.variant(WSINSEL_A::ORIG_FLEX_I2S_SIGNALS)
157    }
158    #[doc = "WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
159    #[inline(always)]
160    pub fn shared_set0_i2s_signals(self) -> &'a mut W {
161        self.variant(WSINSEL_A::SHARED_SET0_I2S_SIGNALS)
162    }
163    #[doc = "WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
164    #[inline(always)]
165    pub fn shared_set1_i2s_signals(self) -> &'a mut W {
166        self.variant(WSINSEL_A::SHARED_SET1_I2S_SIGNALS)
167    }
168}
169#[doc = "Field `DATAINSEL` reader - Selects the source for DATA input to this Flexcomm."]
170pub type DATAINSEL_R = crate::FieldReader<u8, DATAINSEL_A>;
171#[doc = "Selects the source for DATA input to this Flexcomm.\n\nValue on reset: 0"]
172#[derive(Clone, Copy, Debug, PartialEq, Eq)]
173#[repr(u8)]
174pub enum DATAINSEL_A {
175    #[doc = "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm."]
176    ORIG_FLEX_I2S_SIGNALS = 0,
177    #[doc = "1: Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
178    SHARED_SET0_I2S_SIGNALS = 1,
179    #[doc = "2: Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
180    SHARED_SET1_I2S_SIGNALS = 2,
181}
182impl From<DATAINSEL_A> for u8 {
183    #[inline(always)]
184    fn from(variant: DATAINSEL_A) -> Self {
185        variant as _
186    }
187}
188impl DATAINSEL_R {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub fn variant(&self) -> Option<DATAINSEL_A> {
192        match self.bits {
193            0 => Some(DATAINSEL_A::ORIG_FLEX_I2S_SIGNALS),
194            1 => Some(DATAINSEL_A::SHARED_SET0_I2S_SIGNALS),
195            2 => Some(DATAINSEL_A::SHARED_SET1_I2S_SIGNALS),
196            _ => None,
197        }
198    }
199    #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
200    #[inline(always)]
201    pub fn is_orig_flex_i2s_signals(&self) -> bool {
202        *self == DATAINSEL_A::ORIG_FLEX_I2S_SIGNALS
203    }
204    #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
205    #[inline(always)]
206    pub fn is_shared_set0_i2s_signals(&self) -> bool {
207        *self == DATAINSEL_A::SHARED_SET0_I2S_SIGNALS
208    }
209    #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
210    #[inline(always)]
211    pub fn is_shared_set1_i2s_signals(&self) -> bool {
212        *self == DATAINSEL_A::SHARED_SET1_I2S_SIGNALS
213    }
214}
215#[doc = "Field `DATAINSEL` writer - Selects the source for DATA input to this Flexcomm."]
216pub type DATAINSEL_W<'a, const O: u8> =
217    crate::FieldWriter<'a, u32, FCCTRLSEL_SPEC, u8, DATAINSEL_A, 2, O>;
218impl<'a, const O: u8> DATAINSEL_W<'a, O> {
219    #[doc = "Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm."]
220    #[inline(always)]
221    pub fn orig_flex_i2s_signals(self) -> &'a mut W {
222        self.variant(DATAINSEL_A::ORIG_FLEX_I2S_SIGNALS)
223    }
224    #[doc = "Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
225    #[inline(always)]
226    pub fn shared_set0_i2s_signals(self) -> &'a mut W {
227        self.variant(DATAINSEL_A::SHARED_SET0_I2S_SIGNALS)
228    }
229    #[doc = "Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
230    #[inline(always)]
231    pub fn shared_set1_i2s_signals(self) -> &'a mut W {
232        self.variant(DATAINSEL_A::SHARED_SET1_I2S_SIGNALS)
233    }
234}
235#[doc = "Field `DATAOUTSEL` reader - Selects the source for DATA output from this Flexcomm."]
236pub type DATAOUTSEL_R = crate::FieldReader<u8, DATAOUTSEL_A>;
237#[doc = "Selects the source for DATA output from this Flexcomm.\n\nValue on reset: 0"]
238#[derive(Clone, Copy, Debug, PartialEq, Eq)]
239#[repr(u8)]
240pub enum DATAOUTSEL_A {
241    #[doc = "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm."]
242    ORIG_FLEX_I2S_SIGNALS = 0,
243    #[doc = "1: Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
244    SHARED_SET0_I2S_SIGNALS = 1,
245    #[doc = "2: Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
246    SHARED_SET1_I2S_SIGNALS = 2,
247}
248impl From<DATAOUTSEL_A> for u8 {
249    #[inline(always)]
250    fn from(variant: DATAOUTSEL_A) -> Self {
251        variant as _
252    }
253}
254impl DATAOUTSEL_R {
255    #[doc = "Get enumerated values variant"]
256    #[inline(always)]
257    pub fn variant(&self) -> Option<DATAOUTSEL_A> {
258        match self.bits {
259            0 => Some(DATAOUTSEL_A::ORIG_FLEX_I2S_SIGNALS),
260            1 => Some(DATAOUTSEL_A::SHARED_SET0_I2S_SIGNALS),
261            2 => Some(DATAOUTSEL_A::SHARED_SET1_I2S_SIGNALS),
262            _ => None,
263        }
264    }
265    #[doc = "Checks if the value of the field is `ORIG_FLEX_I2S_SIGNALS`"]
266    #[inline(always)]
267    pub fn is_orig_flex_i2s_signals(&self) -> bool {
268        *self == DATAOUTSEL_A::ORIG_FLEX_I2S_SIGNALS
269    }
270    #[doc = "Checks if the value of the field is `SHARED_SET0_I2S_SIGNALS`"]
271    #[inline(always)]
272    pub fn is_shared_set0_i2s_signals(&self) -> bool {
273        *self == DATAOUTSEL_A::SHARED_SET0_I2S_SIGNALS
274    }
275    #[doc = "Checks if the value of the field is `SHARED_SET1_I2S_SIGNALS`"]
276    #[inline(always)]
277    pub fn is_shared_set1_i2s_signals(&self) -> bool {
278        *self == DATAOUTSEL_A::SHARED_SET1_I2S_SIGNALS
279    }
280}
281#[doc = "Field `DATAOUTSEL` writer - Selects the source for DATA output from this Flexcomm."]
282pub type DATAOUTSEL_W<'a, const O: u8> =
283    crate::FieldWriter<'a, u32, FCCTRLSEL_SPEC, u8, DATAOUTSEL_A, 2, O>;
284impl<'a, const O: u8> DATAOUTSEL_W<'a, O> {
285    #[doc = "Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm."]
286    #[inline(always)]
287    pub fn orig_flex_i2s_signals(self) -> &'a mut W {
288        self.variant(DATAOUTSEL_A::ORIG_FLEX_I2S_SIGNALS)
289    }
290    #[doc = "Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0)."]
291    #[inline(always)]
292    pub fn shared_set0_i2s_signals(self) -> &'a mut W {
293        self.variant(DATAOUTSEL_A::SHARED_SET0_I2S_SIGNALS)
294    }
295    #[doc = "Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1)."]
296    #[inline(always)]
297    pub fn shared_set1_i2s_signals(self) -> &'a mut W {
298        self.variant(DATAOUTSEL_A::SHARED_SET1_I2S_SIGNALS)
299    }
300}
301impl R {
302    #[doc = "Bits 0:1 - Selects the source for SCK going into this Flexcomm."]
303    #[inline(always)]
304    pub fn sckinsel(&self) -> SCKINSEL_R {
305        SCKINSEL_R::new((self.bits & 3) as u8)
306    }
307    #[doc = "Bits 8:9 - Selects the source for WS going into this Flexcomm."]
308    #[inline(always)]
309    pub fn wsinsel(&self) -> WSINSEL_R {
310        WSINSEL_R::new(((self.bits >> 8) & 3) as u8)
311    }
312    #[doc = "Bits 16:17 - Selects the source for DATA input to this Flexcomm."]
313    #[inline(always)]
314    pub fn datainsel(&self) -> DATAINSEL_R {
315        DATAINSEL_R::new(((self.bits >> 16) & 3) as u8)
316    }
317    #[doc = "Bits 24:25 - Selects the source for DATA output from this Flexcomm."]
318    #[inline(always)]
319    pub fn dataoutsel(&self) -> DATAOUTSEL_R {
320        DATAOUTSEL_R::new(((self.bits >> 24) & 3) as u8)
321    }
322}
323impl W {
324    #[doc = "Bits 0:1 - Selects the source for SCK going into this Flexcomm."]
325    #[inline(always)]
326    pub fn sckinsel(&mut self) -> SCKINSEL_W<0> {
327        SCKINSEL_W::new(self)
328    }
329    #[doc = "Bits 8:9 - Selects the source for WS going into this Flexcomm."]
330    #[inline(always)]
331    pub fn wsinsel(&mut self) -> WSINSEL_W<8> {
332        WSINSEL_W::new(self)
333    }
334    #[doc = "Bits 16:17 - Selects the source for DATA input to this Flexcomm."]
335    #[inline(always)]
336    pub fn datainsel(&mut self) -> DATAINSEL_W<16> {
337        DATAINSEL_W::new(self)
338    }
339    #[doc = "Bits 24:25 - Selects the source for DATA output from this Flexcomm."]
340    #[inline(always)]
341    pub fn dataoutsel(&mut self) -> DATAOUTSEL_W<24> {
342        DATAOUTSEL_W::new(self)
343    }
344    #[doc = "Writes raw bits to the register."]
345    #[inline(always)]
346    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
347        self.0.bits(bits);
348        self
349    }
350}
351#[doc = "Selects the source for SCK going into Flexcomm index.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcctrlsel](index.html) module"]
352pub struct FCCTRLSEL_SPEC;
353impl crate::RegisterSpec for FCCTRLSEL_SPEC {
354    type Ux = u32;
355}
356#[doc = "`read()` method returns [fcctrlsel::R](R) reader structure"]
357impl crate::Readable for FCCTRLSEL_SPEC {
358    type Reader = R;
359}
360#[doc = "`write(|w| ..)` method takes [fcctrlsel::W](W) writer structure"]
361impl crate::Writable for FCCTRLSEL_SPEC {
362    type Writer = W;
363}
364#[doc = "`reset()` method sets FCCTRLSEL%s to value 0"]
365impl crate::Resettable for FCCTRLSEL_SPEC {
366    #[inline(always)]
367    fn reset_value() -> Self::Ux {
368        0
369    }
370}
lpc550x/sysctl/fcctrlsel.rs

lpc550x/sysctl/
fcctrlsel.rs
