1#[doc = "Register `OSTIMER` reader"]
2pub struct R(crate::R<OSTIMER_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<OSTIMER_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<OSTIMER_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<OSTIMER_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `OSTIMER` writer"]
17pub struct W(crate::W<OSTIMER_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<OSTIMER_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<OSTIMER_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<OSTIMER_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SOFTRESET` reader - Active high reset."]
38pub type SOFTRESET_R = crate::BitReader<bool>;
39#[doc = "Field `SOFTRESET` writer - Active high reset."]
40pub type SOFTRESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSTIMER_SPEC, bool, O>;
41#[doc = "Field `CLOCKENABLE` reader - Enable OS event timer clock."]
42pub type CLOCKENABLE_R = crate::BitReader<bool>;
43#[doc = "Field `CLOCKENABLE` writer - Enable OS event timer clock."]
44pub type CLOCKENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSTIMER_SPEC, bool, O>;
45#[doc = "Field `DPDWAKEUPENABLE` reader - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)."]
46pub type DPDWAKEUPENABLE_R = crate::BitReader<bool>;
47#[doc = "Field `DPDWAKEUPENABLE` writer - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)."]
48pub type DPDWAKEUPENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSTIMER_SPEC, bool, O>;
49#[doc = "Field `OSC32KPD` reader - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K."]
50pub type OSC32KPD_R = crate::BitReader<bool>;
51#[doc = "Field `OSC32KPD` writer - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K."]
52pub type OSC32KPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSTIMER_SPEC, bool, O>;
53#[doc = "Field `OSTIMERCLKSEL` reader - OS event timer clock select."]
54pub type OSTIMERCLKSEL_R = crate::FieldReader<u8, OSTIMERCLKSEL_A>;
55#[doc = "OS event timer clock select.\n\nValue on reset: 0"]
56#[derive(Clone, Copy, Debug, PartialEq, Eq)]
57#[repr(u8)]
58pub enum OSTIMERCLKSEL_A {
59 #[doc = "0: Oscillator 32 kHz clock."]
60 OSC_32KHZ = 0,
61 #[doc = "1: FRO 1MHz clock."]
62 FRO_1MHZ = 1,
63 #[doc = "2: Main clock for OS timer."]
64 MAIN_CLOCK = 2,
65 #[doc = "3: No clock."]
66 NONE = 3,
67}
68impl From<OSTIMERCLKSEL_A> for u8 {
69 #[inline(always)]
70 fn from(variant: OSTIMERCLKSEL_A) -> Self {
71 variant as _
72 }
73}
74impl OSTIMERCLKSEL_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub fn variant(&self) -> OSTIMERCLKSEL_A {
78 match self.bits {
79 0 => OSTIMERCLKSEL_A::OSC_32KHZ,
80 1 => OSTIMERCLKSEL_A::FRO_1MHZ,
81 2 => OSTIMERCLKSEL_A::MAIN_CLOCK,
82 3 => OSTIMERCLKSEL_A::NONE,
83 _ => unreachable!(),
84 }
85 }
86 #[doc = "Checks if the value of the field is `OSC_32KHZ`"]
87 #[inline(always)]
88 pub fn is_osc_32khz(&self) -> bool {
89 *self == OSTIMERCLKSEL_A::OSC_32KHZ
90 }
91 #[doc = "Checks if the value of the field is `FRO_1MHZ`"]
92 #[inline(always)]
93 pub fn is_fro_1mhz(&self) -> bool {
94 *self == OSTIMERCLKSEL_A::FRO_1MHZ
95 }
96 #[doc = "Checks if the value of the field is `MAIN_CLOCK`"]
97 #[inline(always)]
98 pub fn is_main_clock(&self) -> bool {
99 *self == OSTIMERCLKSEL_A::MAIN_CLOCK
100 }
101 #[doc = "Checks if the value of the field is `NONE`"]
102 #[inline(always)]
103 pub fn is_none(&self) -> bool {
104 *self == OSTIMERCLKSEL_A::NONE
105 }
106}
107#[doc = "Field `OSTIMERCLKSEL` writer - OS event timer clock select."]
108pub type OSTIMERCLKSEL_W<'a, const O: u8> =
109 crate::FieldWriterSafe<'a, u32, OSTIMER_SPEC, u8, OSTIMERCLKSEL_A, 2, O>;
110impl<'a, const O: u8> OSTIMERCLKSEL_W<'a, O> {
111 #[doc = "Oscillator 32 kHz clock."]
112 #[inline(always)]
113 pub fn osc_32khz(self) -> &'a mut W {
114 self.variant(OSTIMERCLKSEL_A::OSC_32KHZ)
115 }
116 #[doc = "FRO 1MHz clock."]
117 #[inline(always)]
118 pub fn fro_1mhz(self) -> &'a mut W {
119 self.variant(OSTIMERCLKSEL_A::FRO_1MHZ)
120 }
121 #[doc = "Main clock for OS timer."]
122 #[inline(always)]
123 pub fn main_clock(self) -> &'a mut W {
124 self.variant(OSTIMERCLKSEL_A::MAIN_CLOCK)
125 }
126 #[doc = "No clock."]
127 #[inline(always)]
128 pub fn none(self) -> &'a mut W {
129 self.variant(OSTIMERCLKSEL_A::NONE)
130 }
131}
132impl R {
133 #[doc = "Bit 0 - Active high reset."]
134 #[inline(always)]
135 pub fn softreset(&self) -> SOFTRESET_R {
136 SOFTRESET_R::new((self.bits & 1) != 0)
137 }
138 #[doc = "Bit 1 - Enable OS event timer clock."]
139 #[inline(always)]
140 pub fn clockenable(&self) -> CLOCKENABLE_R {
141 CLOCKENABLE_R::new(((self.bits >> 1) & 1) != 0)
142 }
143 #[doc = "Bit 2 - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)."]
144 #[inline(always)]
145 pub fn dpdwakeupenable(&self) -> DPDWAKEUPENABLE_R {
146 DPDWAKEUPENABLE_R::new(((self.bits >> 2) & 1) != 0)
147 }
148 #[doc = "Bit 3 - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K."]
149 #[inline(always)]
150 pub fn osc32kpd(&self) -> OSC32KPD_R {
151 OSC32KPD_R::new(((self.bits >> 3) & 1) != 0)
152 }
153 #[doc = "Bits 4:5 - OS event timer clock select."]
154 #[inline(always)]
155 pub fn ostimerclksel(&self) -> OSTIMERCLKSEL_R {
156 OSTIMERCLKSEL_R::new(((self.bits >> 4) & 3) as u8)
157 }
158}
159impl W {
160 #[doc = "Bit 0 - Active high reset."]
161 #[inline(always)]
162 pub fn softreset(&mut self) -> SOFTRESET_W<0> {
163 SOFTRESET_W::new(self)
164 }
165 #[doc = "Bit 1 - Enable OS event timer clock."]
166 #[inline(always)]
167 pub fn clockenable(&mut self) -> CLOCKENABLE_W<1> {
168 CLOCKENABLE_W::new(self)
169 }
170 #[doc = "Bit 2 - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)."]
171 #[inline(always)]
172 pub fn dpdwakeupenable(&mut self) -> DPDWAKEUPENABLE_W<2> {
173 DPDWAKEUPENABLE_W::new(self)
174 }
175 #[doc = "Bit 3 - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K."]
176 #[inline(always)]
177 pub fn osc32kpd(&mut self) -> OSC32KPD_W<3> {
178 OSC32KPD_W::new(self)
179 }
180 #[doc = "Bits 4:5 - OS event timer clock select."]
181 #[inline(always)]
182 pub fn ostimerclksel(&mut self) -> OSTIMERCLKSEL_W<4> {
183 OSTIMERCLKSEL_W::new(self)
184 }
185 #[doc = "Writes raw bits to the register."]
186 #[inline(always)]
187 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
188 self.0.bits(bits);
189 self
190 }
191}
192#[doc = "OS Timer control register \\[Reset by: PoR, Brown Out Detectors Reset\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ostimer](index.html) module"]
193pub struct OSTIMER_SPEC;
194impl crate::RegisterSpec for OSTIMER_SPEC {
195 type Ux = u32;
196}
197#[doc = "`read()` method returns [ostimer::R](R) reader structure"]
198impl crate::Readable for OSTIMER_SPEC {
199 type Reader = R;
200}
201#[doc = "`write(|w| ..)` method takes [ostimer::W](W) writer structure"]
202impl crate::Writable for OSTIMER_SPEC {
203 type Writer = W;
204}
205#[doc = "`reset()` method sets OSTIMER to value 0x08"]
206impl crate::Resettable for OSTIMER_SPEC {
207 #[inline(always)]
208 fn reset_value() -> Self::Ux {
209 0x08
210 }
211}