lpc55_pac/syscon/
pll0stat.rs

1#[doc = "Register `PLL0STAT` reader"]
2pub struct R(crate::R<PLL0STAT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLL0STAT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLL0STAT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLL0STAT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLL0STAT` writer"]
17pub struct W(crate::W<PLL0STAT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLL0STAT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLL0STAT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLL0STAT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LOCK` reader - lock detector output (active high) Warning: The lock signal is only reliable between fref\\[2\\]
38:100 kHz to 20 MHz."]
39pub struct LOCK_R(crate::FieldReader<bool, bool>);
40impl LOCK_R {
41    #[inline(always)]
42    pub(crate) fn new(bits: bool) -> Self {
43        LOCK_R(crate::FieldReader::new(bits))
44    }
45}
46impl core::ops::Deref for LOCK_R {
47    type Target = crate::FieldReader<bool, bool>;
48    #[inline(always)]
49    fn deref(&self) -> &Self::Target {
50        &self.0
51    }
52}
53#[doc = "Field `PREDIVACK` reader - pre-divider ratio change acknowledge."]
54pub struct PREDIVACK_R(crate::FieldReader<bool, bool>);
55impl PREDIVACK_R {
56    #[inline(always)]
57    pub(crate) fn new(bits: bool) -> Self {
58        PREDIVACK_R(crate::FieldReader::new(bits))
59    }
60}
61impl core::ops::Deref for PREDIVACK_R {
62    type Target = crate::FieldReader<bool, bool>;
63    #[inline(always)]
64    fn deref(&self) -> &Self::Target {
65        &self.0
66    }
67}
68#[doc = "Field `FEEDDIVACK` reader - feedback divider ratio change acknowledge."]
69pub struct FEEDDIVACK_R(crate::FieldReader<bool, bool>);
70impl FEEDDIVACK_R {
71    #[inline(always)]
72    pub(crate) fn new(bits: bool) -> Self {
73        FEEDDIVACK_R(crate::FieldReader::new(bits))
74    }
75}
76impl core::ops::Deref for FEEDDIVACK_R {
77    type Target = crate::FieldReader<bool, bool>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `POSTDIVACK` reader - post-divider ratio change acknowledge."]
84pub struct POSTDIVACK_R(crate::FieldReader<bool, bool>);
85impl POSTDIVACK_R {
86    #[inline(always)]
87    pub(crate) fn new(bits: bool) -> Self {
88        POSTDIVACK_R(crate::FieldReader::new(bits))
89    }
90}
91impl core::ops::Deref for POSTDIVACK_R {
92    type Target = crate::FieldReader<bool, bool>;
93    #[inline(always)]
94    fn deref(&self) -> &Self::Target {
95        &self.0
96    }
97}
98#[doc = "Field `FRMDET` reader - free running detector output (active high)."]
99pub struct FRMDET_R(crate::FieldReader<bool, bool>);
100impl FRMDET_R {
101    #[inline(always)]
102    pub(crate) fn new(bits: bool) -> Self {
103        FRMDET_R(crate::FieldReader::new(bits))
104    }
105}
106impl core::ops::Deref for FRMDET_R {
107    type Target = crate::FieldReader<bool, bool>;
108    #[inline(always)]
109    fn deref(&self) -> &Self::Target {
110        &self.0
111    }
112}
113impl R {
114    #[doc = "Bit 0 - lock detector output (active high) Warning: The lock signal is only reliable between fref\\[2\\]
115:100 kHz to 20 MHz."]
116    #[inline(always)]
117    pub fn lock(&self) -> LOCK_R {
118        LOCK_R::new((self.bits & 0x01) != 0)
119    }
120    #[doc = "Bit 1 - pre-divider ratio change acknowledge."]
121    #[inline(always)]
122    pub fn predivack(&self) -> PREDIVACK_R {
123        PREDIVACK_R::new(((self.bits >> 1) & 0x01) != 0)
124    }
125    #[doc = "Bit 2 - feedback divider ratio change acknowledge."]
126    #[inline(always)]
127    pub fn feeddivack(&self) -> FEEDDIVACK_R {
128        FEEDDIVACK_R::new(((self.bits >> 2) & 0x01) != 0)
129    }
130    #[doc = "Bit 3 - post-divider ratio change acknowledge."]
131    #[inline(always)]
132    pub fn postdivack(&self) -> POSTDIVACK_R {
133        POSTDIVACK_R::new(((self.bits >> 3) & 0x01) != 0)
134    }
135    #[doc = "Bit 4 - free running detector output (active high)."]
136    #[inline(always)]
137    pub fn frmdet(&self) -> FRMDET_R {
138        FRMDET_R::new(((self.bits >> 4) & 0x01) != 0)
139    }
140}
141impl W {
142    #[doc = "Writes raw bits to the register."]
143    #[inline(always)]
144    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
145        self.0.bits(bits);
146        self
147    }
148}
149#[doc = "PLL0 550m status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0stat](index.html) module"]
150pub struct PLL0STAT_SPEC;
151impl crate::RegisterSpec for PLL0STAT_SPEC {
152    type Ux = u32;
153}
154#[doc = "`read()` method returns [pll0stat::R](R) reader structure"]
155impl crate::Readable for PLL0STAT_SPEC {
156    type Reader = R;
157}
158#[doc = "`write(|w| ..)` method takes [pll0stat::W](W) writer structure"]
159impl crate::Writable for PLL0STAT_SPEC {
160    type Writer = W;
161}
162#[doc = "`reset()` method sets PLL0STAT to value 0"]
163impl crate::Resettable for PLL0STAT_SPEC {
164    #[inline(always)]
165    fn reset_value() -> Self::Ux {
166        0
167    }
168}
lpc55_pac/syscon/pll0stat.rs

lpc55_pac/syscon/
pll0stat.rs
