lpc55_pac/syscon/
clockgenupdatelockout.rs

1#[doc = "Register `CLOCKGENUPDATELOCKOUT` reader"]
2pub struct R(crate::R<CLOCKGENUPDATELOCKOUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLOCKGENUPDATELOCKOUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLOCKGENUPDATELOCKOUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLOCKGENUPDATELOCKOUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLOCKGENUPDATELOCKOUT` writer"]
17pub struct W(crate::W<CLOCKGENUPDATELOCKOUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLOCKGENUPDATELOCKOUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLOCKGENUPDATELOCKOUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLOCKGENUPDATELOCKOUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL).\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u32)]
40pub enum CLOCKGENUPDATELOCKOUT_A {
41    #[doc = "0: all hardware clock configruration are freeze."]
42    FREEZE = 0,
43    #[doc = "1: update all clock configuration."]
44    ENABLE = 1,
45}
46impl From<CLOCKGENUPDATELOCKOUT_A> for u32 {
47    #[inline(always)]
48    fn from(variant: CLOCKGENUPDATELOCKOUT_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `CLOCKGENUPDATELOCKOUT` reader - Control clock configuration registers access (like xxxDIV, xxxSEL)."]
53pub struct CLOCKGENUPDATELOCKOUT_R(crate::FieldReader<u32, CLOCKGENUPDATELOCKOUT_A>);
54impl CLOCKGENUPDATELOCKOUT_R {
55    #[inline(always)]
56    pub(crate) fn new(bits: u32) -> Self {
57        CLOCKGENUPDATELOCKOUT_R(crate::FieldReader::new(bits))
58    }
59    #[doc = r"Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> Option<CLOCKGENUPDATELOCKOUT_A> {
62        match self.bits {
63            0 => Some(CLOCKGENUPDATELOCKOUT_A::FREEZE),
64            1 => Some(CLOCKGENUPDATELOCKOUT_A::ENABLE),
65            _ => None,
66        }
67    }
68    #[doc = "Checks if the value of the field is `FREEZE`"]
69    #[inline(always)]
70    pub fn is_freeze(&self) -> bool {
71        **self == CLOCKGENUPDATELOCKOUT_A::FREEZE
72    }
73    #[doc = "Checks if the value of the field is `ENABLE`"]
74    #[inline(always)]
75    pub fn is_enable(&self) -> bool {
76        **self == CLOCKGENUPDATELOCKOUT_A::ENABLE
77    }
78}
79impl core::ops::Deref for CLOCKGENUPDATELOCKOUT_R {
80    type Target = crate::FieldReader<u32, CLOCKGENUPDATELOCKOUT_A>;
81    #[inline(always)]
82    fn deref(&self) -> &Self::Target {
83        &self.0
84    }
85}
86#[doc = "Field `CLOCKGENUPDATELOCKOUT` writer - Control clock configuration registers access (like xxxDIV, xxxSEL)."]
87pub struct CLOCKGENUPDATELOCKOUT_W<'a> {
88    w: &'a mut W,
89}
90impl<'a> CLOCKGENUPDATELOCKOUT_W<'a> {
91    #[doc = r"Writes `variant` to the field"]
92    #[inline(always)]
93    pub fn variant(self, variant: CLOCKGENUPDATELOCKOUT_A) -> &'a mut W {
94        unsafe { self.bits(variant.into()) }
95    }
96    #[doc = "all hardware clock configruration are freeze."]
97    #[inline(always)]
98    pub fn freeze(self) -> &'a mut W {
99        self.variant(CLOCKGENUPDATELOCKOUT_A::FREEZE)
100    }
101    #[doc = "update all clock configuration."]
102    #[inline(always)]
103    pub fn enable(self) -> &'a mut W {
104        self.variant(CLOCKGENUPDATELOCKOUT_A::ENABLE)
105    }
106    #[doc = r"Writes raw bits to the field"]
107    #[inline(always)]
108    pub unsafe fn bits(self, value: u32) -> &'a mut W {
109        self.w.bits = value as u32;
110        self.w
111    }
112}
113impl R {
114    #[doc = "Bits 0:31 - Control clock configuration registers access (like xxxDIV, xxxSEL)."]
115    #[inline(always)]
116    pub fn clockgenupdatelockout(&self) -> CLOCKGENUPDATELOCKOUT_R {
117        CLOCKGENUPDATELOCKOUT_R::new(self.bits as u32)
118    }
119}
120impl W {
121    #[doc = "Bits 0:31 - Control clock configuration registers access (like xxxDIV, xxxSEL)."]
122    #[inline(always)]
123    pub fn clockgenupdatelockout(&mut self) -> CLOCKGENUPDATELOCKOUT_W {
124        CLOCKGENUPDATELOCKOUT_W { w: self }
125    }
126    #[doc = "Writes raw bits to the register."]
127    #[inline(always)]
128    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
129        self.0.bits(bits);
130        self
131    }
132}
133#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clockgenupdatelockout](index.html) module"]
134pub struct CLOCKGENUPDATELOCKOUT_SPEC;
135impl crate::RegisterSpec for CLOCKGENUPDATELOCKOUT_SPEC {
136    type Ux = u32;
137}
138#[doc = "`read()` method returns [clockgenupdatelockout::R](R) reader structure"]
139impl crate::Readable for CLOCKGENUPDATELOCKOUT_SPEC {
140    type Reader = R;
141}
142#[doc = "`write(|w| ..)` method takes [clockgenupdatelockout::W](W) writer structure"]
143impl crate::Writable for CLOCKGENUPDATELOCKOUT_SPEC {
144    type Writer = W;
145}
146#[doc = "`reset()` method sets CLOCKGENUPDATELOCKOUT to value 0"]
147impl crate::Resettable for CLOCKGENUPDATELOCKOUT_SPEC {
148    #[inline(always)]
149    fn reset_value() -> Self::Ux {
150        0
151    }
152}
lpc55_pac/syscon/clockgenupdatelockout.rs

lpc55_pac/syscon/
clockgenupdatelockout.rs
