lpc55_pac/hashcrypt/
memctrl.rs1#[doc = "Register `MEMCTRL` reader"]
2pub struct R(crate::R<MEMCTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MEMCTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MEMCTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MEMCTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `MEMCTRL` writer"]
17pub struct W(crate::W<MEMCTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MEMCTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MEMCTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MEMCTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Enables mastering.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum MASTER_A {
40 #[doc = "0: Mastering is not used and the normal DMA or Interrupt based model is used with INDATA."]
41 NOT_USED = 0,
42 #[doc = "1: Mastering is enabled and DMA and INDATA should not be used."]
43 ENABLED = 1,
44}
45impl From<MASTER_A> for bool {
46 #[inline(always)]
47 fn from(variant: MASTER_A) -> Self {
48 variant as u8 != 0
49 }
50}
51#[doc = "Field `MASTER` reader - Enables mastering."]
52pub struct MASTER_R(crate::FieldReader<bool, MASTER_A>);
53impl MASTER_R {
54 #[inline(always)]
55 pub(crate) fn new(bits: bool) -> Self {
56 MASTER_R(crate::FieldReader::new(bits))
57 }
58 #[doc = r"Get enumerated values variant"]
59 #[inline(always)]
60 pub fn variant(&self) -> MASTER_A {
61 match self.bits {
62 false => MASTER_A::NOT_USED,
63 true => MASTER_A::ENABLED,
64 }
65 }
66 #[doc = "Checks if the value of the field is `NOT_USED`"]
67 #[inline(always)]
68 pub fn is_not_used(&self) -> bool {
69 **self == MASTER_A::NOT_USED
70 }
71 #[doc = "Checks if the value of the field is `ENABLED`"]
72 #[inline(always)]
73 pub fn is_enabled(&self) -> bool {
74 **self == MASTER_A::ENABLED
75 }
76}
77impl core::ops::Deref for MASTER_R {
78 type Target = crate::FieldReader<bool, MASTER_A>;
79 #[inline(always)]
80 fn deref(&self) -> &Self::Target {
81 &self.0
82 }
83}
84#[doc = "Field `MASTER` writer - Enables mastering."]
85pub struct MASTER_W<'a> {
86 w: &'a mut W,
87}
88impl<'a> MASTER_W<'a> {
89 #[doc = r"Writes `variant` to the field"]
90 #[inline(always)]
91 pub fn variant(self, variant: MASTER_A) -> &'a mut W {
92 self.bit(variant.into())
93 }
94 #[doc = "Mastering is not used and the normal DMA or Interrupt based model is used with INDATA."]
95 #[inline(always)]
96 pub fn not_used(self) -> &'a mut W {
97 self.variant(MASTER_A::NOT_USED)
98 }
99 #[doc = "Mastering is enabled and DMA and INDATA should not be used."]
100 #[inline(always)]
101 pub fn enabled(self) -> &'a mut W {
102 self.variant(MASTER_A::ENABLED)
103 }
104 #[doc = r"Sets the field bit"]
105 #[inline(always)]
106 pub fn set_bit(self) -> &'a mut W {
107 self.bit(true)
108 }
109 #[doc = r"Clears the field bit"]
110 #[inline(always)]
111 pub fn clear_bit(self) -> &'a mut W {
112 self.bit(false)
113 }
114 #[doc = r"Writes raw bits to the field"]
115 #[inline(always)]
116 pub fn bit(self, value: bool) -> &'a mut W {
117 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118 self.w
119 }
120}
121#[doc = "Field `COUNT` reader - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
122pub struct COUNT_R(crate::FieldReader<u16, u16>);
123impl COUNT_R {
124 #[inline(always)]
125 pub(crate) fn new(bits: u16) -> Self {
126 COUNT_R(crate::FieldReader::new(bits))
127 }
128}
129impl core::ops::Deref for COUNT_R {
130 type Target = crate::FieldReader<u16, u16>;
131 #[inline(always)]
132 fn deref(&self) -> &Self::Target {
133 &self.0
134 }
135}
136#[doc = "Field `COUNT` writer - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
137pub struct COUNT_W<'a> {
138 w: &'a mut W,
139}
140impl<'a> COUNT_W<'a> {
141 #[doc = r"Writes raw bits to the field"]
142 #[inline(always)]
143 pub unsafe fn bits(self, value: u16) -> &'a mut W {
144 self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16);
145 self.w
146 }
147}
148impl R {
149 #[doc = "Bit 0 - Enables mastering."]
150 #[inline(always)]
151 pub fn master(&self) -> MASTER_R {
152 MASTER_R::new((self.bits & 0x01) != 0)
153 }
154 #[doc = "Bits 16:26 - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
155 #[inline(always)]
156 pub fn count(&self) -> COUNT_R {
157 COUNT_R::new(((self.bits >> 16) & 0x07ff) as u16)
158 }
159}
160impl W {
161 #[doc = "Bit 0 - Enables mastering."]
162 #[inline(always)]
163 pub fn master(&mut self) -> MASTER_W {
164 MASTER_W { w: self }
165 }
166 #[doc = "Bits 16:26 - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
167 #[inline(always)]
168 pub fn count(&mut self) -> COUNT_W {
169 COUNT_W { w: self }
170 }
171 #[doc = "Writes raw bits to the register."]
172 #[inline(always)]
173 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
174 self.0.bits(bits);
175 self
176 }
177}
178#[doc = "Setup Master to access memory (if available)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memctrl](index.html) module"]
179pub struct MEMCTRL_SPEC;
180impl crate::RegisterSpec for MEMCTRL_SPEC {
181 type Ux = u32;
182}
183#[doc = "`read()` method returns [memctrl::R](R) reader structure"]
184impl crate::Readable for MEMCTRL_SPEC {
185 type Reader = R;
186}
187#[doc = "`write(|w| ..)` method takes [memctrl::W](W) writer structure"]
188impl crate::Writable for MEMCTRL_SPEC {
189 type Writer = W;
190}
191#[doc = "`reset()` method sets MEMCTRL to value 0"]
192impl crate::Resettable for MEMCTRL_SPEC {
193 #[inline(always)]
194 fn reset_value() -> Self::Ux {
195 0
196 }
197}