[−][src]Module lpc54606_pac::usart0::fifotrig
FIFO trigger settings for interrupt and DMA request.
Structs
| RXLVLENA_W | Write proxy for field |
| RXLVL_W | Write proxy for field |
| TXLVLENA_W | Write proxy for field |
| TXLVL_W | Write proxy for field |
Enums
| RXLVLENA_A | Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. |
| TXLVLENA_A | Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. |
Type Definitions
| R | Reader of register FIFOTRIG |
| RXLVLENA_R | Reader of field |
| RXLVL_R | Reader of field |
| TXLVLENA_R | Reader of field |
| TXLVL_R | Reader of field |
| W | Writer for register FIFOTRIG |