Enum lpc54606_pac::usart0::fifotrig::RXLVLENA_A

pub enum RXLVLENA_A {
    DISABLED,
    ENABLED,
}

Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.

Value on reset: 0

Variants

DISABLED

0: Receive FIFO level does not generate a FIFO level trigger.

ENABLED

1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.

Trait Implementations

impl Clone for RXLVLENA_A

fn clone(&self) -> RXLVLENA_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for RXLVLENA_A

impl Debug for RXLVLENA_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<RXLVLENA_A> for bool

fn from(variant: RXLVLENA_A) -> Self

Performs the conversion.

impl PartialEq<RXLVLENA_A> for RXLVLENA_A

fn eq(&self, other: &RXLVLENA_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for RXLVLENA_A