lpc54606-pac 0.1.0

Low-level register mappings for the NXP LPC54606 series of ARM Cortex-M4 microcontrollers
Documentation 
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#[doc = "Reader of register LAR"]
pub type R = crate::R<u32, super::LAR>;
#[doc = "Writer for register LAR"]
pub type W = crate::W<u32, super::LAR>;
#[doc = "Register LAR `reset()`'s with value 0"]
impl crate::ResetValue for super::LAR {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0
    }
}
#[doc = "Reader of field `WriteAccessCode`"]
pub type WRITEACCESSCODE_R = crate::R<u32, u32>;
#[doc = "Write proxy for field `WriteAccessCode`"]
pub struct WRITEACCESSCODE_W<'a> {
    w: &'a mut W,
}
impl<'a> WRITEACCESSCODE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:31 - Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access."]
    #[inline(always)]
    pub fn write_access_code(&self) -> WRITEACCESSCODE_R {
        WRITEACCESSCODE_R::new((self.bits & 0xffff_ffff) as u32)
    }
}
impl W {
    #[doc = "Bits 0:31 - Write Access Code. A write of 0xC5ACCE55 enables further write access to this device. An invalid write will have the affect of removing write access."]
    #[inline(always)]
    pub fn write_access_code(&mut self) -> WRITEACCESSCODE_W {
        WRITEACCESSCODE_W { w: self }
    }
}