1#[doc = "Reader of register SEQ_CTRL%s"]
2pub type R = crate::R<u32, super::SEQ_CTRL>;
3#[doc = "Writer for register SEQ_CTRL%s"]
4pub type W = crate::W<u32, super::SEQ_CTRL>;
5#[doc = "Register SEQ_CTRL%s `reset()`'s with value 0"]
6impl crate::ResetValue for super::SEQ_CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `CHANNELS`"]
14pub type CHANNELS_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `CHANNELS`"]
16pub struct CHANNELS_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> CHANNELS_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u16) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
24 self.w
25 }
26}
27#[doc = "Reader of field `TRIGGER`"]
28pub type TRIGGER_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `TRIGGER`"]
30pub struct TRIGGER_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> TRIGGER_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x3f << 12)) | (((value as u32) & 0x3f) << 12);
38 self.w
39 }
40}
41#[doc = "Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43pub enum TRIGPOL_A {
44 #[doc = "0: Negative edge. A negative edge launches the conversion sequence on the selected trigger input."]
45 NEGATIVE_EDGE = 0,
46 #[doc = "1: Positive edge. A positive edge launches the conversion sequence on the selected trigger input."]
47 POSITIVE_EDGE = 1,
48}
49impl From<TRIGPOL_A> for bool {
50 #[inline(always)]
51 fn from(variant: TRIGPOL_A) -> Self {
52 variant as u8 != 0
53 }
54}
55#[doc = "Reader of field `TRIGPOL`"]
56pub type TRIGPOL_R = crate::R<bool, TRIGPOL_A>;
57impl TRIGPOL_R {
58 #[doc = r"Get enumerated values variant"]
59 #[inline(always)]
60 pub fn variant(&self) -> TRIGPOL_A {
61 match self.bits {
62 false => TRIGPOL_A::NEGATIVE_EDGE,
63 true => TRIGPOL_A::POSITIVE_EDGE,
64 }
65 }
66 #[doc = "Checks if the value of the field is `NEGATIVE_EDGE`"]
67 #[inline(always)]
68 pub fn is_negative_edge(&self) -> bool {
69 *self == TRIGPOL_A::NEGATIVE_EDGE
70 }
71 #[doc = "Checks if the value of the field is `POSITIVE_EDGE`"]
72 #[inline(always)]
73 pub fn is_positive_edge(&self) -> bool {
74 *self == TRIGPOL_A::POSITIVE_EDGE
75 }
76}
77#[doc = "Write proxy for field `TRIGPOL`"]
78pub struct TRIGPOL_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> TRIGPOL_W<'a> {
82 #[doc = r"Writes `variant` to the field"]
83 #[inline(always)]
84 pub fn variant(self, variant: TRIGPOL_A) -> &'a mut W {
85 {
86 self.bit(variant.into())
87 }
88 }
89 #[doc = "Negative edge. A negative edge launches the conversion sequence on the selected trigger input."]
90 #[inline(always)]
91 pub fn negative_edge(self) -> &'a mut W {
92 self.variant(TRIGPOL_A::NEGATIVE_EDGE)
93 }
94 #[doc = "Positive edge. A positive edge launches the conversion sequence on the selected trigger input."]
95 #[inline(always)]
96 pub fn positive_edge(self) -> &'a mut W {
97 self.variant(TRIGPOL_A::POSITIVE_EDGE)
98 }
99 #[doc = r"Sets the field bit"]
100 #[inline(always)]
101 pub fn set_bit(self) -> &'a mut W {
102 self.bit(true)
103 }
104 #[doc = r"Clears the field bit"]
105 #[inline(always)]
106 pub fn clear_bit(self) -> &'a mut W {
107 self.bit(false)
108 }
109 #[doc = r"Writes raw bits to the field"]
110 #[inline(always)]
111 pub fn bit(self, value: bool) -> &'a mut W {
112 self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
113 self.w
114 }
115}
116#[doc = "Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.\n\nValue on reset: 0"]
117#[derive(Clone, Copy, Debug, PartialEq)]
118pub enum SYNCBYPASS_A {
119 #[doc = "0: Enable trigger synchronization. The hardware trigger bypass is not enabled."]
120 ENABLE_TRIGGER_SYNCH = 0,
121 #[doc = "1: Bypass trigger synchronization. The hardware trigger bypass is enabled."]
122 BYPASS_TRIGGER_SYNCH = 1,
123}
124impl From<SYNCBYPASS_A> for bool {
125 #[inline(always)]
126 fn from(variant: SYNCBYPASS_A) -> Self {
127 variant as u8 != 0
128 }
129}
130#[doc = "Reader of field `SYNCBYPASS`"]
131pub type SYNCBYPASS_R = crate::R<bool, SYNCBYPASS_A>;
132impl SYNCBYPASS_R {
133 #[doc = r"Get enumerated values variant"]
134 #[inline(always)]
135 pub fn variant(&self) -> SYNCBYPASS_A {
136 match self.bits {
137 false => SYNCBYPASS_A::ENABLE_TRIGGER_SYNCH,
138 true => SYNCBYPASS_A::BYPASS_TRIGGER_SYNCH,
139 }
140 }
141 #[doc = "Checks if the value of the field is `ENABLE_TRIGGER_SYNCH`"]
142 #[inline(always)]
143 pub fn is_enable_trigger_synch(&self) -> bool {
144 *self == SYNCBYPASS_A::ENABLE_TRIGGER_SYNCH
145 }
146 #[doc = "Checks if the value of the field is `BYPASS_TRIGGER_SYNCH`"]
147 #[inline(always)]
148 pub fn is_bypass_trigger_synch(&self) -> bool {
149 *self == SYNCBYPASS_A::BYPASS_TRIGGER_SYNCH
150 }
151}
152#[doc = "Write proxy for field `SYNCBYPASS`"]
153pub struct SYNCBYPASS_W<'a> {
154 w: &'a mut W,
155}
156impl<'a> SYNCBYPASS_W<'a> {
157 #[doc = r"Writes `variant` to the field"]
158 #[inline(always)]
159 pub fn variant(self, variant: SYNCBYPASS_A) -> &'a mut W {
160 {
161 self.bit(variant.into())
162 }
163 }
164 #[doc = "Enable trigger synchronization. The hardware trigger bypass is not enabled."]
165 #[inline(always)]
166 pub fn enable_trigger_synch(self) -> &'a mut W {
167 self.variant(SYNCBYPASS_A::ENABLE_TRIGGER_SYNCH)
168 }
169 #[doc = "Bypass trigger synchronization. The hardware trigger bypass is enabled."]
170 #[inline(always)]
171 pub fn bypass_trigger_synch(self) -> &'a mut W {
172 self.variant(SYNCBYPASS_A::BYPASS_TRIGGER_SYNCH)
173 }
174 #[doc = r"Sets the field bit"]
175 #[inline(always)]
176 pub fn set_bit(self) -> &'a mut W {
177 self.bit(true)
178 }
179 #[doc = r"Clears the field bit"]
180 #[inline(always)]
181 pub fn clear_bit(self) -> &'a mut W {
182 self.bit(false)
183 }
184 #[doc = r"Writes raw bits to the field"]
185 #[inline(always)]
186 pub fn bit(self, value: bool) -> &'a mut W {
187 self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
188 self.w
189 }
190}
191#[doc = "Reader of field `START`"]
192pub type START_R = crate::R<bool, bool>;
193#[doc = "Write proxy for field `START`"]
194pub struct START_W<'a> {
195 w: &'a mut W,
196}
197impl<'a> START_W<'a> {
198 #[doc = r"Sets the field bit"]
199 #[inline(always)]
200 pub fn set_bit(self) -> &'a mut W {
201 self.bit(true)
202 }
203 #[doc = r"Clears the field bit"]
204 #[inline(always)]
205 pub fn clear_bit(self) -> &'a mut W {
206 self.bit(false)
207 }
208 #[doc = r"Writes raw bits to the field"]
209 #[inline(always)]
210 pub fn bit(self, value: bool) -> &'a mut W {
211 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
212 self.w
213 }
214}
215#[doc = "Reader of field `BURST`"]
216pub type BURST_R = crate::R<bool, bool>;
217#[doc = "Write proxy for field `BURST`"]
218pub struct BURST_W<'a> {
219 w: &'a mut W,
220}
221impl<'a> BURST_W<'a> {
222 #[doc = r"Sets the field bit"]
223 #[inline(always)]
224 pub fn set_bit(self) -> &'a mut W {
225 self.bit(true)
226 }
227 #[doc = r"Clears the field bit"]
228 #[inline(always)]
229 pub fn clear_bit(self) -> &'a mut W {
230 self.bit(false)
231 }
232 #[doc = r"Writes raw bits to the field"]
233 #[inline(always)]
234 pub fn bit(self, value: bool) -> &'a mut W {
235 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
236 self.w
237 }
238}
239#[doc = "Reader of field `SINGLESTEP`"]
240pub type SINGLESTEP_R = crate::R<bool, bool>;
241#[doc = "Write proxy for field `SINGLESTEP`"]
242pub struct SINGLESTEP_W<'a> {
243 w: &'a mut W,
244}
245impl<'a> SINGLESTEP_W<'a> {
246 #[doc = r"Sets the field bit"]
247 #[inline(always)]
248 pub fn set_bit(self) -> &'a mut W {
249 self.bit(true)
250 }
251 #[doc = r"Clears the field bit"]
252 #[inline(always)]
253 pub fn clear_bit(self) -> &'a mut W {
254 self.bit(false)
255 }
256 #[doc = r"Writes raw bits to the field"]
257 #[inline(always)]
258 pub fn bit(self, value: bool) -> &'a mut W {
259 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
260 self.w
261 }
262}
263#[doc = "Set priority for sequence A.\n\nValue on reset: 0"]
264#[derive(Clone, Copy, Debug, PartialEq)]
265pub enum LOWPRIO_A {
266 #[doc = "0: Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost."]
267 LOW_PRIORITY = 0,
268 #[doc = "1: High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point."]
269 HIGH_PRIORITY = 1,
270}
271impl From<LOWPRIO_A> for bool {
272 #[inline(always)]
273 fn from(variant: LOWPRIO_A) -> Self {
274 variant as u8 != 0
275 }
276}
277#[doc = "Reader of field `LOWPRIO`"]
278pub type LOWPRIO_R = crate::R<bool, LOWPRIO_A>;
279impl LOWPRIO_R {
280 #[doc = r"Get enumerated values variant"]
281 #[inline(always)]
282 pub fn variant(&self) -> LOWPRIO_A {
283 match self.bits {
284 false => LOWPRIO_A::LOW_PRIORITY,
285 true => LOWPRIO_A::HIGH_PRIORITY,
286 }
287 }
288 #[doc = "Checks if the value of the field is `LOW_PRIORITY`"]
289 #[inline(always)]
290 pub fn is_low_priority(&self) -> bool {
291 *self == LOWPRIO_A::LOW_PRIORITY
292 }
293 #[doc = "Checks if the value of the field is `HIGH_PRIORITY`"]
294 #[inline(always)]
295 pub fn is_high_priority(&self) -> bool {
296 *self == LOWPRIO_A::HIGH_PRIORITY
297 }
298}
299#[doc = "Write proxy for field `LOWPRIO`"]
300pub struct LOWPRIO_W<'a> {
301 w: &'a mut W,
302}
303impl<'a> LOWPRIO_W<'a> {
304 #[doc = r"Writes `variant` to the field"]
305 #[inline(always)]
306 pub fn variant(self, variant: LOWPRIO_A) -> &'a mut W {
307 {
308 self.bit(variant.into())
309 }
310 }
311 #[doc = "Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost."]
312 #[inline(always)]
313 pub fn low_priority(self) -> &'a mut W {
314 self.variant(LOWPRIO_A::LOW_PRIORITY)
315 }
316 #[doc = "High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point."]
317 #[inline(always)]
318 pub fn high_priority(self) -> &'a mut W {
319 self.variant(LOWPRIO_A::HIGH_PRIORITY)
320 }
321 #[doc = r"Sets the field bit"]
322 #[inline(always)]
323 pub fn set_bit(self) -> &'a mut W {
324 self.bit(true)
325 }
326 #[doc = r"Clears the field bit"]
327 #[inline(always)]
328 pub fn clear_bit(self) -> &'a mut W {
329 self.bit(false)
330 }
331 #[doc = r"Writes raw bits to the field"]
332 #[inline(always)]
333 pub fn bit(self, value: bool) -> &'a mut W {
334 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
335 self.w
336 }
337}
338#[doc = "Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.\n\nValue on reset: 0"]
339#[derive(Clone, Copy, Debug, PartialEq)]
340pub enum MODE_A {
341 #[doc = "0: End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled."]
342 END_OF_CONVERSION = 0,
343 #[doc = "1: End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode."]
344 END_OF_SEQUENCE = 1,
345}
346impl From<MODE_A> for bool {
347 #[inline(always)]
348 fn from(variant: MODE_A) -> Self {
349 variant as u8 != 0
350 }
351}
352#[doc = "Reader of field `MODE`"]
353pub type MODE_R = crate::R<bool, MODE_A>;
354impl MODE_R {
355 #[doc = r"Get enumerated values variant"]
356 #[inline(always)]
357 pub fn variant(&self) -> MODE_A {
358 match self.bits {
359 false => MODE_A::END_OF_CONVERSION,
360 true => MODE_A::END_OF_SEQUENCE,
361 }
362 }
363 #[doc = "Checks if the value of the field is `END_OF_CONVERSION`"]
364 #[inline(always)]
365 pub fn is_end_of_conversion(&self) -> bool {
366 *self == MODE_A::END_OF_CONVERSION
367 }
368 #[doc = "Checks if the value of the field is `END_OF_SEQUENCE`"]
369 #[inline(always)]
370 pub fn is_end_of_sequence(&self) -> bool {
371 *self == MODE_A::END_OF_SEQUENCE
372 }
373}
374#[doc = "Write proxy for field `MODE`"]
375pub struct MODE_W<'a> {
376 w: &'a mut W,
377}
378impl<'a> MODE_W<'a> {
379 #[doc = r"Writes `variant` to the field"]
380 #[inline(always)]
381 pub fn variant(self, variant: MODE_A) -> &'a mut W {
382 {
383 self.bit(variant.into())
384 }
385 }
386 #[doc = "End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled."]
387 #[inline(always)]
388 pub fn end_of_conversion(self) -> &'a mut W {
389 self.variant(MODE_A::END_OF_CONVERSION)
390 }
391 #[doc = "End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode."]
392 #[inline(always)]
393 pub fn end_of_sequence(self) -> &'a mut W {
394 self.variant(MODE_A::END_OF_SEQUENCE)
395 }
396 #[doc = r"Sets the field bit"]
397 #[inline(always)]
398 pub fn set_bit(self) -> &'a mut W {
399 self.bit(true)
400 }
401 #[doc = r"Clears the field bit"]
402 #[inline(always)]
403 pub fn clear_bit(self) -> &'a mut W {
404 self.bit(false)
405 }
406 #[doc = r"Writes raw bits to the field"]
407 #[inline(always)]
408 pub fn bit(self, value: bool) -> &'a mut W {
409 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
410 self.w
411 }
412}
413#[doc = "Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.\n\nValue on reset: 0"]
414#[derive(Clone, Copy, Debug, PartialEq)]
415pub enum SEQ_ENA_A {
416 #[doc = "0: Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel."]
417 DISABLED = 0,
418 #[doc = "1: Enabled. Sequence n is enabled."]
419 ENABLED = 1,
420}
421impl From<SEQ_ENA_A> for bool {
422 #[inline(always)]
423 fn from(variant: SEQ_ENA_A) -> Self {
424 variant as u8 != 0
425 }
426}
427#[doc = "Reader of field `SEQ_ENA`"]
428pub type SEQ_ENA_R = crate::R<bool, SEQ_ENA_A>;
429impl SEQ_ENA_R {
430 #[doc = r"Get enumerated values variant"]
431 #[inline(always)]
432 pub fn variant(&self) -> SEQ_ENA_A {
433 match self.bits {
434 false => SEQ_ENA_A::DISABLED,
435 true => SEQ_ENA_A::ENABLED,
436 }
437 }
438 #[doc = "Checks if the value of the field is `DISABLED`"]
439 #[inline(always)]
440 pub fn is_disabled(&self) -> bool {
441 *self == SEQ_ENA_A::DISABLED
442 }
443 #[doc = "Checks if the value of the field is `ENABLED`"]
444 #[inline(always)]
445 pub fn is_enabled(&self) -> bool {
446 *self == SEQ_ENA_A::ENABLED
447 }
448}
449#[doc = "Write proxy for field `SEQ_ENA`"]
450pub struct SEQ_ENA_W<'a> {
451 w: &'a mut W,
452}
453impl<'a> SEQ_ENA_W<'a> {
454 #[doc = r"Writes `variant` to the field"]
455 #[inline(always)]
456 pub fn variant(self, variant: SEQ_ENA_A) -> &'a mut W {
457 {
458 self.bit(variant.into())
459 }
460 }
461 #[doc = "Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel."]
462 #[inline(always)]
463 pub fn disabled(self) -> &'a mut W {
464 self.variant(SEQ_ENA_A::DISABLED)
465 }
466 #[doc = "Enabled. Sequence n is enabled."]
467 #[inline(always)]
468 pub fn enabled(self) -> &'a mut W {
469 self.variant(SEQ_ENA_A::ENABLED)
470 }
471 #[doc = r"Sets the field bit"]
472 #[inline(always)]
473 pub fn set_bit(self) -> &'a mut W {
474 self.bit(true)
475 }
476 #[doc = r"Clears the field bit"]
477 #[inline(always)]
478 pub fn clear_bit(self) -> &'a mut W {
479 self.bit(false)
480 }
481 #[doc = r"Writes raw bits to the field"]
482 #[inline(always)]
483 pub fn bit(self, value: bool) -> &'a mut W {
484 self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
485 self.w
486 }
487}
488impl R {
489 #[doc = "Bits 0:11 - Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write."]
490 #[inline(always)]
491 pub fn channels(&self) -> CHANNELS_R {
492 CHANNELS_R::new((self.bits & 0x0fff) as u16)
493 }
494 #[doc = "Bits 12:17 - Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
495 #[inline(always)]
496 pub fn trigger(&self) -> TRIGGER_R {
497 TRIGGER_R::new(((self.bits >> 12) & 0x3f) as u8)
498 }
499 #[doc = "Bit 18 - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
500 #[inline(always)]
501 pub fn trigpol(&self) -> TRIGPOL_R {
502 TRIGPOL_R::new(((self.bits >> 18) & 0x01) != 0)
503 }
504 #[doc = "Bit 19 - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."]
505 #[inline(always)]
506 pub fn syncbypass(&self) -> SYNCBYPASS_R {
507 SYNCBYPASS_R::new(((self.bits >> 19) & 0x01) != 0)
508 }
509 #[doc = "Bit 26 - Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero."]
510 #[inline(always)]
511 pub fn start(&self) -> START_R {
512 START_R::new(((self.bits >> 26) & 0x01) != 0)
513 }
514 #[doc = "Bit 27 - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared."]
515 #[inline(always)]
516 pub fn burst(&self) -> BURST_R {
517 BURST_R::new(((self.bits >> 27) & 0x01) != 0)
518 }
519 #[doc = "Bit 28 - When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit."]
520 #[inline(always)]
521 pub fn singlestep(&self) -> SINGLESTEP_R {
522 SINGLESTEP_R::new(((self.bits >> 28) & 0x01) != 0)
523 }
524 #[doc = "Bit 29 - Set priority for sequence A."]
525 #[inline(always)]
526 pub fn lowprio(&self) -> LOWPRIO_R {
527 LOWPRIO_R::new(((self.bits >> 29) & 0x01) != 0)
528 }
529 #[doc = "Bit 30 - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below."]
530 #[inline(always)]
531 pub fn mode(&self) -> MODE_R {
532 MODE_R::new(((self.bits >> 30) & 0x01) != 0)
533 }
534 #[doc = "Bit 31 - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled."]
535 #[inline(always)]
536 pub fn seq_ena(&self) -> SEQ_ENA_R {
537 SEQ_ENA_R::new(((self.bits >> 31) & 0x01) != 0)
538 }
539}
540impl W {
541 #[doc = "Bits 0:11 - Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write."]
542 #[inline(always)]
543 pub fn channels(&mut self) -> CHANNELS_W {
544 CHANNELS_W { w: self }
545 }
546 #[doc = "Bits 12:17 - Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
547 #[inline(always)]
548 pub fn trigger(&mut self) -> TRIGGER_W {
549 TRIGGER_W { w: self }
550 }
551 #[doc = "Bit 18 - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
552 #[inline(always)]
553 pub fn trigpol(&mut self) -> TRIGPOL_W {
554 TRIGPOL_W { w: self }
555 }
556 #[doc = "Bit 19 - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."]
557 #[inline(always)]
558 pub fn syncbypass(&mut self) -> SYNCBYPASS_W {
559 SYNCBYPASS_W { w: self }
560 }
561 #[doc = "Bit 26 - Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero."]
562 #[inline(always)]
563 pub fn start(&mut self) -> START_W {
564 START_W { w: self }
565 }
566 #[doc = "Bit 27 - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared."]
567 #[inline(always)]
568 pub fn burst(&mut self) -> BURST_W {
569 BURST_W { w: self }
570 }
571 #[doc = "Bit 28 - When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit."]
572 #[inline(always)]
573 pub fn singlestep(&mut self) -> SINGLESTEP_W {
574 SINGLESTEP_W { w: self }
575 }
576 #[doc = "Bit 29 - Set priority for sequence A."]
577 #[inline(always)]
578 pub fn lowprio(&mut self) -> LOWPRIO_W {
579 LOWPRIO_W { w: self }
580 }
581 #[doc = "Bit 30 - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below."]
582 #[inline(always)]
583 pub fn mode(&mut self) -> MODE_W {
584 MODE_W { w: self }
585 }
586 #[doc = "Bit 31 - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled."]
587 #[inline(always)]
588 pub fn seq_ena(&mut self) -> SEQ_ENA_W {
589 SEQ_ENA_W { w: self }
590 }
591}