lpc43xx/cgu/pll0usb_ctrl/
mod.rs1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::PLL0USB_CTRL {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `PD`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum PDR {
48 #[doc = "PLL0 enabled"]
49 PLL0_ENABLED,
50 #[doc = "PLL0 powered down"]
51 PLL0_POWERED_DOWN,
52}
53impl PDR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 PDR::PLL0_ENABLED => false,
69 PDR::PLL0_POWERED_DOWN => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> PDR {
76 match value {
77 false => PDR::PLL0_ENABLED,
78 true => PDR::PLL0_POWERED_DOWN,
79 }
80 }
81 #[doc = "Checks if the value of the field is `PLL0_ENABLED`"]
82 #[inline]
83 pub fn is_pll0_enabled(&self) -> bool {
84 *self == PDR::PLL0_ENABLED
85 }
86 #[doc = "Checks if the value of the field is `PLL0_POWERED_DOWN`"]
87 #[inline]
88 pub fn is_pll0_powered_down(&self) -> bool {
89 *self == PDR::PLL0_POWERED_DOWN
90 }
91}
92#[doc = "Possible values of the field `BYPASS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum BYPASSR {
95 #[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
96 CCO_CLOCK_SENT_TO_PO,
97 #[doc = "PLL0 input clock sent to post-dividers (default)."]
98 PLL0_INPUT_CLOCK_SEN,
99}
100impl BYPASSR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 BYPASSR::CCO_CLOCK_SENT_TO_PO => false,
116 BYPASSR::PLL0_INPUT_CLOCK_SEN => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> BYPASSR {
123 match value {
124 false => BYPASSR::CCO_CLOCK_SENT_TO_PO,
125 true => BYPASSR::PLL0_INPUT_CLOCK_SEN,
126 }
127 }
128 #[doc = "Checks if the value of the field is `CCO_CLOCK_SENT_TO_PO`"]
129 #[inline]
130 pub fn is_cco_clock_sent_to_po(&self) -> bool {
131 *self == BYPASSR::CCO_CLOCK_SENT_TO_PO
132 }
133 #[doc = "Checks if the value of the field is `PLL0_INPUT_CLOCK_SEN`"]
134 #[inline]
135 pub fn is_pll0_input_clock_sen(&self) -> bool {
136 *self == BYPASSR::PLL0_INPUT_CLOCK_SEN
137 }
138}
139#[doc = r" Value of the field"]
140pub struct DIRECTIR {
141 bits: bool,
142}
143impl DIRECTIR {
144 #[doc = r" Value of the field as raw bits"]
145 #[inline]
146 pub fn bit(&self) -> bool {
147 self.bits
148 }
149 #[doc = r" Returns `true` if the bit is clear (0)"]
150 #[inline]
151 pub fn bit_is_clear(&self) -> bool {
152 !self.bit()
153 }
154 #[doc = r" Returns `true` if the bit is set (1)"]
155 #[inline]
156 pub fn bit_is_set(&self) -> bool {
157 self.bit()
158 }
159}
160#[doc = r" Value of the field"]
161pub struct DIRECTOR {
162 bits: bool,
163}
164impl DIRECTOR {
165 #[doc = r" Value of the field as raw bits"]
166 #[inline]
167 pub fn bit(&self) -> bool {
168 self.bits
169 }
170 #[doc = r" Returns `true` if the bit is clear (0)"]
171 #[inline]
172 pub fn bit_is_clear(&self) -> bool {
173 !self.bit()
174 }
175 #[doc = r" Returns `true` if the bit is set (1)"]
176 #[inline]
177 pub fn bit_is_set(&self) -> bool {
178 self.bit()
179 }
180}
181#[doc = r" Value of the field"]
182pub struct CLKENR {
183 bits: bool,
184}
185impl CLKENR {
186 #[doc = r" Value of the field as raw bits"]
187 #[inline]
188 pub fn bit(&self) -> bool {
189 self.bits
190 }
191 #[doc = r" Returns `true` if the bit is clear (0)"]
192 #[inline]
193 pub fn bit_is_clear(&self) -> bool {
194 !self.bit()
195 }
196 #[doc = r" Returns `true` if the bit is set (1)"]
197 #[inline]
198 pub fn bit_is_set(&self) -> bool {
199 self.bit()
200 }
201}
202#[doc = r" Value of the field"]
203pub struct FRMR {
204 bits: bool,
205}
206impl FRMR {
207 #[doc = r" Value of the field as raw bits"]
208 #[inline]
209 pub fn bit(&self) -> bool {
210 self.bits
211 }
212 #[doc = r" Returns `true` if the bit is clear (0)"]
213 #[inline]
214 pub fn bit_is_clear(&self) -> bool {
215 !self.bit()
216 }
217 #[doc = r" Returns `true` if the bit is set (1)"]
218 #[inline]
219 pub fn bit_is_set(&self) -> bool {
220 self.bit()
221 }
222}
223#[doc = "Possible values of the field `AUTOBLOCK`"]
224#[derive(Clone, Copy, Debug, PartialEq)]
225pub enum AUTOBLOCKR {
226 #[doc = "Disabled. Autoblocking disabled"]
227 DISABLED,
228 #[doc = "Enabled. Autoblocking enabled"]
229 ENABLED,
230}
231impl AUTOBLOCKR {
232 #[doc = r" Returns `true` if the bit is clear (0)"]
233 #[inline]
234 pub fn bit_is_clear(&self) -> bool {
235 !self.bit()
236 }
237 #[doc = r" Returns `true` if the bit is set (1)"]
238 #[inline]
239 pub fn bit_is_set(&self) -> bool {
240 self.bit()
241 }
242 #[doc = r" Value of the field as raw bits"]
243 #[inline]
244 pub fn bit(&self) -> bool {
245 match *self {
246 AUTOBLOCKR::DISABLED => false,
247 AUTOBLOCKR::ENABLED => true,
248 }
249 }
250 #[allow(missing_docs)]
251 #[doc(hidden)]
252 #[inline]
253 pub fn _from(value: bool) -> AUTOBLOCKR {
254 match value {
255 false => AUTOBLOCKR::DISABLED,
256 true => AUTOBLOCKR::ENABLED,
257 }
258 }
259 #[doc = "Checks if the value of the field is `DISABLED`"]
260 #[inline]
261 pub fn is_disabled(&self) -> bool {
262 *self == AUTOBLOCKR::DISABLED
263 }
264 #[doc = "Checks if the value of the field is `ENABLED`"]
265 #[inline]
266 pub fn is_enabled(&self) -> bool {
267 *self == AUTOBLOCKR::ENABLED
268 }
269}
270#[doc = "Possible values of the field `CLK_SEL`"]
271#[derive(Clone, Copy, Debug, PartialEq)]
272pub enum CLK_SELR {
273 #[doc = "32 kHz oscillator"]
274 _32_KHZ_OSCILLATOR,
275 #[doc = "IRC (default)"]
276 IRC,
277 #[doc = "ENET_RX_CLK"]
278 ENET_RX_CLK,
279 #[doc = "ENET_TX_CLK"]
280 ENET_TX_CLK,
281 #[doc = "GP_CLKIN"]
282 GP_CLKIN,
283 #[doc = "Crystal oscillator"]
284 CRYSTAL_OSCILLATOR,
285 #[doc = "PLL1"]
286 PLL1,
287 #[doc = "IDIVA"]
288 IDIVA,
289 #[doc = "IDIVB"]
290 IDIVB,
291 #[doc = "IDIVC"]
292 IDIVC,
293 #[doc = "IDIVD"]
294 IDIVD,
295 #[doc = "IDIVE"]
296 IDIVE,
297 #[doc = r" Reserved"]
298 _Reserved(u8),
299}
300impl CLK_SELR {
301 #[doc = r" Value of the field as raw bits"]
302 #[inline]
303 pub fn bits(&self) -> u8 {
304 match *self {
305 CLK_SELR::_32_KHZ_OSCILLATOR => 0,
306 CLK_SELR::IRC => 1,
307 CLK_SELR::ENET_RX_CLK => 2,
308 CLK_SELR::ENET_TX_CLK => 3,
309 CLK_SELR::GP_CLKIN => 4,
310 CLK_SELR::CRYSTAL_OSCILLATOR => 6,
311 CLK_SELR::PLL1 => 9,
312 CLK_SELR::IDIVA => 12,
313 CLK_SELR::IDIVB => 13,
314 CLK_SELR::IDIVC => 14,
315 CLK_SELR::IDIVD => 15,
316 CLK_SELR::IDIVE => 16,
317 CLK_SELR::_Reserved(bits) => bits,
318 }
319 }
320 #[allow(missing_docs)]
321 #[doc(hidden)]
322 #[inline]
323 pub fn _from(value: u8) -> CLK_SELR {
324 match value {
325 0 => CLK_SELR::_32_KHZ_OSCILLATOR,
326 1 => CLK_SELR::IRC,
327 2 => CLK_SELR::ENET_RX_CLK,
328 3 => CLK_SELR::ENET_TX_CLK,
329 4 => CLK_SELR::GP_CLKIN,
330 6 => CLK_SELR::CRYSTAL_OSCILLATOR,
331 9 => CLK_SELR::PLL1,
332 12 => CLK_SELR::IDIVA,
333 13 => CLK_SELR::IDIVB,
334 14 => CLK_SELR::IDIVC,
335 15 => CLK_SELR::IDIVD,
336 16 => CLK_SELR::IDIVE,
337 i => CLK_SELR::_Reserved(i),
338 }
339 }
340 #[doc = "Checks if the value of the field is `_32_KHZ_OSCILLATOR`"]
341 #[inline]
342 pub fn is_32_khz_oscillator(&self) -> bool {
343 *self == CLK_SELR::_32_KHZ_OSCILLATOR
344 }
345 #[doc = "Checks if the value of the field is `IRC`"]
346 #[inline]
347 pub fn is_irc(&self) -> bool {
348 *self == CLK_SELR::IRC
349 }
350 #[doc = "Checks if the value of the field is `ENET_RX_CLK`"]
351 #[inline]
352 pub fn is_enet_rx_clk(&self) -> bool {
353 *self == CLK_SELR::ENET_RX_CLK
354 }
355 #[doc = "Checks if the value of the field is `ENET_TX_CLK`"]
356 #[inline]
357 pub fn is_enet_tx_clk(&self) -> bool {
358 *self == CLK_SELR::ENET_TX_CLK
359 }
360 #[doc = "Checks if the value of the field is `GP_CLKIN`"]
361 #[inline]
362 pub fn is_gp_clkin(&self) -> bool {
363 *self == CLK_SELR::GP_CLKIN
364 }
365 #[doc = "Checks if the value of the field is `CRYSTAL_OSCILLATOR`"]
366 #[inline]
367 pub fn is_crystal_oscillator(&self) -> bool {
368 *self == CLK_SELR::CRYSTAL_OSCILLATOR
369 }
370 #[doc = "Checks if the value of the field is `PLL1`"]
371 #[inline]
372 pub fn is_pll1(&self) -> bool {
373 *self == CLK_SELR::PLL1
374 }
375 #[doc = "Checks if the value of the field is `IDIVA`"]
376 #[inline]
377 pub fn is_idiva(&self) -> bool {
378 *self == CLK_SELR::IDIVA
379 }
380 #[doc = "Checks if the value of the field is `IDIVB`"]
381 #[inline]
382 pub fn is_idivb(&self) -> bool {
383 *self == CLK_SELR::IDIVB
384 }
385 #[doc = "Checks if the value of the field is `IDIVC`"]
386 #[inline]
387 pub fn is_idivc(&self) -> bool {
388 *self == CLK_SELR::IDIVC
389 }
390 #[doc = "Checks if the value of the field is `IDIVD`"]
391 #[inline]
392 pub fn is_idivd(&self) -> bool {
393 *self == CLK_SELR::IDIVD
394 }
395 #[doc = "Checks if the value of the field is `IDIVE`"]
396 #[inline]
397 pub fn is_idive(&self) -> bool {
398 *self == CLK_SELR::IDIVE
399 }
400}
401#[doc = "Values that can be written to the field `PD`"]
402pub enum PDW {
403 #[doc = "PLL0 enabled"]
404 PLL0_ENABLED,
405 #[doc = "PLL0 powered down"]
406 PLL0_POWERED_DOWN,
407}
408impl PDW {
409 #[allow(missing_docs)]
410 #[doc(hidden)]
411 #[inline]
412 pub fn _bits(&self) -> bool {
413 match *self {
414 PDW::PLL0_ENABLED => false,
415 PDW::PLL0_POWERED_DOWN => true,
416 }
417 }
418}
419#[doc = r" Proxy"]
420pub struct _PDW<'a> {
421 w: &'a mut W,
422}
423impl<'a> _PDW<'a> {
424 #[doc = r" Writes `variant` to the field"]
425 #[inline]
426 pub fn variant(self, variant: PDW) -> &'a mut W {
427 {
428 self.bit(variant._bits())
429 }
430 }
431 #[doc = "PLL0 enabled"]
432 #[inline]
433 pub fn pll0_enabled(self) -> &'a mut W {
434 self.variant(PDW::PLL0_ENABLED)
435 }
436 #[doc = "PLL0 powered down"]
437 #[inline]
438 pub fn pll0_powered_down(self) -> &'a mut W {
439 self.variant(PDW::PLL0_POWERED_DOWN)
440 }
441 #[doc = r" Sets the field bit"]
442 pub fn set_bit(self) -> &'a mut W {
443 self.bit(true)
444 }
445 #[doc = r" Clears the field bit"]
446 pub fn clear_bit(self) -> &'a mut W {
447 self.bit(false)
448 }
449 #[doc = r" Writes raw bits to the field"]
450 #[inline]
451 pub fn bit(self, value: bool) -> &'a mut W {
452 const MASK: bool = true;
453 const OFFSET: u8 = 0;
454 self.w.bits &= !((MASK as u32) << OFFSET);
455 self.w.bits |= ((value & MASK) as u32) << OFFSET;
456 self.w
457 }
458}
459#[doc = "Values that can be written to the field `BYPASS`"]
460pub enum BYPASSW {
461 #[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
462 CCO_CLOCK_SENT_TO_PO,
463 #[doc = "PLL0 input clock sent to post-dividers (default)."]
464 PLL0_INPUT_CLOCK_SEN,
465}
466impl BYPASSW {
467 #[allow(missing_docs)]
468 #[doc(hidden)]
469 #[inline]
470 pub fn _bits(&self) -> bool {
471 match *self {
472 BYPASSW::CCO_CLOCK_SENT_TO_PO => false,
473 BYPASSW::PLL0_INPUT_CLOCK_SEN => true,
474 }
475 }
476}
477#[doc = r" Proxy"]
478pub struct _BYPASSW<'a> {
479 w: &'a mut W,
480}
481impl<'a> _BYPASSW<'a> {
482 #[doc = r" Writes `variant` to the field"]
483 #[inline]
484 pub fn variant(self, variant: BYPASSW) -> &'a mut W {
485 {
486 self.bit(variant._bits())
487 }
488 }
489 #[doc = "CCO clock sent to post-dividers. Use this in normal operation."]
490 #[inline]
491 pub fn cco_clock_sent_to_po(self) -> &'a mut W {
492 self.variant(BYPASSW::CCO_CLOCK_SENT_TO_PO)
493 }
494 #[doc = "PLL0 input clock sent to post-dividers (default)."]
495 #[inline]
496 pub fn pll0_input_clock_sen(self) -> &'a mut W {
497 self.variant(BYPASSW::PLL0_INPUT_CLOCK_SEN)
498 }
499 #[doc = r" Sets the field bit"]
500 pub fn set_bit(self) -> &'a mut W {
501 self.bit(true)
502 }
503 #[doc = r" Clears the field bit"]
504 pub fn clear_bit(self) -> &'a mut W {
505 self.bit(false)
506 }
507 #[doc = r" Writes raw bits to the field"]
508 #[inline]
509 pub fn bit(self, value: bool) -> &'a mut W {
510 const MASK: bool = true;
511 const OFFSET: u8 = 1;
512 self.w.bits &= !((MASK as u32) << OFFSET);
513 self.w.bits |= ((value & MASK) as u32) << OFFSET;
514 self.w
515 }
516}
517#[doc = r" Proxy"]
518pub struct _DIRECTIW<'a> {
519 w: &'a mut W,
520}
521impl<'a> _DIRECTIW<'a> {
522 #[doc = r" Sets the field bit"]
523 pub fn set_bit(self) -> &'a mut W {
524 self.bit(true)
525 }
526 #[doc = r" Clears the field bit"]
527 pub fn clear_bit(self) -> &'a mut W {
528 self.bit(false)
529 }
530 #[doc = r" Writes raw bits to the field"]
531 #[inline]
532 pub fn bit(self, value: bool) -> &'a mut W {
533 const MASK: bool = true;
534 const OFFSET: u8 = 2;
535 self.w.bits &= !((MASK as u32) << OFFSET);
536 self.w.bits |= ((value & MASK) as u32) << OFFSET;
537 self.w
538 }
539}
540#[doc = r" Proxy"]
541pub struct _DIRECTOW<'a> {
542 w: &'a mut W,
543}
544impl<'a> _DIRECTOW<'a> {
545 #[doc = r" Sets the field bit"]
546 pub fn set_bit(self) -> &'a mut W {
547 self.bit(true)
548 }
549 #[doc = r" Clears the field bit"]
550 pub fn clear_bit(self) -> &'a mut W {
551 self.bit(false)
552 }
553 #[doc = r" Writes raw bits to the field"]
554 #[inline]
555 pub fn bit(self, value: bool) -> &'a mut W {
556 const MASK: bool = true;
557 const OFFSET: u8 = 3;
558 self.w.bits &= !((MASK as u32) << OFFSET);
559 self.w.bits |= ((value & MASK) as u32) << OFFSET;
560 self.w
561 }
562}
563#[doc = r" Proxy"]
564pub struct _CLKENW<'a> {
565 w: &'a mut W,
566}
567impl<'a> _CLKENW<'a> {
568 #[doc = r" Sets the field bit"]
569 pub fn set_bit(self) -> &'a mut W {
570 self.bit(true)
571 }
572 #[doc = r" Clears the field bit"]
573 pub fn clear_bit(self) -> &'a mut W {
574 self.bit(false)
575 }
576 #[doc = r" Writes raw bits to the field"]
577 #[inline]
578 pub fn bit(self, value: bool) -> &'a mut W {
579 const MASK: bool = true;
580 const OFFSET: u8 = 4;
581 self.w.bits &= !((MASK as u32) << OFFSET);
582 self.w.bits |= ((value & MASK) as u32) << OFFSET;
583 self.w
584 }
585}
586#[doc = r" Proxy"]
587pub struct _FRMW<'a> {
588 w: &'a mut W,
589}
590impl<'a> _FRMW<'a> {
591 #[doc = r" Sets the field bit"]
592 pub fn set_bit(self) -> &'a mut W {
593 self.bit(true)
594 }
595 #[doc = r" Clears the field bit"]
596 pub fn clear_bit(self) -> &'a mut W {
597 self.bit(false)
598 }
599 #[doc = r" Writes raw bits to the field"]
600 #[inline]
601 pub fn bit(self, value: bool) -> &'a mut W {
602 const MASK: bool = true;
603 const OFFSET: u8 = 6;
604 self.w.bits &= !((MASK as u32) << OFFSET);
605 self.w.bits |= ((value & MASK) as u32) << OFFSET;
606 self.w
607 }
608}
609#[doc = "Values that can be written to the field `AUTOBLOCK`"]
610pub enum AUTOBLOCKW {
611 #[doc = "Disabled. Autoblocking disabled"]
612 DISABLED,
613 #[doc = "Enabled. Autoblocking enabled"]
614 ENABLED,
615}
616impl AUTOBLOCKW {
617 #[allow(missing_docs)]
618 #[doc(hidden)]
619 #[inline]
620 pub fn _bits(&self) -> bool {
621 match *self {
622 AUTOBLOCKW::DISABLED => false,
623 AUTOBLOCKW::ENABLED => true,
624 }
625 }
626}
627#[doc = r" Proxy"]
628pub struct _AUTOBLOCKW<'a> {
629 w: &'a mut W,
630}
631impl<'a> _AUTOBLOCKW<'a> {
632 #[doc = r" Writes `variant` to the field"]
633 #[inline]
634 pub fn variant(self, variant: AUTOBLOCKW) -> &'a mut W {
635 {
636 self.bit(variant._bits())
637 }
638 }
639 #[doc = "Disabled. Autoblocking disabled"]
640 #[inline]
641 pub fn disabled(self) -> &'a mut W {
642 self.variant(AUTOBLOCKW::DISABLED)
643 }
644 #[doc = "Enabled. Autoblocking enabled"]
645 #[inline]
646 pub fn enabled(self) -> &'a mut W {
647 self.variant(AUTOBLOCKW::ENABLED)
648 }
649 #[doc = r" Sets the field bit"]
650 pub fn set_bit(self) -> &'a mut W {
651 self.bit(true)
652 }
653 #[doc = r" Clears the field bit"]
654 pub fn clear_bit(self) -> &'a mut W {
655 self.bit(false)
656 }
657 #[doc = r" Writes raw bits to the field"]
658 #[inline]
659 pub fn bit(self, value: bool) -> &'a mut W {
660 const MASK: bool = true;
661 const OFFSET: u8 = 11;
662 self.w.bits &= !((MASK as u32) << OFFSET);
663 self.w.bits |= ((value & MASK) as u32) << OFFSET;
664 self.w
665 }
666}
667#[doc = "Values that can be written to the field `CLK_SEL`"]
668pub enum CLK_SELW {
669 #[doc = "32 kHz oscillator"]
670 _32_KHZ_OSCILLATOR,
671 #[doc = "IRC (default)"]
672 IRC,
673 #[doc = "ENET_RX_CLK"]
674 ENET_RX_CLK,
675 #[doc = "ENET_TX_CLK"]
676 ENET_TX_CLK,
677 #[doc = "GP_CLKIN"]
678 GP_CLKIN,
679 #[doc = "Crystal oscillator"]
680 CRYSTAL_OSCILLATOR,
681 #[doc = "PLL1"]
682 PLL1,
683 #[doc = "IDIVA"]
684 IDIVA,
685 #[doc = "IDIVB"]
686 IDIVB,
687 #[doc = "IDIVC"]
688 IDIVC,
689 #[doc = "IDIVD"]
690 IDIVD,
691 #[doc = "IDIVE"]
692 IDIVE,
693}
694impl CLK_SELW {
695 #[allow(missing_docs)]
696 #[doc(hidden)]
697 #[inline]
698 pub fn _bits(&self) -> u8 {
699 match *self {
700 CLK_SELW::_32_KHZ_OSCILLATOR => 0,
701 CLK_SELW::IRC => 1,
702 CLK_SELW::ENET_RX_CLK => 2,
703 CLK_SELW::ENET_TX_CLK => 3,
704 CLK_SELW::GP_CLKIN => 4,
705 CLK_SELW::CRYSTAL_OSCILLATOR => 6,
706 CLK_SELW::PLL1 => 9,
707 CLK_SELW::IDIVA => 12,
708 CLK_SELW::IDIVB => 13,
709 CLK_SELW::IDIVC => 14,
710 CLK_SELW::IDIVD => 15,
711 CLK_SELW::IDIVE => 16,
712 }
713 }
714}
715#[doc = r" Proxy"]
716pub struct _CLK_SELW<'a> {
717 w: &'a mut W,
718}
719impl<'a> _CLK_SELW<'a> {
720 #[doc = r" Writes `variant` to the field"]
721 #[inline]
722 pub fn variant(self, variant: CLK_SELW) -> &'a mut W {
723 unsafe { self.bits(variant._bits()) }
724 }
725 #[doc = "32 kHz oscillator"]
726 #[inline]
727 pub fn _32_khz_oscillator(self) -> &'a mut W {
728 self.variant(CLK_SELW::_32_KHZ_OSCILLATOR)
729 }
730 #[doc = "IRC (default)"]
731 #[inline]
732 pub fn irc(self) -> &'a mut W {
733 self.variant(CLK_SELW::IRC)
734 }
735 #[doc = "ENET_RX_CLK"]
736 #[inline]
737 pub fn enet_rx_clk(self) -> &'a mut W {
738 self.variant(CLK_SELW::ENET_RX_CLK)
739 }
740 #[doc = "ENET_TX_CLK"]
741 #[inline]
742 pub fn enet_tx_clk(self) -> &'a mut W {
743 self.variant(CLK_SELW::ENET_TX_CLK)
744 }
745 #[doc = "GP_CLKIN"]
746 #[inline]
747 pub fn gp_clkin(self) -> &'a mut W {
748 self.variant(CLK_SELW::GP_CLKIN)
749 }
750 #[doc = "Crystal oscillator"]
751 #[inline]
752 pub fn crystal_oscillator(self) -> &'a mut W {
753 self.variant(CLK_SELW::CRYSTAL_OSCILLATOR)
754 }
755 #[doc = "PLL1"]
756 #[inline]
757 pub fn pll1(self) -> &'a mut W {
758 self.variant(CLK_SELW::PLL1)
759 }
760 #[doc = "IDIVA"]
761 #[inline]
762 pub fn idiva(self) -> &'a mut W {
763 self.variant(CLK_SELW::IDIVA)
764 }
765 #[doc = "IDIVB"]
766 #[inline]
767 pub fn idivb(self) -> &'a mut W {
768 self.variant(CLK_SELW::IDIVB)
769 }
770 #[doc = "IDIVC"]
771 #[inline]
772 pub fn idivc(self) -> &'a mut W {
773 self.variant(CLK_SELW::IDIVC)
774 }
775 #[doc = "IDIVD"]
776 #[inline]
777 pub fn idivd(self) -> &'a mut W {
778 self.variant(CLK_SELW::IDIVD)
779 }
780 #[doc = "IDIVE"]
781 #[inline]
782 pub fn idive(self) -> &'a mut W {
783 self.variant(CLK_SELW::IDIVE)
784 }
785 #[doc = r" Writes raw bits to the field"]
786 #[inline]
787 pub unsafe fn bits(self, value: u8) -> &'a mut W {
788 const MASK: u8 = 31;
789 const OFFSET: u8 = 24;
790 self.w.bits &= !((MASK as u32) << OFFSET);
791 self.w.bits |= ((value & MASK) as u32) << OFFSET;
792 self.w
793 }
794}
795impl R {
796 #[doc = r" Value of the register as raw bits"]
797 #[inline]
798 pub fn bits(&self) -> u32 {
799 self.bits
800 }
801 #[doc = "Bit 0 - PLL0 power down"]
802 #[inline]
803 pub fn pd(&self) -> PDR {
804 PDR::_from({
805 const MASK: bool = true;
806 const OFFSET: u8 = 0;
807 ((self.bits >> OFFSET) & MASK as u32) != 0
808 })
809 }
810 #[doc = "Bit 1 - Input clock bypass control"]
811 #[inline]
812 pub fn bypass(&self) -> BYPASSR {
813 BYPASSR::_from({
814 const MASK: bool = true;
815 const OFFSET: u8 = 1;
816 ((self.bits >> OFFSET) & MASK as u32) != 0
817 })
818 }
819 #[doc = "Bit 2 - PLL0 direct input"]
820 #[inline]
821 pub fn directi(&self) -> DIRECTIR {
822 let bits = {
823 const MASK: bool = true;
824 const OFFSET: u8 = 2;
825 ((self.bits >> OFFSET) & MASK as u32) != 0
826 };
827 DIRECTIR { bits }
828 }
829 #[doc = "Bit 3 - PLL0 direct output"]
830 #[inline]
831 pub fn directo(&self) -> DIRECTOR {
832 let bits = {
833 const MASK: bool = true;
834 const OFFSET: u8 = 3;
835 ((self.bits >> OFFSET) & MASK as u32) != 0
836 };
837 DIRECTOR { bits }
838 }
839 #[doc = "Bit 4 - PLL0 clock enable"]
840 #[inline]
841 pub fn clken(&self) -> CLKENR {
842 let bits = {
843 const MASK: bool = true;
844 const OFFSET: u8 = 4;
845 ((self.bits >> OFFSET) & MASK as u32) != 0
846 };
847 CLKENR { bits }
848 }
849 #[doc = "Bit 6 - Free running mode"]
850 #[inline]
851 pub fn frm(&self) -> FRMR {
852 let bits = {
853 const MASK: bool = true;
854 const OFFSET: u8 = 6;
855 ((self.bits >> OFFSET) & MASK as u32) != 0
856 };
857 FRMR { bits }
858 }
859 #[doc = "Bit 11 - Block clock automatically during frequency change"]
860 #[inline]
861 pub fn autoblock(&self) -> AUTOBLOCKR {
862 AUTOBLOCKR::_from({
863 const MASK: bool = true;
864 const OFFSET: u8 = 11;
865 ((self.bits >> OFFSET) & MASK as u32) != 0
866 })
867 }
868 #[doc = "Bits 24:28 - Clock source selection. All other values are reserved."]
869 #[inline]
870 pub fn clk_sel(&self) -> CLK_SELR {
871 CLK_SELR::_from({
872 const MASK: u8 = 31;
873 const OFFSET: u8 = 24;
874 ((self.bits >> OFFSET) & MASK as u32) as u8
875 })
876 }
877}
878impl W {
879 #[doc = r" Reset value of the register"]
880 #[inline]
881 pub fn reset_value() -> W {
882 W { bits: 16777219 }
883 }
884 #[doc = r" Writes raw bits to the register"]
885 #[inline]
886 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
887 self.bits = bits;
888 self
889 }
890 #[doc = "Bit 0 - PLL0 power down"]
891 #[inline]
892 pub fn pd(&mut self) -> _PDW {
893 _PDW { w: self }
894 }
895 #[doc = "Bit 1 - Input clock bypass control"]
896 #[inline]
897 pub fn bypass(&mut self) -> _BYPASSW {
898 _BYPASSW { w: self }
899 }
900 #[doc = "Bit 2 - PLL0 direct input"]
901 #[inline]
902 pub fn directi(&mut self) -> _DIRECTIW {
903 _DIRECTIW { w: self }
904 }
905 #[doc = "Bit 3 - PLL0 direct output"]
906 #[inline]
907 pub fn directo(&mut self) -> _DIRECTOW {
908 _DIRECTOW { w: self }
909 }
910 #[doc = "Bit 4 - PLL0 clock enable"]
911 #[inline]
912 pub fn clken(&mut self) -> _CLKENW {
913 _CLKENW { w: self }
914 }
915 #[doc = "Bit 6 - Free running mode"]
916 #[inline]
917 pub fn frm(&mut self) -> _FRMW {
918 _FRMW { w: self }
919 }
920 #[doc = "Bit 11 - Block clock automatically during frequency change"]
921 #[inline]
922 pub fn autoblock(&mut self) -> _AUTOBLOCKW {
923 _AUTOBLOCKW { w: self }
924 }
925 #[doc = "Bits 24:28 - Clock source selection. All other values are reserved."]
926 #[inline]
927 pub fn clk_sel(&mut self) -> _CLK_SELW {
928 _CLK_SELW { w: self }
929 }
930}