lpc43xx/ethernet/dma_stat/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::DMA_STAT {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct TIR {
47    bits: bool,
48}
49impl TIR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct TPSR {
68    bits: bool,
69}
70impl TPSR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct TUR {
89    bits: bool,
90}
91impl TUR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bit(&self) -> bool {
95        self.bits
96    }
97    #[doc = r" Returns `true` if the bit is clear (0)"]
98    #[inline]
99    pub fn bit_is_clear(&self) -> bool {
100        !self.bit()
101    }
102    #[doc = r" Returns `true` if the bit is set (1)"]
103    #[inline]
104    pub fn bit_is_set(&self) -> bool {
105        self.bit()
106    }
107}
108#[doc = r" Value of the field"]
109pub struct TJTR {
110    bits: bool,
111}
112impl TJTR {
113    #[doc = r" Value of the field as raw bits"]
114    #[inline]
115    pub fn bit(&self) -> bool {
116        self.bits
117    }
118    #[doc = r" Returns `true` if the bit is clear (0)"]
119    #[inline]
120    pub fn bit_is_clear(&self) -> bool {
121        !self.bit()
122    }
123    #[doc = r" Returns `true` if the bit is set (1)"]
124    #[inline]
125    pub fn bit_is_set(&self) -> bool {
126        self.bit()
127    }
128}
129#[doc = r" Value of the field"]
130pub struct OVFR {
131    bits: bool,
132}
133impl OVFR {
134    #[doc = r" Value of the field as raw bits"]
135    #[inline]
136    pub fn bit(&self) -> bool {
137        self.bits
138    }
139    #[doc = r" Returns `true` if the bit is clear (0)"]
140    #[inline]
141    pub fn bit_is_clear(&self) -> bool {
142        !self.bit()
143    }
144    #[doc = r" Returns `true` if the bit is set (1)"]
145    #[inline]
146    pub fn bit_is_set(&self) -> bool {
147        self.bit()
148    }
149}
150#[doc = r" Value of the field"]
151pub struct UNFR {
152    bits: bool,
153}
154impl UNFR {
155    #[doc = r" Value of the field as raw bits"]
156    #[inline]
157    pub fn bit(&self) -> bool {
158        self.bits
159    }
160    #[doc = r" Returns `true` if the bit is clear (0)"]
161    #[inline]
162    pub fn bit_is_clear(&self) -> bool {
163        !self.bit()
164    }
165    #[doc = r" Returns `true` if the bit is set (1)"]
166    #[inline]
167    pub fn bit_is_set(&self) -> bool {
168        self.bit()
169    }
170}
171#[doc = r" Value of the field"]
172pub struct RIR {
173    bits: bool,
174}
175impl RIR {
176    #[doc = r" Value of the field as raw bits"]
177    #[inline]
178    pub fn bit(&self) -> bool {
179        self.bits
180    }
181    #[doc = r" Returns `true` if the bit is clear (0)"]
182    #[inline]
183    pub fn bit_is_clear(&self) -> bool {
184        !self.bit()
185    }
186    #[doc = r" Returns `true` if the bit is set (1)"]
187    #[inline]
188    pub fn bit_is_set(&self) -> bool {
189        self.bit()
190    }
191}
192#[doc = r" Value of the field"]
193pub struct RUR {
194    bits: bool,
195}
196impl RUR {
197    #[doc = r" Value of the field as raw bits"]
198    #[inline]
199    pub fn bit(&self) -> bool {
200        self.bits
201    }
202    #[doc = r" Returns `true` if the bit is clear (0)"]
203    #[inline]
204    pub fn bit_is_clear(&self) -> bool {
205        !self.bit()
206    }
207    #[doc = r" Returns `true` if the bit is set (1)"]
208    #[inline]
209    pub fn bit_is_set(&self) -> bool {
210        self.bit()
211    }
212}
213#[doc = r" Value of the field"]
214pub struct RPSR {
215    bits: bool,
216}
217impl RPSR {
218    #[doc = r" Value of the field as raw bits"]
219    #[inline]
220    pub fn bit(&self) -> bool {
221        self.bits
222    }
223    #[doc = r" Returns `true` if the bit is clear (0)"]
224    #[inline]
225    pub fn bit_is_clear(&self) -> bool {
226        !self.bit()
227    }
228    #[doc = r" Returns `true` if the bit is set (1)"]
229    #[inline]
230    pub fn bit_is_set(&self) -> bool {
231        self.bit()
232    }
233}
234#[doc = r" Value of the field"]
235pub struct RWTR {
236    bits: bool,
237}
238impl RWTR {
239    #[doc = r" Value of the field as raw bits"]
240    #[inline]
241    pub fn bit(&self) -> bool {
242        self.bits
243    }
244    #[doc = r" Returns `true` if the bit is clear (0)"]
245    #[inline]
246    pub fn bit_is_clear(&self) -> bool {
247        !self.bit()
248    }
249    #[doc = r" Returns `true` if the bit is set (1)"]
250    #[inline]
251    pub fn bit_is_set(&self) -> bool {
252        self.bit()
253    }
254}
255#[doc = r" Value of the field"]
256pub struct ETIR {
257    bits: bool,
258}
259impl ETIR {
260    #[doc = r" Value of the field as raw bits"]
261    #[inline]
262    pub fn bit(&self) -> bool {
263        self.bits
264    }
265    #[doc = r" Returns `true` if the bit is clear (0)"]
266    #[inline]
267    pub fn bit_is_clear(&self) -> bool {
268        !self.bit()
269    }
270    #[doc = r" Returns `true` if the bit is set (1)"]
271    #[inline]
272    pub fn bit_is_set(&self) -> bool {
273        self.bit()
274    }
275}
276#[doc = r" Value of the field"]
277pub struct FBIR {
278    bits: bool,
279}
280impl FBIR {
281    #[doc = r" Value of the field as raw bits"]
282    #[inline]
283    pub fn bit(&self) -> bool {
284        self.bits
285    }
286    #[doc = r" Returns `true` if the bit is clear (0)"]
287    #[inline]
288    pub fn bit_is_clear(&self) -> bool {
289        !self.bit()
290    }
291    #[doc = r" Returns `true` if the bit is set (1)"]
292    #[inline]
293    pub fn bit_is_set(&self) -> bool {
294        self.bit()
295    }
296}
297#[doc = r" Value of the field"]
298pub struct ERIR {
299    bits: bool,
300}
301impl ERIR {
302    #[doc = r" Value of the field as raw bits"]
303    #[inline]
304    pub fn bit(&self) -> bool {
305        self.bits
306    }
307    #[doc = r" Returns `true` if the bit is clear (0)"]
308    #[inline]
309    pub fn bit_is_clear(&self) -> bool {
310        !self.bit()
311    }
312    #[doc = r" Returns `true` if the bit is set (1)"]
313    #[inline]
314    pub fn bit_is_set(&self) -> bool {
315        self.bit()
316    }
317}
318#[doc = r" Value of the field"]
319pub struct AIER {
320    bits: bool,
321}
322impl AIER {
323    #[doc = r" Value of the field as raw bits"]
324    #[inline]
325    pub fn bit(&self) -> bool {
326        self.bits
327    }
328    #[doc = r" Returns `true` if the bit is clear (0)"]
329    #[inline]
330    pub fn bit_is_clear(&self) -> bool {
331        !self.bit()
332    }
333    #[doc = r" Returns `true` if the bit is set (1)"]
334    #[inline]
335    pub fn bit_is_set(&self) -> bool {
336        self.bit()
337    }
338}
339#[doc = r" Value of the field"]
340pub struct NISR {
341    bits: bool,
342}
343impl NISR {
344    #[doc = r" Value of the field as raw bits"]
345    #[inline]
346    pub fn bit(&self) -> bool {
347        self.bits
348    }
349    #[doc = r" Returns `true` if the bit is clear (0)"]
350    #[inline]
351    pub fn bit_is_clear(&self) -> bool {
352        !self.bit()
353    }
354    #[doc = r" Returns `true` if the bit is set (1)"]
355    #[inline]
356    pub fn bit_is_set(&self) -> bool {
357        self.bit()
358    }
359}
360#[doc = r" Value of the field"]
361pub struct RSR {
362    bits: u8,
363}
364impl RSR {
365    #[doc = r" Value of the field as raw bits"]
366    #[inline]
367    pub fn bits(&self) -> u8 {
368        self.bits
369    }
370}
371#[doc = r" Value of the field"]
372pub struct TSR {
373    bits: u8,
374}
375impl TSR {
376    #[doc = r" Value of the field as raw bits"]
377    #[inline]
378    pub fn bits(&self) -> u8 {
379        self.bits
380    }
381}
382#[doc = r" Value of the field"]
383pub struct EB1R {
384    bits: bool,
385}
386impl EB1R {
387    #[doc = r" Value of the field as raw bits"]
388    #[inline]
389    pub fn bit(&self) -> bool {
390        self.bits
391    }
392    #[doc = r" Returns `true` if the bit is clear (0)"]
393    #[inline]
394    pub fn bit_is_clear(&self) -> bool {
395        !self.bit()
396    }
397    #[doc = r" Returns `true` if the bit is set (1)"]
398    #[inline]
399    pub fn bit_is_set(&self) -> bool {
400        self.bit()
401    }
402}
403#[doc = r" Value of the field"]
404pub struct EB2R {
405    bits: bool,
406}
407impl EB2R {
408    #[doc = r" Value of the field as raw bits"]
409    #[inline]
410    pub fn bit(&self) -> bool {
411        self.bits
412    }
413    #[doc = r" Returns `true` if the bit is clear (0)"]
414    #[inline]
415    pub fn bit_is_clear(&self) -> bool {
416        !self.bit()
417    }
418    #[doc = r" Returns `true` if the bit is set (1)"]
419    #[inline]
420    pub fn bit_is_set(&self) -> bool {
421        self.bit()
422    }
423}
424#[doc = r" Value of the field"]
425pub struct EB3R {
426    bits: bool,
427}
428impl EB3R {
429    #[doc = r" Value of the field as raw bits"]
430    #[inline]
431    pub fn bit(&self) -> bool {
432        self.bits
433    }
434    #[doc = r" Returns `true` if the bit is clear (0)"]
435    #[inline]
436    pub fn bit_is_clear(&self) -> bool {
437        !self.bit()
438    }
439    #[doc = r" Returns `true` if the bit is set (1)"]
440    #[inline]
441    pub fn bit_is_set(&self) -> bool {
442        self.bit()
443    }
444}
445#[doc = r" Proxy"]
446pub struct _TIW<'a> {
447    w: &'a mut W,
448}
449impl<'a> _TIW<'a> {
450    #[doc = r" Sets the field bit"]
451    pub fn set_bit(self) -> &'a mut W {
452        self.bit(true)
453    }
454    #[doc = r" Clears the field bit"]
455    pub fn clear_bit(self) -> &'a mut W {
456        self.bit(false)
457    }
458    #[doc = r" Writes raw bits to the field"]
459    #[inline]
460    pub fn bit(self, value: bool) -> &'a mut W {
461        const MASK: bool = true;
462        const OFFSET: u8 = 0;
463        self.w.bits &= !((MASK as u32) << OFFSET);
464        self.w.bits |= ((value & MASK) as u32) << OFFSET;
465        self.w
466    }
467}
468#[doc = r" Proxy"]
469pub struct _TPSW<'a> {
470    w: &'a mut W,
471}
472impl<'a> _TPSW<'a> {
473    #[doc = r" Sets the field bit"]
474    pub fn set_bit(self) -> &'a mut W {
475        self.bit(true)
476    }
477    #[doc = r" Clears the field bit"]
478    pub fn clear_bit(self) -> &'a mut W {
479        self.bit(false)
480    }
481    #[doc = r" Writes raw bits to the field"]
482    #[inline]
483    pub fn bit(self, value: bool) -> &'a mut W {
484        const MASK: bool = true;
485        const OFFSET: u8 = 1;
486        self.w.bits &= !((MASK as u32) << OFFSET);
487        self.w.bits |= ((value & MASK) as u32) << OFFSET;
488        self.w
489    }
490}
491#[doc = r" Proxy"]
492pub struct _TUW<'a> {
493    w: &'a mut W,
494}
495impl<'a> _TUW<'a> {
496    #[doc = r" Sets the field bit"]
497    pub fn set_bit(self) -> &'a mut W {
498        self.bit(true)
499    }
500    #[doc = r" Clears the field bit"]
501    pub fn clear_bit(self) -> &'a mut W {
502        self.bit(false)
503    }
504    #[doc = r" Writes raw bits to the field"]
505    #[inline]
506    pub fn bit(self, value: bool) -> &'a mut W {
507        const MASK: bool = true;
508        const OFFSET: u8 = 2;
509        self.w.bits &= !((MASK as u32) << OFFSET);
510        self.w.bits |= ((value & MASK) as u32) << OFFSET;
511        self.w
512    }
513}
514#[doc = r" Proxy"]
515pub struct _TJTW<'a> {
516    w: &'a mut W,
517}
518impl<'a> _TJTW<'a> {
519    #[doc = r" Sets the field bit"]
520    pub fn set_bit(self) -> &'a mut W {
521        self.bit(true)
522    }
523    #[doc = r" Clears the field bit"]
524    pub fn clear_bit(self) -> &'a mut W {
525        self.bit(false)
526    }
527    #[doc = r" Writes raw bits to the field"]
528    #[inline]
529    pub fn bit(self, value: bool) -> &'a mut W {
530        const MASK: bool = true;
531        const OFFSET: u8 = 3;
532        self.w.bits &= !((MASK as u32) << OFFSET);
533        self.w.bits |= ((value & MASK) as u32) << OFFSET;
534        self.w
535    }
536}
537#[doc = r" Proxy"]
538pub struct _OVFW<'a> {
539    w: &'a mut W,
540}
541impl<'a> _OVFW<'a> {
542    #[doc = r" Sets the field bit"]
543    pub fn set_bit(self) -> &'a mut W {
544        self.bit(true)
545    }
546    #[doc = r" Clears the field bit"]
547    pub fn clear_bit(self) -> &'a mut W {
548        self.bit(false)
549    }
550    #[doc = r" Writes raw bits to the field"]
551    #[inline]
552    pub fn bit(self, value: bool) -> &'a mut W {
553        const MASK: bool = true;
554        const OFFSET: u8 = 4;
555        self.w.bits &= !((MASK as u32) << OFFSET);
556        self.w.bits |= ((value & MASK) as u32) << OFFSET;
557        self.w
558    }
559}
560#[doc = r" Proxy"]
561pub struct _UNFW<'a> {
562    w: &'a mut W,
563}
564impl<'a> _UNFW<'a> {
565    #[doc = r" Sets the field bit"]
566    pub fn set_bit(self) -> &'a mut W {
567        self.bit(true)
568    }
569    #[doc = r" Clears the field bit"]
570    pub fn clear_bit(self) -> &'a mut W {
571        self.bit(false)
572    }
573    #[doc = r" Writes raw bits to the field"]
574    #[inline]
575    pub fn bit(self, value: bool) -> &'a mut W {
576        const MASK: bool = true;
577        const OFFSET: u8 = 5;
578        self.w.bits &= !((MASK as u32) << OFFSET);
579        self.w.bits |= ((value & MASK) as u32) << OFFSET;
580        self.w
581    }
582}
583#[doc = r" Proxy"]
584pub struct _RIW<'a> {
585    w: &'a mut W,
586}
587impl<'a> _RIW<'a> {
588    #[doc = r" Sets the field bit"]
589    pub fn set_bit(self) -> &'a mut W {
590        self.bit(true)
591    }
592    #[doc = r" Clears the field bit"]
593    pub fn clear_bit(self) -> &'a mut W {
594        self.bit(false)
595    }
596    #[doc = r" Writes raw bits to the field"]
597    #[inline]
598    pub fn bit(self, value: bool) -> &'a mut W {
599        const MASK: bool = true;
600        const OFFSET: u8 = 6;
601        self.w.bits &= !((MASK as u32) << OFFSET);
602        self.w.bits |= ((value & MASK) as u32) << OFFSET;
603        self.w
604    }
605}
606#[doc = r" Proxy"]
607pub struct _RUW<'a> {
608    w: &'a mut W,
609}
610impl<'a> _RUW<'a> {
611    #[doc = r" Sets the field bit"]
612    pub fn set_bit(self) -> &'a mut W {
613        self.bit(true)
614    }
615    #[doc = r" Clears the field bit"]
616    pub fn clear_bit(self) -> &'a mut W {
617        self.bit(false)
618    }
619    #[doc = r" Writes raw bits to the field"]
620    #[inline]
621    pub fn bit(self, value: bool) -> &'a mut W {
622        const MASK: bool = true;
623        const OFFSET: u8 = 7;
624        self.w.bits &= !((MASK as u32) << OFFSET);
625        self.w.bits |= ((value & MASK) as u32) << OFFSET;
626        self.w
627    }
628}
629#[doc = r" Proxy"]
630pub struct _RPSW<'a> {
631    w: &'a mut W,
632}
633impl<'a> _RPSW<'a> {
634    #[doc = r" Sets the field bit"]
635    pub fn set_bit(self) -> &'a mut W {
636        self.bit(true)
637    }
638    #[doc = r" Clears the field bit"]
639    pub fn clear_bit(self) -> &'a mut W {
640        self.bit(false)
641    }
642    #[doc = r" Writes raw bits to the field"]
643    #[inline]
644    pub fn bit(self, value: bool) -> &'a mut W {
645        const MASK: bool = true;
646        const OFFSET: u8 = 8;
647        self.w.bits &= !((MASK as u32) << OFFSET);
648        self.w.bits |= ((value & MASK) as u32) << OFFSET;
649        self.w
650    }
651}
652#[doc = r" Proxy"]
653pub struct _RWTW<'a> {
654    w: &'a mut W,
655}
656impl<'a> _RWTW<'a> {
657    #[doc = r" Sets the field bit"]
658    pub fn set_bit(self) -> &'a mut W {
659        self.bit(true)
660    }
661    #[doc = r" Clears the field bit"]
662    pub fn clear_bit(self) -> &'a mut W {
663        self.bit(false)
664    }
665    #[doc = r" Writes raw bits to the field"]
666    #[inline]
667    pub fn bit(self, value: bool) -> &'a mut W {
668        const MASK: bool = true;
669        const OFFSET: u8 = 9;
670        self.w.bits &= !((MASK as u32) << OFFSET);
671        self.w.bits |= ((value & MASK) as u32) << OFFSET;
672        self.w
673    }
674}
675#[doc = r" Proxy"]
676pub struct _ETIW<'a> {
677    w: &'a mut W,
678}
679impl<'a> _ETIW<'a> {
680    #[doc = r" Sets the field bit"]
681    pub fn set_bit(self) -> &'a mut W {
682        self.bit(true)
683    }
684    #[doc = r" Clears the field bit"]
685    pub fn clear_bit(self) -> &'a mut W {
686        self.bit(false)
687    }
688    #[doc = r" Writes raw bits to the field"]
689    #[inline]
690    pub fn bit(self, value: bool) -> &'a mut W {
691        const MASK: bool = true;
692        const OFFSET: u8 = 10;
693        self.w.bits &= !((MASK as u32) << OFFSET);
694        self.w.bits |= ((value & MASK) as u32) << OFFSET;
695        self.w
696    }
697}
698#[doc = r" Proxy"]
699pub struct _FBIW<'a> {
700    w: &'a mut W,
701}
702impl<'a> _FBIW<'a> {
703    #[doc = r" Sets the field bit"]
704    pub fn set_bit(self) -> &'a mut W {
705        self.bit(true)
706    }
707    #[doc = r" Clears the field bit"]
708    pub fn clear_bit(self) -> &'a mut W {
709        self.bit(false)
710    }
711    #[doc = r" Writes raw bits to the field"]
712    #[inline]
713    pub fn bit(self, value: bool) -> &'a mut W {
714        const MASK: bool = true;
715        const OFFSET: u8 = 13;
716        self.w.bits &= !((MASK as u32) << OFFSET);
717        self.w.bits |= ((value & MASK) as u32) << OFFSET;
718        self.w
719    }
720}
721#[doc = r" Proxy"]
722pub struct _ERIW<'a> {
723    w: &'a mut W,
724}
725impl<'a> _ERIW<'a> {
726    #[doc = r" Sets the field bit"]
727    pub fn set_bit(self) -> &'a mut W {
728        self.bit(true)
729    }
730    #[doc = r" Clears the field bit"]
731    pub fn clear_bit(self) -> &'a mut W {
732        self.bit(false)
733    }
734    #[doc = r" Writes raw bits to the field"]
735    #[inline]
736    pub fn bit(self, value: bool) -> &'a mut W {
737        const MASK: bool = true;
738        const OFFSET: u8 = 14;
739        self.w.bits &= !((MASK as u32) << OFFSET);
740        self.w.bits |= ((value & MASK) as u32) << OFFSET;
741        self.w
742    }
743}
744#[doc = r" Proxy"]
745pub struct _AIEW<'a> {
746    w: &'a mut W,
747}
748impl<'a> _AIEW<'a> {
749    #[doc = r" Sets the field bit"]
750    pub fn set_bit(self) -> &'a mut W {
751        self.bit(true)
752    }
753    #[doc = r" Clears the field bit"]
754    pub fn clear_bit(self) -> &'a mut W {
755        self.bit(false)
756    }
757    #[doc = r" Writes raw bits to the field"]
758    #[inline]
759    pub fn bit(self, value: bool) -> &'a mut W {
760        const MASK: bool = true;
761        const OFFSET: u8 = 15;
762        self.w.bits &= !((MASK as u32) << OFFSET);
763        self.w.bits |= ((value & MASK) as u32) << OFFSET;
764        self.w
765    }
766}
767#[doc = r" Proxy"]
768pub struct _NISW<'a> {
769    w: &'a mut W,
770}
771impl<'a> _NISW<'a> {
772    #[doc = r" Sets the field bit"]
773    pub fn set_bit(self) -> &'a mut W {
774        self.bit(true)
775    }
776    #[doc = r" Clears the field bit"]
777    pub fn clear_bit(self) -> &'a mut W {
778        self.bit(false)
779    }
780    #[doc = r" Writes raw bits to the field"]
781    #[inline]
782    pub fn bit(self, value: bool) -> &'a mut W {
783        const MASK: bool = true;
784        const OFFSET: u8 = 16;
785        self.w.bits &= !((MASK as u32) << OFFSET);
786        self.w.bits |= ((value & MASK) as u32) << OFFSET;
787        self.w
788    }
789}
790#[doc = r" Proxy"]
791pub struct _RSW<'a> {
792    w: &'a mut W,
793}
794impl<'a> _RSW<'a> {
795    #[doc = r" Writes raw bits to the field"]
796    #[inline]
797    pub unsafe fn bits(self, value: u8) -> &'a mut W {
798        const MASK: u8 = 7;
799        const OFFSET: u8 = 17;
800        self.w.bits &= !((MASK as u32) << OFFSET);
801        self.w.bits |= ((value & MASK) as u32) << OFFSET;
802        self.w
803    }
804}
805#[doc = r" Proxy"]
806pub struct _TSW<'a> {
807    w: &'a mut W,
808}
809impl<'a> _TSW<'a> {
810    #[doc = r" Writes raw bits to the field"]
811    #[inline]
812    pub unsafe fn bits(self, value: u8) -> &'a mut W {
813        const MASK: u8 = 7;
814        const OFFSET: u8 = 20;
815        self.w.bits &= !((MASK as u32) << OFFSET);
816        self.w.bits |= ((value & MASK) as u32) << OFFSET;
817        self.w
818    }
819}
820#[doc = r" Proxy"]
821pub struct _EB1W<'a> {
822    w: &'a mut W,
823}
824impl<'a> _EB1W<'a> {
825    #[doc = r" Sets the field bit"]
826    pub fn set_bit(self) -> &'a mut W {
827        self.bit(true)
828    }
829    #[doc = r" Clears the field bit"]
830    pub fn clear_bit(self) -> &'a mut W {
831        self.bit(false)
832    }
833    #[doc = r" Writes raw bits to the field"]
834    #[inline]
835    pub fn bit(self, value: bool) -> &'a mut W {
836        const MASK: bool = true;
837        const OFFSET: u8 = 23;
838        self.w.bits &= !((MASK as u32) << OFFSET);
839        self.w.bits |= ((value & MASK) as u32) << OFFSET;
840        self.w
841    }
842}
843#[doc = r" Proxy"]
844pub struct _EB2W<'a> {
845    w: &'a mut W,
846}
847impl<'a> _EB2W<'a> {
848    #[doc = r" Sets the field bit"]
849    pub fn set_bit(self) -> &'a mut W {
850        self.bit(true)
851    }
852    #[doc = r" Clears the field bit"]
853    pub fn clear_bit(self) -> &'a mut W {
854        self.bit(false)
855    }
856    #[doc = r" Writes raw bits to the field"]
857    #[inline]
858    pub fn bit(self, value: bool) -> &'a mut W {
859        const MASK: bool = true;
860        const OFFSET: u8 = 24;
861        self.w.bits &= !((MASK as u32) << OFFSET);
862        self.w.bits |= ((value & MASK) as u32) << OFFSET;
863        self.w
864    }
865}
866#[doc = r" Proxy"]
867pub struct _EB3W<'a> {
868    w: &'a mut W,
869}
870impl<'a> _EB3W<'a> {
871    #[doc = r" Sets the field bit"]
872    pub fn set_bit(self) -> &'a mut W {
873        self.bit(true)
874    }
875    #[doc = r" Clears the field bit"]
876    pub fn clear_bit(self) -> &'a mut W {
877        self.bit(false)
878    }
879    #[doc = r" Writes raw bits to the field"]
880    #[inline]
881    pub fn bit(self, value: bool) -> &'a mut W {
882        const MASK: bool = true;
883        const OFFSET: u8 = 25;
884        self.w.bits &= !((MASK as u32) << OFFSET);
885        self.w.bits |= ((value & MASK) as u32) << OFFSET;
886        self.w
887    }
888}
889impl R {
890    #[doc = r" Value of the register as raw bits"]
891    #[inline]
892    pub fn bits(&self) -> u32 {
893        self.bits
894    }
895    #[doc = "Bit 0 - Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor."]
896    #[inline]
897    pub fn ti(&self) -> TIR {
898        let bits = {
899            const MASK: bool = true;
900            const OFFSET: u8 = 0;
901            ((self.bits >> OFFSET) & MASK as u32) != 0
902        };
903        TIR { bits }
904    }
905    #[doc = "Bit 1 - Transmit process stopped This bit is set when the transmission is stopped."]
906    #[inline]
907    pub fn tps(&self) -> TPSR {
908        let bits = {
909            const MASK: bool = true;
910            const OFFSET: u8 = 1;
911            ((self.bits >> OFFSET) & MASK as u32) != 0
912        };
913        TPSR { bits }
914    }
915    #[doc = "Bit 2 - Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command."]
916    #[inline]
917    pub fn tu(&self) -> TUR {
918        let bits = {
919            const MASK: bool = true;
920            const OFFSET: u8 = 2;
921            ((self.bits >> OFFSET) & MASK as u32) != 0
922        };
923        TUR { bits }
924    }
925    #[doc = "Bit 3 - Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert."]
926    #[inline]
927    pub fn tjt(&self) -> TJTR {
928        let bits = {
929            const MASK: bool = true;
930            const OFFSET: u8 = 3;
931            ((self.bits >> OFFSET) & MASK as u32) != 0
932        };
933        TJTR { bits }
934    }
935    #[doc = "Bit 4 - Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]."]
936    #[inline]
937    pub fn ovf(&self) -> OVFR {
938        let bits = {
939            const MASK: bool = true;
940            const OFFSET: u8 = 4;
941            ((self.bits >> OFFSET) & MASK as u32) != 0
942        };
943        OVFR { bits }
944    }
945    #[doc = "Bit 5 - Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set."]
946    #[inline]
947    pub fn unf(&self) -> UNFR {
948        let bits = {
949            const MASK: bool = true;
950            const OFFSET: u8 = 5;
951            ((self.bits >> OFFSET) & MASK as u32) != 0
952        };
953        UNFR { bits }
954    }
955    #[doc = "Bit 6 - Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state."]
956    #[inline]
957    pub fn ri(&self) -> RIR {
958        let bits = {
959            const MASK: bool = true;
960            const OFFSET: u8 = 6;
961            ((self.bits >> OFFSET) & MASK as u32) != 0
962        };
963        RIR { bits }
964    }
965    #[doc = "Bit 7 - Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA."]
966    #[inline]
967    pub fn ru(&self) -> RUR {
968        let bits = {
969            const MASK: bool = true;
970            const OFFSET: u8 = 7;
971            ((self.bits >> OFFSET) & MASK as u32) != 0
972        };
973        RUR { bits }
974    }
975    #[doc = "Bit 8 - Received process stopped This bit is asserted when the Receive Process enters the Stopped state."]
976    #[inline]
977    pub fn rps(&self) -> RPSR {
978        let bits = {
979            const MASK: bool = true;
980            const OFFSET: u8 = 8;
981            ((self.bits >> OFFSET) & MASK as u32) != 0
982        };
983        RPSR { bits }
984    }
985    #[doc = "Bit 9 - Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)."]
986    #[inline]
987    pub fn rwt(&self) -> RWTR {
988        let bits = {
989            const MASK: bool = true;
990            const OFFSET: u8 = 9;
991            ((self.bits >> OFFSET) & MASK as u32) != 0
992        };
993        RWTR { bits }
994    }
995    #[doc = "Bit 10 - Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO."]
996    #[inline]
997    pub fn eti(&self) -> ETIR {
998        let bits = {
999            const MASK: bool = true;
1000            const OFFSET: u8 = 10;
1001            ((self.bits >> OFFSET) & MASK as u32) != 0
1002        };
1003        ETIR { bits }
1004    }
1005    #[doc = "Bit 13 - Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses."]
1006    #[inline]
1007    pub fn fbi(&self) -> FBIR {
1008        let bits = {
1009            const MASK: bool = true;
1010            const OFFSET: u8 = 13;
1011            ((self.bits >> OFFSET) & MASK as u32) != 0
1012        };
1013        FBIR { bits }
1014    }
1015    #[doc = "Bit 14 - Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit."]
1016    #[inline]
1017    pub fn eri(&self) -> ERIR {
1018        let bits = {
1019            const MASK: bool = true;
1020            const OFFSET: u8 = 14;
1021            ((self.bits >> OFFSET) & MASK as u32) != 0
1022        };
1023        ERIR { bits }
1024    }
1025    #[doc = "Bit 15 - Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared."]
1026    #[inline]
1027    pub fn aie(&self) -> AIER {
1028        let bits = {
1029            const MASK: bool = true;
1030            const OFFSET: u8 = 15;
1031            ((self.bits >> OFFSET) & MASK as u32) != 0
1032        };
1033        AIER { bits }
1034    }
1035    #[doc = "Bit 16 - Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared."]
1036    #[inline]
1037    pub fn nis(&self) -> NISR {
1038        let bits = {
1039            const MASK: bool = true;
1040            const OFFSET: u8 = 16;
1041            ((self.bits >> OFFSET) & MASK as u32) != 0
1042        };
1043        NISR { bits }
1044    }
1045    #[doc = "Bits 17:19 - Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory."]
1046    #[inline]
1047    pub fn rs(&self) -> RSR {
1048        let bits = {
1049            const MASK: u8 = 7;
1050            const OFFSET: u8 = 17;
1051            ((self.bits >> OFFSET) & MASK as u32) as u8
1052        };
1053        RSR { bits }
1054    }
1055    #[doc = "Bits 20:22 - Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor."]
1056    #[inline]
1057    pub fn ts(&self) -> TSR {
1058        let bits = {
1059            const MASK: u8 = 7;
1060            const OFFSET: u8 = 20;
1061            ((self.bits >> OFFSET) & MASK as u32) as u8
1062        };
1063        TSR { bits }
1064    }
1065    #[doc = "Bit 23 - Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA."]
1066    #[inline]
1067    pub fn eb1(&self) -> EB1R {
1068        let bits = {
1069            const MASK: bool = true;
1070            const OFFSET: u8 = 23;
1071            ((self.bits >> OFFSET) & MASK as u32) != 0
1072        };
1073        EB1R { bits }
1074    }
1075    #[doc = "Bit 24 - Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer."]
1076    #[inline]
1077    pub fn eb2(&self) -> EB2R {
1078        let bits = {
1079            const MASK: bool = true;
1080            const OFFSET: u8 = 24;
1081            ((self.bits >> OFFSET) & MASK as u32) != 0
1082        };
1083        EB2R { bits }
1084    }
1085    #[doc = "Bit 25 - Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access."]
1086    #[inline]
1087    pub fn eb3(&self) -> EB3R {
1088        let bits = {
1089            const MASK: bool = true;
1090            const OFFSET: u8 = 25;
1091            ((self.bits >> OFFSET) & MASK as u32) != 0
1092        };
1093        EB3R { bits }
1094    }
1095}
1096impl W {
1097    #[doc = r" Reset value of the register"]
1098    #[inline]
1099    pub fn reset_value() -> W {
1100        W { bits: 0 }
1101    }
1102    #[doc = r" Writes raw bits to the register"]
1103    #[inline]
1104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1105        self.bits = bits;
1106        self
1107    }
1108    #[doc = "Bit 0 - Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor."]
1109    #[inline]
1110    pub fn ti(&mut self) -> _TIW {
1111        _TIW { w: self }
1112    }
1113    #[doc = "Bit 1 - Transmit process stopped This bit is set when the transmission is stopped."]
1114    #[inline]
1115    pub fn tps(&mut self) -> _TPSW {
1116        _TPSW { w: self }
1117    }
1118    #[doc = "Bit 2 - Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command."]
1119    #[inline]
1120    pub fn tu(&mut self) -> _TUW {
1121        _TUW { w: self }
1122    }
1123    #[doc = "Bit 3 - Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert."]
1124    #[inline]
1125    pub fn tjt(&mut self) -> _TJTW {
1126        _TJTW { w: self }
1127    }
1128    #[doc = "Bit 4 - Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]."]
1129    #[inline]
1130    pub fn ovf(&mut self) -> _OVFW {
1131        _OVFW { w: self }
1132    }
1133    #[doc = "Bit 5 - Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set."]
1134    #[inline]
1135    pub fn unf(&mut self) -> _UNFW {
1136        _UNFW { w: self }
1137    }
1138    #[doc = "Bit 6 - Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state."]
1139    #[inline]
1140    pub fn ri(&mut self) -> _RIW {
1141        _RIW { w: self }
1142    }
1143    #[doc = "Bit 7 - Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA."]
1144    #[inline]
1145    pub fn ru(&mut self) -> _RUW {
1146        _RUW { w: self }
1147    }
1148    #[doc = "Bit 8 - Received process stopped This bit is asserted when the Receive Process enters the Stopped state."]
1149    #[inline]
1150    pub fn rps(&mut self) -> _RPSW {
1151        _RPSW { w: self }
1152    }
1153    #[doc = "Bit 9 - Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)."]
1154    #[inline]
1155    pub fn rwt(&mut self) -> _RWTW {
1156        _RWTW { w: self }
1157    }
1158    #[doc = "Bit 10 - Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO."]
1159    #[inline]
1160    pub fn eti(&mut self) -> _ETIW {
1161        _ETIW { w: self }
1162    }
1163    #[doc = "Bit 13 - Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses."]
1164    #[inline]
1165    pub fn fbi(&mut self) -> _FBIW {
1166        _FBIW { w: self }
1167    }
1168    #[doc = "Bit 14 - Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit."]
1169    #[inline]
1170    pub fn eri(&mut self) -> _ERIW {
1171        _ERIW { w: self }
1172    }
1173    #[doc = "Bit 15 - Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared."]
1174    #[inline]
1175    pub fn aie(&mut self) -> _AIEW {
1176        _AIEW { w: self }
1177    }
1178    #[doc = "Bit 16 - Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared."]
1179    #[inline]
1180    pub fn nis(&mut self) -> _NISW {
1181        _NISW { w: self }
1182    }
1183    #[doc = "Bits 17:19 - Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory."]
1184    #[inline]
1185    pub fn rs(&mut self) -> _RSW {
1186        _RSW { w: self }
1187    }
1188    #[doc = "Bits 20:22 - Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor."]
1189    #[inline]
1190    pub fn ts(&mut self) -> _TSW {
1191        _TSW { w: self }
1192    }
1193    #[doc = "Bit 23 - Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA."]
1194    #[inline]
1195    pub fn eb1(&mut self) -> _EB1W {
1196        _EB1W { w: self }
1197    }
1198    #[doc = "Bit 24 - Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer."]
1199    #[inline]
1200    pub fn eb2(&mut self) -> _EB2W {
1201        _EB2W { w: self }
1202    }
1203    #[doc = "Bit 25 - Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access."]
1204    #[inline]
1205    pub fn eb3(&mut self) -> _EB3W {
1206        _EB3W { w: self }
1207    }
1208}
lpc43xx/ethernet/dma_stat/mod.rs

lpc43xx/ethernet/dma_stat/
mod.rs
