#![doc = "Peripheral access API for LPC176X5X microcontrollers (generated using svd2rust v0.14.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.14.0/svd2rust/#peripheral-api"]#![deny(missing_docs)]
#![deny(warnings)]
#![allow(non_camel_case_types)]
#![no_std]
#![feature(untagged_unions)]
extern crate bare_metal;
extern crate cortex_m;
#[cfg(feature = "rt")]
extern crate cortex_m_rt;
extern crate vcell;
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r" Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 5;
#[cfg(feature = "rt-no-cortex")]
extern "C" {
fn WDT();
fn TIMER0();
fn TIMER1();
fn TIMER2();
fn TIMER3();
fn UART0();
fn UART1();
fn UART2();
fn UART3();
fn PWM1();
fn I2C0();
fn I2C1();
fn I2C2();
fn SPI();
fn SSP0();
fn SSP1();
fn PLL0();
fn RTC();
fn EINT0();
fn EINT1();
fn EINT2();
fn EINT3();
fn ADC();
fn BOD();
fn USB();
fn CAN();
fn DMA();
fn I2S();
fn ENET();
fn RIT();
fn MCPWM();
fn QEI();
fn PLL1();
fn USBACTIVITY();
fn CANACTIVITY();
}
#[doc(hidden)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt-no-cortex")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 35] = [
Vector { _handler: WDT },
Vector { _handler: TIMER0 },
Vector { _handler: TIMER1 },
Vector { _handler: TIMER2 },
Vector { _handler: TIMER3 },
Vector { _handler: UART0 },
Vector { _handler: UART1 },
Vector { _handler: UART2 },
Vector { _handler: UART3 },
Vector { _handler: PWM1 },
Vector { _handler: I2C0 },
Vector { _handler: I2C1 },
Vector { _handler: I2C2 },
Vector { _handler: SPI },
Vector { _handler: SSP0 },
Vector { _handler: SSP1 },
Vector { _handler: PLL0 },
Vector { _handler: RTC },
Vector { _handler: EINT0 },
Vector { _handler: EINT1 },
Vector { _handler: EINT2 },
Vector { _handler: EINT3 },
Vector { _handler: ADC },
Vector { _handler: BOD },
Vector { _handler: USB },
Vector { _handler: CAN },
Vector { _handler: DMA },
Vector { _handler: I2S },
Vector { _handler: ENET },
Vector { _handler: RIT },
Vector { _handler: MCPWM },
Vector { _handler: QEI },
Vector { _handler: PLL1 },
Vector {
_handler: USBACTIVITY,
},
Vector {
_handler: CANACTIVITY,
},
];
#[doc = r" Enumeration of all the interrupts"]
pub enum Interrupt {
#[doc = "0 - WDT"]
WDT,
#[doc = "1 - TIMER0"]
TIMER0,
#[doc = "2 - TIMER1"]
TIMER1,
#[doc = "3 - TIMER2"]
TIMER2,
#[doc = "4 - TIMER3"]
TIMER3,
#[doc = "5 - UART0"]
UART0,
#[doc = "6 - UART1"]
UART1,
#[doc = "7 - UART2"]
UART2,
#[doc = "8 - UART3"]
UART3,
#[doc = "9 - PWM1"]
PWM1,
#[doc = "10 - I2C0"]
I2C0,
#[doc = "11 - I2C1"]
I2C1,
#[doc = "12 - I2C2"]
I2C2,
#[doc = "13 - SPI"]
SPI,
#[doc = "14 - SSP0"]
SSP0,
#[doc = "15 - SSP1"]
SSP1,
#[doc = "16 - PLL0"]
PLL0,
#[doc = "17 - RTC"]
RTC,
#[doc = "18 - EINT0"]
EINT0,
#[doc = "19 - EINT1"]
EINT1,
#[doc = "20 - EINT2"]
EINT2,
#[doc = "21 - EINT3"]
EINT3,
#[doc = "22 - ADC"]
ADC,
#[doc = "23 - BOD"]
BOD,
#[doc = "24 - USB"]
USB,
#[doc = "25 - CAN"]
CAN,
#[doc = "26 - DMA"]
DMA,
#[doc = "27 - I2S"]
I2S,
#[doc = "28 - ENET"]
ENET,
#[doc = "29 - RIT"]
RIT,
#[doc = "30 - MCPWM"]
MCPWM,
#[doc = "31 - QEI"]
QEI,
#[doc = "32 - PLL1"]
PLL1,
#[doc = "33 - USBActivity"]
USBACTIVITY,
#[doc = "34 - CANActivity"]
CANACTIVITY,
}
unsafe impl ::bare_metal::Nr for Interrupt {
#[inline]
fn nr(&self) -> u8 {
match *self {
Interrupt::WDT => 0,
Interrupt::TIMER0 => 1,
Interrupt::TIMER1 => 2,
Interrupt::TIMER2 => 3,
Interrupt::TIMER3 => 4,
Interrupt::UART0 => 5,
Interrupt::UART1 => 6,
Interrupt::UART2 => 7,
Interrupt::UART3 => 8,
Interrupt::PWM1 => 9,
Interrupt::I2C0 => 10,
Interrupt::I2C1 => 11,
Interrupt::I2C2 => 12,
Interrupt::SPI => 13,
Interrupt::SSP0 => 14,
Interrupt::SSP1 => 15,
Interrupt::PLL0 => 16,
Interrupt::RTC => 17,
Interrupt::EINT0 => 18,
Interrupt::EINT1 => 19,
Interrupt::EINT2 => 20,
Interrupt::EINT3 => 21,
Interrupt::ADC => 22,
Interrupt::BOD => 23,
Interrupt::USB => 24,
Interrupt::CAN => 25,
Interrupt::DMA => 26,
Interrupt::I2S => 27,
Interrupt::ENET => 28,
Interrupt::RIT => 29,
Interrupt::MCPWM => 30,
Interrupt::QEI => 31,
Interrupt::PLL1 => 32,
Interrupt::USBACTIVITY => 33,
Interrupt::CANACTIVITY => 34,
}
}
}
#[cfg(feature = "rt-no-cortex")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[doc = "Watchdog Timer (WDT)"]
pub struct WDT {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for WDT {}
impl WDT {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const wdt::RegisterBlock {
0x4000_0000 as *const _
}
}
impl Deref for WDT {
type Target = wdt::RegisterBlock;
fn deref(&self) -> &wdt::RegisterBlock {
unsafe { &*WDT::ptr() }
}
}
#[doc = "Watchdog Timer (WDT)"]
pub mod wdt {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer."]
pub mod_: MOD,
#[doc = "0x04 - Watchdog timer constant register. The value in this register determines the time-out value."]
pub tc: TC,
#[doc = "0x08 - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."]
pub feed: FEED,
#[doc = "0x0c - Watchdog timer value register. This register reads out the current value of the Watchdog timer."]
pub tv: TV,
#[doc = "0x10 - Watchdog clock select register."]
pub clksel: CLKSEL,
}
#[doc = "Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer."]
pub struct MOD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer."]
pub mod mod_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MOD {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `WDEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WDENR {
#[doc = "The watchdog timer is stopped."]
STOP,
#[doc = "The watchdog timer is running."]
RUN,
}
impl WDENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WDENR::STOP => false,
WDENR::RUN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WDENR {
match value {
false => WDENR::STOP,
true => WDENR::RUN,
}
}
#[doc = "Checks if the value of the field is `STOP`"]
#[inline]
pub fn is_stop(&self) -> bool {
*self == WDENR::STOP
}
#[doc = "Checks if the value of the field is `RUN`"]
#[inline]
pub fn is_run(&self) -> bool {
*self == WDENR::RUN
}
}
#[doc = "Possible values of the field `WDRESET`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WDRESETR {
#[doc = "A watchdog timeout will not cause a chip reset."]
NORESET,
#[doc = "A watchdog timeout will cause a chip reset."]
RESET,
}
impl WDRESETR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WDRESETR::NORESET => false,
WDRESETR::RESET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WDRESETR {
match value {
false => WDRESETR::NORESET,
true => WDRESETR::RESET,
}
}
#[doc = "Checks if the value of the field is `NORESET`"]
#[inline]
pub fn is_noreset(&self) -> bool {
*self == WDRESETR::NORESET
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == WDRESETR::RESET
}
}
#[doc = r" Value of the field"]
pub struct WDTOFR {
bits: bool,
}
impl WDTOFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WDINTR {
bits: bool,
}
impl WDINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `WDEN`"]
pub enum WDENW {
#[doc = "The watchdog timer is stopped."]
STOP,
#[doc = "The watchdog timer is running."]
RUN,
}
impl WDENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WDENW::STOP => false,
WDENW::RUN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WDENW<'a> {
w: &'a mut W,
}
impl<'a> _WDENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WDENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The watchdog timer is stopped."]
#[inline]
pub fn stop(self) -> &'a mut W {
self.variant(WDENW::STOP)
}
#[doc = "The watchdog timer is running."]
#[inline]
pub fn run(self) -> &'a mut W {
self.variant(WDENW::RUN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WDRESET`"]
pub enum WDRESETW {
#[doc = "A watchdog timeout will not cause a chip reset."]
NORESET,
#[doc = "A watchdog timeout will cause a chip reset."]
RESET,
}
impl WDRESETW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WDRESETW::NORESET => false,
WDRESETW::RESET => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WDRESETW<'a> {
w: &'a mut W,
}
impl<'a> _WDRESETW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WDRESETW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A watchdog timeout will not cause a chip reset."]
#[inline]
pub fn noreset(self) -> &'a mut W {
self.variant(WDRESETW::NORESET)
}
#[doc = "A watchdog timeout will cause a chip reset."]
#[inline]
pub fn reset(self) -> &'a mut W {
self.variant(WDRESETW::RESET)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WDTOFW<'a> {
w: &'a mut W,
}
impl<'a> _WDTOFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WDINTW<'a> {
w: &'a mut W,
}
impl<'a> _WDINTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Watchdog enable bit. This bit is Set Only."]
#[inline]
pub fn wden(&self) -> WDENR {
WDENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Watchdog reset enable bit. This bit is Set Only. See Table 652."]
#[inline]
pub fn wdreset(&self) -> WDRESETR {
WDRESETR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, cleared by software."]
#[inline]
pub fn wdtof(&self) -> WDTOFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WDTOFR { bits }
}
#[doc = "Bit 3 - Watchdog interrupt flag. Cleared by software."]
#[inline]
pub fn wdint(&self) -> WDINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WDINTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Watchdog enable bit. This bit is Set Only."]
#[inline]
pub fn wden(&mut self) -> _WDENW {
_WDENW { w: self }
}
#[doc = "Bit 1 - Watchdog reset enable bit. This bit is Set Only. See Table 652."]
#[inline]
pub fn wdreset(&mut self) -> _WDRESETW {
_WDRESETW { w: self }
}
#[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, cleared by software."]
#[inline]
pub fn wdtof(&mut self) -> _WDTOFW {
_WDTOFW { w: self }
}
#[doc = "Bit 3 - Watchdog interrupt flag. Cleared by software."]
#[inline]
pub fn wdint(&mut self) -> _WDINTW {
_WDINTW { w: self }
}
}
}
#[doc = "Watchdog timer constant register. The value in this register determines the time-out value."]
pub struct TC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Watchdog timer constant register. The value in this register determines the time-out value."]
pub mod tc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct COUNTR {
bits: u32,
}
impl COUNTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _COUNTW<'a> {
w: &'a mut W,
}
impl<'a> _COUNTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Watchdog time-out interval."]
#[inline]
pub fn count(&self) -> COUNTR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
COUNTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Watchdog time-out interval."]
#[inline]
pub fn count(&mut self) -> _COUNTW {
_COUNTW { w: self }
}
}
}
#[doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."]
pub struct FEED {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."]
pub mod feed {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FEED {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _FEEDW<'a> {
w: &'a mut W,
}
impl<'a> _FEEDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Feed value should be 0xAA followed by 0x55."]
#[inline]
pub fn feed(&mut self) -> _FEEDW {
_FEEDW { w: self }
}
}
}
#[doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer."]
pub struct TV {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer."]
pub mod tv {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::TV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct COUNTR {
bits: u32,
}
impl COUNTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Counter timer value."]
#[inline]
pub fn count(&self) -> COUNTR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
COUNTR { bits }
}
}
}
#[doc = "Watchdog clock select register."]
pub struct CLKSEL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Watchdog clock select register."]
pub mod clksel {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLKSEL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKSELR {
#[doc = "IRC"]
IRC,
#[doc = "Peripheral clock"]
PCLK,
#[doc = "RTC oscillator"]
RTCOSC,
}
impl CLKSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CLKSELR::IRC => 0,
CLKSELR::PCLK => 0x01,
CLKSELR::RTCOSC => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CLKSELR {
match value {
0 => CLKSELR::IRC,
1 => CLKSELR::PCLK,
2 => CLKSELR::RTCOSC,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `IRC`"]
#[inline]
pub fn is_irc(&self) -> bool {
*self == CLKSELR::IRC
}
#[doc = "Checks if the value of the field is `PCLK`"]
#[inline]
pub fn is_pclk(&self) -> bool {
*self == CLKSELR::PCLK
}
#[doc = "Checks if the value of the field is `RTCOSC`"]
#[inline]
pub fn is_rtcosc(&self) -> bool {
*self == CLKSELR::RTCOSC
}
}
#[doc = "Possible values of the field `LOCK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LOCKR {
#[doc = "This bit is set to 0 on any reset. It cannot be cleared by software."]
UNLOCKED,
#[doc = "Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register\r\n\t\t\t\t\t\t\t\t\t\tcannot be modified."]
LOCKED,
}
impl LOCKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LOCKR::UNLOCKED => false,
LOCKR::LOCKED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LOCKR {
match value {
false => LOCKR::UNLOCKED,
true => LOCKR::LOCKED,
}
}
#[doc = "Checks if the value of the field is `UNLOCKED`"]
#[inline]
pub fn is_unlocked(&self) -> bool {
*self == LOCKR::UNLOCKED
}
#[doc = "Checks if the value of the field is `LOCKED`"]
#[inline]
pub fn is_locked(&self) -> bool {
*self == LOCKR::LOCKED
}
}
#[doc = "Values that can be written to the field `CLKSEL`"]
pub enum CLKSELW {
#[doc = "IRC"]
IRC,
#[doc = "Peripheral clock"]
PCLK,
#[doc = "RTC oscillator"]
RTCOSC,
}
impl CLKSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CLKSELW::IRC => 0,
CLKSELW::PCLK => 1,
CLKSELW::RTCOSC => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _CLKSELW<'a> {
w: &'a mut W,
}
impl<'a> _CLKSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLKSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "IRC"]
#[inline]
pub fn irc(self) -> &'a mut W {
self.variant(CLKSELW::IRC)
}
#[doc = "Peripheral clock"]
#[inline]
pub fn pclk(self) -> &'a mut W {
self.variant(CLKSELW::PCLK)
}
#[doc = "RTC oscillator"]
#[inline]
pub fn rtcosc(self) -> &'a mut W {
self.variant(CLKSELW::RTCOSC)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LOCK`"]
pub enum LOCKW {
#[doc = "This bit is set to 0 on any reset. It cannot be cleared by software."]
UNLOCKED,
#[doc = "Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register\r\n\t\t\t\t\t\t\t\t\t\tcannot be modified."]
LOCKED,
}
impl LOCKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LOCKW::UNLOCKED => false,
LOCKW::LOCKED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LOCKW<'a> {
w: &'a mut W,
}
impl<'a> _LOCKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LOCKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This bit is set to 0 on any reset. It cannot be cleared by software."]
#[inline]
pub fn unlocked(self) -> &'a mut W {
self.variant(LOCKW::UNLOCKED)
}
#[doc = "Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified."]
#[inline]
pub fn locked(self) -> &'a mut W {
self.variant(LOCKW::LOCKED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Selects source of WDT clock"]
#[inline]
pub fn clksel(&self) -> CLKSELR {
CLKSELR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 31 - If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0."]
#[inline]
pub fn lock(&self) -> LOCKR {
LOCKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Selects source of WDT clock"]
#[inline]
pub fn clksel(&mut self) -> _CLKSELW {
_CLKSELW { w: self }
}
#[doc = "Bit 31 - If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0."]
#[inline]
pub fn lock(&mut self) -> _LOCKW {
_LOCKW { w: self }
}
}
}
}
#[doc = "Timer0/1/2/3"]
pub struct TIMER0 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMER0 {}
impl TIMER0 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const timer0::RegisterBlock {
0x4000_4000 as *const _
}
}
impl Deref for TIMER0 {
type Target = timer0::RegisterBlock;
fn deref(&self) -> &timer0::RegisterBlock {
unsafe { &*TIMER0::ptr() }
}
}
#[doc = "Timer0/1/2/3"]
pub mod timer0 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
pub ir: IR,
#[doc = "0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
pub tcr: TCR,
#[doc = "0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub tc: TC,
#[doc = "0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
pub pr: PR,
#[doc = "0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
pub pc: PC,
#[doc = "0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
pub mcr: MCR,
#[doc = "0x18 - Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
pub mr: [MR; 4],
#[doc = "0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
pub ccr: CCR,
#[doc = "0x2c - Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
pub cr: [CR; 2],
_reserved9: [u8; 8usize],
#[doc = "0x3c - External Match Register. The EMR controls the external match pins."]
pub emr: EMR,
_reserved10: [u8; 48usize],
#[doc = "0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub ctcr: CTCR,
}
#[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
pub struct IR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
pub mod ir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MR0INTR {
bits: bool,
}
impl MR0INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MR1INTR {
bits: bool,
}
impl MR1INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MR2INTR {
bits: bool,
}
impl MR2INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MR3INTR {
bits: bool,
}
impl MR3INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CR0INTR {
bits: bool,
}
impl CR0INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CR1INTR {
bits: bool,
}
impl CR1INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _MR0INTW<'a> {
w: &'a mut W,
}
impl<'a> _MR0INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MR1INTW<'a> {
w: &'a mut W,
}
impl<'a> _MR1INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MR2INTW<'a> {
w: &'a mut W,
}
impl<'a> _MR2INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MR3INTW<'a> {
w: &'a mut W,
}
impl<'a> _MR3INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CR0INTW<'a> {
w: &'a mut W,
}
impl<'a> _CR0INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CR1INTW<'a> {
w: &'a mut W,
}
impl<'a> _CR1INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt flag for match channel 0."]
#[inline]
pub fn mr0int(&self) -> MR0INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MR0INTR { bits }
}
#[doc = "Bit 1 - Interrupt flag for match channel 1."]
#[inline]
pub fn mr1int(&self) -> MR1INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MR1INTR { bits }
}
#[doc = "Bit 2 - Interrupt flag for match channel 2."]
#[inline]
pub fn mr2int(&self) -> MR2INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MR2INTR { bits }
}
#[doc = "Bit 3 - Interrupt flag for match channel 3."]
#[inline]
pub fn mr3int(&self) -> MR3INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MR3INTR { bits }
}
#[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
#[inline]
pub fn cr0int(&self) -> CR0INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CR0INTR { bits }
}
#[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
#[inline]
pub fn cr1int(&self) -> CR1INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CR1INTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt flag for match channel 0."]
#[inline]
pub fn mr0int(&mut self) -> _MR0INTW {
_MR0INTW { w: self }
}
#[doc = "Bit 1 - Interrupt flag for match channel 1."]
#[inline]
pub fn mr1int(&mut self) -> _MR1INTW {
_MR1INTW { w: self }
}
#[doc = "Bit 2 - Interrupt flag for match channel 2."]
#[inline]
pub fn mr2int(&mut self) -> _MR2INTW {
_MR2INTW { w: self }
}
#[doc = "Bit 3 - Interrupt flag for match channel 3."]
#[inline]
pub fn mr3int(&mut self) -> _MR3INTW {
_MR3INTW { w: self }
}
#[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
#[inline]
pub fn cr0int(&mut self) -> _CR0INTW {
_CR0INTW { w: self }
}
#[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
#[inline]
pub fn cr1int(&mut self) -> _CR1INTW {
_CR1INTW { w: self }
}
}
}
#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
pub struct TCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
pub mod tcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CENR {
bits: bool,
}
impl CENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CRSTR {
bits: bool,
}
impl CRSTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _CENW<'a> {
w: &'a mut W,
}
impl<'a> _CENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CRSTW<'a> {
w: &'a mut W,
}
impl<'a> _CRSTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline]
pub fn cen(&self) -> CENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CENR { bits }
}
#[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] is returned to zero."]
#[inline]
pub fn crst(&self) -> CRSTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CRSTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline]
pub fn cen(&mut self) -> _CENW {
_CENW { w: self }
}
#[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] is returned to zero."]
#[inline]
pub fn crst(&mut self) -> _CRSTW {
_CRSTW { w: self }
}
}
}
#[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub struct TC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub mod tc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TCR {
bits: u32,
}
impl TCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TCW<'a> {
w: &'a mut W,
}
impl<'a> _TCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Timer counter value."]
#[inline]
pub fn tc(&self) -> TCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
TCR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Timer counter value."]
#[inline]
pub fn tc(&mut self) -> _TCW {
_TCW { w: self }
}
}
}
#[doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
pub struct PR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
pub mod pr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PMR {
bits: u32,
}
impl PMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PMW<'a> {
w: &'a mut W,
}
impl<'a> _PMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Prescale counter maximum value."]
#[inline]
pub fn pm(&self) -> PMR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Prescale counter maximum value."]
#[inline]
pub fn pm(&mut self) -> _PMW {
_PMW { w: self }
}
}
}
#[doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
pub struct PC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
pub mod pc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PCR {
bits: u32,
}
impl PCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PCW<'a> {
w: &'a mut W,
}
impl<'a> _PCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Prescale counter value."]
#[inline]
pub fn pc(&self) -> PCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PCR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Prescale counter value."]
#[inline]
pub fn pc(&mut self) -> _PCW {
_PCW { w: self }
}
}
}
#[doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
pub struct MCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
pub mod mcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `MR0I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR0IR {
#[doc = "Interrupt is generated when MR0 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "Interrupt is disabled"]
INTERRUPT_IS_DISABLE,
}
impl MR0IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR0IR::INTERRUPT_IS_GENERAT => true,
MR0IR::INTERRUPT_IS_DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR0IR {
match value {
true => MR0IR::INTERRUPT_IS_GENERAT,
false => MR0IR::INTERRUPT_IS_DISABLE,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_GENERAT`"]
#[inline]
pub fn is_interrupt_is_generat(&self) -> bool {
*self == MR0IR::INTERRUPT_IS_GENERAT
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_DISABLE`"]
#[inline]
pub fn is_interrupt_is_disable(&self) -> bool {
*self == MR0IR::INTERRUPT_IS_DISABLE
}
}
#[doc = "Possible values of the field `MR0R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR0RR {
#[doc = "TC will be reset if MR0 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR0RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR0RR::TC_WILL_BE_RESET_IF_ => true,
MR0RR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR0RR {
match value {
true => MR0RR::TC_WILL_BE_RESET_IF_,
false => MR0RR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_WILL_BE_RESET_IF_`"]
#[inline]
pub fn is_tc_will_be_reset_if_(&self) -> bool {
*self == MR0RR::TC_WILL_BE_RESET_IF_
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR0RR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR0S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR0SR {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR0 matches the TC."]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR0SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR0SR::TC_AND_PC_WILL_BE_ST => true,
MR0SR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR0SR {
match value {
true => MR0SR::TC_AND_PC_WILL_BE_ST,
false => MR0SR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_AND_PC_WILL_BE_ST`"]
#[inline]
pub fn is_tc_and_pc_will_be_st(&self) -> bool {
*self == MR0SR::TC_AND_PC_WILL_BE_ST
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR0SR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR1I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR1IR {
#[doc = "Interrupt is generated when MR1 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "Interrupt is disabled."]
INTERRUPT_IS_DISABLE,
}
impl MR1IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR1IR::INTERRUPT_IS_GENERAT => true,
MR1IR::INTERRUPT_IS_DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR1IR {
match value {
true => MR1IR::INTERRUPT_IS_GENERAT,
false => MR1IR::INTERRUPT_IS_DISABLE,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_GENERAT`"]
#[inline]
pub fn is_interrupt_is_generat(&self) -> bool {
*self == MR1IR::INTERRUPT_IS_GENERAT
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_DISABLE`"]
#[inline]
pub fn is_interrupt_is_disable(&self) -> bool {
*self == MR1IR::INTERRUPT_IS_DISABLE
}
}
#[doc = "Possible values of the field `MR1R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR1RR {
#[doc = "TC will be reset if MR1 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR1RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR1RR::TC_WILL_BE_RESET_IF_ => true,
MR1RR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR1RR {
match value {
true => MR1RR::TC_WILL_BE_RESET_IF_,
false => MR1RR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_WILL_BE_RESET_IF_`"]
#[inline]
pub fn is_tc_will_be_reset_if_(&self) -> bool {
*self == MR1RR::TC_WILL_BE_RESET_IF_
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR1RR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR1S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR1SR {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR1 matches the TC."]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR1SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR1SR::TC_AND_PC_WILL_BE_ST => true,
MR1SR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR1SR {
match value {
true => MR1SR::TC_AND_PC_WILL_BE_ST,
false => MR1SR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_AND_PC_WILL_BE_ST`"]
#[inline]
pub fn is_tc_and_pc_will_be_st(&self) -> bool {
*self == MR1SR::TC_AND_PC_WILL_BE_ST
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR1SR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR2I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR2IR {
#[doc = "Interrupt is generated when MR2 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "Interrupt is disabled"]
INTERRUPT_IS_DISABLE,
}
impl MR2IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR2IR::INTERRUPT_IS_GENERAT => true,
MR2IR::INTERRUPT_IS_DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR2IR {
match value {
true => MR2IR::INTERRUPT_IS_GENERAT,
false => MR2IR::INTERRUPT_IS_DISABLE,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_GENERAT`"]
#[inline]
pub fn is_interrupt_is_generat(&self) -> bool {
*self == MR2IR::INTERRUPT_IS_GENERAT
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_DISABLE`"]
#[inline]
pub fn is_interrupt_is_disable(&self) -> bool {
*self == MR2IR::INTERRUPT_IS_DISABLE
}
}
#[doc = "Possible values of the field `MR2R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR2RR {
#[doc = "TC will be reset if MR2 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR2RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR2RR::TC_WILL_BE_RESET_IF_ => true,
MR2RR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR2RR {
match value {
true => MR2RR::TC_WILL_BE_RESET_IF_,
false => MR2RR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_WILL_BE_RESET_IF_`"]
#[inline]
pub fn is_tc_will_be_reset_if_(&self) -> bool {
*self == MR2RR::TC_WILL_BE_RESET_IF_
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR2RR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR2S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR2SR {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR2 matches the TC"]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR2SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR2SR::TC_AND_PC_WILL_BE_ST => true,
MR2SR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR2SR {
match value {
true => MR2SR::TC_AND_PC_WILL_BE_ST,
false => MR2SR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_AND_PC_WILL_BE_ST`"]
#[inline]
pub fn is_tc_and_pc_will_be_st(&self) -> bool {
*self == MR2SR::TC_AND_PC_WILL_BE_ST
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR2SR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR3I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR3IR {
#[doc = "Interrupt is generated when MR3 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "This interrupt is disabled"]
THIS_INTERRUPT_IS_DI,
}
impl MR3IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR3IR::INTERRUPT_IS_GENERAT => true,
MR3IR::THIS_INTERRUPT_IS_DI => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR3IR {
match value {
true => MR3IR::INTERRUPT_IS_GENERAT,
false => MR3IR::THIS_INTERRUPT_IS_DI,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_IS_GENERAT`"]
#[inline]
pub fn is_interrupt_is_generat(&self) -> bool {
*self == MR3IR::INTERRUPT_IS_GENERAT
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_IS_DI`"]
#[inline]
pub fn is_this_interrupt_is_di(&self) -> bool {
*self == MR3IR::THIS_INTERRUPT_IS_DI
}
}
#[doc = "Possible values of the field `MR3R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR3RR {
#[doc = "TC will be reset if MR3 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR3RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR3RR::TC_WILL_BE_RESET_IF_ => true,
MR3RR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR3RR {
match value {
true => MR3RR::TC_WILL_BE_RESET_IF_,
false => MR3RR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_WILL_BE_RESET_IF_`"]
#[inline]
pub fn is_tc_will_be_reset_if_(&self) -> bool {
*self == MR3RR::TC_WILL_BE_RESET_IF_
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR3RR::FEATURE_DISABLED_
}
}
#[doc = "Possible values of the field `MR3S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MR3SR {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR3 matches the TC."]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR3SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MR3SR::TC_AND_PC_WILL_BE_ST => true,
MR3SR::FEATURE_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MR3SR {
match value {
true => MR3SR::TC_AND_PC_WILL_BE_ST,
false => MR3SR::FEATURE_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TC_AND_PC_WILL_BE_ST`"]
#[inline]
pub fn is_tc_and_pc_will_be_st(&self) -> bool {
*self == MR3SR::TC_AND_PC_WILL_BE_ST
}
#[doc = "Checks if the value of the field is `FEATURE_DISABLED_`"]
#[inline]
pub fn is_feature_disabled_(&self) -> bool {
*self == MR3SR::FEATURE_DISABLED_
}
}
#[doc = "Values that can be written to the field `MR0I`"]
pub enum MR0IW {
#[doc = "Interrupt is generated when MR0 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "Interrupt is disabled"]
INTERRUPT_IS_DISABLE,
}
impl MR0IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR0IW::INTERRUPT_IS_GENERAT => true,
MR0IW::INTERRUPT_IS_DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR0IW<'a> {
w: &'a mut W,
}
impl<'a> _MR0IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR0IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt is generated when MR0 matches the value in the TC."]
#[inline]
pub fn interrupt_is_generat(self) -> &'a mut W {
self.variant(MR0IW::INTERRUPT_IS_GENERAT)
}
#[doc = "Interrupt is disabled"]
#[inline]
pub fn interrupt_is_disable(self) -> &'a mut W {
self.variant(MR0IW::INTERRUPT_IS_DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR0R`"]
pub enum MR0RW {
#[doc = "TC will be reset if MR0 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR0RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR0RW::TC_WILL_BE_RESET_IF_ => true,
MR0RW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR0RW<'a> {
w: &'a mut W,
}
impl<'a> _MR0RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR0RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC will be reset if MR0 matches it."]
#[inline]
pub fn tc_will_be_reset_if_(self) -> &'a mut W {
self.variant(MR0RW::TC_WILL_BE_RESET_IF_)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR0RW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR0S`"]
pub enum MR0SW {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR0 matches the TC."]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR0SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR0SW::TC_AND_PC_WILL_BE_ST => true,
MR0SW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR0SW<'a> {
w: &'a mut W,
}
impl<'a> _MR0SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR0SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR0 matches the TC."]
#[inline]
pub fn tc_and_pc_will_be_st(self) -> &'a mut W {
self.variant(MR0SW::TC_AND_PC_WILL_BE_ST)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR0SW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR1I`"]
pub enum MR1IW {
#[doc = "Interrupt is generated when MR1 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "Interrupt is disabled."]
INTERRUPT_IS_DISABLE,
}
impl MR1IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR1IW::INTERRUPT_IS_GENERAT => true,
MR1IW::INTERRUPT_IS_DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR1IW<'a> {
w: &'a mut W,
}
impl<'a> _MR1IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR1IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt is generated when MR1 matches the value in the TC."]
#[inline]
pub fn interrupt_is_generat(self) -> &'a mut W {
self.variant(MR1IW::INTERRUPT_IS_GENERAT)
}
#[doc = "Interrupt is disabled."]
#[inline]
pub fn interrupt_is_disable(self) -> &'a mut W {
self.variant(MR1IW::INTERRUPT_IS_DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR1R`"]
pub enum MR1RW {
#[doc = "TC will be reset if MR1 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR1RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR1RW::TC_WILL_BE_RESET_IF_ => true,
MR1RW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR1RW<'a> {
w: &'a mut W,
}
impl<'a> _MR1RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR1RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC will be reset if MR1 matches it."]
#[inline]
pub fn tc_will_be_reset_if_(self) -> &'a mut W {
self.variant(MR1RW::TC_WILL_BE_RESET_IF_)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR1RW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR1S`"]
pub enum MR1SW {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR1 matches the TC."]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR1SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR1SW::TC_AND_PC_WILL_BE_ST => true,
MR1SW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR1SW<'a> {
w: &'a mut W,
}
impl<'a> _MR1SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR1SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR1 matches the TC."]
#[inline]
pub fn tc_and_pc_will_be_st(self) -> &'a mut W {
self.variant(MR1SW::TC_AND_PC_WILL_BE_ST)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR1SW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR2I`"]
pub enum MR2IW {
#[doc = "Interrupt is generated when MR2 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "Interrupt is disabled"]
INTERRUPT_IS_DISABLE,
}
impl MR2IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR2IW::INTERRUPT_IS_GENERAT => true,
MR2IW::INTERRUPT_IS_DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR2IW<'a> {
w: &'a mut W,
}
impl<'a> _MR2IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR2IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt is generated when MR2 matches the value in the TC."]
#[inline]
pub fn interrupt_is_generat(self) -> &'a mut W {
self.variant(MR2IW::INTERRUPT_IS_GENERAT)
}
#[doc = "Interrupt is disabled"]
#[inline]
pub fn interrupt_is_disable(self) -> &'a mut W {
self.variant(MR2IW::INTERRUPT_IS_DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR2R`"]
pub enum MR2RW {
#[doc = "TC will be reset if MR2 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR2RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR2RW::TC_WILL_BE_RESET_IF_ => true,
MR2RW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR2RW<'a> {
w: &'a mut W,
}
impl<'a> _MR2RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR2RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC will be reset if MR2 matches it."]
#[inline]
pub fn tc_will_be_reset_if_(self) -> &'a mut W {
self.variant(MR2RW::TC_WILL_BE_RESET_IF_)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR2RW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR2S`"]
pub enum MR2SW {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR2 matches the TC"]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR2SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR2SW::TC_AND_PC_WILL_BE_ST => true,
MR2SW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR2SW<'a> {
w: &'a mut W,
}
impl<'a> _MR2SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR2SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR2 matches the TC"]
#[inline]
pub fn tc_and_pc_will_be_st(self) -> &'a mut W {
self.variant(MR2SW::TC_AND_PC_WILL_BE_ST)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR2SW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR3I`"]
pub enum MR3IW {
#[doc = "Interrupt is generated when MR3 matches the value in the TC."]
INTERRUPT_IS_GENERAT,
#[doc = "This interrupt is disabled"]
THIS_INTERRUPT_IS_DI,
}
impl MR3IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR3IW::INTERRUPT_IS_GENERAT => true,
MR3IW::THIS_INTERRUPT_IS_DI => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR3IW<'a> {
w: &'a mut W,
}
impl<'a> _MR3IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR3IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupt is generated when MR3 matches the value in the TC."]
#[inline]
pub fn interrupt_is_generat(self) -> &'a mut W {
self.variant(MR3IW::INTERRUPT_IS_GENERAT)
}
#[doc = "This interrupt is disabled"]
#[inline]
pub fn this_interrupt_is_di(self) -> &'a mut W {
self.variant(MR3IW::THIS_INTERRUPT_IS_DI)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR3R`"]
pub enum MR3RW {
#[doc = "TC will be reset if MR3 matches it."]
TC_WILL_BE_RESET_IF_,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR3RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR3RW::TC_WILL_BE_RESET_IF_ => true,
MR3RW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR3RW<'a> {
w: &'a mut W,
}
impl<'a> _MR3RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR3RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC will be reset if MR3 matches it."]
#[inline]
pub fn tc_will_be_reset_if_(self) -> &'a mut W {
self.variant(MR3RW::TC_WILL_BE_RESET_IF_)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR3RW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MR3S`"]
pub enum MR3SW {
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR3 matches the TC."]
TC_AND_PC_WILL_BE_ST,
#[doc = "Feature disabled."]
FEATURE_DISABLED_,
}
impl MR3SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MR3SW::TC_AND_PC_WILL_BE_ST => true,
MR3SW::FEATURE_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MR3SW<'a> {
w: &'a mut W,
}
impl<'a> _MR3SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MR3SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "TC and PC will be stopped and TCR\\[0\\] will be set to 0 if MR3 matches the TC."]
#[inline]
pub fn tc_and_pc_will_be_st(self) -> &'a mut W {
self.variant(MR3SW::TC_AND_PC_WILL_BE_ST)
}
#[doc = "Feature disabled."]
#[inline]
pub fn feature_disabled_(self) -> &'a mut W {
self.variant(MR3SW::FEATURE_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt on MR0"]
#[inline]
pub fn mr0i(&self) -> MR0IR {
MR0IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Reset on MR0"]
#[inline]
pub fn mr0r(&self) -> MR0RR {
MR0RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Stop on MR0"]
#[inline]
pub fn mr0s(&self) -> MR0SR {
MR0SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Interrupt on MR1"]
#[inline]
pub fn mr1i(&self) -> MR1IR {
MR1IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Reset on MR1"]
#[inline]
pub fn mr1r(&self) -> MR1RR {
MR1RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Stop on MR1"]
#[inline]
pub fn mr1s(&self) -> MR1SR {
MR1SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Interrupt on MR2"]
#[inline]
pub fn mr2i(&self) -> MR2IR {
MR2IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Reset on MR2"]
#[inline]
pub fn mr2r(&self) -> MR2RR {
MR2RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Stop on MR2."]
#[inline]
pub fn mr2s(&self) -> MR2SR {
MR2SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Interrupt on MR3"]
#[inline]
pub fn mr3i(&self) -> MR3IR {
MR3IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Reset on MR3"]
#[inline]
pub fn mr3r(&self) -> MR3RR {
MR3RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Stop on MR3"]
#[inline]
pub fn mr3s(&self) -> MR3SR {
MR3SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt on MR0"]
#[inline]
pub fn mr0i(&mut self) -> _MR0IW {
_MR0IW { w: self }
}
#[doc = "Bit 1 - Reset on MR0"]
#[inline]
pub fn mr0r(&mut self) -> _MR0RW {
_MR0RW { w: self }
}
#[doc = "Bit 2 - Stop on MR0"]
#[inline]
pub fn mr0s(&mut self) -> _MR0SW {
_MR0SW { w: self }
}
#[doc = "Bit 3 - Interrupt on MR1"]
#[inline]
pub fn mr1i(&mut self) -> _MR1IW {
_MR1IW { w: self }
}
#[doc = "Bit 4 - Reset on MR1"]
#[inline]
pub fn mr1r(&mut self) -> _MR1RW {
_MR1RW { w: self }
}
#[doc = "Bit 5 - Stop on MR1"]
#[inline]
pub fn mr1s(&mut self) -> _MR1SW {
_MR1SW { w: self }
}
#[doc = "Bit 6 - Interrupt on MR2"]
#[inline]
pub fn mr2i(&mut self) -> _MR2IW {
_MR2IW { w: self }
}
#[doc = "Bit 7 - Reset on MR2"]
#[inline]
pub fn mr2r(&mut self) -> _MR2RW {
_MR2RW { w: self }
}
#[doc = "Bit 8 - Stop on MR2."]
#[inline]
pub fn mr2s(&mut self) -> _MR2SW {
_MR2SW { w: self }
}
#[doc = "Bit 9 - Interrupt on MR3"]
#[inline]
pub fn mr3i(&mut self) -> _MR3IW {
_MR3IW { w: self }
}
#[doc = "Bit 10 - Reset on MR3"]
#[inline]
pub fn mr3r(&mut self) -> _MR3RW {
_MR3RW { w: self }
}
#[doc = "Bit 11 - Stop on MR3"]
#[inline]
pub fn mr3s(&mut self) -> _MR3SW {
_MR3SW { w: self }
}
}
}
#[doc = "Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
pub struct MR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC."]
pub mod mr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MATCHR {
bits: u32,
}
impl MATCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MATCHW<'a> {
w: &'a mut W,
}
impl<'a> _MATCHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Timer counter match value."]
#[inline]
pub fn match_(&self) -> MATCHR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MATCHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Timer counter match value."]
#[inline]
pub fn match_(&mut self) -> _MATCHW {
_MATCHW { w: self }
}
}
}
#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
pub struct CCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
pub mod ccr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CAP0RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0RER {
#[doc = "A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP0RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP0RER::ENABLE => true,
CAP0RER::DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP0RER {
match value {
true => CAP0RER::ENABLE,
false => CAP0RER::DISABLE,
}
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CAP0RER::ENABLE
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CAP0RER::DISABLE
}
}
#[doc = "Possible values of the field `CAP0FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0FER {
#[doc = "A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP0FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP0FER::ENABLE => true,
CAP0FER::DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP0FER {
match value {
true => CAP0FER::ENABLE,
false => CAP0FER::DISABLE,
}
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CAP0FER::ENABLE
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CAP0FER::DISABLE
}
}
#[doc = "Possible values of the field `CAP0I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0IR {
#[doc = "A CR0 load due to a CAPn.0 event will generate an interrupt."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP0IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP0IR::ENABLE => true,
CAP0IR::DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP0IR {
match value {
true => CAP0IR::ENABLE,
false => CAP0IR::DISABLE,
}
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CAP0IR::ENABLE
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CAP0IR::DISABLE
}
}
#[doc = "Possible values of the field `CAP1RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1RER {
#[doc = "A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP1RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP1RER::ENABLE => true,
CAP1RER::DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP1RER {
match value {
true => CAP1RER::ENABLE,
false => CAP1RER::DISABLE,
}
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CAP1RER::ENABLE
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CAP1RER::DISABLE
}
}
#[doc = "Possible values of the field `CAP1FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1FER {
#[doc = "A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP1FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP1FER::ENABLE => true,
CAP1FER::DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP1FER {
match value {
true => CAP1FER::ENABLE,
false => CAP1FER::DISABLE,
}
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CAP1FER::ENABLE
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CAP1FER::DISABLE
}
}
#[doc = "Possible values of the field `CAP1I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1IR {
#[doc = "A CR1 load due to a CAPn.1 event will generate an interrupt."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP1IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP1IR::ENABLE => true,
CAP1IR::DISABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP1IR {
match value {
true => CAP1IR::ENABLE,
false => CAP1IR::DISABLE,
}
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CAP1IR::ENABLE
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CAP1IR::DISABLE
}
}
#[doc = "Values that can be written to the field `CAP0RE`"]
pub enum CAP0REW {
#[doc = "A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP0REW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP0REW::ENABLE => true,
CAP0REW::DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP0REW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0REW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP0REW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CAP0REW::ENABLE)
}
#[doc = "This feature is disabled."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CAP0REW::DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP0FE`"]
pub enum CAP0FEW {
#[doc = "A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP0FEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP0FEW::ENABLE => true,
CAP0FEW::DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP0FEW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0FEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP0FEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CAP0FEW::ENABLE)
}
#[doc = "This feature is disabled."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CAP0FEW::DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP0I`"]
pub enum CAP0IW {
#[doc = "A CR0 load due to a CAPn.0 event will generate an interrupt."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP0IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP0IW::ENABLE => true,
CAP0IW::DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP0IW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP0IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A CR0 load due to a CAPn.0 event will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CAP0IW::ENABLE)
}
#[doc = "This feature is disabled."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CAP0IW::DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP1RE`"]
pub enum CAP1REW {
#[doc = "A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP1REW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP1REW::ENABLE => true,
CAP1REW::DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP1REW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1REW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP1REW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CAP1REW::ENABLE)
}
#[doc = "This feature is disabled."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CAP1REW::DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP1FE`"]
pub enum CAP1FEW {
#[doc = "A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP1FEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP1FEW::ENABLE => true,
CAP1FEW::DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP1FEW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1FEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP1FEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CAP1FEW::ENABLE)
}
#[doc = "This feature is disabled."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CAP1FEW::DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP1I`"]
pub enum CAP1IW {
#[doc = "A CR1 load due to a CAPn.1 event will generate an interrupt."]
ENABLE,
#[doc = "This feature is disabled."]
DISABLE,
}
impl CAP1IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP1IW::ENABLE => true,
CAP1IW::DISABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP1IW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP1IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A CR1 load due to a CAPn.1 event will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CAP1IW::ENABLE)
}
#[doc = "This feature is disabled."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CAP1IW::DISABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Capture on CAPn.0 rising edge"]
#[inline]
pub fn cap0re(&self) -> CAP0RER {
CAP0RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Capture on CAPn.0 falling edge"]
#[inline]
pub fn cap0fe(&self) -> CAP0FER {
CAP0FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Interrupt on CAPn.0 event"]
#[inline]
pub fn cap0i(&self) -> CAP0IR {
CAP0IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Capture on CAPn.1 rising edge"]
#[inline]
pub fn cap1re(&self) -> CAP1RER {
CAP1RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Capture on CAPn.1 falling edge"]
#[inline]
pub fn cap1fe(&self) -> CAP1FER {
CAP1FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Interrupt on CAPn.1 event"]
#[inline]
pub fn cap1i(&self) -> CAP1IR {
CAP1IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Capture on CAPn.0 rising edge"]
#[inline]
pub fn cap0re(&mut self) -> _CAP0REW {
_CAP0REW { w: self }
}
#[doc = "Bit 1 - Capture on CAPn.0 falling edge"]
#[inline]
pub fn cap0fe(&mut self) -> _CAP0FEW {
_CAP0FEW { w: self }
}
#[doc = "Bit 2 - Interrupt on CAPn.0 event"]
#[inline]
pub fn cap0i(&mut self) -> _CAP0IW {
_CAP0IW { w: self }
}
#[doc = "Bit 3 - Capture on CAPn.1 rising edge"]
#[inline]
pub fn cap1re(&mut self) -> _CAP1REW {
_CAP1REW { w: self }
}
#[doc = "Bit 4 - Capture on CAPn.1 falling edge"]
#[inline]
pub fn cap1fe(&mut self) -> _CAP1FEW {
_CAP1FEW { w: self }
}
#[doc = "Bit 5 - Interrupt on CAPn.1 event"]
#[inline]
pub fn cap1i(&mut self) -> _CAP1IW {
_CAP1IW { w: self }
}
}
}
#[doc = "Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
pub struct CR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input."]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CAPR {
bits: u32,
}
impl CAPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Timer counter capture value."]
#[inline]
pub fn cap(&self) -> CAPR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
CAPR { bits }
}
}
}
#[doc = "External Match Register. The EMR controls the external match pins."]
pub struct EMR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "External Match Register. The EMR controls the external match pins."]
pub mod emr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EMR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EM0R {
bits: bool,
}
impl EM0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EM1R {
bits: bool,
}
impl EM1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EM2R {
bits: bool,
}
impl EM2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EM3R {
bits: bool,
}
impl EM3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `EMC0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EMC0R {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
EMC0R::DO_NOTHING_ => 0,
EMC0R::CLEAR_THE_CORRESPOND => 0x01,
EMC0R::SET_THE_CORRESPONDIN => 0x02,
EMC0R::TOGGLE_THE_CORRESPON => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> EMC0R {
match value {
0 => EMC0R::DO_NOTHING_,
1 => EMC0R::CLEAR_THE_CORRESPOND,
2 => EMC0R::SET_THE_CORRESPONDIN,
3 => EMC0R::TOGGLE_THE_CORRESPON,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DO_NOTHING_`"]
#[inline]
pub fn is_do_nothing_(&self) -> bool {
*self == EMC0R::DO_NOTHING_
}
#[doc = "Checks if the value of the field is `CLEAR_THE_CORRESPOND`"]
#[inline]
pub fn is_clear_the_correspond(&self) -> bool {
*self == EMC0R::CLEAR_THE_CORRESPOND
}
#[doc = "Checks if the value of the field is `SET_THE_CORRESPONDIN`"]
#[inline]
pub fn is_set_the_correspondin(&self) -> bool {
*self == EMC0R::SET_THE_CORRESPONDIN
}
#[doc = "Checks if the value of the field is `TOGGLE_THE_CORRESPON`"]
#[inline]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == EMC0R::TOGGLE_THE_CORRESPON
}
}
#[doc = "Possible values of the field `EMC1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EMC1R {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
EMC1R::DO_NOTHING_ => 0,
EMC1R::CLEAR_THE_CORRESPOND => 0x01,
EMC1R::SET_THE_CORRESPONDIN => 0x02,
EMC1R::TOGGLE_THE_CORRESPON => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> EMC1R {
match value {
0 => EMC1R::DO_NOTHING_,
1 => EMC1R::CLEAR_THE_CORRESPOND,
2 => EMC1R::SET_THE_CORRESPONDIN,
3 => EMC1R::TOGGLE_THE_CORRESPON,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DO_NOTHING_`"]
#[inline]
pub fn is_do_nothing_(&self) -> bool {
*self == EMC1R::DO_NOTHING_
}
#[doc = "Checks if the value of the field is `CLEAR_THE_CORRESPOND`"]
#[inline]
pub fn is_clear_the_correspond(&self) -> bool {
*self == EMC1R::CLEAR_THE_CORRESPOND
}
#[doc = "Checks if the value of the field is `SET_THE_CORRESPONDIN`"]
#[inline]
pub fn is_set_the_correspondin(&self) -> bool {
*self == EMC1R::SET_THE_CORRESPONDIN
}
#[doc = "Checks if the value of the field is `TOGGLE_THE_CORRESPON`"]
#[inline]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == EMC1R::TOGGLE_THE_CORRESPON
}
}
#[doc = "Possible values of the field `EMC2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EMC2R {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
EMC2R::DO_NOTHING_ => 0,
EMC2R::CLEAR_THE_CORRESPOND => 0x01,
EMC2R::SET_THE_CORRESPONDIN => 0x02,
EMC2R::TOGGLE_THE_CORRESPON => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> EMC2R {
match value {
0 => EMC2R::DO_NOTHING_,
1 => EMC2R::CLEAR_THE_CORRESPOND,
2 => EMC2R::SET_THE_CORRESPONDIN,
3 => EMC2R::TOGGLE_THE_CORRESPON,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DO_NOTHING_`"]
#[inline]
pub fn is_do_nothing_(&self) -> bool {
*self == EMC2R::DO_NOTHING_
}
#[doc = "Checks if the value of the field is `CLEAR_THE_CORRESPOND`"]
#[inline]
pub fn is_clear_the_correspond(&self) -> bool {
*self == EMC2R::CLEAR_THE_CORRESPOND
}
#[doc = "Checks if the value of the field is `SET_THE_CORRESPONDIN`"]
#[inline]
pub fn is_set_the_correspondin(&self) -> bool {
*self == EMC2R::SET_THE_CORRESPONDIN
}
#[doc = "Checks if the value of the field is `TOGGLE_THE_CORRESPON`"]
#[inline]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == EMC2R::TOGGLE_THE_CORRESPON
}
}
#[doc = "Possible values of the field `EMC3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EMC3R {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
EMC3R::DO_NOTHING_ => 0,
EMC3R::CLEAR_THE_CORRESPOND => 0x01,
EMC3R::SET_THE_CORRESPONDIN => 0x02,
EMC3R::TOGGLE_THE_CORRESPON => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> EMC3R {
match value {
0 => EMC3R::DO_NOTHING_,
1 => EMC3R::CLEAR_THE_CORRESPOND,
2 => EMC3R::SET_THE_CORRESPONDIN,
3 => EMC3R::TOGGLE_THE_CORRESPON,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DO_NOTHING_`"]
#[inline]
pub fn is_do_nothing_(&self) -> bool {
*self == EMC3R::DO_NOTHING_
}
#[doc = "Checks if the value of the field is `CLEAR_THE_CORRESPOND`"]
#[inline]
pub fn is_clear_the_correspond(&self) -> bool {
*self == EMC3R::CLEAR_THE_CORRESPOND
}
#[doc = "Checks if the value of the field is `SET_THE_CORRESPONDIN`"]
#[inline]
pub fn is_set_the_correspondin(&self) -> bool {
*self == EMC3R::SET_THE_CORRESPONDIN
}
#[doc = "Checks if the value of the field is `TOGGLE_THE_CORRESPON`"]
#[inline]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == EMC3R::TOGGLE_THE_CORRESPON
}
}
#[doc = r" Proxy"]
pub struct _EM0W<'a> {
w: &'a mut W,
}
impl<'a> _EM0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EM1W<'a> {
w: &'a mut W,
}
impl<'a> _EM1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EM2W<'a> {
w: &'a mut W,
}
impl<'a> _EM2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EM3W<'a> {
w: &'a mut W,
}
impl<'a> _EM3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EMC0`"]
pub enum EMC0W {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
EMC0W::DO_NOTHING_ => 0,
EMC0W::CLEAR_THE_CORRESPOND => 1,
EMC0W::SET_THE_CORRESPONDIN => 2,
EMC0W::TOGGLE_THE_CORRESPON => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _EMC0W<'a> {
w: &'a mut W,
}
impl<'a> _EMC0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EMC0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Do Nothing."]
#[inline]
pub fn do_nothing_(self) -> &'a mut W {
self.variant(EMC0W::DO_NOTHING_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
#[inline]
pub fn clear_the_correspond(self) -> &'a mut W {
self.variant(EMC0W::CLEAR_THE_CORRESPOND)
}
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
#[inline]
pub fn set_the_correspondin(self) -> &'a mut W {
self.variant(EMC0W::SET_THE_CORRESPONDIN)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline]
pub fn toggle_the_correspon(self) -> &'a mut W {
self.variant(EMC0W::TOGGLE_THE_CORRESPON)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EMC1`"]
pub enum EMC1W {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
EMC1W::DO_NOTHING_ => 0,
EMC1W::CLEAR_THE_CORRESPOND => 1,
EMC1W::SET_THE_CORRESPONDIN => 2,
EMC1W::TOGGLE_THE_CORRESPON => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _EMC1W<'a> {
w: &'a mut W,
}
impl<'a> _EMC1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EMC1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Do Nothing."]
#[inline]
pub fn do_nothing_(self) -> &'a mut W {
self.variant(EMC1W::DO_NOTHING_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
#[inline]
pub fn clear_the_correspond(self) -> &'a mut W {
self.variant(EMC1W::CLEAR_THE_CORRESPOND)
}
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
#[inline]
pub fn set_the_correspondin(self) -> &'a mut W {
self.variant(EMC1W::SET_THE_CORRESPONDIN)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline]
pub fn toggle_the_correspon(self) -> &'a mut W {
self.variant(EMC1W::TOGGLE_THE_CORRESPON)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EMC2`"]
pub enum EMC2W {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
EMC2W::DO_NOTHING_ => 0,
EMC2W::CLEAR_THE_CORRESPOND => 1,
EMC2W::SET_THE_CORRESPONDIN => 2,
EMC2W::TOGGLE_THE_CORRESPON => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _EMC2W<'a> {
w: &'a mut W,
}
impl<'a> _EMC2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EMC2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Do Nothing."]
#[inline]
pub fn do_nothing_(self) -> &'a mut W {
self.variant(EMC2W::DO_NOTHING_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
#[inline]
pub fn clear_the_correspond(self) -> &'a mut W {
self.variant(EMC2W::CLEAR_THE_CORRESPOND)
}
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
#[inline]
pub fn set_the_correspondin(self) -> &'a mut W {
self.variant(EMC2W::SET_THE_CORRESPONDIN)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline]
pub fn toggle_the_correspon(self) -> &'a mut W {
self.variant(EMC2W::TOGGLE_THE_CORRESPON)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EMC3`"]
pub enum EMC3W {
#[doc = "Do Nothing."]
DO_NOTHING_,
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
CLEAR_THE_CORRESPOND,
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
SET_THE_CORRESPONDIN,
#[doc = "Toggle the corresponding External Match bit/output."]
TOGGLE_THE_CORRESPON,
}
impl EMC3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
EMC3W::DO_NOTHING_ => 0,
EMC3W::CLEAR_THE_CORRESPOND => 1,
EMC3W::SET_THE_CORRESPONDIN => 2,
EMC3W::TOGGLE_THE_CORRESPON => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _EMC3W<'a> {
w: &'a mut W,
}
impl<'a> _EMC3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EMC3W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Do Nothing."]
#[inline]
pub fn do_nothing_(self) -> &'a mut W {
self.variant(EMC3W::DO_NOTHING_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)."]
#[inline]
pub fn clear_the_correspond(self) -> &'a mut W {
self.variant(EMC3W::CLEAR_THE_CORRESPOND)
}
#[doc = "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)."]
#[inline]
pub fn set_the_correspondin(self) -> &'a mut W {
self.variant(EMC3W::SET_THE_CORRESPONDIN)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline]
pub fn toggle_the_correspon(self) -> &'a mut W {
self.variant(EMC3W::TOGGLE_THE_CORRESPON)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em0(&self) -> EM0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EM0R { bits }
}
#[doc = "Bit 1 - External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em1(&self) -> EM1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EM1R { bits }
}
#[doc = "Bit 2 - External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em2(&self) -> EM2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EM2R { bits }
}
#[doc = "Bit 3 - External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em3(&self) -> EM3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EM3R { bits }
}
#[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
#[inline]
pub fn emc0(&self) -> EMC0R {
EMC0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
#[inline]
pub fn emc1(&self) -> EMC1R {
EMC1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
#[inline]
pub fn emc2(&self) -> EMC2R {
EMC2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
#[inline]
pub fn emc3(&self) -> EMC3R {
EMC3R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em0(&mut self) -> _EM0W {
_EM0W { w: self }
}
#[doc = "Bit 1 - External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em1(&mut self) -> _EM1W {
_EM1W { w: self }
}
#[doc = "Bit 2 - External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em2(&mut self) -> _EM2W {
_EM2W { w: self }
}
#[doc = "Bit 3 - External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)."]
#[inline]
pub fn em3(&mut self) -> _EM3W {
_EM3W { w: self }
}
#[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
#[inline]
pub fn emc0(&mut self) -> _EMC0W {
_EMC0W { w: self }
}
#[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
#[inline]
pub fn emc1(&mut self) -> _EMC1W {
_EMC1W { w: self }
}
#[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
#[inline]
pub fn emc2(&mut self) -> _EMC2W {
_EMC2W { w: self }
}
#[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
#[inline]
pub fn emc3(&mut self) -> _EMC3W {
_EMC3W { w: self }
}
}
}
#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub struct CTCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub mod ctcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CTMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CTMODER {
#[doc = "Timer Mode: every rising PCLK edge"]
TIMER_MODE_EVERY_RI,
#[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
RISING,
#[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
FALLING,
#[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
DUALEDGE,
}
impl CTMODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CTMODER::TIMER_MODE_EVERY_RI => 0,
CTMODER::RISING => 0x01,
CTMODER::FALLING => 0x02,
CTMODER::DUALEDGE => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CTMODER {
match value {
0 => CTMODER::TIMER_MODE_EVERY_RI,
1 => CTMODER::RISING,
2 => CTMODER::FALLING,
3 => CTMODER::DUALEDGE,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TIMER_MODE_EVERY_RI`"]
#[inline]
pub fn is_timer_mode_every_ri(&self) -> bool {
*self == CTMODER::TIMER_MODE_EVERY_RI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == CTMODER::RISING
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == CTMODER::FALLING
}
#[doc = "Checks if the value of the field is `DUALEDGE`"]
#[inline]
pub fn is_dualedge(&self) -> bool {
*self == CTMODER::DUALEDGE
}
}
#[doc = "Possible values of the field `CINSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CINSELR {
#[doc = "CAPn.0 for TIMERn"]
CAPN_0_FOR_TIMERN,
#[doc = "CAPn.1 for TIMERn"]
CAPN_1_FOR_TIMERN,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl CINSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CINSELR::CAPN_0_FOR_TIMERN => 0,
CINSELR::CAPN_1_FOR_TIMERN => 0x01,
CINSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CINSELR {
match value {
0 => CINSELR::CAPN_0_FOR_TIMERN,
1 => CINSELR::CAPN_1_FOR_TIMERN,
i => CINSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `CAPN_0_FOR_TIMERN`"]
#[inline]
pub fn is_capn_0_for_timern(&self) -> bool {
*self == CINSELR::CAPN_0_FOR_TIMERN
}
#[doc = "Checks if the value of the field is `CAPN_1_FOR_TIMERN`"]
#[inline]
pub fn is_capn_1_for_timern(&self) -> bool {
*self == CINSELR::CAPN_1_FOR_TIMERN
}
}
#[doc = "Values that can be written to the field `CTMODE`"]
pub enum CTMODEW {
#[doc = "Timer Mode: every rising PCLK edge"]
TIMER_MODE_EVERY_RI,
#[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
RISING,
#[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
FALLING,
#[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
DUALEDGE,
}
impl CTMODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CTMODEW::TIMER_MODE_EVERY_RI => 0,
CTMODEW::RISING => 1,
CTMODEW::FALLING => 2,
CTMODEW::DUALEDGE => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _CTMODEW<'a> {
w: &'a mut W,
}
impl<'a> _CTMODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CTMODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Timer Mode: every rising PCLK edge"]
#[inline]
pub fn timer_mode_every_ri(self) -> &'a mut W {
self.variant(CTMODEW::TIMER_MODE_EVERY_RI)
}
#[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
#[inline]
pub fn rising(self) -> &'a mut W {
self.variant(CTMODEW::RISING)
}
#[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
#[inline]
pub fn falling(self) -> &'a mut W {
self.variant(CTMODEW::FALLING)
}
#[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
#[inline]
pub fn dualedge(self) -> &'a mut W {
self.variant(CTMODEW::DUALEDGE)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CINSEL`"]
pub enum CINSELW {
#[doc = "CAPn.0 for TIMERn"]
CAPN_0_FOR_TIMERN,
#[doc = "CAPn.1 for TIMERn"]
CAPN_1_FOR_TIMERN,
}
impl CINSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CINSELW::CAPN_0_FOR_TIMERN => 0,
CINSELW::CAPN_1_FOR_TIMERN => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _CINSELW<'a> {
w: &'a mut W,
}
impl<'a> _CINSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CINSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "CAPn.0 for TIMERn"]
#[inline]
pub fn capn_0_for_timern(self) -> &'a mut W {
self.variant(CINSELW::CAPN_0_FOR_TIMERN)
}
#[doc = "CAPn.1 for TIMERn"]
#[inline]
pub fn capn_1_for_timern(self) -> &'a mut W {
self.variant(CINSELW::CAPN_1_FOR_TIMERN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
#[inline]
pub fn ctmode(&self) -> CTMODER {
CTMODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
#[inline]
pub fn cinsel(&self) -> CINSELR {
CINSELR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register."]
#[inline]
pub fn ctmode(&mut self) -> _CTMODEW {
_CTMODEW { w: self }
}
#[doc = "Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer."]
#[inline]
pub fn cinsel(&mut self) -> _CINSELW {
_CINSELW { w: self }
}
}
}
}
#[doc = "TIMER1"]
pub struct TIMER1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMER1 {}
impl TIMER1 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const timer0::RegisterBlock {
0x4000_8000 as *const _
}
}
impl Deref for TIMER1 {
type Target = timer0::RegisterBlock;
fn deref(&self) -> &timer0::RegisterBlock {
unsafe { &*TIMER1::ptr() }
}
}
#[doc = "UART0/2/3"]
pub struct UART0 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART0 {}
impl UART0 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const uart0::RegisterBlock {
0x4000_c000 as *const _
}
}
impl Deref for UART0 {
type Target = uart0::RegisterBlock;
fn deref(&self) -> &uart0::RegisterBlock {
unsafe { &*UART0::ptr() }
}
}
#[doc = "UART0/2/3"]
pub mod uart0 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). Receiver Buffer Register. Contains the next received character to be read (DLAB =0)."]
pub dll: DLL_UNION,
#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub dlm: DLM_UNION,
#[doc = "FIFO Control Register. Controls UART FIFO usage and modes. Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub fcr: FCR_UNION,
#[doc = "0x0c - Line Control Register. Contains controls for frame formatting and break generation."]
pub lcr: LCR,
_reserved4: [u8; 4usize],
#[doc = "0x14 - Line Status Register. Contains flags for transmit and receive status, including line errors."]
pub lsr: LSR,
_reserved5: [u8; 4usize],
#[doc = "0x1c - Scratch Pad Register. 8-bit temporary storage for software."]
pub scr: SCR,
#[doc = "0x20 - Auto-baud Control Register. Contains controls for the auto-baud feature."]
pub acr: ACR,
_reserved7: [u8; 4usize],
#[doc = "0x28 - Fractional Divider Register. Generates a clock input for the baud rate divider."]
pub fdr: FDR,
_reserved8: [u8; 4usize],
#[doc = "0x30 - Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
pub ter: TER,
_reserved9: [u8; 24usize],
#[doc = "0x4c - RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
pub rs485ctrl: RS485CTRL,
#[doc = "0x50 - RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
pub rs485adrmatch: RS485ADRMATCH,
#[doc = "0x54 - RS-485/EIA-485 direction control delay."]
pub rs485dly: RS485DLY,
}
#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). Receiver Buffer Register. Contains the next received character to be read (DLAB =0)."]
#[repr(C)]
pub union DLL_UNION {
#[doc = "0x00 - Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub dll: DLL,
#[doc = "0x00 - Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)."]
pub thr: THR,
#[doc = "0x00 - Receiver Buffer Register. Contains the next received character to be read (DLAB =0)."]
pub rbr: RBR,
}
#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
#[repr(C)]
pub union DLM_UNION {
#[doc = "0x04 - Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)."]
pub ier: IER,
#[doc = "0x04 - Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub dlm: DLM,
}
#[doc = "FIFO Control Register. Controls UART FIFO usage and modes. Interrupt ID Register. Identifies which interrupt(s) are pending."]
#[repr(C)]
pub union FCR_UNION {
#[doc = "0x08 - FIFO Control Register. Controls UART FIFO usage and modes."]
pub fcr: FCR,
#[doc = "0x08 - Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub iir: IIR,
}
#[doc = "Receiver Buffer Register. Contains the next received character to be read (DLAB =0)."]
pub struct RBR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receiver Buffer Register. Contains the next received character to be read (DLAB =0)."]
pub mod rbr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RBR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RBRR {
bits: u8,
}
impl RBRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO."]
#[inline]
pub fn rbr(&self) -> RBRR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RBRR { bits }
}
}
}
#[doc = "Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)."]
pub struct THR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)."]
pub mod thr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::THR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _THRW<'a> {
w: &'a mut W,
}
impl<'a> _THRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available."]
#[inline]
pub fn thr(&mut self) -> _THRW {
_THRW { w: self }
}
}
}
#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub struct DLL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub mod dll {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DLL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DLLSBR {
bits: u8,
}
impl DLLSBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DLLSBW<'a> {
w: &'a mut W,
}
impl<'a> _DLLSBW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn."]
#[inline]
pub fn dllsb(&self) -> DLLSBR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLLSBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x01 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn."]
#[inline]
pub fn dllsb(&mut self) -> _DLLSBW {
_DLLSBW { w: self }
}
}
}
#[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub struct DLM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)."]
pub mod dlm {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DLM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DLMSBR {
bits: u8,
}
impl DLMSBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DLMSBW<'a> {
w: &'a mut W,
}
impl<'a> _DLMSBW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn."]
#[inline]
pub fn dlmsb(&self) -> DLMSBR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLMSBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn."]
#[inline]
pub fn dlmsb(&mut self) -> _DLMSBW {
_DLMSBW { w: self }
}
}
}
#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)."]
pub struct IER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)."]
pub mod ier {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RBRIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RBRIER {
#[doc = "Disable the RDA interrupts."]
DISABLE_THE_RDA_INTE,
#[doc = "Enable the RDA interrupts."]
ENABLE_THE_RDA_INTER,
}
impl RBRIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RBRIER::DISABLE_THE_RDA_INTE => false,
RBRIER::ENABLE_THE_RDA_INTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RBRIER {
match value {
false => RBRIER::DISABLE_THE_RDA_INTE,
true => RBRIER::ENABLE_THE_RDA_INTER,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_RDA_INTE`"]
#[inline]
pub fn is_disable_the_rda_inte(&self) -> bool {
*self == RBRIER::DISABLE_THE_RDA_INTE
}
#[doc = "Checks if the value of the field is `ENABLE_THE_RDA_INTER`"]
#[inline]
pub fn is_enable_the_rda_inter(&self) -> bool {
*self == RBRIER::ENABLE_THE_RDA_INTER
}
}
#[doc = "Possible values of the field `THREIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum THREIER {
#[doc = "Disable the THRE interrupts."]
DISABLE_THE_THRE_INT,
#[doc = "Enable the THRE interrupts."]
ENABLE_THE_THRE_INTE,
}
impl THREIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
THREIER::DISABLE_THE_THRE_INT => false,
THREIER::ENABLE_THE_THRE_INTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> THREIER {
match value {
false => THREIER::DISABLE_THE_THRE_INT,
true => THREIER::ENABLE_THE_THRE_INTE,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_THRE_INT`"]
#[inline]
pub fn is_disable_the_thre_int(&self) -> bool {
*self == THREIER::DISABLE_THE_THRE_INT
}
#[doc = "Checks if the value of the field is `ENABLE_THE_THRE_INTE`"]
#[inline]
pub fn is_enable_the_thre_inte(&self) -> bool {
*self == THREIER::ENABLE_THE_THRE_INTE
}
}
#[doc = "Possible values of the field `RXIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXIER {
#[doc = "Disable the RX line status interrupts."]
DISABLE_THE_RX_LINE_,
#[doc = "Enable the RX line status interrupts."]
ENABLE_THE_RX_LINE_S,
}
impl RXIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RXIER::DISABLE_THE_RX_LINE_ => false,
RXIER::ENABLE_THE_RX_LINE_S => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RXIER {
match value {
false => RXIER::DISABLE_THE_RX_LINE_,
true => RXIER::ENABLE_THE_RX_LINE_S,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_RX_LINE_`"]
#[inline]
pub fn is_disable_the_rx_line_(&self) -> bool {
*self == RXIER::DISABLE_THE_RX_LINE_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_RX_LINE_S`"]
#[inline]
pub fn is_enable_the_rx_line_s(&self) -> bool {
*self == RXIER::ENABLE_THE_RX_LINE_S
}
}
#[doc = "Possible values of the field `ABEOINTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABEOINTENR {
#[doc = "Disable end of auto-baud Interrupt."]
DISABLE_END_OF_AUTO_,
#[doc = "Enable end of auto-baud Interrupt."]
ENABLE_END_OF_AUTO_B,
}
impl ABEOINTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABEOINTENR::DISABLE_END_OF_AUTO_ => false,
ABEOINTENR::ENABLE_END_OF_AUTO_B => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABEOINTENR {
match value {
false => ABEOINTENR::DISABLE_END_OF_AUTO_,
true => ABEOINTENR::ENABLE_END_OF_AUTO_B,
}
}
#[doc = "Checks if the value of the field is `DISABLE_END_OF_AUTO_`"]
#[inline]
pub fn is_disable_end_of_auto_(&self) -> bool {
*self == ABEOINTENR::DISABLE_END_OF_AUTO_
}
#[doc = "Checks if the value of the field is `ENABLE_END_OF_AUTO_B`"]
#[inline]
pub fn is_enable_end_of_auto_b(&self) -> bool {
*self == ABEOINTENR::ENABLE_END_OF_AUTO_B
}
}
#[doc = "Possible values of the field `ABTOINTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABTOINTENR {
#[doc = "Disable auto-baud time-out Interrupt."]
DISABLE_AUTO_BAUD_TI,
#[doc = "Enable auto-baud time-out Interrupt."]
ENABLE_AUTO_BAUD_TIM,
}
impl ABTOINTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABTOINTENR::DISABLE_AUTO_BAUD_TI => false,
ABTOINTENR::ENABLE_AUTO_BAUD_TIM => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABTOINTENR {
match value {
false => ABTOINTENR::DISABLE_AUTO_BAUD_TI,
true => ABTOINTENR::ENABLE_AUTO_BAUD_TIM,
}
}
#[doc = "Checks if the value of the field is `DISABLE_AUTO_BAUD_TI`"]
#[inline]
pub fn is_disable_auto_baud_ti(&self) -> bool {
*self == ABTOINTENR::DISABLE_AUTO_BAUD_TI
}
#[doc = "Checks if the value of the field is `ENABLE_AUTO_BAUD_TIM`"]
#[inline]
pub fn is_enable_auto_baud_tim(&self) -> bool {
*self == ABTOINTENR::ENABLE_AUTO_BAUD_TIM
}
}
#[doc = "Values that can be written to the field `RBRIE`"]
pub enum RBRIEW {
#[doc = "Disable the RDA interrupts."]
DISABLE_THE_RDA_INTE,
#[doc = "Enable the RDA interrupts."]
ENABLE_THE_RDA_INTER,
}
impl RBRIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RBRIEW::DISABLE_THE_RDA_INTE => false,
RBRIEW::ENABLE_THE_RDA_INTER => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RBRIEW<'a> {
w: &'a mut W,
}
impl<'a> _RBRIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RBRIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the RDA interrupts."]
#[inline]
pub fn disable_the_rda_inte(self) -> &'a mut W {
self.variant(RBRIEW::DISABLE_THE_RDA_INTE)
}
#[doc = "Enable the RDA interrupts."]
#[inline]
pub fn enable_the_rda_inter(self) -> &'a mut W {
self.variant(RBRIEW::ENABLE_THE_RDA_INTER)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `THREIE`"]
pub enum THREIEW {
#[doc = "Disable the THRE interrupts."]
DISABLE_THE_THRE_INT,
#[doc = "Enable the THRE interrupts."]
ENABLE_THE_THRE_INTE,
}
impl THREIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
THREIEW::DISABLE_THE_THRE_INT => false,
THREIEW::ENABLE_THE_THRE_INTE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _THREIEW<'a> {
w: &'a mut W,
}
impl<'a> _THREIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: THREIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the THRE interrupts."]
#[inline]
pub fn disable_the_thre_int(self) -> &'a mut W {
self.variant(THREIEW::DISABLE_THE_THRE_INT)
}
#[doc = "Enable the THRE interrupts."]
#[inline]
pub fn enable_the_thre_inte(self) -> &'a mut W {
self.variant(THREIEW::ENABLE_THE_THRE_INTE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXIE`"]
pub enum RXIEW {
#[doc = "Disable the RX line status interrupts."]
DISABLE_THE_RX_LINE_,
#[doc = "Enable the RX line status interrupts."]
ENABLE_THE_RX_LINE_S,
}
impl RXIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RXIEW::DISABLE_THE_RX_LINE_ => false,
RXIEW::ENABLE_THE_RX_LINE_S => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RXIEW<'a> {
w: &'a mut W,
}
impl<'a> _RXIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the RX line status interrupts."]
#[inline]
pub fn disable_the_rx_line_(self) -> &'a mut W {
self.variant(RXIEW::DISABLE_THE_RX_LINE_)
}
#[doc = "Enable the RX line status interrupts."]
#[inline]
pub fn enable_the_rx_line_s(self) -> &'a mut W {
self.variant(RXIEW::ENABLE_THE_RX_LINE_S)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABEOINTEN`"]
pub enum ABEOINTENW {
#[doc = "Disable end of auto-baud Interrupt."]
DISABLE_END_OF_AUTO_,
#[doc = "Enable end of auto-baud Interrupt."]
ENABLE_END_OF_AUTO_B,
}
impl ABEOINTENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABEOINTENW::DISABLE_END_OF_AUTO_ => false,
ABEOINTENW::ENABLE_END_OF_AUTO_B => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABEOINTENW<'a> {
w: &'a mut W,
}
impl<'a> _ABEOINTENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABEOINTENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable end of auto-baud Interrupt."]
#[inline]
pub fn disable_end_of_auto_(self) -> &'a mut W {
self.variant(ABEOINTENW::DISABLE_END_OF_AUTO_)
}
#[doc = "Enable end of auto-baud Interrupt."]
#[inline]
pub fn enable_end_of_auto_b(self) -> &'a mut W {
self.variant(ABEOINTENW::ENABLE_END_OF_AUTO_B)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABTOINTEN`"]
pub enum ABTOINTENW {
#[doc = "Disable auto-baud time-out Interrupt."]
DISABLE_AUTO_BAUD_TI,
#[doc = "Enable auto-baud time-out Interrupt."]
ENABLE_AUTO_BAUD_TIM,
}
impl ABTOINTENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABTOINTENW::DISABLE_AUTO_BAUD_TI => false,
ABTOINTENW::ENABLE_AUTO_BAUD_TIM => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABTOINTENW<'a> {
w: &'a mut W,
}
impl<'a> _ABTOINTENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABTOINTENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable auto-baud time-out Interrupt."]
#[inline]
pub fn disable_auto_baud_ti(self) -> &'a mut W {
self.variant(ABTOINTENW::DISABLE_AUTO_BAUD_TI)
}
#[doc = "Enable auto-baud time-out Interrupt."]
#[inline]
pub fn enable_auto_baud_tim(self) -> &'a mut W {
self.variant(ABTOINTENW::ENABLE_AUTO_BAUD_TIM)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."]
#[inline]
pub fn rbrie(&self) -> RBRIER {
RBRIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR\\[5\\]."]
#[inline]
pub fn threie(&self) -> THREIER {
THREIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR\\[4:1\\]."]
#[inline]
pub fn rxie(&self) -> RXIER {
RXIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Enables the end of auto-baud interrupt."]
#[inline]
pub fn abeointen(&self) -> ABEOINTENR {
ABEOINTENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Enables the auto-baud time-out interrupt."]
#[inline]
pub fn abtointen(&self) -> ABTOINTENR {
ABTOINTENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt."]
#[inline]
pub fn rbrie(&mut self) -> _RBRIEW {
_RBRIEW { w: self }
}
#[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR\\[5\\]."]
#[inline]
pub fn threie(&mut self) -> _THREIEW {
_THREIEW { w: self }
}
#[doc = "Bit 2 - RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR\\[4:1\\]."]
#[inline]
pub fn rxie(&mut self) -> _RXIEW {
_RXIEW { w: self }
}
#[doc = "Bit 8 - Enables the end of auto-baud interrupt."]
#[inline]
pub fn abeointen(&mut self) -> _ABEOINTENW {
_ABEOINTENW { w: self }
}
#[doc = "Bit 9 - Enables the auto-baud time-out interrupt."]
#[inline]
pub fn abtointen(&mut self) -> _ABTOINTENW {
_ABTOINTENW { w: self }
}
}
}
#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub struct IIR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub mod iir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::IIR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `INTSTATUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTSTATUSR {
#[doc = "At least one interrupt is pending."]
AT_LEAST_ONE_INTERRU,
#[doc = "No interrupt is pending."]
NO_INTERRUPT_IS_PEND,
}
impl INTSTATUSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
INTSTATUSR::AT_LEAST_ONE_INTERRU => false,
INTSTATUSR::NO_INTERRUPT_IS_PEND => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> INTSTATUSR {
match value {
false => INTSTATUSR::AT_LEAST_ONE_INTERRU,
true => INTSTATUSR::NO_INTERRUPT_IS_PEND,
}
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_INTERRU`"]
#[inline]
pub fn is_at_least_one_interru(&self) -> bool {
*self == INTSTATUSR::AT_LEAST_ONE_INTERRU
}
#[doc = "Checks if the value of the field is `NO_INTERRUPT_IS_PEND`"]
#[inline]
pub fn is_no_interrupt_is_pend(&self) -> bool {
*self == INTSTATUSR::NO_INTERRUPT_IS_PEND
}
}
#[doc = "Possible values of the field `INTID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTIDR {
#[doc = "1 - Receive Line Status (RLS)."]
_1_RECEIVE_LINE_S,
#[doc = "2a - Receive Data Available (RDA)."]
_2A_RECEIVE_DATA_AV,
#[doc = "2b - Character Time-out Indicator (CTI)."]
_2B_CHARACTER_TIME_,
#[doc = "3 - THRE Interrupt"]
_3_THRE_INTERRUPT,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl INTIDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
INTIDR::_1_RECEIVE_LINE_S => 0x03,
INTIDR::_2A_RECEIVE_DATA_AV => 0x02,
INTIDR::_2B_CHARACTER_TIME_ => 0x06,
INTIDR::_3_THRE_INTERRUPT => 0x01,
INTIDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> INTIDR {
match value {
3 => INTIDR::_1_RECEIVE_LINE_S,
2 => INTIDR::_2A_RECEIVE_DATA_AV,
6 => INTIDR::_2B_CHARACTER_TIME_,
1 => INTIDR::_3_THRE_INTERRUPT,
i => INTIDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_1_RECEIVE_LINE_S`"]
#[inline]
pub fn is_1_receive_line_s(&self) -> bool {
*self == INTIDR::_1_RECEIVE_LINE_S
}
#[doc = "Checks if the value of the field is `_2A__RECEIVE_DATA_AV`"]
#[inline]
pub fn is_2a_receive_data_av(&self) -> bool {
*self == INTIDR::_2A_RECEIVE_DATA_AV
}
#[doc = "Checks if the value of the field is `_2B__CHARACTER_TIME_`"]
#[inline]
pub fn is_2b_character_time_(&self) -> bool {
*self == INTIDR::_2B_CHARACTER_TIME_
}
#[doc = "Checks if the value of the field is `_3_THRE_INTERRUPT`"]
#[inline]
pub fn is_3_thre_interrupt(&self) -> bool {
*self == INTIDR::_3_THRE_INTERRUPT
}
}
#[doc = r" Value of the field"]
pub struct FIFOENABLER {
bits: u8,
}
impl FIFOENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct ABEOINTR {
bits: bool,
}
impl ABEOINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ABTOINTR {
bits: bool,
}
impl ABTOINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt status. Note that UnIIR\\[0\\] is active low. The pending interrupt can be determined by evaluating UnIIR\\[3:1\\]."]
#[inline]
pub fn intstatus(&self) -> INTSTATUSR {
INTSTATUSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 1:3 - Interrupt identification. UnIER\\[3:1\\] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER\\[3:1\\] not listed below are reserved (000,100,101,111)."]
#[inline]
pub fn intid(&self) -> INTIDR {
INTIDR::_from({
const MASK: u8 = 0x07;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Copies of UnFCR\\[0\\]."]
#[inline]
pub fn fifoenable(&self) -> FIFOENABLER {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FIFOENABLER { bits }
}
#[doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled."]
#[inline]
pub fn abeoint(&self) -> ABEOINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABEOINTR { bits }
}
#[doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled."]
#[inline]
pub fn abtoint(&self) -> ABTOINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABTOINTR { bits }
}
}
}
#[doc = "FIFO Control Register. Controls UART FIFO usage and modes."]
pub struct FCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "FIFO Control Register. Controls UART FIFO usage and modes."]
pub mod fcr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FCR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `FIFOEN`"]
pub enum FIFOENW {
#[doc = "UARTn FIFOs are disabled. Must not be used in the application."]
UARTN_FIFOS_ARE_DISA,
#[doc = "Active high enable for both UARTn Rx and TX FIFOs and UnFCR\\[7:1\\] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs."]
ACTIVE_HIGH_ENABLE_F,
}
impl FIFOENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FIFOENW::UARTN_FIFOS_ARE_DISA => false,
FIFOENW::ACTIVE_HIGH_ENABLE_F => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FIFOENW<'a> {
w: &'a mut W,
}
impl<'a> _FIFOENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIFOENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "UARTn FIFOs are disabled. Must not be used in the application."]
#[inline]
pub fn uartn_fifos_are_disa(self) -> &'a mut W {
self.variant(FIFOENW::UARTN_FIFOS_ARE_DISA)
}
#[doc = "Active high enable for both UARTn Rx and TX FIFOs and UnFCR\\[7:1\\] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs."]
#[inline]
pub fn active_high_enable_f(self) -> &'a mut W {
self.variant(FIFOENW::ACTIVE_HIGH_ENABLE_F)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXFIFORES`"]
pub enum RXFIFORESW {
#[doc = "No impact on either of UARTn FIFOs."]
NO_IMPACT_ON_EITHER_,
#[doc = "Writing a logic 1 to UnFCR\\[1\\] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing."]
WRITING_A_LOGIC_1_TO,
}
impl RXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RXFIFORESW::NO_IMPACT_ON_EITHER_ => false,
RXFIFORESW::WRITING_A_LOGIC_1_TO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RXFIFORESW<'a> {
w: &'a mut W,
}
impl<'a> _RXFIFORESW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXFIFORESW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No impact on either of UARTn FIFOs."]
#[inline]
pub fn no_impact_on_either_(self) -> &'a mut W {
self.variant(RXFIFORESW::NO_IMPACT_ON_EITHER_)
}
#[doc = "Writing a logic 1 to UnFCR\\[1\\] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing."]
#[inline]
pub fn writing_a_logic_1_to(self) -> &'a mut W {
self.variant(RXFIFORESW::WRITING_A_LOGIC_1_TO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TXFIFORES`"]
pub enum TXFIFORESW {
#[doc = "No impact on either of UARTn FIFOs."]
NO_IMPACT_ON_EITHER_,
#[doc = "Writing a logic 1 to UnFCR\\[2\\] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing."]
WRITING_A_LOGIC_1_TO,
}
impl TXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TXFIFORESW::NO_IMPACT_ON_EITHER_ => false,
TXFIFORESW::WRITING_A_LOGIC_1_TO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TXFIFORESW<'a> {
w: &'a mut W,
}
impl<'a> _TXFIFORESW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TXFIFORESW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No impact on either of UARTn FIFOs."]
#[inline]
pub fn no_impact_on_either_(self) -> &'a mut W {
self.variant(TXFIFORESW::NO_IMPACT_ON_EITHER_)
}
#[doc = "Writing a logic 1 to UnFCR\\[2\\] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing."]
#[inline]
pub fn writing_a_logic_1_to(self) -> &'a mut W {
self.variant(TXFIFORESW::WRITING_A_LOGIC_1_TO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMAMODEW<'a> {
w: &'a mut W,
}
impl<'a> _DMAMODEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXTRIGLVL`"]
pub enum RXTRIGLVLW {
#[doc = "Trigger level 0 (1 character or 0x01)."]
TRIGGER_LEVEL_0_1_C,
#[doc = "Trigger level 1 (4 characters or 0x04)."]
TRIGGER_LEVEL_1_4_C,
#[doc = "Trigger level 2 (8 characters or 0x08)."]
TRIGGER_LEVEL_2_8_C,
#[doc = "Trigger level 3 (14 characters or 0x0E)."]
TRIGGER_LEVEL_3_14_,
}
impl RXTRIGLVLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
RXTRIGLVLW::TRIGGER_LEVEL_0_1_C => 0,
RXTRIGLVLW::TRIGGER_LEVEL_1_4_C => 1,
RXTRIGLVLW::TRIGGER_LEVEL_2_8_C => 2,
RXTRIGLVLW::TRIGGER_LEVEL_3_14_ => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _RXTRIGLVLW<'a> {
w: &'a mut W,
}
impl<'a> _RXTRIGLVLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXTRIGLVLW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Trigger level 0 (1 character or 0x01)."]
#[inline]
pub fn trigger_level_0_1_c(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_0_1_C)
}
#[doc = "Trigger level 1 (4 characters or 0x04)."]
#[inline]
pub fn trigger_level_1_4_c(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_1_4_C)
}
#[doc = "Trigger level 2 (8 characters or 0x08)."]
#[inline]
pub fn trigger_level_2_8_c(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_2_8_C)
}
#[doc = "Trigger level 3 (14 characters or 0x0E)."]
#[inline]
pub fn trigger_level_3_14_(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_3_14_)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - FIFO Enable."]
#[inline]
pub fn fifoen(&mut self) -> _FIFOENW {
_FIFOENW { w: self }
}
#[doc = "Bit 1 - RX FIFO Reset."]
#[inline]
pub fn rxfifores(&mut self) -> _RXFIFORESW {
_RXFIFORESW { w: self }
}
#[doc = "Bit 2 - TX FIFO Reset."]
#[inline]
pub fn txfifores(&mut self) -> _TXFIFORESW {
_TXFIFORESW { w: self }
}
#[doc = "Bit 3 - DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1."]
#[inline]
pub fn dmamode(&mut self) -> _DMAMODEW {
_DMAMODEW { w: self }
}
#[doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated."]
#[inline]
pub fn rxtriglvl(&mut self) -> _RXTRIGLVLW {
_RXTRIGLVLW { w: self }
}
}
}
#[doc = "Line Control Register. Contains controls for frame formatting and break generation."]
pub struct LCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Line Control Register. Contains controls for frame formatting and break generation."]
pub mod lcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::LCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `WLS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WLSR {
#[doc = "5-bit character length"]
_5_BIT_CHARACTER_LENG,
#[doc = "6-bit character length"]
_6_BIT_CHARACTER_LENG,
#[doc = "7-bit character length"]
_7_BIT_CHARACTER_LENG,
#[doc = "8-bit character length"]
_8_BIT_CHARACTER_LENG,
}
impl WLSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
WLSR::_5_BIT_CHARACTER_LENG => 0,
WLSR::_6_BIT_CHARACTER_LENG => 0x01,
WLSR::_7_BIT_CHARACTER_LENG => 0x02,
WLSR::_8_BIT_CHARACTER_LENG => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> WLSR {
match value {
0 => WLSR::_5_BIT_CHARACTER_LENG,
1 => WLSR::_6_BIT_CHARACTER_LENG,
2 => WLSR::_7_BIT_CHARACTER_LENG,
3 => WLSR::_8_BIT_CHARACTER_LENG,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_5_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_5_bit_character_leng(&self) -> bool {
*self == WLSR::_5_BIT_CHARACTER_LENG
}
#[doc = "Checks if the value of the field is `_6_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_6_bit_character_leng(&self) -> bool {
*self == WLSR::_6_BIT_CHARACTER_LENG
}
#[doc = "Checks if the value of the field is `_7_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_7_bit_character_leng(&self) -> bool {
*self == WLSR::_7_BIT_CHARACTER_LENG
}
#[doc = "Checks if the value of the field is `_8_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_8_bit_character_leng(&self) -> bool {
*self == WLSR::_8_BIT_CHARACTER_LENG
}
}
#[doc = "Possible values of the field `SBS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SBSR {
#[doc = "1 stop bit."]
_1_STOP_BIT_,
#[doc = "2 stop bits (1.5 if UnLCR\\[1:0\\]=00)."]
_2_STOP_BITS_1_5_IF_,
}
impl SBSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SBSR::_1_STOP_BIT_ => false,
SBSR::_2_STOP_BITS_1_5_IF_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SBSR {
match value {
false => SBSR::_1_STOP_BIT_,
true => SBSR::_2_STOP_BITS_1_5_IF_,
}
}
#[doc = "Checks if the value of the field is `_1_STOP_BIT_`"]
#[inline]
pub fn is_1_stop_bit_(&self) -> bool {
*self == SBSR::_1_STOP_BIT_
}
#[doc = "Checks if the value of the field is `_2_STOP_BITS_1_5_IF_`"]
#[inline]
pub fn is_2_stop_bits_1_5_if_(&self) -> bool {
*self == SBSR::_2_STOP_BITS_1_5_IF_
}
}
#[doc = "Possible values of the field `PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PER {
#[doc = "Disable parity generation and checking."]
DISABLE_PARITY_GENER,
#[doc = "Enable parity generation and checking."]
ENABLE_PARITY_GENERA,
}
impl PER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PER::DISABLE_PARITY_GENER => false,
PER::ENABLE_PARITY_GENERA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PER {
match value {
false => PER::DISABLE_PARITY_GENER,
true => PER::ENABLE_PARITY_GENERA,
}
}
#[doc = "Checks if the value of the field is `DISABLE_PARITY_GENER`"]
#[inline]
pub fn is_disable_parity_gener(&self) -> bool {
*self == PER::DISABLE_PARITY_GENER
}
#[doc = "Checks if the value of the field is `ENABLE_PARITY_GENERA`"]
#[inline]
pub fn is_enable_parity_genera(&self) -> bool {
*self == PER::ENABLE_PARITY_GENERA
}
}
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSR {
#[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
ODD_PARITY_NUMBER_O,
#[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
EVEN_PARITY_NUMBER_,
#[doc = "Forced 1 stick parity."]
FORCED_1_STICK_PARIT,
#[doc = "Forced 0 stick parity."]
FORCED_0_STICK_PARIT,
}
impl PSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PSR::ODD_PARITY_NUMBER_O => 0,
PSR::EVEN_PARITY_NUMBER_ => 0x01,
PSR::FORCED_1_STICK_PARIT => 0x02,
PSR::FORCED_0_STICK_PARIT => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PSR {
match value {
0 => PSR::ODD_PARITY_NUMBER_O,
1 => PSR::EVEN_PARITY_NUMBER_,
2 => PSR::FORCED_1_STICK_PARIT,
3 => PSR::FORCED_0_STICK_PARIT,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `ODD_PARITY_NUMBER_O`"]
#[inline]
pub fn is_odd_parity_number_o(&self) -> bool {
*self == PSR::ODD_PARITY_NUMBER_O
}
#[doc = "Checks if the value of the field is `EVEN_PARITY_NUMBER_`"]
#[inline]
pub fn is_even_parity_number_(&self) -> bool {
*self == PSR::EVEN_PARITY_NUMBER_
}
#[doc = "Checks if the value of the field is `FORCED_1_STICK_PARIT`"]
#[inline]
pub fn is_forced_1_stick_parit(&self) -> bool {
*self == PSR::FORCED_1_STICK_PARIT
}
#[doc = "Checks if the value of the field is `FORCED_0_STICK_PARIT`"]
#[inline]
pub fn is_forced_0_stick_parit(&self) -> bool {
*self == PSR::FORCED_0_STICK_PARIT
}
}
#[doc = "Possible values of the field `BC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BCR {
#[doc = "Disable break transmission."]
DISABLE_BREAK_TRANSM,
#[doc = "Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR\\[6\\] is active high."]
ENABLE_BREAK_TRANSMI,
}
impl BCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BCR::DISABLE_BREAK_TRANSM => false,
BCR::ENABLE_BREAK_TRANSMI => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BCR {
match value {
false => BCR::DISABLE_BREAK_TRANSM,
true => BCR::ENABLE_BREAK_TRANSMI,
}
}
#[doc = "Checks if the value of the field is `DISABLE_BREAK_TRANSM`"]
#[inline]
pub fn is_disable_break_transm(&self) -> bool {
*self == BCR::DISABLE_BREAK_TRANSM
}
#[doc = "Checks if the value of the field is `ENABLE_BREAK_TRANSMI`"]
#[inline]
pub fn is_enable_break_transmi(&self) -> bool {
*self == BCR::ENABLE_BREAK_TRANSMI
}
}
#[doc = "Possible values of the field `DLAB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DLABR {
#[doc = "Disable access to Divisor Latches."]
DISABLE_ACCESS_TO_DI,
#[doc = "Enable access to Divisor Latches."]
ENABLE_ACCESS_TO_DIV,
}
impl DLABR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DLABR::DISABLE_ACCESS_TO_DI => false,
DLABR::ENABLE_ACCESS_TO_DIV => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DLABR {
match value {
false => DLABR::DISABLE_ACCESS_TO_DI,
true => DLABR::ENABLE_ACCESS_TO_DIV,
}
}
#[doc = "Checks if the value of the field is `DISABLE_ACCESS_TO_DI`"]
#[inline]
pub fn is_disable_access_to_di(&self) -> bool {
*self == DLABR::DISABLE_ACCESS_TO_DI
}
#[doc = "Checks if the value of the field is `ENABLE_ACCESS_TO_DIV`"]
#[inline]
pub fn is_enable_access_to_div(&self) -> bool {
*self == DLABR::ENABLE_ACCESS_TO_DIV
}
}
#[doc = "Values that can be written to the field `WLS`"]
pub enum WLSW {
#[doc = "5-bit character length"]
_5_BIT_CHARACTER_LENG,
#[doc = "6-bit character length"]
_6_BIT_CHARACTER_LENG,
#[doc = "7-bit character length"]
_7_BIT_CHARACTER_LENG,
#[doc = "8-bit character length"]
_8_BIT_CHARACTER_LENG,
}
impl WLSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
WLSW::_5_BIT_CHARACTER_LENG => 0,
WLSW::_6_BIT_CHARACTER_LENG => 1,
WLSW::_7_BIT_CHARACTER_LENG => 2,
WLSW::_8_BIT_CHARACTER_LENG => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _WLSW<'a> {
w: &'a mut W,
}
impl<'a> _WLSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WLSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "5-bit character length"]
#[inline]
pub fn _5_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_5_BIT_CHARACTER_LENG)
}
#[doc = "6-bit character length"]
#[inline]
pub fn _6_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_6_BIT_CHARACTER_LENG)
}
#[doc = "7-bit character length"]
#[inline]
pub fn _7_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_7_BIT_CHARACTER_LENG)
}
#[doc = "8-bit character length"]
#[inline]
pub fn _8_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_8_BIT_CHARACTER_LENG)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SBS`"]
pub enum SBSW {
#[doc = "1 stop bit."]
_1_STOP_BIT_,
#[doc = "2 stop bits (1.5 if UnLCR\\[1:0\\]=00)."]
_2_STOP_BITS_1_5_IF_,
}
impl SBSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SBSW::_1_STOP_BIT_ => false,
SBSW::_2_STOP_BITS_1_5_IF_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SBSW<'a> {
w: &'a mut W,
}
impl<'a> _SBSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SBSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "1 stop bit."]
#[inline]
pub fn _1_stop_bit_(self) -> &'a mut W {
self.variant(SBSW::_1_STOP_BIT_)
}
#[doc = "2 stop bits (1.5 if UnLCR\\[1:0\\]=00)."]
#[inline]
pub fn _2_stop_bits_1_5_if_(self) -> &'a mut W {
self.variant(SBSW::_2_STOP_BITS_1_5_IF_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PE`"]
pub enum PEW {
#[doc = "Disable parity generation and checking."]
DISABLE_PARITY_GENER,
#[doc = "Enable parity generation and checking."]
ENABLE_PARITY_GENERA,
}
impl PEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PEW::DISABLE_PARITY_GENER => false,
PEW::ENABLE_PARITY_GENERA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PEW<'a> {
w: &'a mut W,
}
impl<'a> _PEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable parity generation and checking."]
#[inline]
pub fn disable_parity_gener(self) -> &'a mut W {
self.variant(PEW::DISABLE_PARITY_GENER)
}
#[doc = "Enable parity generation and checking."]
#[inline]
pub fn enable_parity_genera(self) -> &'a mut W {
self.variant(PEW::ENABLE_PARITY_GENERA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PS`"]
pub enum PSW {
#[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
ODD_PARITY_NUMBER_O,
#[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
EVEN_PARITY_NUMBER_,
#[doc = "Forced 1 stick parity."]
FORCED_1_STICK_PARIT,
#[doc = "Forced 0 stick parity."]
FORCED_0_STICK_PARIT,
}
impl PSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PSW::ODD_PARITY_NUMBER_O => 0,
PSW::EVEN_PARITY_NUMBER_ => 1,
PSW::FORCED_1_STICK_PARIT => 2,
PSW::FORCED_0_STICK_PARIT => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PSW<'a> {
w: &'a mut W,
}
impl<'a> _PSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
#[inline]
pub fn odd_parity_number_o(self) -> &'a mut W {
self.variant(PSW::ODD_PARITY_NUMBER_O)
}
#[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
#[inline]
pub fn even_parity_number_(self) -> &'a mut W {
self.variant(PSW::EVEN_PARITY_NUMBER_)
}
#[doc = "Forced 1 stick parity."]
#[inline]
pub fn forced_1_stick_parit(self) -> &'a mut W {
self.variant(PSW::FORCED_1_STICK_PARIT)
}
#[doc = "Forced 0 stick parity."]
#[inline]
pub fn forced_0_stick_parit(self) -> &'a mut W {
self.variant(PSW::FORCED_0_STICK_PARIT)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BC`"]
pub enum BCW {
#[doc = "Disable break transmission."]
DISABLE_BREAK_TRANSM,
#[doc = "Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR\\[6\\] is active high."]
ENABLE_BREAK_TRANSMI,
}
impl BCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BCW::DISABLE_BREAK_TRANSM => false,
BCW::ENABLE_BREAK_TRANSMI => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BCW<'a> {
w: &'a mut W,
}
impl<'a> _BCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BCW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable break transmission."]
#[inline]
pub fn disable_break_transm(self) -> &'a mut W {
self.variant(BCW::DISABLE_BREAK_TRANSM)
}
#[doc = "Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR\\[6\\] is active high."]
#[inline]
pub fn enable_break_transmi(self) -> &'a mut W {
self.variant(BCW::ENABLE_BREAK_TRANSMI)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DLAB`"]
pub enum DLABW {
#[doc = "Disable access to Divisor Latches."]
DISABLE_ACCESS_TO_DI,
#[doc = "Enable access to Divisor Latches."]
ENABLE_ACCESS_TO_DIV,
}
impl DLABW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DLABW::DISABLE_ACCESS_TO_DI => false,
DLABW::ENABLE_ACCESS_TO_DIV => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DLABW<'a> {
w: &'a mut W,
}
impl<'a> _DLABW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DLABW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable access to Divisor Latches."]
#[inline]
pub fn disable_access_to_di(self) -> &'a mut W {
self.variant(DLABW::DISABLE_ACCESS_TO_DI)
}
#[doc = "Enable access to Divisor Latches."]
#[inline]
pub fn enable_access_to_div(self) -> &'a mut W {
self.variant(DLABW::ENABLE_ACCESS_TO_DIV)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Word Length Select."]
#[inline]
pub fn wls(&self) -> WLSR {
WLSR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Stop Bit Select"]
#[inline]
pub fn sbs(&self) -> SBSR {
SBSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Parity Enable."]
#[inline]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 4:5 - Parity Select"]
#[inline]
pub fn ps(&self) -> PSR {
PSR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Break Control"]
#[inline]
pub fn bc(&self) -> BCR {
BCR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Divisor Latch Access Bit"]
#[inline]
pub fn dlab(&self) -> DLABR {
DLABR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Word Length Select."]
#[inline]
pub fn wls(&mut self) -> _WLSW {
_WLSW { w: self }
}
#[doc = "Bit 2 - Stop Bit Select"]
#[inline]
pub fn sbs(&mut self) -> _SBSW {
_SBSW { w: self }
}
#[doc = "Bit 3 - Parity Enable."]
#[inline]
pub fn pe(&mut self) -> _PEW {
_PEW { w: self }
}
#[doc = "Bits 4:5 - Parity Select"]
#[inline]
pub fn ps(&mut self) -> _PSW {
_PSW { w: self }
}
#[doc = "Bit 6 - Break Control"]
#[inline]
pub fn bc(&mut self) -> _BCW {
_BCW { w: self }
}
#[doc = "Bit 7 - Divisor Latch Access Bit"]
#[inline]
pub fn dlab(&mut self) -> _DLABW {
_DLABW { w: self }
}
}
}
#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
pub struct LSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
pub mod lsr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::LSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `RDR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RDRR {
#[doc = "The UARTn receiver FIFO is empty."]
EMPTY,
#[doc = "The UARTn receiver FIFO is not empty."]
NOTEMPTY,
}
impl RDRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RDRR::EMPTY => false,
RDRR::NOTEMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RDRR {
match value {
false => RDRR::EMPTY,
true => RDRR::NOTEMPTY,
}
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == RDRR::EMPTY
}
#[doc = "Checks if the value of the field is `NOTEMPTY`"]
#[inline]
pub fn is_notempty(&self) -> bool {
*self == RDRR::NOTEMPTY
}
}
#[doc = "Possible values of the field `OE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OER {
#[doc = "Overrun error status is inactive."]
INACTIVE,
#[doc = "Overrun error status is active."]
ACTIVE,
}
impl OER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OER::INACTIVE => false,
OER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OER {
match value {
false => OER::INACTIVE,
true => OER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == OER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == OER::ACTIVE
}
}
#[doc = "Possible values of the field `PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PER {
#[doc = "Parity error status is inactive."]
INACTIVE,
#[doc = "Parity error status is active."]
ACTIVE,
}
impl PER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PER::INACTIVE => false,
PER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PER {
match value {
false => PER::INACTIVE,
true => PER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == PER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == PER::ACTIVE
}
}
#[doc = "Possible values of the field `FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FER {
#[doc = "Framing error status is inactive."]
INACTIVE,
#[doc = "Framing error status is active."]
ACTIVE,
}
impl FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FER::INACTIVE => false,
FER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FER {
match value {
false => FER::INACTIVE,
true => FER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == FER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == FER::ACTIVE
}
}
#[doc = "Possible values of the field `BI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIR {
#[doc = "Break interrupt status is inactive."]
INACTIVE,
#[doc = "Break interrupt status is active."]
ACTIVE,
}
impl BIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BIR::INACTIVE => false,
BIR::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BIR {
match value {
false => BIR::INACTIVE,
true => BIR::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == BIR::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == BIR::ACTIVE
}
}
#[doc = "Possible values of the field `THRE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum THRER {
#[doc = "UnTHR contains valid data."]
VALIDDATA,
#[doc = "UnTHR is empty."]
EMPTY,
}
impl THRER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
THRER::VALIDDATA => false,
THRER::EMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> THRER {
match value {
false => THRER::VALIDDATA,
true => THRER::EMPTY,
}
}
#[doc = "Checks if the value of the field is `VALIDDATA`"]
#[inline]
pub fn is_validdata(&self) -> bool {
*self == THRER::VALIDDATA
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == THRER::EMPTY
}
}
#[doc = "Possible values of the field `TEMT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TEMTR {
#[doc = "UnTHR and/or the UnTSR contains valid data."]
VALIDDATA,
#[doc = "UnTHR and the UnTSR are empty."]
EMPTY,
}
impl TEMTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TEMTR::VALIDDATA => false,
TEMTR::EMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TEMTR {
match value {
false => TEMTR::VALIDDATA,
true => TEMTR::EMPTY,
}
}
#[doc = "Checks if the value of the field is `VALIDDATA`"]
#[inline]
pub fn is_validdata(&self) -> bool {
*self == TEMTR::VALIDDATA
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == TEMTR::EMPTY
}
}
#[doc = "Possible values of the field `RXFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXFER {
#[doc = "UnRBR contains no UARTn RX errors or UnFCR\\[0\\]=0."]
NOERROR,
#[doc = "UARTn RBR contains at least one UARTn RX error."]
ERRORS,
}
impl RXFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RXFER::NOERROR => false,
RXFER::ERRORS => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RXFER {
match value {
false => RXFER::NOERROR,
true => RXFER::ERRORS,
}
}
#[doc = "Checks if the value of the field is `NOERROR`"]
#[inline]
pub fn is_noerror(&self) -> bool {
*self == RXFER::NOERROR
}
#[doc = "Checks if the value of the field is `ERRORS`"]
#[inline]
pub fn is_errors(&self) -> bool {
*self == RXFER::ERRORS
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receiver Data Ready. UnLSR\\[0\\] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty."]
#[inline]
pub fn rdr(&self) -> RDRR {
RDRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR\\[1\\]. UnLSR\\[1\\] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost."]
#[inline]
pub fn oe(&self) -> OER {
OER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR\\[2\\]. Time of parity error detection is dependent on UnFCR\\[0\\]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO."]
#[inline]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR\\[3\\]. The time of the framing error detection is dependent on UnFCR\\[0\\]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO."]
#[inline]
pub fn fe(&self) -> FER {
FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR\\[0\\]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO."]
#[inline]
pub fn bi(&self) -> BIR {
BIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write."]
#[inline]
pub fn thre(&self) -> THRER {
THRER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data."]
#[inline]
pub fn temt(&self) -> TEMTR {
TEMTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Error in RX FIFO . UnLSR\\[7\\] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO."]
#[inline]
pub fn rxfe(&self) -> RXFER {
RXFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "Scratch Pad Register. 8-bit temporary storage for software."]
pub struct SCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Scratch Pad Register. 8-bit temporary storage for software."]
pub mod scr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PADR {
bits: u8,
}
impl PADR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PADW<'a> {
w: &'a mut W,
}
impl<'a> _PADW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - A readable, writable byte."]
#[inline]
pub fn pad(&self) -> PADR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PADR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - A readable, writable byte."]
#[inline]
pub fn pad(&mut self) -> _PADW {
_PADW { w: self }
}
}
}
#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature."]
pub struct ACR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature."]
pub mod acr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ACR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `START`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum STARTR {
#[doc = "Auto-baud stop (auto-baud is not running)."]
AUTO_BAUD_STOP_AUTO,
#[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
AUTO_BAUD_START_AUT,
}
impl STARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
STARTR::AUTO_BAUD_STOP_AUTO => false,
STARTR::AUTO_BAUD_START_AUT => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> STARTR {
match value {
false => STARTR::AUTO_BAUD_STOP_AUTO,
true => STARTR::AUTO_BAUD_START_AUT,
}
}
#[doc = "Checks if the value of the field is `AUTO_BAUD_STOP_AUTO`"]
#[inline]
pub fn is_auto_baud_stop_auto(&self) -> bool {
*self == STARTR::AUTO_BAUD_STOP_AUTO
}
#[doc = "Checks if the value of the field is `AUTO_BAUD_START_AUT`"]
#[inline]
pub fn is_auto_baud_start_aut(&self) -> bool {
*self == STARTR::AUTO_BAUD_START_AUT
}
}
#[doc = "Possible values of the field `MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MODER {
#[doc = "Mode 0."]
MODE_0_,
#[doc = "Mode 1."]
MODE_1_,
}
impl MODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MODER::MODE_0_ => false,
MODER::MODE_1_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MODER {
match value {
false => MODER::MODE_0_,
true => MODER::MODE_1_,
}
}
#[doc = "Checks if the value of the field is `MODE_0_`"]
#[inline]
pub fn is_mode_0_(&self) -> bool {
*self == MODER::MODE_0_
}
#[doc = "Checks if the value of the field is `MODE_1_`"]
#[inline]
pub fn is_mode_1_(&self) -> bool {
*self == MODER::MODE_1_
}
}
#[doc = "Possible values of the field `AUTORESTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AUTORESTARTR {
#[doc = "No restart."]
NO_RESTART_,
#[doc = "Restart in case of time-out (counter restarts at next UARTn Rx falling edge)"]
RESTART_IN_CASE_OF_T,
}
impl AUTORESTARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AUTORESTARTR::NO_RESTART_ => false,
AUTORESTARTR::RESTART_IN_CASE_OF_T => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AUTORESTARTR {
match value {
false => AUTORESTARTR::NO_RESTART_,
true => AUTORESTARTR::RESTART_IN_CASE_OF_T,
}
}
#[doc = "Checks if the value of the field is `NO_RESTART_`"]
#[inline]
pub fn is_no_restart_(&self) -> bool {
*self == AUTORESTARTR::NO_RESTART_
}
#[doc = "Checks if the value of the field is `RESTART_IN_CASE_OF_T`"]
#[inline]
pub fn is_restart_in_case_of_t(&self) -> bool {
*self == AUTORESTARTR::RESTART_IN_CASE_OF_T
}
}
#[doc = "Possible values of the field `ABEOINTCLR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABEOINTCLRR {
#[doc = "No impact."]
NO_IMPACT_,
#[doc = "Clear the corresponding interrupt in the IIR."]
CLEAR_THE_CORRESPOND,
}
impl ABEOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABEOINTCLRR::NO_IMPACT_ => false,
ABEOINTCLRR::CLEAR_THE_CORRESPOND => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABEOINTCLRR {
match value {
false => ABEOINTCLRR::NO_IMPACT_,
true => ABEOINTCLRR::CLEAR_THE_CORRESPOND,
}
}
#[doc = "Checks if the value of the field is `NO_IMPACT_`"]
#[inline]
pub fn is_no_impact_(&self) -> bool {
*self == ABEOINTCLRR::NO_IMPACT_
}
#[doc = "Checks if the value of the field is `CLEAR_THE_CORRESPOND`"]
#[inline]
pub fn is_clear_the_correspond(&self) -> bool {
*self == ABEOINTCLRR::CLEAR_THE_CORRESPOND
}
}
#[doc = "Possible values of the field `ABTOINTCLR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABTOINTCLRR {
#[doc = "No impact."]
NO_IMPACT_,
#[doc = "Clear the corresponding interrupt in the IIR."]
CLEAR_THE_CORRESPOND,
}
impl ABTOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABTOINTCLRR::NO_IMPACT_ => false,
ABTOINTCLRR::CLEAR_THE_CORRESPOND => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABTOINTCLRR {
match value {
false => ABTOINTCLRR::NO_IMPACT_,
true => ABTOINTCLRR::CLEAR_THE_CORRESPOND,
}
}
#[doc = "Checks if the value of the field is `NO_IMPACT_`"]
#[inline]
pub fn is_no_impact_(&self) -> bool {
*self == ABTOINTCLRR::NO_IMPACT_
}
#[doc = "Checks if the value of the field is `CLEAR_THE_CORRESPOND`"]
#[inline]
pub fn is_clear_the_correspond(&self) -> bool {
*self == ABTOINTCLRR::CLEAR_THE_CORRESPOND
}
}
#[doc = "Values that can be written to the field `START`"]
pub enum STARTW {
#[doc = "Auto-baud stop (auto-baud is not running)."]
AUTO_BAUD_STOP_AUTO,
#[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
AUTO_BAUD_START_AUT,
}
impl STARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
STARTW::AUTO_BAUD_STOP_AUTO => false,
STARTW::AUTO_BAUD_START_AUT => true,
}
}
}
#[doc = r" Proxy"]
pub struct _STARTW<'a> {
w: &'a mut W,
}
impl<'a> _STARTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Auto-baud stop (auto-baud is not running)."]
#[inline]
pub fn auto_baud_stop_auto(self) -> &'a mut W {
self.variant(STARTW::AUTO_BAUD_STOP_AUTO)
}
#[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
#[inline]
pub fn auto_baud_start_aut(self) -> &'a mut W {
self.variant(STARTW::AUTO_BAUD_START_AUT)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "Mode 0."]
MODE_0_,
#[doc = "Mode 1."]
MODE_1_,
}
impl MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MODEW::MODE_0_ => false,
MODEW::MODE_1_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MODEW<'a> {
w: &'a mut W,
}
impl<'a> _MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MODEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Mode 0."]
#[inline]
pub fn mode_0_(self) -> &'a mut W {
self.variant(MODEW::MODE_0_)
}
#[doc = "Mode 1."]
#[inline]
pub fn mode_1_(self) -> &'a mut W {
self.variant(MODEW::MODE_1_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AUTORESTART`"]
pub enum AUTORESTARTW {
#[doc = "No restart."]
NO_RESTART_,
#[doc = "Restart in case of time-out (counter restarts at next UARTn Rx falling edge)"]
RESTART_IN_CASE_OF_T,
}
impl AUTORESTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AUTORESTARTW::NO_RESTART_ => false,
AUTORESTARTW::RESTART_IN_CASE_OF_T => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AUTORESTARTW<'a> {
w: &'a mut W,
}
impl<'a> _AUTORESTARTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AUTORESTARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No restart."]
#[inline]
pub fn no_restart_(self) -> &'a mut W {
self.variant(AUTORESTARTW::NO_RESTART_)
}
#[doc = "Restart in case of time-out (counter restarts at next UARTn Rx falling edge)"]
#[inline]
pub fn restart_in_case_of_t(self) -> &'a mut W {
self.variant(AUTORESTARTW::RESTART_IN_CASE_OF_T)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABEOINTCLR`"]
pub enum ABEOINTCLRW {
#[doc = "No impact."]
NO_IMPACT_,
#[doc = "Clear the corresponding interrupt in the IIR."]
CLEAR_THE_CORRESPOND,
}
impl ABEOINTCLRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABEOINTCLRW::NO_IMPACT_ => false,
ABEOINTCLRW::CLEAR_THE_CORRESPOND => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABEOINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABEOINTCLRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABEOINTCLRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No impact."]
#[inline]
pub fn no_impact_(self) -> &'a mut W {
self.variant(ABEOINTCLRW::NO_IMPACT_)
}
#[doc = "Clear the corresponding interrupt in the IIR."]
#[inline]
pub fn clear_the_correspond(self) -> &'a mut W {
self.variant(ABEOINTCLRW::CLEAR_THE_CORRESPOND)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABTOINTCLR`"]
pub enum ABTOINTCLRW {
#[doc = "No impact."]
NO_IMPACT_,
#[doc = "Clear the corresponding interrupt in the IIR."]
CLEAR_THE_CORRESPOND,
}
impl ABTOINTCLRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABTOINTCLRW::NO_IMPACT_ => false,
ABTOINTCLRW::CLEAR_THE_CORRESPOND => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABTOINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABTOINTCLRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABTOINTCLRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No impact."]
#[inline]
pub fn no_impact_(self) -> &'a mut W {
self.variant(ABTOINTCLRW::NO_IMPACT_)
}
#[doc = "Clear the corresponding interrupt in the IIR."]
#[inline]
pub fn clear_the_correspond(self) -> &'a mut W {
self.variant(ABTOINTCLRW::CLEAR_THE_CORRESPOND)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion."]
#[inline]
pub fn start(&self) -> STARTR {
STARTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Auto-baud mode select bit."]
#[inline]
pub fn mode(&self) -> MODER {
MODER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Restart bit."]
#[inline]
pub fn autorestart(&self) -> AUTORESTARTR {
AUTORESTARTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."]
#[inline]
pub fn abeointclr(&self) -> ABEOINTCLRR {
ABEOINTCLRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."]
#[inline]
pub fn abtointclr(&self) -> ABTOINTCLRR {
ABTOINTCLRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion."]
#[inline]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
#[doc = "Bit 1 - Auto-baud mode select bit."]
#[inline]
pub fn mode(&mut self) -> _MODEW {
_MODEW { w: self }
}
#[doc = "Bit 2 - Restart bit."]
#[inline]
pub fn autorestart(&mut self) -> _AUTORESTARTW {
_AUTORESTARTW { w: self }
}
#[doc = "Bit 8 - End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."]
#[inline]
pub fn abeointclr(&mut self) -> _ABEOINTCLRW {
_ABEOINTCLRW { w: self }
}
#[doc = "Bit 9 - Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact."]
#[inline]
pub fn abtointclr(&mut self) -> _ABTOINTCLRW {
_ABTOINTCLRW { w: self }
}
}
}
#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider."]
pub struct FDR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider."]
pub mod fdr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FDR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DIVADDVALR {
bits: u8,
}
impl DIVADDVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MULVALR {
bits: u8,
}
impl MULVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DIVADDVALW<'a> {
w: &'a mut W,
}
impl<'a> _DIVADDVALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MULVALW<'a> {
w: &'a mut W,
}
impl<'a> _MULVALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate."]
#[inline]
pub fn divaddval(&self) -> DIVADDVALR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DIVADDVALR { bits }
}
#[doc = "Bits 4:7 - Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not."]
#[inline]
pub fn mulval(&self) -> MULVALR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MULVALR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x10 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate."]
#[inline]
pub fn divaddval(&mut self) -> _DIVADDVALW {
_DIVADDVALW { w: self }
}
#[doc = "Bits 4:7 - Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not."]
#[inline]
pub fn mulval(&mut self) -> _MULVALW {
_MULVALW { w: self }
}
}
}
#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
pub struct TER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
pub mod ter {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXENR {
bits: bool,
}
impl TXENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _TXENW<'a> {
w: &'a mut W,
}
impl<'a> _TXENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character."]
#[inline]
pub fn txen(&self) -> TXENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x80 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character."]
#[inline]
pub fn txen(&mut self) -> _TXENW {
_TXENW { w: self }
}
}
}
#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
pub struct RS485CTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
pub mod rs485ctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RS485CTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `NMMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NMMENR {
#[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
DISABLED,
#[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation."]
ENABLED,
}
impl NMMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
NMMENR::DISABLED => false,
NMMENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> NMMENR {
match value {
false => NMMENR::DISABLED,
true => NMMENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == NMMENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == NMMENR::ENABLED
}
}
#[doc = "Possible values of the field `RXDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXDISR {
#[doc = "The receiver is enabled."]
ENABLED,
#[doc = "The receiver is disabled."]
DISABLED,
}
impl RXDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RXDISR::ENABLED => false,
RXDISR::DISABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RXDISR {
match value {
false => RXDISR::ENABLED,
true => RXDISR::DISABLED,
}
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == RXDISR::ENABLED
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == RXDISR::DISABLED
}
}
#[doc = "Possible values of the field `AADEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AADENR {
#[doc = "Auto Address Detect (AAD) is disabled."]
DISABLED,
#[doc = "Auto Address Detect (AAD) is enabled."]
ENABLED,
}
impl AADENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AADENR::DISABLED => false,
AADENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AADENR {
match value {
false => AADENR::DISABLED,
true => AADENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == AADENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == AADENR::ENABLED
}
}
#[doc = "Possible values of the field `DCTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCTRLR {
#[doc = "Disable Auto Direction Control."]
DISABLE_AUTO_DIRECTI,
#[doc = "Enable Auto Direction Control."]
ENABLE_AUTO_DIRECTIO,
}
impl DCTRLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCTRLR::DISABLE_AUTO_DIRECTI => false,
DCTRLR::ENABLE_AUTO_DIRECTIO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCTRLR {
match value {
false => DCTRLR::DISABLE_AUTO_DIRECTI,
true => DCTRLR::ENABLE_AUTO_DIRECTIO,
}
}
#[doc = "Checks if the value of the field is `DISABLE_AUTO_DIRECTI`"]
#[inline]
pub fn is_disable_auto_directi(&self) -> bool {
*self == DCTRLR::DISABLE_AUTO_DIRECTI
}
#[doc = "Checks if the value of the field is `ENABLE_AUTO_DIRECTIO`"]
#[inline]
pub fn is_enable_auto_directio(&self) -> bool {
*self == DCTRLR::ENABLE_AUTO_DIRECTIO
}
}
#[doc = "Possible values of the field `OINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OINVR {
#[doc = "The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
DIRLOW,
#[doc = "The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
DIRHIGH,
}
impl OINVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OINVR::DIRLOW => false,
OINVR::DIRHIGH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OINVR {
match value {
false => OINVR::DIRLOW,
true => OINVR::DIRHIGH,
}
}
#[doc = "Checks if the value of the field is `DIRLOW`"]
#[inline]
pub fn is_dirlow(&self) -> bool {
*self == OINVR::DIRLOW
}
#[doc = "Checks if the value of the field is `DIRHIGH`"]
#[inline]
pub fn is_dirhigh(&self) -> bool {
*self == OINVR::DIRHIGH
}
}
#[doc = "Values that can be written to the field `NMMEN`"]
pub enum NMMENW {
#[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
DISABLED,
#[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation."]
ENABLED,
}
impl NMMENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
NMMENW::DISABLED => false,
NMMENW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _NMMENW<'a> {
w: &'a mut W,
}
impl<'a> _NMMENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: NMMENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(NMMENW::DISABLED)
}
#[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(NMMENW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXDIS`"]
pub enum RXDISW {
#[doc = "The receiver is enabled."]
ENABLED,
#[doc = "The receiver is disabled."]
DISABLED,
}
impl RXDISW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RXDISW::ENABLED => false,
RXDISW::DISABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RXDISW<'a> {
w: &'a mut W,
}
impl<'a> _RXDISW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXDISW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The receiver is enabled."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(RXDISW::ENABLED)
}
#[doc = "The receiver is disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(RXDISW::DISABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AADEN`"]
pub enum AADENW {
#[doc = "Auto Address Detect (AAD) is disabled."]
DISABLED,
#[doc = "Auto Address Detect (AAD) is enabled."]
ENABLED,
}
impl AADENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AADENW::DISABLED => false,
AADENW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AADENW<'a> {
w: &'a mut W,
}
impl<'a> _AADENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AADENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Auto Address Detect (AAD) is disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(AADENW::DISABLED)
}
#[doc = "Auto Address Detect (AAD) is enabled."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(AADENW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DCTRL`"]
pub enum DCTRLW {
#[doc = "Disable Auto Direction Control."]
DISABLE_AUTO_DIRECTI,
#[doc = "Enable Auto Direction Control."]
ENABLE_AUTO_DIRECTIO,
}
impl DCTRLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DCTRLW::DISABLE_AUTO_DIRECTI => false,
DCTRLW::ENABLE_AUTO_DIRECTIO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _DCTRLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DCTRLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable Auto Direction Control."]
#[inline]
pub fn disable_auto_directi(self) -> &'a mut W {
self.variant(DCTRLW::DISABLE_AUTO_DIRECTI)
}
#[doc = "Enable Auto Direction Control."]
#[inline]
pub fn enable_auto_directio(self) -> &'a mut W {
self.variant(DCTRLW::ENABLE_AUTO_DIRECTIO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `OINV`"]
pub enum OINVW {
#[doc = "The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
DIRLOW,
#[doc = "The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
DIRHIGH,
}
impl OINVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OINVW::DIRLOW => false,
OINVW::DIRHIGH => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OINVW<'a> {
w: &'a mut W,
}
impl<'a> _OINVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OINVW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
#[inline]
pub fn dirlow(self) -> &'a mut W {
self.variant(OINVW::DIRLOW)
}
#[doc = "The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
#[inline]
pub fn dirhigh(self) -> &'a mut W {
self.variant(OINVW::DIRHIGH)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - NMM enable."]
#[inline]
pub fn nmmen(&self) -> NMMENR {
NMMENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Receiver enable."]
#[inline]
pub fn rxdis(&self) -> RXDISR {
RXDISR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - AAD enable."]
#[inline]
pub fn aaden(&self) -> AADENR {
AADENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Direction control enable."]
#[inline]
pub fn dctrl(&self) -> DCTRLR {
DCTRLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."]
#[inline]
pub fn oinv(&self) -> OINVR {
OINVR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - NMM enable."]
#[inline]
pub fn nmmen(&mut self) -> _NMMENW {
_NMMENW { w: self }
}
#[doc = "Bit 1 - Receiver enable."]
#[inline]
pub fn rxdis(&mut self) -> _RXDISW {
_RXDISW { w: self }
}
#[doc = "Bit 2 - AAD enable."]
#[inline]
pub fn aaden(&mut self) -> _AADENW {
_AADENW { w: self }
}
#[doc = "Bit 4 - Direction control enable."]
#[inline]
pub fn dctrl(&mut self) -> _DCTRLW {
_DCTRLW { w: self }
}
#[doc = "Bit 5 - Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin."]
#[inline]
pub fn oinv(&mut self) -> _OINVW {
_OINVW { w: self }
}
}
}
#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
pub struct RS485ADRMATCH {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
pub mod rs485adrmatch {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RS485ADRMATCH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADRMATCHR {
bits: u8,
}
impl ADRMATCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADRMATCHW<'a> {
w: &'a mut W,
}
impl<'a> _ADRMATCHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Contains the address match value."]
#[inline]
pub fn adrmatch(&self) -> ADRMATCHR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ADRMATCHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Contains the address match value."]
#[inline]
pub fn adrmatch(&mut self) -> _ADRMATCHW {
_ADRMATCHW { w: self }
}
}
}
#[doc = "RS-485/EIA-485 direction control delay."]
pub struct RS485DLY {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RS-485/EIA-485 direction control delay."]
pub mod rs485dly {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RS485DLY {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DLYR {
bits: u8,
}
impl DLYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DLYW<'a> {
w: &'a mut W,
}
impl<'a> _DLYW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter."]
#[inline]
pub fn dly(&self) -> DLYR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLYR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter."]
#[inline]
pub fn dly(&mut self) -> _DLYW {
_DLYW { w: self }
}
}
}
}
#[doc = "UART1"]
pub struct UART1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART1 {}
impl UART1 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const uart1::RegisterBlock {
0x4001_0000 as *const _
}
}
impl Deref for UART1 {
type Target = uart1::RegisterBlock;
fn deref(&self) -> &uart1::RegisterBlock {
unsafe { &*UART1::ptr() }
}
}
#[doc = "UART1"]
pub mod uart1 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. DLAB =0 Receiver Buffer Register. Contains the next received character to be read."]
pub dll: DLL_UNION,
#[doc = "DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub dlm: DLM_UNION,
#[doc = "FIFO Control Register. Controls UART1 FIFO usage and modes. Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub fcr: FCR_UNION,
#[doc = "0x0c - Line Control Register. Contains controls for frame formatting and break generation."]
pub lcr: LCR,
#[doc = "0x10 - Modem Control Register. Contains controls for flow control handshaking and loopback mode."]
pub mcr: MCR,
#[doc = "0x14 - Line Status Register. Contains flags for transmit and receive status, including line errors."]
pub lsr: LSR,
#[doc = "0x18 - Modem Status Register. Contains handshake signal status flags."]
pub msr: MSR,
#[doc = "0x1c - Scratch Pad Register. 8-bit temporary storage for software."]
pub scr: SCR,
#[doc = "0x20 - Auto-baud Control Register. Contains controls for the auto-baud feature."]
pub acr: ACR,
_reserved9: [u8; 4usize],
#[doc = "0x28 - Fractional Divider Register. Generates a clock input for the baud rate divider."]
pub fdr: FDR,
_reserved10: [u8; 4usize],
#[doc = "0x30 - Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
pub ter: TER,
_reserved11: [u8; 24usize],
#[doc = "0x4c - RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
pub rs485ctrl: RS485CTRL,
#[doc = "0x50 - RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
pub rs485adrmatch: RS485ADRMATCH,
#[doc = "0x54 - RS-485/EIA-485 direction control delay."]
pub rs485dly: RS485DLY,
}
#[doc = "DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. DLAB =0 Receiver Buffer Register. Contains the next received character to be read."]
#[repr(C)]
pub union DLL_UNION {
#[doc = "0x00 - DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub dll: DLL,
#[doc = "0x00 - DLAB =0. Transmit Holding Register. The next character to be transmitted is written here."]
pub thr: THR,
#[doc = "0x00 - DLAB =0 Receiver Buffer Register. Contains the next received character to be read."]
pub rbr: RBR,
}
#[doc = "DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
#[repr(C)]
pub union DLM_UNION {
#[doc = "0x04 - DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts."]
pub ier: IER,
#[doc = "0x04 - DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub dlm: DLM,
}
#[doc = "FIFO Control Register. Controls UART1 FIFO usage and modes. Interrupt ID Register. Identifies which interrupt(s) are pending."]
#[repr(C)]
pub union FCR_UNION {
#[doc = "0x08 - FIFO Control Register. Controls UART1 FIFO usage and modes."]
pub fcr: FCR,
#[doc = "0x08 - Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub iir: IIR,
}
#[doc = "DLAB =0 Receiver Buffer Register. Contains the next received character to be read."]
pub struct RBR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DLAB =0 Receiver Buffer Register. Contains the next received character to be read."]
pub mod rbr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RBR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RBRR {
bits: u8,
}
impl RBRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO."]
#[inline]
pub fn rbr(&self) -> RBRR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RBRR { bits }
}
}
}
#[doc = "DLAB =0. Transmit Holding Register. The next character to be transmitted is written here."]
pub struct THR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DLAB =0. Transmit Holding Register. The next character to be transmitted is written here."]
pub mod thr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::THR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _THRW<'a> {
w: &'a mut W,
}
impl<'a> _THRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available."]
#[inline]
pub fn thr(&mut self) -> _THRW {
_THRW { w: self }
}
}
}
#[doc = "DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub struct DLL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub mod dll {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DLL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DLLSBR {
bits: u8,
}
impl DLLSBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DLLSBW<'a> {
w: &'a mut W,
}
impl<'a> _DLLSBW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1."]
#[inline]
pub fn dllsb(&self) -> DLLSBR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLLSBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x01 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1."]
#[inline]
pub fn dllsb(&mut self) -> _DLLSBW {
_DLLSBW { w: self }
}
}
}
#[doc = "DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub struct DLM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider."]
pub mod dlm {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DLM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DLMSBR {
bits: u8,
}
impl DLMSBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DLMSBW<'a> {
w: &'a mut W,
}
impl<'a> _DLMSBW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1."]
#[inline]
pub fn dlmsb(&self) -> DLMSBR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLMSBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1."]
#[inline]
pub fn dlmsb(&mut self) -> _DLMSBW {
_DLMSBW { w: self }
}
}
}
#[doc = "DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts."]
pub struct IER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts."]
pub mod ier {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RBRIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RBRIER {
#[doc = "Disable the RDA interrupts."]
DISABLE_THE_RDA_INTE,
#[doc = "Enable the RDA interrupts."]
ENABLE_THE_RDA_INTER,
}
impl RBRIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RBRIER::DISABLE_THE_RDA_INTE => false,
RBRIER::ENABLE_THE_RDA_INTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RBRIER {
match value {
false => RBRIER::DISABLE_THE_RDA_INTE,
true => RBRIER::ENABLE_THE_RDA_INTER,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_RDA_INTE`"]
#[inline]
pub fn is_disable_the_rda_inte(&self) -> bool {
*self == RBRIER::DISABLE_THE_RDA_INTE
}
#[doc = "Checks if the value of the field is `ENABLE_THE_RDA_INTER`"]
#[inline]
pub fn is_enable_the_rda_inter(&self) -> bool {
*self == RBRIER::ENABLE_THE_RDA_INTER
}
}
#[doc = "Possible values of the field `THREIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum THREIER {
#[doc = "Disable the THRE interrupts."]
DISABLE_THE_THRE_INT,
#[doc = "Enable the THRE interrupts."]
ENABLE_THE_THRE_INTE,
}
impl THREIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
THREIER::DISABLE_THE_THRE_INT => false,
THREIER::ENABLE_THE_THRE_INTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> THREIER {
match value {
false => THREIER::DISABLE_THE_THRE_INT,
true => THREIER::ENABLE_THE_THRE_INTE,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_THRE_INT`"]
#[inline]
pub fn is_disable_the_thre_int(&self) -> bool {
*self == THREIER::DISABLE_THE_THRE_INT
}
#[doc = "Checks if the value of the field is `ENABLE_THE_THRE_INTE`"]
#[inline]
pub fn is_enable_the_thre_inte(&self) -> bool {
*self == THREIER::ENABLE_THE_THRE_INTE
}
}
#[doc = "Possible values of the field `RXIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXIER {
#[doc = "Disable the RX line status interrupts."]
DISABLE_THE_RX_LINE_,
#[doc = "Enable the RX line status interrupts."]
ENABLE_THE_RX_LINE_S,
}
impl RXIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RXIER::DISABLE_THE_RX_LINE_ => false,
RXIER::ENABLE_THE_RX_LINE_S => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RXIER {
match value {
false => RXIER::DISABLE_THE_RX_LINE_,
true => RXIER::ENABLE_THE_RX_LINE_S,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_RX_LINE_`"]
#[inline]
pub fn is_disable_the_rx_line_(&self) -> bool {
*self == RXIER::DISABLE_THE_RX_LINE_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_RX_LINE_S`"]
#[inline]
pub fn is_enable_the_rx_line_s(&self) -> bool {
*self == RXIER::ENABLE_THE_RX_LINE_S
}
}
#[doc = "Possible values of the field `MSIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MSIER {
#[doc = "Disable the modem interrupt."]
DISABLE_THE_MODEM_IN,
#[doc = "Enable the modem interrupt."]
ENABLE_THE_MODEM_INT,
}
impl MSIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MSIER::DISABLE_THE_MODEM_IN => false,
MSIER::ENABLE_THE_MODEM_INT => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MSIER {
match value {
false => MSIER::DISABLE_THE_MODEM_IN,
true => MSIER::ENABLE_THE_MODEM_INT,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_MODEM_IN`"]
#[inline]
pub fn is_disable_the_modem_in(&self) -> bool {
*self == MSIER::DISABLE_THE_MODEM_IN
}
#[doc = "Checks if the value of the field is `ENABLE_THE_MODEM_INT`"]
#[inline]
pub fn is_enable_the_modem_int(&self) -> bool {
*self == MSIER::ENABLE_THE_MODEM_INT
}
}
#[doc = "Possible values of the field `CTSIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CTSIER {
#[doc = "Disable the CTS interrupt."]
DISABLE_THE_CTS_INTE,
#[doc = "Enable the CTS interrupt."]
ENABLE_THE_CTS_INTER,
}
impl CTSIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CTSIER::DISABLE_THE_CTS_INTE => false,
CTSIER::ENABLE_THE_CTS_INTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CTSIER {
match value {
false => CTSIER::DISABLE_THE_CTS_INTE,
true => CTSIER::ENABLE_THE_CTS_INTER,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_CTS_INTE`"]
#[inline]
pub fn is_disable_the_cts_inte(&self) -> bool {
*self == CTSIER::DISABLE_THE_CTS_INTE
}
#[doc = "Checks if the value of the field is `ENABLE_THE_CTS_INTER`"]
#[inline]
pub fn is_enable_the_cts_inter(&self) -> bool {
*self == CTSIER::ENABLE_THE_CTS_INTER
}
}
#[doc = "Possible values of the field `ABEOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABEOIER {
#[doc = "Disable end of auto-baud Interrupt."]
DISABLE_END_OF_AUTO_,
#[doc = "Enable end of auto-baud Interrupt."]
ENABLE_END_OF_AUTO_B,
}
impl ABEOIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABEOIER::DISABLE_END_OF_AUTO_ => false,
ABEOIER::ENABLE_END_OF_AUTO_B => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABEOIER {
match value {
false => ABEOIER::DISABLE_END_OF_AUTO_,
true => ABEOIER::ENABLE_END_OF_AUTO_B,
}
}
#[doc = "Checks if the value of the field is `DISABLE_END_OF_AUTO_`"]
#[inline]
pub fn is_disable_end_of_auto_(&self) -> bool {
*self == ABEOIER::DISABLE_END_OF_AUTO_
}
#[doc = "Checks if the value of the field is `ENABLE_END_OF_AUTO_B`"]
#[inline]
pub fn is_enable_end_of_auto_b(&self) -> bool {
*self == ABEOIER::ENABLE_END_OF_AUTO_B
}
}
#[doc = "Possible values of the field `ABTOIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABTOIER {
#[doc = "Disable auto-baud time-out Interrupt."]
DISABLE_AUTO_BAUD_TI,
#[doc = "Enable auto-baud time-out Interrupt."]
ENABLE_AUTO_BAUD_TIM,
}
impl ABTOIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABTOIER::DISABLE_AUTO_BAUD_TI => false,
ABTOIER::ENABLE_AUTO_BAUD_TIM => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABTOIER {
match value {
false => ABTOIER::DISABLE_AUTO_BAUD_TI,
true => ABTOIER::ENABLE_AUTO_BAUD_TIM,
}
}
#[doc = "Checks if the value of the field is `DISABLE_AUTO_BAUD_TI`"]
#[inline]
pub fn is_disable_auto_baud_ti(&self) -> bool {
*self == ABTOIER::DISABLE_AUTO_BAUD_TI
}
#[doc = "Checks if the value of the field is `ENABLE_AUTO_BAUD_TIM`"]
#[inline]
pub fn is_enable_auto_baud_tim(&self) -> bool {
*self == ABTOIER::ENABLE_AUTO_BAUD_TIM
}
}
#[doc = "Values that can be written to the field `RBRIE`"]
pub enum RBRIEW {
#[doc = "Disable the RDA interrupts."]
DISABLE_THE_RDA_INTE,
#[doc = "Enable the RDA interrupts."]
ENABLE_THE_RDA_INTER,
}
impl RBRIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RBRIEW::DISABLE_THE_RDA_INTE => false,
RBRIEW::ENABLE_THE_RDA_INTER => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RBRIEW<'a> {
w: &'a mut W,
}
impl<'a> _RBRIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RBRIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the RDA interrupts."]
#[inline]
pub fn disable_the_rda_inte(self) -> &'a mut W {
self.variant(RBRIEW::DISABLE_THE_RDA_INTE)
}
#[doc = "Enable the RDA interrupts."]
#[inline]
pub fn enable_the_rda_inter(self) -> &'a mut W {
self.variant(RBRIEW::ENABLE_THE_RDA_INTER)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `THREIE`"]
pub enum THREIEW {
#[doc = "Disable the THRE interrupts."]
DISABLE_THE_THRE_INT,
#[doc = "Enable the THRE interrupts."]
ENABLE_THE_THRE_INTE,
}
impl THREIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
THREIEW::DISABLE_THE_THRE_INT => false,
THREIEW::ENABLE_THE_THRE_INTE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _THREIEW<'a> {
w: &'a mut W,
}
impl<'a> _THREIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: THREIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the THRE interrupts."]
#[inline]
pub fn disable_the_thre_int(self) -> &'a mut W {
self.variant(THREIEW::DISABLE_THE_THRE_INT)
}
#[doc = "Enable the THRE interrupts."]
#[inline]
pub fn enable_the_thre_inte(self) -> &'a mut W {
self.variant(THREIEW::ENABLE_THE_THRE_INTE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXIE`"]
pub enum RXIEW {
#[doc = "Disable the RX line status interrupts."]
DISABLE_THE_RX_LINE_,
#[doc = "Enable the RX line status interrupts."]
ENABLE_THE_RX_LINE_S,
}
impl RXIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RXIEW::DISABLE_THE_RX_LINE_ => false,
RXIEW::ENABLE_THE_RX_LINE_S => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RXIEW<'a> {
w: &'a mut W,
}
impl<'a> _RXIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the RX line status interrupts."]
#[inline]
pub fn disable_the_rx_line_(self) -> &'a mut W {
self.variant(RXIEW::DISABLE_THE_RX_LINE_)
}
#[doc = "Enable the RX line status interrupts."]
#[inline]
pub fn enable_the_rx_line_s(self) -> &'a mut W {
self.variant(RXIEW::ENABLE_THE_RX_LINE_S)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MSIE`"]
pub enum MSIEW {
#[doc = "Disable the modem interrupt."]
DISABLE_THE_MODEM_IN,
#[doc = "Enable the modem interrupt."]
ENABLE_THE_MODEM_INT,
}
impl MSIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MSIEW::DISABLE_THE_MODEM_IN => false,
MSIEW::ENABLE_THE_MODEM_INT => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MSIEW<'a> {
w: &'a mut W,
}
impl<'a> _MSIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MSIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the modem interrupt."]
#[inline]
pub fn disable_the_modem_in(self) -> &'a mut W {
self.variant(MSIEW::DISABLE_THE_MODEM_IN)
}
#[doc = "Enable the modem interrupt."]
#[inline]
pub fn enable_the_modem_int(self) -> &'a mut W {
self.variant(MSIEW::ENABLE_THE_MODEM_INT)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CTSIE`"]
pub enum CTSIEW {
#[doc = "Disable the CTS interrupt."]
DISABLE_THE_CTS_INTE,
#[doc = "Enable the CTS interrupt."]
ENABLE_THE_CTS_INTER,
}
impl CTSIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CTSIEW::DISABLE_THE_CTS_INTE => false,
CTSIEW::ENABLE_THE_CTS_INTER => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CTSIEW<'a> {
w: &'a mut W,
}
impl<'a> _CTSIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CTSIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the CTS interrupt."]
#[inline]
pub fn disable_the_cts_inte(self) -> &'a mut W {
self.variant(CTSIEW::DISABLE_THE_CTS_INTE)
}
#[doc = "Enable the CTS interrupt."]
#[inline]
pub fn enable_the_cts_inter(self) -> &'a mut W {
self.variant(CTSIEW::ENABLE_THE_CTS_INTER)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABEOIE`"]
pub enum ABEOIEW {
#[doc = "Disable end of auto-baud Interrupt."]
DISABLE_END_OF_AUTO_,
#[doc = "Enable end of auto-baud Interrupt."]
ENABLE_END_OF_AUTO_B,
}
impl ABEOIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABEOIEW::DISABLE_END_OF_AUTO_ => false,
ABEOIEW::ENABLE_END_OF_AUTO_B => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABEOIEW<'a> {
w: &'a mut W,
}
impl<'a> _ABEOIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABEOIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable end of auto-baud Interrupt."]
#[inline]
pub fn disable_end_of_auto_(self) -> &'a mut W {
self.variant(ABEOIEW::DISABLE_END_OF_AUTO_)
}
#[doc = "Enable end of auto-baud Interrupt."]
#[inline]
pub fn enable_end_of_auto_b(self) -> &'a mut W {
self.variant(ABEOIEW::ENABLE_END_OF_AUTO_B)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABTOIE`"]
pub enum ABTOIEW {
#[doc = "Disable auto-baud time-out Interrupt."]
DISABLE_AUTO_BAUD_TI,
#[doc = "Enable auto-baud time-out Interrupt."]
ENABLE_AUTO_BAUD_TIM,
}
impl ABTOIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABTOIEW::DISABLE_AUTO_BAUD_TI => false,
ABTOIEW::ENABLE_AUTO_BAUD_TIM => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABTOIEW<'a> {
w: &'a mut W,
}
impl<'a> _ABTOIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABTOIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable auto-baud time-out Interrupt."]
#[inline]
pub fn disable_auto_baud_ti(self) -> &'a mut W {
self.variant(ABTOIEW::DISABLE_AUTO_BAUD_TI)
}
#[doc = "Enable auto-baud time-out Interrupt."]
#[inline]
pub fn enable_auto_baud_tim(self) -> &'a mut W {
self.variant(ABTOIEW::ENABLE_AUTO_BAUD_TIM)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."]
#[inline]
pub fn rbrie(&self) -> RBRIER {
RBRIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR\\[5\\]."]
#[inline]
pub fn threie(&self) -> THREIER {
THREIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\]."]
#[inline]
pub fn rxie(&self) -> RXIER {
RXIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR\\[3:0\\]."]
#[inline]
pub fn msie(&self) -> MSIER {
MSIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER\\[3\\]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER\\[3\\] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER\\[3\\] and IER\\[7\\] bits are set."]
#[inline]
pub fn ctsie(&self) -> CTSIER {
CTSIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Enables the end of auto-baud interrupt."]
#[inline]
pub fn abeoie(&self) -> ABEOIER {
ABEOIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Enables the auto-baud time-out interrupt."]
#[inline]
pub fn abtoie(&self) -> ABTOIER {
ABTOIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt."]
#[inline]
pub fn rbrie(&mut self) -> _RBRIEW {
_RBRIEW { w: self }
}
#[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR\\[5\\]."]
#[inline]
pub fn threie(&mut self) -> _THREIEW {
_THREIEW { w: self }
}
#[doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\]."]
#[inline]
pub fn rxie(&mut self) -> _RXIEW {
_RXIEW { w: self }
}
#[doc = "Bit 3 - Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR\\[3:0\\]."]
#[inline]
pub fn msie(&mut self) -> _MSIEW {
_MSIEW { w: self }
}
#[doc = "Bit 7 - CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER\\[3\\]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER\\[3\\] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER\\[3\\] and IER\\[7\\] bits are set."]
#[inline]
pub fn ctsie(&mut self) -> _CTSIEW {
_CTSIEW { w: self }
}
#[doc = "Bit 8 - Enables the end of auto-baud interrupt."]
#[inline]
pub fn abeoie(&mut self) -> _ABEOIEW {
_ABEOIEW { w: self }
}
#[doc = "Bit 9 - Enables the auto-baud time-out interrupt."]
#[inline]
pub fn abtoie(&mut self) -> _ABTOIEW {
_ABTOIEW { w: self }
}
}
}
#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub struct IIR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending."]
pub mod iir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::IIR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `INTSTATUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTSTATUSR {
#[doc = "At least one interrupt is pending."]
AT_LEAST_ONE_INTERRU,
#[doc = "No interrupt is pending."]
NO_INTERRUPT_IS_PEND,
}
impl INTSTATUSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
INTSTATUSR::AT_LEAST_ONE_INTERRU => false,
INTSTATUSR::NO_INTERRUPT_IS_PEND => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> INTSTATUSR {
match value {
false => INTSTATUSR::AT_LEAST_ONE_INTERRU,
true => INTSTATUSR::NO_INTERRUPT_IS_PEND,
}
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_INTERRU`"]
#[inline]
pub fn is_at_least_one_interru(&self) -> bool {
*self == INTSTATUSR::AT_LEAST_ONE_INTERRU
}
#[doc = "Checks if the value of the field is `NO_INTERRUPT_IS_PEND`"]
#[inline]
pub fn is_no_interrupt_is_pend(&self) -> bool {
*self == INTSTATUSR::NO_INTERRUPT_IS_PEND
}
}
#[doc = "Possible values of the field `INTID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INTIDR {
#[doc = "1 - Receive Line Status (RLS)."]
RLS,
#[doc = "2a - Receive Data Available (RDA)."]
RDA,
#[doc = "2b - Character Time-out Indicator (CTI)."]
CTI,
#[doc = "3 - THRE Interrupt."]
THRE,
#[doc = "4 - Modem Interrupt."]
MODEM,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl INTIDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
INTIDR::RLS => 0x03,
INTIDR::RDA => 0x02,
INTIDR::CTI => 0x06,
INTIDR::THRE => 0x01,
INTIDR::MODEM => 0,
INTIDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> INTIDR {
match value {
3 => INTIDR::RLS,
2 => INTIDR::RDA,
6 => INTIDR::CTI,
1 => INTIDR::THRE,
0 => INTIDR::MODEM,
i => INTIDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RLS`"]
#[inline]
pub fn is_rls(&self) -> bool {
*self == INTIDR::RLS
}
#[doc = "Checks if the value of the field is `RDA`"]
#[inline]
pub fn is_rda(&self) -> bool {
*self == INTIDR::RDA
}
#[doc = "Checks if the value of the field is `CTI`"]
#[inline]
pub fn is_cti(&self) -> bool {
*self == INTIDR::CTI
}
#[doc = "Checks if the value of the field is `THRE`"]
#[inline]
pub fn is_thre(&self) -> bool {
*self == INTIDR::THRE
}
#[doc = "Checks if the value of the field is `MODEM`"]
#[inline]
pub fn is_modem(&self) -> bool {
*self == INTIDR::MODEM
}
}
#[doc = r" Value of the field"]
pub struct FIFOENABLER {
bits: u8,
}
impl FIFOENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct ABEOINTR {
bits: bool,
}
impl ABEOINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ABTOINTR {
bits: bool,
}
impl ABTOINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt status. Note that IIR\\[0\\] is active low. The pending interrupt can be determined by evaluating IIR\\[3:1\\]."]
#[inline]
pub fn intstatus(&self) -> INTSTATUSR {
INTSTATUSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 1:3 - Interrupt identification. IER\\[3:1\\] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER\\[3:1\\] not listed below are reserved (100,101,111)."]
#[inline]
pub fn intid(&self) -> INTIDR {
INTIDR::_from({
const MASK: u8 = 0x07;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Copies of FCR\\[0\\]."]
#[inline]
pub fn fifoenable(&self) -> FIFOENABLER {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FIFOENABLER { bits }
}
#[doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled."]
#[inline]
pub fn abeoint(&self) -> ABEOINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABEOINTR { bits }
}
#[doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled."]
#[inline]
pub fn abtoint(&self) -> ABTOINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABTOINTR { bits }
}
}
}
#[doc = "FIFO Control Register. Controls UART1 FIFO usage and modes."]
pub struct FCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "FIFO Control Register. Controls UART1 FIFO usage and modes."]
pub mod fcr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FCR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `FIFOEN`"]
pub enum FIFOENW {
#[doc = "Must not be used in the application."]
MUST_NOT_BE_USED_IN_,
#[doc = "Active high enable for both UART1 Rx and TX FIFOs and FCR\\[7:1\\] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs."]
ACTIVE_HIGH_ENABLE_F,
}
impl FIFOENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FIFOENW::MUST_NOT_BE_USED_IN_ => false,
FIFOENW::ACTIVE_HIGH_ENABLE_F => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FIFOENW<'a> {
w: &'a mut W,
}
impl<'a> _FIFOENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIFOENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Must not be used in the application."]
#[inline]
pub fn must_not_be_used_in_(self) -> &'a mut W {
self.variant(FIFOENW::MUST_NOT_BE_USED_IN_)
}
#[doc = "Active high enable for both UART1 Rx and TX FIFOs and FCR\\[7:1\\] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs."]
#[inline]
pub fn active_high_enable_f(self) -> &'a mut W {
self.variant(FIFOENW::ACTIVE_HIGH_ENABLE_F)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXFIFORES`"]
pub enum RXFIFORESW {
#[doc = "No impact on either of UART1 FIFOs."]
NO_IMPACT_ON_EITHER_,
#[doc = "Writing a logic 1 to FCR\\[1\\] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing."]
WRITING_A_LOGIC_1_TO,
}
impl RXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RXFIFORESW::NO_IMPACT_ON_EITHER_ => false,
RXFIFORESW::WRITING_A_LOGIC_1_TO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RXFIFORESW<'a> {
w: &'a mut W,
}
impl<'a> _RXFIFORESW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXFIFORESW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No impact on either of UART1 FIFOs."]
#[inline]
pub fn no_impact_on_either_(self) -> &'a mut W {
self.variant(RXFIFORESW::NO_IMPACT_ON_EITHER_)
}
#[doc = "Writing a logic 1 to FCR\\[1\\] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing."]
#[inline]
pub fn writing_a_logic_1_to(self) -> &'a mut W {
self.variant(RXFIFORESW::WRITING_A_LOGIC_1_TO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TXFIFORES`"]
pub enum TXFIFORESW {
#[doc = "No impact on either of UART1 FIFOs."]
NO_IMPACT_ON_EITHER_,
#[doc = "Writing a logic 1 to FCR\\[2\\] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing."]
WRITING_A_LOGIC_1_TO,
}
impl TXFIFORESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TXFIFORESW::NO_IMPACT_ON_EITHER_ => false,
TXFIFORESW::WRITING_A_LOGIC_1_TO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TXFIFORESW<'a> {
w: &'a mut W,
}
impl<'a> _TXFIFORESW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TXFIFORESW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No impact on either of UART1 FIFOs."]
#[inline]
pub fn no_impact_on_either_(self) -> &'a mut W {
self.variant(TXFIFORESW::NO_IMPACT_ON_EITHER_)
}
#[doc = "Writing a logic 1 to FCR\\[2\\] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing."]
#[inline]
pub fn writing_a_logic_1_to(self) -> &'a mut W {
self.variant(TXFIFORESW::WRITING_A_LOGIC_1_TO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMAMODEW<'a> {
w: &'a mut W,
}
impl<'a> _DMAMODEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXTRIGLVL`"]
pub enum RXTRIGLVLW {
#[doc = "Trigger level 0 (1 character or 0x01)."]
TRIGGER_LEVEL_0_1_C,
#[doc = "Trigger level 1 (4 characters or 0x04)."]
TRIGGER_LEVEL_1_4_C,
#[doc = "Trigger level 2 (8 characters or 0x08)."]
TRIGGER_LEVEL_2_8_C,
#[doc = "Trigger level 3 (14 characters or 0x0E)."]
TRIGGER_LEVEL_3_14_,
}
impl RXTRIGLVLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
RXTRIGLVLW::TRIGGER_LEVEL_0_1_C => 0,
RXTRIGLVLW::TRIGGER_LEVEL_1_4_C => 1,
RXTRIGLVLW::TRIGGER_LEVEL_2_8_C => 2,
RXTRIGLVLW::TRIGGER_LEVEL_3_14_ => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _RXTRIGLVLW<'a> {
w: &'a mut W,
}
impl<'a> _RXTRIGLVLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXTRIGLVLW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Trigger level 0 (1 character or 0x01)."]
#[inline]
pub fn trigger_level_0_1_c(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_0_1_C)
}
#[doc = "Trigger level 1 (4 characters or 0x04)."]
#[inline]
pub fn trigger_level_1_4_c(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_1_4_C)
}
#[doc = "Trigger level 2 (8 characters or 0x08)."]
#[inline]
pub fn trigger_level_2_8_c(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_2_8_C)
}
#[doc = "Trigger level 3 (14 characters or 0x0E)."]
#[inline]
pub fn trigger_level_3_14_(self) -> &'a mut W {
self.variant(RXTRIGLVLW::TRIGGER_LEVEL_3_14_)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - FIFO enable."]
#[inline]
pub fn fifoen(&mut self) -> _FIFOENW {
_FIFOENW { w: self }
}
#[doc = "Bit 1 - RX FIFO Reset."]
#[inline]
pub fn rxfifores(&mut self) -> _RXFIFORESW {
_RXFIFORESW { w: self }
}
#[doc = "Bit 2 - TX FIFO Reset."]
#[inline]
pub fn txfifores(&mut self) -> _TXFIFORESW {
_TXFIFORESW { w: self }
}
#[doc = "Bit 3 - DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1."]
#[inline]
pub fn dmamode(&mut self) -> _DMAMODEW {
_DMAMODEW { w: self }
}
#[doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated."]
#[inline]
pub fn rxtriglvl(&mut self) -> _RXTRIGLVLW {
_RXTRIGLVLW { w: self }
}
}
}
#[doc = "Line Control Register. Contains controls for frame formatting and break generation."]
pub struct LCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Line Control Register. Contains controls for frame formatting and break generation."]
pub mod lcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::LCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `WLS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WLSR {
#[doc = "5-bit character length."]
_5_BIT_CHARACTER_LENG,
#[doc = "6-bit character length."]
_6_BIT_CHARACTER_LENG,
#[doc = "7-bit character length."]
_7_BIT_CHARACTER_LENG,
#[doc = "8-bit character length."]
_8_BIT_CHARACTER_LENG,
}
impl WLSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
WLSR::_5_BIT_CHARACTER_LENG => 0,
WLSR::_6_BIT_CHARACTER_LENG => 0x01,
WLSR::_7_BIT_CHARACTER_LENG => 0x02,
WLSR::_8_BIT_CHARACTER_LENG => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> WLSR {
match value {
0 => WLSR::_5_BIT_CHARACTER_LENG,
1 => WLSR::_6_BIT_CHARACTER_LENG,
2 => WLSR::_7_BIT_CHARACTER_LENG,
3 => WLSR::_8_BIT_CHARACTER_LENG,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_5_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_5_bit_character_leng(&self) -> bool {
*self == WLSR::_5_BIT_CHARACTER_LENG
}
#[doc = "Checks if the value of the field is `_6_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_6_bit_character_leng(&self) -> bool {
*self == WLSR::_6_BIT_CHARACTER_LENG
}
#[doc = "Checks if the value of the field is `_7_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_7_bit_character_leng(&self) -> bool {
*self == WLSR::_7_BIT_CHARACTER_LENG
}
#[doc = "Checks if the value of the field is `_8_BIT_CHARACTER_LENG`"]
#[inline]
pub fn is_8_bit_character_leng(&self) -> bool {
*self == WLSR::_8_BIT_CHARACTER_LENG
}
}
#[doc = "Possible values of the field `SBS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SBSR {
#[doc = "1 stop bit."]
_1_STOP_BIT_,
#[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."]
_2_STOP_BITS_1_5_IF_,
}
impl SBSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SBSR::_1_STOP_BIT_ => false,
SBSR::_2_STOP_BITS_1_5_IF_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SBSR {
match value {
false => SBSR::_1_STOP_BIT_,
true => SBSR::_2_STOP_BITS_1_5_IF_,
}
}
#[doc = "Checks if the value of the field is `_1_STOP_BIT_`"]
#[inline]
pub fn is_1_stop_bit_(&self) -> bool {
*self == SBSR::_1_STOP_BIT_
}
#[doc = "Checks if the value of the field is `_2_STOP_BITS_1_5_IF_`"]
#[inline]
pub fn is_2_stop_bits_1_5_if_(&self) -> bool {
*self == SBSR::_2_STOP_BITS_1_5_IF_
}
}
#[doc = "Possible values of the field `PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PER {
#[doc = "Disable parity generation and checking."]
DISABLE_PARITY_GENER,
#[doc = "Enable parity generation and checking."]
ENABLE_PARITY_GENERA,
}
impl PER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PER::DISABLE_PARITY_GENER => false,
PER::ENABLE_PARITY_GENERA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PER {
match value {
false => PER::DISABLE_PARITY_GENER,
true => PER::ENABLE_PARITY_GENERA,
}
}
#[doc = "Checks if the value of the field is `DISABLE_PARITY_GENER`"]
#[inline]
pub fn is_disable_parity_gener(&self) -> bool {
*self == PER::DISABLE_PARITY_GENER
}
#[doc = "Checks if the value of the field is `ENABLE_PARITY_GENERA`"]
#[inline]
pub fn is_enable_parity_genera(&self) -> bool {
*self == PER::ENABLE_PARITY_GENERA
}
}
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSR {
#[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
ODD_PARITY_NUMBER_O,
#[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
EVEN_PARITY_NUMBER_,
#[doc = "Forced 1 stick parity."]
FORCED1STICK_PAR,
#[doc = "Forced 0 stick parity."]
FORCED0STICK_PAR,
}
impl PSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PSR::ODD_PARITY_NUMBER_O => 0,
PSR::EVEN_PARITY_NUMBER_ => 0x01,
PSR::FORCED1STICK_PAR => 0x02,
PSR::FORCED0STICK_PAR => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PSR {
match value {
0 => PSR::ODD_PARITY_NUMBER_O,
1 => PSR::EVEN_PARITY_NUMBER_,
2 => PSR::FORCED1STICK_PAR,
3 => PSR::FORCED0STICK_PAR,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `ODD_PARITY_NUMBER_O`"]
#[inline]
pub fn is_odd_parity_number_o(&self) -> bool {
*self == PSR::ODD_PARITY_NUMBER_O
}
#[doc = "Checks if the value of the field is `EVEN_PARITY_NUMBER_`"]
#[inline]
pub fn is_even_parity_number_(&self) -> bool {
*self == PSR::EVEN_PARITY_NUMBER_
}
#[doc = "Checks if the value of the field is `FORCED1STICK_PAR`"]
#[inline]
pub fn is_forced1stick_par(&self) -> bool {
*self == PSR::FORCED1STICK_PAR
}
#[doc = "Checks if the value of the field is `FORCED0STICK_PAR`"]
#[inline]
pub fn is_forced0stick_par(&self) -> bool {
*self == PSR::FORCED0STICK_PAR
}
}
#[doc = "Possible values of the field `BC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BCR {
#[doc = "Disable break transmission."]
DISABLE_BREAK_TRANSM,
#[doc = "Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR\\[6\\] is active high."]
ENABLE_BREAK_TRANSMI,
}
impl BCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BCR::DISABLE_BREAK_TRANSM => false,
BCR::ENABLE_BREAK_TRANSMI => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BCR {
match value {
false => BCR::DISABLE_BREAK_TRANSM,
true => BCR::ENABLE_BREAK_TRANSMI,
}
}
#[doc = "Checks if the value of the field is `DISABLE_BREAK_TRANSM`"]
#[inline]
pub fn is_disable_break_transm(&self) -> bool {
*self == BCR::DISABLE_BREAK_TRANSM
}
#[doc = "Checks if the value of the field is `ENABLE_BREAK_TRANSMI`"]
#[inline]
pub fn is_enable_break_transmi(&self) -> bool {
*self == BCR::ENABLE_BREAK_TRANSMI
}
}
#[doc = "Possible values of the field `DLAB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DLABR {
#[doc = "Disable access to Divisor Latches."]
DISABLE_ACCESS_TO_DI,
#[doc = "Enable access to Divisor Latches."]
ENABLE_ACCESS_TO_DIV,
}
impl DLABR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DLABR::DISABLE_ACCESS_TO_DI => false,
DLABR::ENABLE_ACCESS_TO_DIV => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DLABR {
match value {
false => DLABR::DISABLE_ACCESS_TO_DI,
true => DLABR::ENABLE_ACCESS_TO_DIV,
}
}
#[doc = "Checks if the value of the field is `DISABLE_ACCESS_TO_DI`"]
#[inline]
pub fn is_disable_access_to_di(&self) -> bool {
*self == DLABR::DISABLE_ACCESS_TO_DI
}
#[doc = "Checks if the value of the field is `ENABLE_ACCESS_TO_DIV`"]
#[inline]
pub fn is_enable_access_to_div(&self) -> bool {
*self == DLABR::ENABLE_ACCESS_TO_DIV
}
}
#[doc = "Values that can be written to the field `WLS`"]
pub enum WLSW {
#[doc = "5-bit character length."]
_5_BIT_CHARACTER_LENG,
#[doc = "6-bit character length."]
_6_BIT_CHARACTER_LENG,
#[doc = "7-bit character length."]
_7_BIT_CHARACTER_LENG,
#[doc = "8-bit character length."]
_8_BIT_CHARACTER_LENG,
}
impl WLSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
WLSW::_5_BIT_CHARACTER_LENG => 0,
WLSW::_6_BIT_CHARACTER_LENG => 1,
WLSW::_7_BIT_CHARACTER_LENG => 2,
WLSW::_8_BIT_CHARACTER_LENG => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _WLSW<'a> {
w: &'a mut W,
}
impl<'a> _WLSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WLSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "5-bit character length."]
#[inline]
pub fn _5_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_5_BIT_CHARACTER_LENG)
}
#[doc = "6-bit character length."]
#[inline]
pub fn _6_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_6_BIT_CHARACTER_LENG)
}
#[doc = "7-bit character length."]
#[inline]
pub fn _7_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_7_BIT_CHARACTER_LENG)
}
#[doc = "8-bit character length."]
#[inline]
pub fn _8_bit_character_leng(self) -> &'a mut W {
self.variant(WLSW::_8_BIT_CHARACTER_LENG)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SBS`"]
pub enum SBSW {
#[doc = "1 stop bit."]
_1_STOP_BIT_,
#[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."]
_2_STOP_BITS_1_5_IF_,
}
impl SBSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SBSW::_1_STOP_BIT_ => false,
SBSW::_2_STOP_BITS_1_5_IF_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SBSW<'a> {
w: &'a mut W,
}
impl<'a> _SBSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SBSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "1 stop bit."]
#[inline]
pub fn _1_stop_bit_(self) -> &'a mut W {
self.variant(SBSW::_1_STOP_BIT_)
}
#[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."]
#[inline]
pub fn _2_stop_bits_1_5_if_(self) -> &'a mut W {
self.variant(SBSW::_2_STOP_BITS_1_5_IF_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PE`"]
pub enum PEW {
#[doc = "Disable parity generation and checking."]
DISABLE_PARITY_GENER,
#[doc = "Enable parity generation and checking."]
ENABLE_PARITY_GENERA,
}
impl PEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PEW::DISABLE_PARITY_GENER => false,
PEW::ENABLE_PARITY_GENERA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PEW<'a> {
w: &'a mut W,
}
impl<'a> _PEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable parity generation and checking."]
#[inline]
pub fn disable_parity_gener(self) -> &'a mut W {
self.variant(PEW::DISABLE_PARITY_GENER)
}
#[doc = "Enable parity generation and checking."]
#[inline]
pub fn enable_parity_genera(self) -> &'a mut W {
self.variant(PEW::ENABLE_PARITY_GENERA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PS`"]
pub enum PSW {
#[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
ODD_PARITY_NUMBER_O,
#[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
EVEN_PARITY_NUMBER_,
#[doc = "Forced 1 stick parity."]
FORCED1STICK_PAR,
#[doc = "Forced 0 stick parity."]
FORCED0STICK_PAR,
}
impl PSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PSW::ODD_PARITY_NUMBER_O => 0,
PSW::EVEN_PARITY_NUMBER_ => 1,
PSW::FORCED1STICK_PAR => 2,
PSW::FORCED0STICK_PAR => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PSW<'a> {
w: &'a mut W,
}
impl<'a> _PSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."]
#[inline]
pub fn odd_parity_number_o(self) -> &'a mut W {
self.variant(PSW::ODD_PARITY_NUMBER_O)
}
#[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."]
#[inline]
pub fn even_parity_number_(self) -> &'a mut W {
self.variant(PSW::EVEN_PARITY_NUMBER_)
}
#[doc = "Forced 1 stick parity."]
#[inline]
pub fn forced1stick_par(self) -> &'a mut W {
self.variant(PSW::FORCED1STICK_PAR)
}
#[doc = "Forced 0 stick parity."]
#[inline]
pub fn forced0stick_par(self) -> &'a mut W {
self.variant(PSW::FORCED0STICK_PAR)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BC`"]
pub enum BCW {
#[doc = "Disable break transmission."]
DISABLE_BREAK_TRANSM,
#[doc = "Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR\\[6\\] is active high."]
ENABLE_BREAK_TRANSMI,
}
impl BCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BCW::DISABLE_BREAK_TRANSM => false,
BCW::ENABLE_BREAK_TRANSMI => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BCW<'a> {
w: &'a mut W,
}
impl<'a> _BCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BCW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable break transmission."]
#[inline]
pub fn disable_break_transm(self) -> &'a mut W {
self.variant(BCW::DISABLE_BREAK_TRANSM)
}
#[doc = "Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR\\[6\\] is active high."]
#[inline]
pub fn enable_break_transmi(self) -> &'a mut W {
self.variant(BCW::ENABLE_BREAK_TRANSMI)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DLAB`"]
pub enum DLABW {
#[doc = "Disable access to Divisor Latches."]
DISABLE_ACCESS_TO_DI,
#[doc = "Enable access to Divisor Latches."]
ENABLE_ACCESS_TO_DIV,
}
impl DLABW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DLABW::DISABLE_ACCESS_TO_DI => false,
DLABW::ENABLE_ACCESS_TO_DIV => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DLABW<'a> {
w: &'a mut W,
}
impl<'a> _DLABW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DLABW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable access to Divisor Latches."]
#[inline]
pub fn disable_access_to_di(self) -> &'a mut W {
self.variant(DLABW::DISABLE_ACCESS_TO_DI)
}
#[doc = "Enable access to Divisor Latches."]
#[inline]
pub fn enable_access_to_div(self) -> &'a mut W {
self.variant(DLABW::ENABLE_ACCESS_TO_DIV)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Word Length Select."]
#[inline]
pub fn wls(&self) -> WLSR {
WLSR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Stop Bit Select."]
#[inline]
pub fn sbs(&self) -> SBSR {
SBSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Parity Enable."]
#[inline]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 4:5 - Parity Select."]
#[inline]
pub fn ps(&self) -> PSR {
PSR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Break Control."]
#[inline]
pub fn bc(&self) -> BCR {
BCR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Divisor Latch Access Bit (DLAB)"]
#[inline]
pub fn dlab(&self) -> DLABR {
DLABR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Word Length Select."]
#[inline]
pub fn wls(&mut self) -> _WLSW {
_WLSW { w: self }
}
#[doc = "Bit 2 - Stop Bit Select."]
#[inline]
pub fn sbs(&mut self) -> _SBSW {
_SBSW { w: self }
}
#[doc = "Bit 3 - Parity Enable."]
#[inline]
pub fn pe(&mut self) -> _PEW {
_PEW { w: self }
}
#[doc = "Bits 4:5 - Parity Select."]
#[inline]
pub fn ps(&mut self) -> _PSW {
_PSW { w: self }
}
#[doc = "Bit 6 - Break Control."]
#[inline]
pub fn bc(&mut self) -> _BCW {
_BCW { w: self }
}
#[doc = "Bit 7 - Divisor Latch Access Bit (DLAB)"]
#[inline]
pub fn dlab(&mut self) -> _DLABW {
_DLABW { w: self }
}
}
}
#[doc = "Modem Control Register. Contains controls for flow control handshaking and loopback mode."]
pub struct MCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Modem Control Register. Contains controls for flow control handshaking and loopback mode."]
pub mod mcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DTRCTRLR {
bits: bool,
}
impl DTRCTRLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RTSCTRLR {
bits: bool,
}
impl RTSCTRLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `LMS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LMSR {
#[doc = "Disable modem loopback mode."]
DISABLE_MODEM_LOOPBA,
#[doc = "Enable modem loopback mode."]
ENABLE_MODEM_LOOPBAC,
}
impl LMSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LMSR::DISABLE_MODEM_LOOPBA => false,
LMSR::ENABLE_MODEM_LOOPBAC => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LMSR {
match value {
false => LMSR::DISABLE_MODEM_LOOPBA,
true => LMSR::ENABLE_MODEM_LOOPBAC,
}
}
#[doc = "Checks if the value of the field is `DISABLE_MODEM_LOOPBA`"]
#[inline]
pub fn is_disable_modem_loopba(&self) -> bool {
*self == LMSR::DISABLE_MODEM_LOOPBA
}
#[doc = "Checks if the value of the field is `ENABLE_MODEM_LOOPBAC`"]
#[inline]
pub fn is_enable_modem_loopbac(&self) -> bool {
*self == LMSR::ENABLE_MODEM_LOOPBAC
}
}
#[doc = "Possible values of the field `RTSEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTSENR {
#[doc = "Disable auto-rts flow control."]
DISABLE_AUTO_RTS_FLO,
#[doc = "Enable auto-rts flow control."]
ENABLE_AUTO_RTS_FLOW,
}
impl RTSENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RTSENR::DISABLE_AUTO_RTS_FLO => false,
RTSENR::ENABLE_AUTO_RTS_FLOW => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RTSENR {
match value {
false => RTSENR::DISABLE_AUTO_RTS_FLO,
true => RTSENR::ENABLE_AUTO_RTS_FLOW,
}
}
#[doc = "Checks if the value of the field is `DISABLE_AUTO_RTS_FLO`"]
#[inline]
pub fn is_disable_auto_rts_flo(&self) -> bool {
*self == RTSENR::DISABLE_AUTO_RTS_FLO
}
#[doc = "Checks if the value of the field is `ENABLE_AUTO_RTS_FLOW`"]
#[inline]
pub fn is_enable_auto_rts_flow(&self) -> bool {
*self == RTSENR::ENABLE_AUTO_RTS_FLOW
}
}
#[doc = "Possible values of the field `CTSEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CTSENR {
#[doc = "Disable auto-cts flow control."]
DISABLE_AUTO_CTS_FLO,
#[doc = "Enable auto-cts flow control."]
ENABLE_AUTO_CTS_FLOW,
}
impl CTSENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CTSENR::DISABLE_AUTO_CTS_FLO => false,
CTSENR::ENABLE_AUTO_CTS_FLOW => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CTSENR {
match value {
false => CTSENR::DISABLE_AUTO_CTS_FLO,
true => CTSENR::ENABLE_AUTO_CTS_FLOW,
}
}
#[doc = "Checks if the value of the field is `DISABLE_AUTO_CTS_FLO`"]
#[inline]
pub fn is_disable_auto_cts_flo(&self) -> bool {
*self == CTSENR::DISABLE_AUTO_CTS_FLO
}
#[doc = "Checks if the value of the field is `ENABLE_AUTO_CTS_FLOW`"]
#[inline]
pub fn is_enable_auto_cts_flow(&self) -> bool {
*self == CTSENR::ENABLE_AUTO_CTS_FLOW
}
}
#[doc = r" Proxy"]
pub struct _DTRCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _DTRCTRLW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTSCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _RTSCTRLW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LMS`"]
pub enum LMSW {
#[doc = "Disable modem loopback mode."]
DISABLE_MODEM_LOOPBA,
#[doc = "Enable modem loopback mode."]
ENABLE_MODEM_LOOPBAC,
}
impl LMSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LMSW::DISABLE_MODEM_LOOPBA => false,
LMSW::ENABLE_MODEM_LOOPBAC => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LMSW<'a> {
w: &'a mut W,
}
impl<'a> _LMSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LMSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable modem loopback mode."]
#[inline]
pub fn disable_modem_loopba(self) -> &'a mut W {
self.variant(LMSW::DISABLE_MODEM_LOOPBA)
}
#[doc = "Enable modem loopback mode."]
#[inline]
pub fn enable_modem_loopbac(self) -> &'a mut W {
self.variant(LMSW::ENABLE_MODEM_LOOPBAC)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RTSEN`"]
pub enum RTSENW {
#[doc = "Disable auto-rts flow control."]
DISABLE_AUTO_RTS_FLO,
#[doc = "Enable auto-rts flow control."]
ENABLE_AUTO_RTS_FLOW,
}
impl RTSENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RTSENW::DISABLE_AUTO_RTS_FLO => false,
RTSENW::ENABLE_AUTO_RTS_FLOW => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RTSENW<'a> {
w: &'a mut W,
}
impl<'a> _RTSENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RTSENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable auto-rts flow control."]
#[inline]
pub fn disable_auto_rts_flo(self) -> &'a mut W {
self.variant(RTSENW::DISABLE_AUTO_RTS_FLO)
}
#[doc = "Enable auto-rts flow control."]
#[inline]
pub fn enable_auto_rts_flow(self) -> &'a mut W {
self.variant(RTSENW::ENABLE_AUTO_RTS_FLOW)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CTSEN`"]
pub enum CTSENW {
#[doc = "Disable auto-cts flow control."]
DISABLE_AUTO_CTS_FLO,
#[doc = "Enable auto-cts flow control."]
ENABLE_AUTO_CTS_FLOW,
}
impl CTSENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CTSENW::DISABLE_AUTO_CTS_FLO => false,
CTSENW::ENABLE_AUTO_CTS_FLOW => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CTSENW<'a> {
w: &'a mut W,
}
impl<'a> _CTSENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CTSENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable auto-cts flow control."]
#[inline]
pub fn disable_auto_cts_flo(self) -> &'a mut W {
self.variant(CTSENW::DISABLE_AUTO_CTS_FLO)
}
#[doc = "Enable auto-cts flow control."]
#[inline]
pub fn enable_auto_cts_flow(self) -> &'a mut W {
self.variant(CTSENW::ENABLE_AUTO_CTS_FLOW)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."]
#[inline]
pub fn dtrctrl(&self) -> DTRCTRLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DTRCTRLR { bits }
}
#[doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."]
#[inline]
pub fn rtsctrl(&self) -> RTSCTRLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTSCTRLR { bits }
}
#[doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."]
#[inline]
pub fn lms(&self) -> LMSR {
LMSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - RTS enable."]
#[inline]
pub fn rtsen(&self) -> RTSENR {
RTSENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - CTS enable."]
#[inline]
pub fn ctsen(&self) -> CTSENR {
CTSENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."]
#[inline]
pub fn dtrctrl(&mut self) -> _DTRCTRLW {
_DTRCTRLW { w: self }
}
#[doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."]
#[inline]
pub fn rtsctrl(&mut self) -> _RTSCTRLW {
_RTSCTRLW { w: self }
}
#[doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR."]
#[inline]
pub fn lms(&mut self) -> _LMSW {
_LMSW { w: self }
}
#[doc = "Bit 6 - RTS enable."]
#[inline]
pub fn rtsen(&mut self) -> _RTSENW {
_RTSENW { w: self }
}
#[doc = "Bit 7 - CTS enable."]
#[inline]
pub fn ctsen(&mut self) -> _CTSENW {
_CTSENW { w: self }
}
}
}
#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
pub struct LSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
pub mod lsr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::LSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `RDR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RDRR {
#[doc = "The UART1 receiver FIFO is empty."]
EMPTY,
#[doc = "The UART1 receiver FIFO is not empty."]
NOTEMPTY,
}
impl RDRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RDRR::EMPTY => false,
RDRR::NOTEMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RDRR {
match value {
false => RDRR::EMPTY,
true => RDRR::NOTEMPTY,
}
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == RDRR::EMPTY
}
#[doc = "Checks if the value of the field is `NOTEMPTY`"]
#[inline]
pub fn is_notempty(&self) -> bool {
*self == RDRR::NOTEMPTY
}
}
#[doc = "Possible values of the field `OE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OER {
#[doc = "Overrun error status is inactive."]
INACTIVE,
#[doc = "Overrun error status is active."]
ACTIVE,
}
impl OER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OER::INACTIVE => false,
OER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OER {
match value {
false => OER::INACTIVE,
true => OER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == OER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == OER::ACTIVE
}
}
#[doc = "Possible values of the field `PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PER {
#[doc = "Parity error status is inactive."]
INACTIVE,
#[doc = "Parity error status is active."]
ACTIVE,
}
impl PER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PER::INACTIVE => false,
PER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PER {
match value {
false => PER::INACTIVE,
true => PER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == PER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == PER::ACTIVE
}
}
#[doc = "Possible values of the field `FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FER {
#[doc = "Framing error status is inactive."]
INACTIVE,
#[doc = "Framing error status is active."]
ACTIVE,
}
impl FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FER::INACTIVE => false,
FER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FER {
match value {
false => FER::INACTIVE,
true => FER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == FER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == FER::ACTIVE
}
}
#[doc = "Possible values of the field `BI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIR {
#[doc = "Break interrupt status is inactive."]
INACTIVE,
#[doc = "Break interrupt status is active."]
ACTIVE,
}
impl BIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BIR::INACTIVE => false,
BIR::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BIR {
match value {
false => BIR::INACTIVE,
true => BIR::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline]
pub fn is_inactive(&self) -> bool {
*self == BIR::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline]
pub fn is_active(&self) -> bool {
*self == BIR::ACTIVE
}
}
#[doc = "Possible values of the field `THRE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum THRER {
#[doc = "THR contains valid data."]
VALID,
#[doc = "THR is empty."]
THR_IS_EMPTY_,
}
impl THRER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
THRER::VALID => false,
THRER::THR_IS_EMPTY_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> THRER {
match value {
false => THRER::VALID,
true => THRER::THR_IS_EMPTY_,
}
}
#[doc = "Checks if the value of the field is `VALID`"]
#[inline]
pub fn is_valid(&self) -> bool {
*self == THRER::VALID
}
#[doc = "Checks if the value of the field is `THR_IS_EMPTY_`"]
#[inline]
pub fn is_thr_is_empty_(&self) -> bool {
*self == THRER::THR_IS_EMPTY_
}
}
#[doc = "Possible values of the field `TEMT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TEMTR {
#[doc = "THR and/or the TSR contains valid data."]
VALID,
#[doc = "THR and the TSR are empty."]
EMPTY,
}
impl TEMTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TEMTR::VALID => false,
TEMTR::EMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TEMTR {
match value {
false => TEMTR::VALID,
true => TEMTR::EMPTY,
}
}
#[doc = "Checks if the value of the field is `VALID`"]
#[inline]
pub fn is_valid(&self) -> bool {
*self == TEMTR::VALID
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == TEMTR::EMPTY
}
}
#[doc = "Possible values of the field `RXFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXFER {
#[doc = "RBR contains no UART1 RX errors or FCR\\[0\\]=0."]
NOERROR,
#[doc = "UART1 RBR contains at least one UART1 RX error."]
ERRORS,
}
impl RXFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RXFER::NOERROR => false,
RXFER::ERRORS => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RXFER {
match value {
false => RXFER::NOERROR,
true => RXFER::ERRORS,
}
}
#[doc = "Checks if the value of the field is `NOERROR`"]
#[inline]
pub fn is_noerror(&self) -> bool {
*self == RXFER::NOERROR
}
#[doc = "Checks if the value of the field is `ERRORS`"]
#[inline]
pub fn is_errors(&self) -> bool {
*self == RXFER::ERRORS
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receiver Data Ready. LSR\\[0\\] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty."]
#[inline]
pub fn rdr(&self) -> RDRR {
RDRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR\\[1\\]. LSR\\[1\\] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost."]
#[inline]
pub fn oe(&self) -> OER {
OER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR\\[2\\]. Time of parity error detection is dependent on FCR\\[0\\]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO."]
#[inline]
pub fn pe(&self) -> PER {
PER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR\\[3\\]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO."]
#[inline]
pub fn fe(&self) -> FER {
FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR\\[0\\]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO."]
#[inline]
pub fn bi(&self) -> BIR {
BIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write."]
#[inline]
pub fn thre(&self) -> THRER {
THRER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."]
#[inline]
pub fn temt(&self) -> TEMTR {
TEMTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Error in RX FIFO. LSR\\[7\\] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO."]
#[inline]
pub fn rxfe(&self) -> RXFER {
RXFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "Modem Status Register. Contains handshake signal status flags."]
pub struct MSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Modem Status Register. Contains handshake signal status flags."]
pub mod msr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::MSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `DCTS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCTSR {
#[doc = "No change detected on modem input, CTS."]
NO_CHANGE_DETECTED_O,
#[doc = "State change detected on modem input, CTS."]
STATE_CHANGE_DETECTE,
}
impl DCTSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCTSR::NO_CHANGE_DETECTED_O => false,
DCTSR::STATE_CHANGE_DETECTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCTSR {
match value {
false => DCTSR::NO_CHANGE_DETECTED_O,
true => DCTSR::STATE_CHANGE_DETECTE,
}
}
#[doc = "Checks if the value of the field is `NO_CHANGE_DETECTED_O`"]
#[inline]
pub fn is_no_change_detected_o(&self) -> bool {
*self == DCTSR::NO_CHANGE_DETECTED_O
}
#[doc = "Checks if the value of the field is `STATE_CHANGE_DETECTE`"]
#[inline]
pub fn is_state_change_detecte(&self) -> bool {
*self == DCTSR::STATE_CHANGE_DETECTE
}
}
#[doc = "Possible values of the field `DDSR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DDSRR {
#[doc = "No change detected on modem input, DSR."]
NO_CHANGE_DETECTED_O,
#[doc = "State change detected on modem input, DSR."]
STATE_CHANGE_DETECTE,
}
impl DDSRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DDSRR::NO_CHANGE_DETECTED_O => false,
DDSRR::STATE_CHANGE_DETECTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DDSRR {
match value {
false => DDSRR::NO_CHANGE_DETECTED_O,
true => DDSRR::STATE_CHANGE_DETECTE,
}
}
#[doc = "Checks if the value of the field is `NO_CHANGE_DETECTED_O`"]
#[inline]
pub fn is_no_change_detected_o(&self) -> bool {
*self == DDSRR::NO_CHANGE_DETECTED_O
}
#[doc = "Checks if the value of the field is `STATE_CHANGE_DETECTE`"]
#[inline]
pub fn is_state_change_detecte(&self) -> bool {
*self == DDSRR::STATE_CHANGE_DETECTE
}
}
#[doc = "Possible values of the field `TERI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TERIR {
#[doc = "No change detected on modem input, RI."]
NO_CHANGE_DETECTED_O,
#[doc = "Low-to-high transition detected on RI."]
LOW_TO_HIGH_TRANSITI,
}
impl TERIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TERIR::NO_CHANGE_DETECTED_O => false,
TERIR::LOW_TO_HIGH_TRANSITI => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TERIR {
match value {
false => TERIR::NO_CHANGE_DETECTED_O,
true => TERIR::LOW_TO_HIGH_TRANSITI,
}
}
#[doc = "Checks if the value of the field is `NO_CHANGE_DETECTED_O`"]
#[inline]
pub fn is_no_change_detected_o(&self) -> bool {
*self == TERIR::NO_CHANGE_DETECTED_O
}
#[doc = "Checks if the value of the field is `LOW_TO_HIGH_TRANSITI`"]
#[inline]
pub fn is_low_to_high_transiti(&self) -> bool {
*self == TERIR::LOW_TO_HIGH_TRANSITI
}
}
#[doc = "Possible values of the field `DDCD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DDCDR {
#[doc = "No change detected on modem input, DCD."]
NO_CHANGE_DETECTED_O,
#[doc = "State change detected on modem input, DCD."]
STATE_CHANGE_DETECTE,
}
impl DDCDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DDCDR::NO_CHANGE_DETECTED_O => false,
DDCDR::STATE_CHANGE_DETECTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DDCDR {
match value {
false => DDCDR::NO_CHANGE_DETECTED_O,
true => DDCDR::STATE_CHANGE_DETECTE,
}
}
#[doc = "Checks if the value of the field is `NO_CHANGE_DETECTED_O`"]
#[inline]
pub fn is_no_change_detected_o(&self) -> bool {
*self == DDCDR::NO_CHANGE_DETECTED_O
}
#[doc = "Checks if the value of the field is `STATE_CHANGE_DETECTE`"]
#[inline]
pub fn is_state_change_detecte(&self) -> bool {
*self == DDCDR::STATE_CHANGE_DETECTE
}
}
#[doc = r" Value of the field"]
pub struct CTSR {
bits: bool,
}
impl CTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DSRR {
bits: bool,
}
impl DSRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RIR {
bits: bool,
}
impl RIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DCDR {
bits: bool,
}
impl DCDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Delta CTS. Set upon state change of input CTS. Cleared on an MSR read."]
#[inline]
pub fn dcts(&self) -> DCTSR {
DCTSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Delta DSR. Set upon state change of input DSR. Cleared on an MSR read."]
#[inline]
pub fn ddsr(&self) -> DDSRR {
DDSRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read."]
#[inline]
pub fn teri(&self) -> TERIR {
TERIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Delta DCD. Set upon state change of input DCD. Cleared on an MSR read."]
#[inline]
pub fn ddcd(&self) -> DDCDR {
DDCDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Clear To Send State. Complement of input signal CTS. This bit is connected to MCR\\[1\\] in modem loopback mode."]
#[inline]
pub fn cts(&self) -> CTSR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CTSR { bits }
}
#[doc = "Bit 5 - Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR\\[0\\] in modem loopback mode."]
#[inline]
pub fn dsr(&self) -> DSRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DSRR { bits }
}
#[doc = "Bit 6 - Ring Indicator State. Complement of input RI. This bit is connected to MCR\\[2\\] in modem loopback mode."]
#[inline]
pub fn ri(&self) -> RIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RIR { bits }
}
#[doc = "Bit 7 - Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR\\[3\\] in modem loopback mode."]
#[inline]
pub fn dcd(&self) -> DCDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DCDR { bits }
}
}
}
#[doc = "Scratch Pad Register. 8-bit temporary storage for software."]
pub struct SCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Scratch Pad Register. 8-bit temporary storage for software."]
pub mod scr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PADR {
bits: u8,
}
impl PADR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PADW<'a> {
w: &'a mut W,
}
impl<'a> _PADW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - A readable, writable byte."]
#[inline]
pub fn pad(&self) -> PADR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PADR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - A readable, writable byte."]
#[inline]
pub fn pad(&mut self) -> _PADW {
_PADW { w: self }
}
}
}
#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature."]
pub struct ACR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature."]
pub mod acr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ACR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `START`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum STARTR {
#[doc = "Auto-baud stop (auto-baud is not running)."]
STOP,
#[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
START,
}
impl STARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
STARTR::STOP => false,
STARTR::START => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> STARTR {
match value {
false => STARTR::STOP,
true => STARTR::START,
}
}
#[doc = "Checks if the value of the field is `STOP`"]
#[inline]
pub fn is_stop(&self) -> bool {
*self == STARTR::STOP
}
#[doc = "Checks if the value of the field is `START`"]
#[inline]
pub fn is_start(&self) -> bool {
*self == STARTR::START
}
}
#[doc = "Possible values of the field `MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MODER {
#[doc = "Mode 0."]
MODE_0_,
#[doc = "Mode 1."]
MODE_1_,
}
impl MODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MODER::MODE_0_ => false,
MODER::MODE_1_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MODER {
match value {
false => MODER::MODE_0_,
true => MODER::MODE_1_,
}
}
#[doc = "Checks if the value of the field is `MODE_0_`"]
#[inline]
pub fn is_mode_0_(&self) -> bool {
*self == MODER::MODE_0_
}
#[doc = "Checks if the value of the field is `MODE_1_`"]
#[inline]
pub fn is_mode_1_(&self) -> bool {
*self == MODER::MODE_1_
}
}
#[doc = "Possible values of the field `AUTORESTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AUTORESTARTR {
#[doc = "No restart"]
NO_RESTART,
#[doc = "Restart in case of time-out (counter restarts at next UART1 Rx falling edge)"]
RESTART_IN_CASE_OF_T,
}
impl AUTORESTARTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AUTORESTARTR::NO_RESTART => false,
AUTORESTARTR::RESTART_IN_CASE_OF_T => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AUTORESTARTR {
match value {
false => AUTORESTARTR::NO_RESTART,
true => AUTORESTARTR::RESTART_IN_CASE_OF_T,
}
}
#[doc = "Checks if the value of the field is `NO_RESTART`"]
#[inline]
pub fn is_no_restart(&self) -> bool {
*self == AUTORESTARTR::NO_RESTART
}
#[doc = "Checks if the value of the field is `RESTART_IN_CASE_OF_T`"]
#[inline]
pub fn is_restart_in_case_of_t(&self) -> bool {
*self == AUTORESTARTR::RESTART_IN_CASE_OF_T
}
}
#[doc = "Possible values of the field `ABEOINTCLR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABEOINTCLRR {
#[doc = "Writing a 0 has no impact."]
WRITING_A_0_HAS_NO_I,
#[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."]
WRITING_A_1_WILL_CLE,
}
impl ABEOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABEOINTCLRR::WRITING_A_0_HAS_NO_I => false,
ABEOINTCLRR::WRITING_A_1_WILL_CLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABEOINTCLRR {
match value {
false => ABEOINTCLRR::WRITING_A_0_HAS_NO_I,
true => ABEOINTCLRR::WRITING_A_1_WILL_CLE,
}
}
#[doc = "Checks if the value of the field is `WRITING_A_0_HAS_NO_I`"]
#[inline]
pub fn is_writing_a_0_has_no_i(&self) -> bool {
*self == ABEOINTCLRR::WRITING_A_0_HAS_NO_I
}
#[doc = "Checks if the value of the field is `WRITING_A_1_WILL_CLE`"]
#[inline]
pub fn is_writing_a_1_will_cle(&self) -> bool {
*self == ABEOINTCLRR::WRITING_A_1_WILL_CLE
}
}
#[doc = "Possible values of the field `ABTOINTCLR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABTOINTCLRR {
#[doc = "Writing a 0 has no impact."]
WRITING_A_0_HAS_NO_I,
#[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."]
WRITING_A_1_WILL_CLE,
}
impl ABTOINTCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABTOINTCLRR::WRITING_A_0_HAS_NO_I => false,
ABTOINTCLRR::WRITING_A_1_WILL_CLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABTOINTCLRR {
match value {
false => ABTOINTCLRR::WRITING_A_0_HAS_NO_I,
true => ABTOINTCLRR::WRITING_A_1_WILL_CLE,
}
}
#[doc = "Checks if the value of the field is `WRITING_A_0_HAS_NO_I`"]
#[inline]
pub fn is_writing_a_0_has_no_i(&self) -> bool {
*self == ABTOINTCLRR::WRITING_A_0_HAS_NO_I
}
#[doc = "Checks if the value of the field is `WRITING_A_1_WILL_CLE`"]
#[inline]
pub fn is_writing_a_1_will_cle(&self) -> bool {
*self == ABTOINTCLRR::WRITING_A_1_WILL_CLE
}
}
#[doc = "Values that can be written to the field `START`"]
pub enum STARTW {
#[doc = "Auto-baud stop (auto-baud is not running)."]
STOP,
#[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
START,
}
impl STARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
STARTW::STOP => false,
STARTW::START => true,
}
}
}
#[doc = r" Proxy"]
pub struct _STARTW<'a> {
w: &'a mut W,
}
impl<'a> _STARTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Auto-baud stop (auto-baud is not running)."]
#[inline]
pub fn stop(self) -> &'a mut W {
self.variant(STARTW::STOP)
}
#[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."]
#[inline]
pub fn start(self) -> &'a mut W {
self.variant(STARTW::START)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "Mode 0."]
MODE_0_,
#[doc = "Mode 1."]
MODE_1_,
}
impl MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MODEW::MODE_0_ => false,
MODEW::MODE_1_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MODEW<'a> {
w: &'a mut W,
}
impl<'a> _MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MODEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Mode 0."]
#[inline]
pub fn mode_0_(self) -> &'a mut W {
self.variant(MODEW::MODE_0_)
}
#[doc = "Mode 1."]
#[inline]
pub fn mode_1_(self) -> &'a mut W {
self.variant(MODEW::MODE_1_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AUTORESTART`"]
pub enum AUTORESTARTW {
#[doc = "No restart"]
NO_RESTART,
#[doc = "Restart in case of time-out (counter restarts at next UART1 Rx falling edge)"]
RESTART_IN_CASE_OF_T,
}
impl AUTORESTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AUTORESTARTW::NO_RESTART => false,
AUTORESTARTW::RESTART_IN_CASE_OF_T => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AUTORESTARTW<'a> {
w: &'a mut W,
}
impl<'a> _AUTORESTARTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AUTORESTARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No restart"]
#[inline]
pub fn no_restart(self) -> &'a mut W {
self.variant(AUTORESTARTW::NO_RESTART)
}
#[doc = "Restart in case of time-out (counter restarts at next UART1 Rx falling edge)"]
#[inline]
pub fn restart_in_case_of_t(self) -> &'a mut W {
self.variant(AUTORESTARTW::RESTART_IN_CASE_OF_T)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABEOINTCLR`"]
pub enum ABEOINTCLRW {
#[doc = "Writing a 0 has no impact."]
WRITING_A_0_HAS_NO_I,
#[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."]
WRITING_A_1_WILL_CLE,
}
impl ABEOINTCLRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABEOINTCLRW::WRITING_A_0_HAS_NO_I => false,
ABEOINTCLRW::WRITING_A_1_WILL_CLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABEOINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABEOINTCLRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABEOINTCLRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Writing a 0 has no impact."]
#[inline]
pub fn writing_a_0_has_no_i(self) -> &'a mut W {
self.variant(ABEOINTCLRW::WRITING_A_0_HAS_NO_I)
}
#[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."]
#[inline]
pub fn writing_a_1_will_cle(self) -> &'a mut W {
self.variant(ABEOINTCLRW::WRITING_A_1_WILL_CLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ABTOINTCLR`"]
pub enum ABTOINTCLRW {
#[doc = "Writing a 0 has no impact."]
WRITING_A_0_HAS_NO_I,
#[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."]
WRITING_A_1_WILL_CLE,
}
impl ABTOINTCLRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ABTOINTCLRW::WRITING_A_0_HAS_NO_I => false,
ABTOINTCLRW::WRITING_A_1_WILL_CLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ABTOINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABTOINTCLRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ABTOINTCLRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Writing a 0 has no impact."]
#[inline]
pub fn writing_a_0_has_no_i(self) -> &'a mut W {
self.variant(ABTOINTCLRW::WRITING_A_0_HAS_NO_I)
}
#[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."]
#[inline]
pub fn writing_a_1_will_cle(self) -> &'a mut W {
self.variant(ABTOINTCLRW::WRITING_A_1_WILL_CLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Auto-baud start bit. This bit is automatically cleared after auto-baud completion."]
#[inline]
pub fn start(&self) -> STARTR {
STARTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Auto-baud mode select bit."]
#[inline]
pub fn mode(&self) -> MODER {
MODER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Auto-baud restart bit."]
#[inline]
pub fn autorestart(&self) -> AUTORESTARTR {
AUTORESTARTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - End of auto-baud interrupt clear bit (write-only)."]
#[inline]
pub fn abeointclr(&self) -> ABEOINTCLRR {
ABEOINTCLRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Auto-baud time-out interrupt clear bit (write-only)."]
#[inline]
pub fn abtointclr(&self) -> ABTOINTCLRR {
ABTOINTCLRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Auto-baud start bit. This bit is automatically cleared after auto-baud completion."]
#[inline]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
#[doc = "Bit 1 - Auto-baud mode select bit."]
#[inline]
pub fn mode(&mut self) -> _MODEW {
_MODEW { w: self }
}
#[doc = "Bit 2 - Auto-baud restart bit."]
#[inline]
pub fn autorestart(&mut self) -> _AUTORESTARTW {
_AUTORESTARTW { w: self }
}
#[doc = "Bit 8 - End of auto-baud interrupt clear bit (write-only)."]
#[inline]
pub fn abeointclr(&mut self) -> _ABEOINTCLRW {
_ABEOINTCLRW { w: self }
}
#[doc = "Bit 9 - Auto-baud time-out interrupt clear bit (write-only)."]
#[inline]
pub fn abtointclr(&mut self) -> _ABTOINTCLRW {
_ABTOINTCLRW { w: self }
}
}
}
#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider."]
pub struct FDR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider."]
pub mod fdr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FDR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DIVADDVALR {
bits: u8,
}
impl DIVADDVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MULVALR {
bits: u8,
}
impl MULVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DIVADDVALW<'a> {
w: &'a mut W,
}
impl<'a> _DIVADDVALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MULVALW<'a> {
w: &'a mut W,
}
impl<'a> _MULVALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate."]
#[inline]
pub fn divaddval(&self) -> DIVADDVALR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DIVADDVALR { bits }
}
#[doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not."]
#[inline]
pub fn mulval(&self) -> MULVALR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MULVALR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x10 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate."]
#[inline]
pub fn divaddval(&mut self) -> _DIVADDVALW {
_DIVADDVALW { w: self }
}
#[doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not."]
#[inline]
pub fn mulval(&mut self) -> _MULVALW {
_MULVALW { w: self }
}
}
}
#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
pub struct TER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
pub mod ter {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXENR {
bits: bool,
}
impl TXENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _TXENW<'a> {
w: &'a mut W,
}
impl<'a> _TXENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."]
#[inline]
pub fn txen(&self) -> TXENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x80 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."]
#[inline]
pub fn txen(&mut self) -> _TXENW {
_TXENW { w: self }
}
}
}
#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
pub struct RS485CTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
pub mod rs485ctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RS485CTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `NMMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NMMENR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt."]
ENABLED_IN_THIS_MOD,
}
impl NMMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
NMMENR::DISABLED_ => false,
NMMENR::ENABLED_IN_THIS_MOD => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> NMMENR {
match value {
false => NMMENR::DISABLED_,
true => NMMENR::ENABLED_IN_THIS_MOD,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == NMMENR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_IN_THIS_MOD`"]
#[inline]
pub fn is_enabled_in_this_mod(&self) -> bool {
*self == NMMENR::ENABLED_IN_THIS_MOD
}
}
#[doc = "Possible values of the field `RXDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXDISR {
#[doc = "Enabled."]
ENABLED_,
#[doc = "Disabled."]
DISABLED_,
}
impl RXDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RXDISR::ENABLED_ => false,
RXDISR::DISABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RXDISR {
match value {
false => RXDISR::ENABLED_,
true => RXDISR::DISABLED_,
}
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == RXDISR::ENABLED_
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == RXDISR::DISABLED_
}
}
#[doc = "Possible values of the field `AADEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AADENR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl AADENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AADENR::DISABLED_ => false,
AADENR::ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AADENR {
match value {
false => AADENR::DISABLED_,
true => AADENR::ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == AADENR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == AADENR::ENABLED_
}
}
#[doc = "Possible values of the field `SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SELR {
#[doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."]
RTS_IF_DIRECTION_CO,
#[doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."]
DTR_IF_DIRECTION_CO,
}
impl SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SELR::RTS_IF_DIRECTION_CO => false,
SELR::DTR_IF_DIRECTION_CO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SELR {
match value {
false => SELR::RTS_IF_DIRECTION_CO,
true => SELR::DTR_IF_DIRECTION_CO,
}
}
#[doc = "Checks if the value of the field is `RTS_IF_DIRECTION_CO`"]
#[inline]
pub fn is_rts_if_direction_co(&self) -> bool {
*self == SELR::RTS_IF_DIRECTION_CO
}
#[doc = "Checks if the value of the field is `DTR_IF_DIRECTION_CO`"]
#[inline]
pub fn is_dtr_if_direction_co(&self) -> bool {
*self == SELR::DTR_IF_DIRECTION_CO
}
}
#[doc = "Possible values of the field `DCTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCTRLR {
#[doc = "Disable Auto Direction Control."]
DISABLE_AUTO_DIRECTI,
#[doc = "Enable Auto Direction Control."]
ENABLE_AUTO_DIRECTIO,
}
impl DCTRLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCTRLR::DISABLE_AUTO_DIRECTI => false,
DCTRLR::ENABLE_AUTO_DIRECTIO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCTRLR {
match value {
false => DCTRLR::DISABLE_AUTO_DIRECTI,
true => DCTRLR::ENABLE_AUTO_DIRECTIO,
}
}
#[doc = "Checks if the value of the field is `DISABLE_AUTO_DIRECTI`"]
#[inline]
pub fn is_disable_auto_directi(&self) -> bool {
*self == DCTRLR::DISABLE_AUTO_DIRECTI
}
#[doc = "Checks if the value of the field is `ENABLE_AUTO_DIRECTIO`"]
#[inline]
pub fn is_enable_auto_directio(&self) -> bool {
*self == DCTRLR::ENABLE_AUTO_DIRECTIO
}
}
#[doc = "Possible values of the field `OINV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OINVR {
#[doc = "LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
LOW_THE_DIRECTION_C,
#[doc = "HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
HIGH_THE_DIRECTION_,
}
impl OINVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OINVR::LOW_THE_DIRECTION_C => false,
OINVR::HIGH_THE_DIRECTION_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OINVR {
match value {
false => OINVR::LOW_THE_DIRECTION_C,
true => OINVR::HIGH_THE_DIRECTION_,
}
}
#[doc = "Checks if the value of the field is `LOW_THE_DIRECTION_C`"]
#[inline]
pub fn is_low_the_direction_c(&self) -> bool {
*self == OINVR::LOW_THE_DIRECTION_C
}
#[doc = "Checks if the value of the field is `HIGH_THE_DIRECTION_`"]
#[inline]
pub fn is_high_the_direction_(&self) -> bool {
*self == OINVR::HIGH_THE_DIRECTION_
}
}
#[doc = "Values that can be written to the field `NMMEN`"]
pub enum NMMENW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt."]
ENABLED_IN_THIS_MOD,
}
impl NMMENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
NMMENW::DISABLED_ => false,
NMMENW::ENABLED_IN_THIS_MOD => true,
}
}
}
#[doc = r" Proxy"]
pub struct _NMMENW<'a> {
w: &'a mut W,
}
impl<'a> _NMMENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: NMMENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(NMMENW::DISABLED_)
}
#[doc = "Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt."]
#[inline]
pub fn enabled_in_this_mod(self) -> &'a mut W {
self.variant(NMMENW::ENABLED_IN_THIS_MOD)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RXDIS`"]
pub enum RXDISW {
#[doc = "Enabled."]
ENABLED_,
#[doc = "Disabled."]
DISABLED_,
}
impl RXDISW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RXDISW::ENABLED_ => false,
RXDISW::DISABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RXDISW<'a> {
w: &'a mut W,
}
impl<'a> _RXDISW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXDISW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(RXDISW::ENABLED_)
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(RXDISW::DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AADEN`"]
pub enum AADENW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl AADENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AADENW::DISABLED_ => false,
AADENW::ENABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AADENW<'a> {
w: &'a mut W,
}
impl<'a> _AADENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AADENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(AADENW::DISABLED_)
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(AADENW::ENABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SEL`"]
pub enum SELW {
#[doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."]
RTS_IF_DIRECTION_CO,
#[doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."]
DTR_IF_DIRECTION_CO,
}
impl SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SELW::RTS_IF_DIRECTION_CO => false,
SELW::DTR_IF_DIRECTION_CO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SELW<'a> {
w: &'a mut W,
}
impl<'a> _SELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SELW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."]
#[inline]
pub fn rts_if_direction_co(self) -> &'a mut W {
self.variant(SELW::RTS_IF_DIRECTION_CO)
}
#[doc = "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."]
#[inline]
pub fn dtr_if_direction_co(self) -> &'a mut W {
self.variant(SELW::DTR_IF_DIRECTION_CO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DCTRL`"]
pub enum DCTRLW {
#[doc = "Disable Auto Direction Control."]
DISABLE_AUTO_DIRECTI,
#[doc = "Enable Auto Direction Control."]
ENABLE_AUTO_DIRECTIO,
}
impl DCTRLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DCTRLW::DISABLE_AUTO_DIRECTI => false,
DCTRLW::ENABLE_AUTO_DIRECTIO => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _DCTRLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DCTRLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable Auto Direction Control."]
#[inline]
pub fn disable_auto_directi(self) -> &'a mut W {
self.variant(DCTRLW::DISABLE_AUTO_DIRECTI)
}
#[doc = "Enable Auto Direction Control."]
#[inline]
pub fn enable_auto_directio(self) -> &'a mut W {
self.variant(DCTRLW::ENABLE_AUTO_DIRECTIO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `OINV`"]
pub enum OINVW {
#[doc = "LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
LOW_THE_DIRECTION_C,
#[doc = "HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
HIGH_THE_DIRECTION_,
}
impl OINVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OINVW::LOW_THE_DIRECTION_C => false,
OINVW::HIGH_THE_DIRECTION_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OINVW<'a> {
w: &'a mut W,
}
impl<'a> _OINVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OINVW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."]
#[inline]
pub fn low_the_direction_c(self) -> &'a mut W {
self.variant(OINVW::LOW_THE_DIRECTION_C)
}
#[doc = "HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."]
#[inline]
pub fn high_the_direction_(self) -> &'a mut W {
self.variant(OINVW::HIGH_THE_DIRECTION_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select."]
#[inline]
pub fn nmmen(&self) -> NMMENR {
NMMENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Receive enable."]
#[inline]
pub fn rxdis(&self) -> RXDISR {
RXDISR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Auto Address Detect (AAD) enable."]
#[inline]
pub fn aaden(&self) -> AADENR {
AADENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Direction control."]
#[inline]
pub fn sel(&self) -> SELR {
SELR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Direction control enable."]
#[inline]
pub fn dctrl(&self) -> DCTRLR {
DCTRLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."]
#[inline]
pub fn oinv(&self) -> OINVR {
OINVR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select."]
#[inline]
pub fn nmmen(&mut self) -> _NMMENW {
_NMMENW { w: self }
}
#[doc = "Bit 1 - Receive enable."]
#[inline]
pub fn rxdis(&mut self) -> _RXDISW {
_RXDISW { w: self }
}
#[doc = "Bit 2 - Auto Address Detect (AAD) enable."]
#[inline]
pub fn aaden(&mut self) -> _AADENW {
_AADENW { w: self }
}
#[doc = "Bit 3 - Direction control."]
#[inline]
pub fn sel(&mut self) -> _SELW {
_SELW { w: self }
}
#[doc = "Bit 4 - Direction control enable."]
#[inline]
pub fn dctrl(&mut self) -> _DCTRLW {
_DCTRLW { w: self }
}
#[doc = "Bit 5 - Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."]
#[inline]
pub fn oinv(&mut self) -> _OINVW {
_OINVW { w: self }
}
}
}
#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
pub struct RS485ADRMATCH {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
pub mod rs485adrmatch {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RS485ADRMATCH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADRMATCHR {
bits: u8,
}
impl ADRMATCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADRMATCHW<'a> {
w: &'a mut W,
}
impl<'a> _ADRMATCHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Contains the address match value."]
#[inline]
pub fn adrmatch(&self) -> ADRMATCHR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ADRMATCHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Contains the address match value."]
#[inline]
pub fn adrmatch(&mut self) -> _ADRMATCHW {
_ADRMATCHW { w: self }
}
}
}
#[doc = "RS-485/EIA-485 direction control delay."]
pub struct RS485DLY {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RS-485/EIA-485 direction control delay."]
pub mod rs485dly {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RS485DLY {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DLYR {
bits: u8,
}
impl DLYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DLYW<'a> {
w: &'a mut W,
}
impl<'a> _DLYW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."]
#[inline]
pub fn dly(&self) -> DLYR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLYR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."]
#[inline]
pub fn dly(&mut self) -> _DLYW {
_DLYW { w: self }
}
}
}
}
#[doc = "Pulse Width Modulators (PWM1)"]
pub struct PWM1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for PWM1 {}
impl PWM1 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const pwm1::RegisterBlock {
0x4001_8000 as *const _
}
}
impl Deref for PWM1 {
type Target = pwm1::RegisterBlock;
fn deref(&self) -> &pwm1::RegisterBlock {
unsafe { &*PWM1::ptr() }
}
}
#[doc = "Pulse Width Modulators (PWM1)"]
pub mod pwm1 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending."]
pub ir: IR,
#[doc = "0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions."]
pub tcr: TCR,
#[doc = "0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub tc: TC,
#[doc = "0x0c - Prescale Register. Determines how often the PWM counter is incremented."]
pub pr: PR,
#[doc = "0x10 - Prescale Counter. Prescaler for the main PWM counter."]
pub pc: PC,
#[doc = "0x14 - Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs."]
pub mcr: MCR,
#[doc = "0x18 - Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges."]
pub mr: [MR; 4],
#[doc = "0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event."]
pub ccr: CCR,
#[doc = "0x2c - PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs."]
pub cr: [CR; 2],
_reserved9: [u8; 12usize],
#[doc = "0x40 - Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges."]
pub mr4: MR,
#[doc = "0x44 - Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges."]
pub mr5: MR,
#[doc = "0x48 - Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges."]
pub mr6: MR,
#[doc = "0x4c - PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs."]
pub pcr: PCR,
#[doc = "0x50 - Load Enable Register. Enables use of updated PWM match values."]
pub ler: LER,
_reserved14: [u8; 28usize],
#[doc = "0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub ctcr: CTCR,
}
#[doc = "Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending."]
pub struct IR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending."]
pub mod ir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PWMMR0INTR {
bits: bool,
}
impl PWMMR0INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMMR1INTR {
bits: bool,
}
impl PWMMR1INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMMR2INTR {
bits: bool,
}
impl PWMMR2INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMMR3INTR {
bits: bool,
}
impl PWMMR3INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMCAP0INTR {
bits: bool,
}
impl PWMCAP0INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMCAP1INTR {
bits: bool,
}
impl PWMCAP1INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMMR4INTR {
bits: bool,
}
impl PWMMR4INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMMR5INTR {
bits: bool,
}
impl PWMMR5INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PWMMR6INTR {
bits: bool,
}
impl PWMMR6INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PWMMR0INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR0INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMMR1INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR1INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMMR2INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR2INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMMR3INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR3INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMCAP0INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMCAP0INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMCAP1INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMCAP1INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMMR4INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR4INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMMR5INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR5INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PWMMR6INTW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR6INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt flag for PWM match channel 0."]
#[inline]
pub fn pwmmr0int(&self) -> PWMMR0INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR0INTR { bits }
}
#[doc = "Bit 1 - Interrupt flag for PWM match channel 1."]
#[inline]
pub fn pwmmr1int(&self) -> PWMMR1INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR1INTR { bits }
}
#[doc = "Bit 2 - Interrupt flag for PWM match channel 2."]
#[inline]
pub fn pwmmr2int(&self) -> PWMMR2INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR2INTR { bits }
}
#[doc = "Bit 3 - Interrupt flag for PWM match channel 3."]
#[inline]
pub fn pwmmr3int(&self) -> PWMMR3INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR3INTR { bits }
}
#[doc = "Bit 4 - Interrupt flag for capture input 0"]
#[inline]
pub fn pwmcap0int(&self) -> PWMCAP0INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMCAP0INTR { bits }
}
#[doc = "Bit 5 - Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)."]
#[inline]
pub fn pwmcap1int(&self) -> PWMCAP1INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMCAP1INTR { bits }
}
#[doc = "Bit 8 - Interrupt flag for PWM match channel 4."]
#[inline]
pub fn pwmmr4int(&self) -> PWMMR4INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR4INTR { bits }
}
#[doc = "Bit 9 - Interrupt flag for PWM match channel 5."]
#[inline]
pub fn pwmmr5int(&self) -> PWMMR5INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR5INTR { bits }
}
#[doc = "Bit 10 - Interrupt flag for PWM match channel 6."]
#[inline]
pub fn pwmmr6int(&self) -> PWMMR6INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PWMMR6INTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt flag for PWM match channel 0."]
#[inline]
pub fn pwmmr0int(&mut self) -> _PWMMR0INTW {
_PWMMR0INTW { w: self }
}
#[doc = "Bit 1 - Interrupt flag for PWM match channel 1."]
#[inline]
pub fn pwmmr1int(&mut self) -> _PWMMR1INTW {
_PWMMR1INTW { w: self }
}
#[doc = "Bit 2 - Interrupt flag for PWM match channel 2."]
#[inline]
pub fn pwmmr2int(&mut self) -> _PWMMR2INTW {
_PWMMR2INTW { w: self }
}
#[doc = "Bit 3 - Interrupt flag for PWM match channel 3."]
#[inline]
pub fn pwmmr3int(&mut self) -> _PWMMR3INTW {
_PWMMR3INTW { w: self }
}
#[doc = "Bit 4 - Interrupt flag for capture input 0"]
#[inline]
pub fn pwmcap0int(&mut self) -> _PWMCAP0INTW {
_PWMCAP0INTW { w: self }
}
#[doc = "Bit 5 - Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)."]
#[inline]
pub fn pwmcap1int(&mut self) -> _PWMCAP1INTW {
_PWMCAP1INTW { w: self }
}
#[doc = "Bit 8 - Interrupt flag for PWM match channel 4."]
#[inline]
pub fn pwmmr4int(&mut self) -> _PWMMR4INTW {
_PWMMR4INTW { w: self }
}
#[doc = "Bit 9 - Interrupt flag for PWM match channel 5."]
#[inline]
pub fn pwmmr5int(&mut self) -> _PWMMR5INTW {
_PWMMR5INTW { w: self }
}
#[doc = "Bit 10 - Interrupt flag for PWM match channel 6."]
#[inline]
pub fn pwmmr6int(&mut self) -> _PWMMR6INTW {
_PWMMR6INTW { w: self }
}
}
}
#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions."]
pub struct TCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions."]
pub mod tcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CER {
#[doc = "The PWM Timer Counter and PWM Prescale Counter are enabled for counting."]
THE_PWM_TIMER_COUNTE,
#[doc = "The counters are disabled."]
THE_COUNTERS_ARE_DIS,
}
impl CER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CER::THE_PWM_TIMER_COUNTE => true,
CER::THE_COUNTERS_ARE_DIS => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CER {
match value {
true => CER::THE_PWM_TIMER_COUNTE,
false => CER::THE_COUNTERS_ARE_DIS,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_TIMER_COUNTE`"]
#[inline]
pub fn is_the_pwm_timer_counte(&self) -> bool {
*self == CER::THE_PWM_TIMER_COUNTE
}
#[doc = "Checks if the value of the field is `THE_COUNTERS_ARE_DIS`"]
#[inline]
pub fn is_the_counters_are_dis(&self) -> bool {
*self == CER::THE_COUNTERS_ARE_DIS
}
}
#[doc = "Possible values of the field `CR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRR {
#[doc = "The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero."]
THE_PWM_TIMER_COUNTE,
#[doc = "Clear reset."]
CLEAR_RESET_,
}
impl CRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CRR::THE_PWM_TIMER_COUNTE => true,
CRR::CLEAR_RESET_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CRR {
match value {
true => CRR::THE_PWM_TIMER_COUNTE,
false => CRR::CLEAR_RESET_,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_TIMER_COUNTE`"]
#[inline]
pub fn is_the_pwm_timer_counte(&self) -> bool {
*self == CRR::THE_PWM_TIMER_COUNTE
}
#[doc = "Checks if the value of the field is `CLEAR_RESET_`"]
#[inline]
pub fn is_clear_reset_(&self) -> bool {
*self == CRR::CLEAR_RESET_
}
}
#[doc = "Possible values of the field `PWMEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENR {
#[doc = "PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective."]
PWM_MODE_IS_ENABLED_,
#[doc = "Timer mode is enabled (counter resets to 0)."]
TIMER_MODE_IS_ENABLE,
}
impl PWMENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENR::PWM_MODE_IS_ENABLED_ => true,
PWMENR::TIMER_MODE_IS_ENABLE => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENR {
match value {
true => PWMENR::PWM_MODE_IS_ENABLED_,
false => PWMENR::TIMER_MODE_IS_ENABLE,
}
}
#[doc = "Checks if the value of the field is `PWM_MODE_IS_ENABLED_`"]
#[inline]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == PWMENR::PWM_MODE_IS_ENABLED_
}
#[doc = "Checks if the value of the field is `TIMER_MODE_IS_ENABLE`"]
#[inline]
pub fn is_timer_mode_is_enable(&self) -> bool {
*self == PWMENR::TIMER_MODE_IS_ENABLE
}
}
#[doc = "Possible values of the field `MDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MDISR {
#[doc = "Master use. PWM0 is the master, and both PWMs are enabled for counting."]
MASTER_USE_PWM0_IS_,
#[doc = "Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs."]
INDIVIDUAL_USE_THE_,
}
impl MDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MDISR::MASTER_USE_PWM0_IS_ => true,
MDISR::INDIVIDUAL_USE_THE_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MDISR {
match value {
true => MDISR::MASTER_USE_PWM0_IS_,
false => MDISR::INDIVIDUAL_USE_THE_,
}
}
#[doc = "Checks if the value of the field is `MASTER_USE_PWM0_IS_`"]
#[inline]
pub fn is_master_use_pwm0_is_(&self) -> bool {
*self == MDISR::MASTER_USE_PWM0_IS_
}
#[doc = "Checks if the value of the field is `INDIVIDUAL_USE_THE_`"]
#[inline]
pub fn is_individual_use_the_(&self) -> bool {
*self == MDISR::INDIVIDUAL_USE_THE_
}
}
#[doc = "Values that can be written to the field `CE`"]
pub enum CEW {
#[doc = "The PWM Timer Counter and PWM Prescale Counter are enabled for counting."]
THE_PWM_TIMER_COUNTE,
#[doc = "The counters are disabled."]
THE_COUNTERS_ARE_DIS,
}
impl CEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CEW::THE_PWM_TIMER_COUNTE => true,
CEW::THE_COUNTERS_ARE_DIS => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CEW<'a> {
w: &'a mut W,
}
impl<'a> _CEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM Timer Counter and PWM Prescale Counter are enabled for counting."]
#[inline]
pub fn the_pwm_timer_counte(self) -> &'a mut W {
self.variant(CEW::THE_PWM_TIMER_COUNTE)
}
#[doc = "The counters are disabled."]
#[inline]
pub fn the_counters_are_dis(self) -> &'a mut W {
self.variant(CEW::THE_COUNTERS_ARE_DIS)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CR`"]
pub enum CRW {
#[doc = "The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero."]
THE_PWM_TIMER_COUNTE,
#[doc = "Clear reset."]
CLEAR_RESET_,
}
impl CRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CRW::THE_PWM_TIMER_COUNTE => true,
CRW::CLEAR_RESET_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CRW<'a> {
w: &'a mut W,
}
impl<'a> _CRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero."]
#[inline]
pub fn the_pwm_timer_counte(self) -> &'a mut W {
self.variant(CRW::THE_PWM_TIMER_COUNTE)
}
#[doc = "Clear reset."]
#[inline]
pub fn clear_reset_(self) -> &'a mut W {
self.variant(CRW::CLEAR_RESET_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMEN`"]
pub enum PWMENW {
#[doc = "PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective."]
PWM_MODE_IS_ENABLED_,
#[doc = "Timer mode is enabled (counter resets to 0)."]
TIMER_MODE_IS_ENABLE,
}
impl PWMENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENW::PWM_MODE_IS_ENABLED_ => true,
PWMENW::TIMER_MODE_IS_ENABLE => false,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENW<'a> {
w: &'a mut W,
}
impl<'a> _PWMENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective."]
#[inline]
pub fn pwm_mode_is_enabled_(self) -> &'a mut W {
self.variant(PWMENW::PWM_MODE_IS_ENABLED_)
}
#[doc = "Timer mode is enabled (counter resets to 0)."]
#[inline]
pub fn timer_mode_is_enable(self) -> &'a mut W {
self.variant(PWMENW::TIMER_MODE_IS_ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MDIS`"]
pub enum MDISW {
#[doc = "Master use. PWM0 is the master, and both PWMs are enabled for counting."]
MASTER_USE_PWM0_IS_,
#[doc = "Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs."]
INDIVIDUAL_USE_THE_,
}
impl MDISW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MDISW::MASTER_USE_PWM0_IS_ => true,
MDISW::INDIVIDUAL_USE_THE_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _MDISW<'a> {
w: &'a mut W,
}
impl<'a> _MDISW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MDISW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Master use. PWM0 is the master, and both PWMs are enabled for counting."]
#[inline]
pub fn master_use_pwm0_is_(self) -> &'a mut W {
self.variant(MDISW::MASTER_USE_PWM0_IS_)
}
#[doc = "Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs."]
#[inline]
pub fn individual_use_the_(self) -> &'a mut W {
self.variant(MDISW::INDIVIDUAL_USE_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Counter Enable"]
#[inline]
pub fn ce(&self) -> CER {
CER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Counter Reset"]
#[inline]
pub fn cr(&self) -> CRR {
CRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - PWM Enable"]
#[inline]
pub fn pwmen(&self) -> PWMENR {
PWMENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1)."]
#[inline]
pub fn mdis(&self) -> MDISR {
MDISR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Counter Enable"]
#[inline]
pub fn ce(&mut self) -> _CEW {
_CEW { w: self }
}
#[doc = "Bit 1 - Counter Reset"]
#[inline]
pub fn cr(&mut self) -> _CRW {
_CRW { w: self }
}
#[doc = "Bit 3 - PWM Enable"]
#[inline]
pub fn pwmen(&mut self) -> _PWMENW {
_PWMENW { w: self }
}
#[doc = "Bit 4 - Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1)."]
#[inline]
pub fn mdis(&mut self) -> _MDISW {
_MDISW { w: self }
}
}
}
#[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub struct TC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub mod tc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TCR {
bits: u32,
}
impl TCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TCW<'a> {
w: &'a mut W,
}
impl<'a> _TCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Timer counter value."]
#[inline]
pub fn tc(&self) -> TCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
TCR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Timer counter value."]
#[inline]
pub fn tc(&mut self) -> _TCW {
_TCW { w: self }
}
}
}
#[doc = "Prescale Register. Determines how often the PWM counter is incremented."]
pub struct PR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Prescale Register. Determines how often the PWM counter is incremented."]
pub mod pr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PMR {
bits: u32,
}
impl PMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PMW<'a> {
w: &'a mut W,
}
impl<'a> _PMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Prescale counter maximum value."]
#[inline]
pub fn pm(&self) -> PMR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Prescale counter maximum value."]
#[inline]
pub fn pm(&mut self) -> _PMW {
_PMW { w: self }
}
}
}
#[doc = "Prescale Counter. Prescaler for the main PWM counter."]
pub struct PC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Prescale Counter. Prescaler for the main PWM counter."]
pub mod pc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PCR {
bits: u32,
}
impl PCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PCW<'a> {
w: &'a mut W,
}
impl<'a> _PCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Prescale counter value."]
#[inline]
pub fn pc(&self) -> PCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PCR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Prescale counter value."]
#[inline]
pub fn pc(&mut self) -> _PCW {
_PCW { w: self }
}
}
}
#[doc = "Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs."]
pub struct MCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs."]
pub mod mcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `PWMMR0I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR0IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR0,
}
impl PWMMR0IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR0IR::DISABLED_ => false,
PWMMR0IR::INTERRUPT_ON_PWMMR0 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR0IR {
match value {
false => PWMMR0IR::DISABLED_,
true => PWMMR0IR::INTERRUPT_ON_PWMMR0,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR0IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR0`"]
#[inline]
pub fn is_interrupt_on_pwmmr0(&self) -> bool {
*self == PWMMR0IR::INTERRUPT_ON_PWMMR0
}
}
#[doc = "Possible values of the field `PWMMR0R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR0RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it."]
RESET_ON_PWMMR0_THE,
}
impl PWMMR0RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR0RR::DISABLED_ => false,
PWMMR0RR::RESET_ON_PWMMR0_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR0RR {
match value {
false => PWMMR0RR::DISABLED_,
true => PWMMR0RR::RESET_ON_PWMMR0_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR0RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR0_THE`"]
#[inline]
pub fn is_reset_on_pwmmr0_the(&self) -> bool {
*self == PWMMR0RR::RESET_ON_PWMMR0_THE
}
}
#[doc = "Possible values of the field `PWMMR0S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR0SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
STOP_ON_PWMMR0_THE_,
}
impl PWMMR0SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR0SR::DISABLED => false,
PWMMR0SR::STOP_ON_PWMMR0_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR0SR {
match value {
false => PWMMR0SR::DISABLED,
true => PWMMR0SR::STOP_ON_PWMMR0_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR0SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR0_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr0_the_(&self) -> bool {
*self == PWMMR0SR::STOP_ON_PWMMR0_THE_
}
}
#[doc = "Possible values of the field `PWMMR1I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR1IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR1,
}
impl PWMMR1IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR1IR::DISABLED_ => false,
PWMMR1IR::INTERRUPT_ON_PWMMR1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR1IR {
match value {
false => PWMMR1IR::DISABLED_,
true => PWMMR1IR::INTERRUPT_ON_PWMMR1,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR1IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR1`"]
#[inline]
pub fn is_interrupt_on_pwmmr1(&self) -> bool {
*self == PWMMR1IR::INTERRUPT_ON_PWMMR1
}
}
#[doc = "Possible values of the field `PWMMR1R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR1RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it."]
RESET_ON_PWMMR1_THE,
}
impl PWMMR1RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR1RR::DISABLED_ => false,
PWMMR1RR::RESET_ON_PWMMR1_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR1RR {
match value {
false => PWMMR1RR::DISABLED_,
true => PWMMR1RR::RESET_ON_PWMMR1_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR1RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR1_THE`"]
#[inline]
pub fn is_reset_on_pwmmr1_the(&self) -> bool {
*self == PWMMR1RR::RESET_ON_PWMMR1_THE
}
}
#[doc = "Possible values of the field `PWMMR1S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR1SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC."]
STOP_ON_PWMMR1_THE_,
}
impl PWMMR1SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR1SR::DISABLED => false,
PWMMR1SR::STOP_ON_PWMMR1_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR1SR {
match value {
false => PWMMR1SR::DISABLED,
true => PWMMR1SR::STOP_ON_PWMMR1_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR1SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR1_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr1_the_(&self) -> bool {
*self == PWMMR1SR::STOP_ON_PWMMR1_THE_
}
}
#[doc = "Possible values of the field `PWMMR2I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR2IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR2,
}
impl PWMMR2IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR2IR::DISABLED_ => false,
PWMMR2IR::INTERRUPT_ON_PWMMR2 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR2IR {
match value {
false => PWMMR2IR::DISABLED_,
true => PWMMR2IR::INTERRUPT_ON_PWMMR2,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR2IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR2`"]
#[inline]
pub fn is_interrupt_on_pwmmr2(&self) -> bool {
*self == PWMMR2IR::INTERRUPT_ON_PWMMR2
}
}
#[doc = "Possible values of the field `PWMMR2R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR2RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it."]
RESET_ON_PWMMR2_THE,
}
impl PWMMR2RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR2RR::DISABLED_ => false,
PWMMR2RR::RESET_ON_PWMMR2_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR2RR {
match value {
false => PWMMR2RR::DISABLED_,
true => PWMMR2RR::RESET_ON_PWMMR2_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR2RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR2_THE`"]
#[inline]
pub fn is_reset_on_pwmmr2_the(&self) -> bool {
*self == PWMMR2RR::RESET_ON_PWMMR2_THE
}
}
#[doc = "Possible values of the field `PWMMR2S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR2SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
STOP_ON_PWMMR2_THE_,
}
impl PWMMR2SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR2SR::DISABLED => false,
PWMMR2SR::STOP_ON_PWMMR2_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR2SR {
match value {
false => PWMMR2SR::DISABLED,
true => PWMMR2SR::STOP_ON_PWMMR2_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR2SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR2_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr2_the_(&self) -> bool {
*self == PWMMR2SR::STOP_ON_PWMMR2_THE_
}
}
#[doc = "Possible values of the field `PWMMR3I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR3IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR3,
}
impl PWMMR3IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR3IR::DISABLED_ => false,
PWMMR3IR::INTERRUPT_ON_PWMMR3 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR3IR {
match value {
false => PWMMR3IR::DISABLED_,
true => PWMMR3IR::INTERRUPT_ON_PWMMR3,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR3IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR3`"]
#[inline]
pub fn is_interrupt_on_pwmmr3(&self) -> bool {
*self == PWMMR3IR::INTERRUPT_ON_PWMMR3
}
}
#[doc = "Possible values of the field `PWMMR3R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR3RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it."]
RESET_ON_PWMMR3_THE,
}
impl PWMMR3RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR3RR::DISABLED_ => false,
PWMMR3RR::RESET_ON_PWMMR3_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR3RR {
match value {
false => PWMMR3RR::DISABLED_,
true => PWMMR3RR::RESET_ON_PWMMR3_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR3RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR3_THE`"]
#[inline]
pub fn is_reset_on_pwmmr3_the(&self) -> bool {
*self == PWMMR3RR::RESET_ON_PWMMR3_THE
}
}
#[doc = "Possible values of the field `PWMMR3S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR3SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
STOP_ON_PWMMR3_THE_,
}
impl PWMMR3SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR3SR::DISABLED => false,
PWMMR3SR::STOP_ON_PWMMR3_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR3SR {
match value {
false => PWMMR3SR::DISABLED,
true => PWMMR3SR::STOP_ON_PWMMR3_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR3SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR3_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr3_the_(&self) -> bool {
*self == PWMMR3SR::STOP_ON_PWMMR3_THE_
}
}
#[doc = "Possible values of the field `PWMMR4I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR4IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR4,
}
impl PWMMR4IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR4IR::DISABLED_ => false,
PWMMR4IR::INTERRUPT_ON_PWMMR4 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR4IR {
match value {
false => PWMMR4IR::DISABLED_,
true => PWMMR4IR::INTERRUPT_ON_PWMMR4,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR4IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR4`"]
#[inline]
pub fn is_interrupt_on_pwmmr4(&self) -> bool {
*self == PWMMR4IR::INTERRUPT_ON_PWMMR4
}
}
#[doc = "Possible values of the field `PWMMR4R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR4RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it."]
RESET_ON_PWMMR4_THE,
}
impl PWMMR4RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR4RR::DISABLED_ => false,
PWMMR4RR::RESET_ON_PWMMR4_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR4RR {
match value {
false => PWMMR4RR::DISABLED_,
true => PWMMR4RR::RESET_ON_PWMMR4_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR4RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR4_THE`"]
#[inline]
pub fn is_reset_on_pwmmr4_the(&self) -> bool {
*self == PWMMR4RR::RESET_ON_PWMMR4_THE
}
}
#[doc = "Possible values of the field `PWMMR4S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR4SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC."]
STOP_ON_PWMMR4_THE_,
}
impl PWMMR4SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR4SR::DISABLED => false,
PWMMR4SR::STOP_ON_PWMMR4_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR4SR {
match value {
false => PWMMR4SR::DISABLED,
true => PWMMR4SR::STOP_ON_PWMMR4_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR4SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR4_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr4_the_(&self) -> bool {
*self == PWMMR4SR::STOP_ON_PWMMR4_THE_
}
}
#[doc = "Possible values of the field `PWMMR5I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR5IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR5,
}
impl PWMMR5IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR5IR::DISABLED_ => false,
PWMMR5IR::INTERRUPT_ON_PWMMR5 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR5IR {
match value {
false => PWMMR5IR::DISABLED_,
true => PWMMR5IR::INTERRUPT_ON_PWMMR5,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR5IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR5`"]
#[inline]
pub fn is_interrupt_on_pwmmr5(&self) -> bool {
*self == PWMMR5IR::INTERRUPT_ON_PWMMR5
}
}
#[doc = "Possible values of the field `PWMMR5R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR5RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it."]
RESET_ON_PWMMR5_THE,
}
impl PWMMR5RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR5RR::DISABLED_ => false,
PWMMR5RR::RESET_ON_PWMMR5_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR5RR {
match value {
false => PWMMR5RR::DISABLED_,
true => PWMMR5RR::RESET_ON_PWMMR5_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR5RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR5_THE`"]
#[inline]
pub fn is_reset_on_pwmmr5_the(&self) -> bool {
*self == PWMMR5RR::RESET_ON_PWMMR5_THE
}
}
#[doc = "Possible values of the field `PWMMR5S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR5SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC."]
STOP_ON_PWMMR5_THE_,
}
impl PWMMR5SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR5SR::DISABLED => false,
PWMMR5SR::STOP_ON_PWMMR5_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR5SR {
match value {
false => PWMMR5SR::DISABLED,
true => PWMMR5SR::STOP_ON_PWMMR5_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR5SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR5_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr5_the_(&self) -> bool {
*self == PWMMR5SR::STOP_ON_PWMMR5_THE_
}
}
#[doc = "Possible values of the field `PWMMR6I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR6IR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR6,
}
impl PWMMR6IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR6IR::DISABLED_ => false,
PWMMR6IR::INTERRUPT_ON_PWMMR6 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR6IR {
match value {
false => PWMMR6IR::DISABLED_,
true => PWMMR6IR::INTERRUPT_ON_PWMMR6,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR6IR::DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ON_PWMMR6`"]
#[inline]
pub fn is_interrupt_on_pwmmr6(&self) -> bool {
*self == PWMMR6IR::INTERRUPT_ON_PWMMR6
}
}
#[doc = "Possible values of the field `PWMMR6R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR6RR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it."]
RESET_ON_PWMMR6_THE,
}
impl PWMMR6RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR6RR::DISABLED_ => false,
PWMMR6RR::RESET_ON_PWMMR6_THE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR6RR {
match value {
false => PWMMR6RR::DISABLED_,
true => PWMMR6RR::RESET_ON_PWMMR6_THE,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == PWMMR6RR::DISABLED_
}
#[doc = "Checks if the value of the field is `RESET_ON_PWMMR6_THE`"]
#[inline]
pub fn is_reset_on_pwmmr6_the(&self) -> bool {
*self == PWMMR6RR::RESET_ON_PWMMR6_THE
}
}
#[doc = "Possible values of the field `PWMMR6S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMMR6SR {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC."]
STOP_ON_PWMMR6_THE_,
}
impl PWMMR6SR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMMR6SR::DISABLED => false,
PWMMR6SR::STOP_ON_PWMMR6_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMMR6SR {
match value {
false => PWMMR6SR::DISABLED,
true => PWMMR6SR::STOP_ON_PWMMR6_THE_,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == PWMMR6SR::DISABLED
}
#[doc = "Checks if the value of the field is `STOP_ON_PWMMR6_THE_`"]
#[inline]
pub fn is_stop_on_pwmmr6_the_(&self) -> bool {
*self == PWMMR6SR::STOP_ON_PWMMR6_THE_
}
}
#[doc = "Values that can be written to the field `PWMMR0I`"]
pub enum PWMMR0IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR0,
}
impl PWMMR0IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR0IW::DISABLED_ => false,
PWMMR0IW::INTERRUPT_ON_PWMMR0 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR0IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR0IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR0IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR0IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr0(self) -> &'a mut W {
self.variant(PWMMR0IW::INTERRUPT_ON_PWMMR0)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR0R`"]
pub enum PWMMR0RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it."]
RESET_ON_PWMMR0_THE,
}
impl PWMMR0RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR0RW::DISABLED_ => false,
PWMMR0RW::RESET_ON_PWMMR0_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR0RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR0RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR0RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR0RW::DISABLED_)
}
#[doc = "Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it."]
#[inline]
pub fn reset_on_pwmmr0_the(self) -> &'a mut W {
self.variant(PWMMR0RW::RESET_ON_PWMMR0_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR0S`"]
pub enum PWMMR0SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
STOP_ON_PWMMR0_THE_,
}
impl PWMMR0SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR0SW::DISABLED => false,
PWMMR0SW::STOP_ON_PWMMR0_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR0SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR0SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR0SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR0SW::DISABLED)
}
#[doc = "Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr0_the_(self) -> &'a mut W {
self.variant(PWMMR0SW::STOP_ON_PWMMR0_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR1I`"]
pub enum PWMMR1IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR1,
}
impl PWMMR1IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR1IW::DISABLED_ => false,
PWMMR1IW::INTERRUPT_ON_PWMMR1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR1IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR1IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR1IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR1IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr1(self) -> &'a mut W {
self.variant(PWMMR1IW::INTERRUPT_ON_PWMMR1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR1R`"]
pub enum PWMMR1RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it."]
RESET_ON_PWMMR1_THE,
}
impl PWMMR1RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR1RW::DISABLED_ => false,
PWMMR1RW::RESET_ON_PWMMR1_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR1RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR1RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR1RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR1RW::DISABLED_)
}
#[doc = "Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it."]
#[inline]
pub fn reset_on_pwmmr1_the(self) -> &'a mut W {
self.variant(PWMMR1RW::RESET_ON_PWMMR1_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR1S`"]
pub enum PWMMR1SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC."]
STOP_ON_PWMMR1_THE_,
}
impl PWMMR1SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR1SW::DISABLED => false,
PWMMR1SW::STOP_ON_PWMMR1_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR1SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR1SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR1SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR1SW::DISABLED)
}
#[doc = "Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr1_the_(self) -> &'a mut W {
self.variant(PWMMR1SW::STOP_ON_PWMMR1_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR2I`"]
pub enum PWMMR2IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR2,
}
impl PWMMR2IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR2IW::DISABLED_ => false,
PWMMR2IW::INTERRUPT_ON_PWMMR2 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR2IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR2IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR2IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR2IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr2(self) -> &'a mut W {
self.variant(PWMMR2IW::INTERRUPT_ON_PWMMR2)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR2R`"]
pub enum PWMMR2RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it."]
RESET_ON_PWMMR2_THE,
}
impl PWMMR2RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR2RW::DISABLED_ => false,
PWMMR2RW::RESET_ON_PWMMR2_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR2RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR2RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR2RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR2RW::DISABLED_)
}
#[doc = "Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it."]
#[inline]
pub fn reset_on_pwmmr2_the(self) -> &'a mut W {
self.variant(PWMMR2RW::RESET_ON_PWMMR2_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR2S`"]
pub enum PWMMR2SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
STOP_ON_PWMMR2_THE_,
}
impl PWMMR2SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR2SW::DISABLED => false,
PWMMR2SW::STOP_ON_PWMMR2_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR2SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR2SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR2SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR2SW::DISABLED)
}
#[doc = "Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr2_the_(self) -> &'a mut W {
self.variant(PWMMR2SW::STOP_ON_PWMMR2_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR3I`"]
pub enum PWMMR3IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR3,
}
impl PWMMR3IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR3IW::DISABLED_ => false,
PWMMR3IW::INTERRUPT_ON_PWMMR3 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR3IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR3IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR3IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR3IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr3(self) -> &'a mut W {
self.variant(PWMMR3IW::INTERRUPT_ON_PWMMR3)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR3R`"]
pub enum PWMMR3RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it."]
RESET_ON_PWMMR3_THE,
}
impl PWMMR3RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR3RW::DISABLED_ => false,
PWMMR3RW::RESET_ON_PWMMR3_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR3RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR3RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR3RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR3RW::DISABLED_)
}
#[doc = "Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it."]
#[inline]
pub fn reset_on_pwmmr3_the(self) -> &'a mut W {
self.variant(PWMMR3RW::RESET_ON_PWMMR3_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR3S`"]
pub enum PWMMR3SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
STOP_ON_PWMMR3_THE_,
}
impl PWMMR3SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR3SW::DISABLED => false,
PWMMR3SW::STOP_ON_PWMMR3_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR3SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR3SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR3SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR3SW::DISABLED)
}
#[doc = "Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr3_the_(self) -> &'a mut W {
self.variant(PWMMR3SW::STOP_ON_PWMMR3_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR4I`"]
pub enum PWMMR4IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR4,
}
impl PWMMR4IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR4IW::DISABLED_ => false,
PWMMR4IW::INTERRUPT_ON_PWMMR4 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR4IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR4IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR4IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR4IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr4(self) -> &'a mut W {
self.variant(PWMMR4IW::INTERRUPT_ON_PWMMR4)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR4R`"]
pub enum PWMMR4RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it."]
RESET_ON_PWMMR4_THE,
}
impl PWMMR4RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR4RW::DISABLED_ => false,
PWMMR4RW::RESET_ON_PWMMR4_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR4RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR4RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR4RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR4RW::DISABLED_)
}
#[doc = "Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it."]
#[inline]
pub fn reset_on_pwmmr4_the(self) -> &'a mut W {
self.variant(PWMMR4RW::RESET_ON_PWMMR4_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR4S`"]
pub enum PWMMR4SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC."]
STOP_ON_PWMMR4_THE_,
}
impl PWMMR4SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR4SW::DISABLED => false,
PWMMR4SW::STOP_ON_PWMMR4_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR4SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR4SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR4SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR4SW::DISABLED)
}
#[doc = "Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr4_the_(self) -> &'a mut W {
self.variant(PWMMR4SW::STOP_ON_PWMMR4_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR5I`"]
pub enum PWMMR5IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR5,
}
impl PWMMR5IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR5IW::DISABLED_ => false,
PWMMR5IW::INTERRUPT_ON_PWMMR5 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR5IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR5IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR5IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR5IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr5(self) -> &'a mut W {
self.variant(PWMMR5IW::INTERRUPT_ON_PWMMR5)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR5R`"]
pub enum PWMMR5RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it."]
RESET_ON_PWMMR5_THE,
}
impl PWMMR5RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR5RW::DISABLED_ => false,
PWMMR5RW::RESET_ON_PWMMR5_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR5RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR5RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR5RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR5RW::DISABLED_)
}
#[doc = "Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it."]
#[inline]
pub fn reset_on_pwmmr5_the(self) -> &'a mut W {
self.variant(PWMMR5RW::RESET_ON_PWMMR5_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR5S`"]
pub enum PWMMR5SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC."]
STOP_ON_PWMMR5_THE_,
}
impl PWMMR5SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR5SW::DISABLED => false,
PWMMR5SW::STOP_ON_PWMMR5_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR5SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR5SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR5SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR5SW::DISABLED)
}
#[doc = "Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr5_the_(self) -> &'a mut W {
self.variant(PWMMR5SW::STOP_ON_PWMMR5_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR6I`"]
pub enum PWMMR6IW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC."]
INTERRUPT_ON_PWMMR6,
}
impl PWMMR6IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR6IW::DISABLED_ => false,
PWMMR6IW::INTERRUPT_ON_PWMMR6 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR6IW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR6IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR6IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR6IW::DISABLED_)
}
#[doc = "Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC."]
#[inline]
pub fn interrupt_on_pwmmr6(self) -> &'a mut W {
self.variant(PWMMR6IW::INTERRUPT_ON_PWMMR6)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR6R`"]
pub enum PWMMR6RW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it."]
RESET_ON_PWMMR6_THE,
}
impl PWMMR6RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR6RW::DISABLED_ => false,
PWMMR6RW::RESET_ON_PWMMR6_THE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR6RW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR6RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR6RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(PWMMR6RW::DISABLED_)
}
#[doc = "Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it."]
#[inline]
pub fn reset_on_pwmmr6_the(self) -> &'a mut W {
self.variant(PWMMR6RW::RESET_ON_PWMMR6_THE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMMR6S`"]
pub enum PWMMR6SW {
#[doc = "Disabled"]
DISABLED,
#[doc = "Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC."]
STOP_ON_PWMMR6_THE_,
}
impl PWMMR6SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMMR6SW::DISABLED => false,
PWMMR6SW::STOP_ON_PWMMR6_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMMR6SW<'a> {
w: &'a mut W,
}
impl<'a> _PWMMR6SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMMR6SW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(PWMMR6SW::DISABLED)
}
#[doc = "Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC."]
#[inline]
pub fn stop_on_pwmmr6_the_(self) -> &'a mut W {
self.variant(PWMMR6SW::STOP_ON_PWMMR6_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt PWM0"]
#[inline]
pub fn pwmmr0i(&self) -> PWMMR0IR {
PWMMR0IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Reset PWM0"]
#[inline]
pub fn pwmmr0r(&self) -> PWMMR0RR {
PWMMR0RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Stop PWM0"]
#[inline]
pub fn pwmmr0s(&self) -> PWMMR0SR {
PWMMR0SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Interrupt PWM1"]
#[inline]
pub fn pwmmr1i(&self) -> PWMMR1IR {
PWMMR1IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Reset PWM1"]
#[inline]
pub fn pwmmr1r(&self) -> PWMMR1RR {
PWMMR1RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Stop PWM1"]
#[inline]
pub fn pwmmr1s(&self) -> PWMMR1SR {
PWMMR1SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Interrupt PWM0"]
#[inline]
pub fn pwmmr2i(&self) -> PWMMR2IR {
PWMMR2IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Reset PWM0"]
#[inline]
pub fn pwmmr2r(&self) -> PWMMR2RR {
PWMMR2RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Stop PWM0"]
#[inline]
pub fn pwmmr2s(&self) -> PWMMR2SR {
PWMMR2SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Interrupt PWM3"]
#[inline]
pub fn pwmmr3i(&self) -> PWMMR3IR {
PWMMR3IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Reset PWM3"]
#[inline]
pub fn pwmmr3r(&self) -> PWMMR3RR {
PWMMR3RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Stop PWM0"]
#[inline]
pub fn pwmmr3s(&self) -> PWMMR3SR {
PWMMR3SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Interrupt PWM4"]
#[inline]
pub fn pwmmr4i(&self) -> PWMMR4IR {
PWMMR4IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - Reset PWM4"]
#[inline]
pub fn pwmmr4r(&self) -> PWMMR4RR {
PWMMR4RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Stop PWM4"]
#[inline]
pub fn pwmmr4s(&self) -> PWMMR4SR {
PWMMR4SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Interrupt PWM5"]
#[inline]
pub fn pwmmr5i(&self) -> PWMMR5IR {
PWMMR5IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Reset PWM5"]
#[inline]
pub fn pwmmr5r(&self) -> PWMMR5RR {
PWMMR5RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Stop PWM5"]
#[inline]
pub fn pwmmr5s(&self) -> PWMMR5SR {
PWMMR5SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Interrupt PWM6"]
#[inline]
pub fn pwmmr6i(&self) -> PWMMR6IR {
PWMMR6IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 19 - Reset PWM6"]
#[inline]
pub fn pwmmr6r(&self) -> PWMMR6RR {
PWMMR6RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 20 - Stop PWM6"]
#[inline]
pub fn pwmmr6s(&self) -> PWMMR6SR {
PWMMR6SR::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt PWM0"]
#[inline]
pub fn pwmmr0i(&mut self) -> _PWMMR0IW {
_PWMMR0IW { w: self }
}
#[doc = "Bit 1 - Reset PWM0"]
#[inline]
pub fn pwmmr0r(&mut self) -> _PWMMR0RW {
_PWMMR0RW { w: self }
}
#[doc = "Bit 2 - Stop PWM0"]
#[inline]
pub fn pwmmr0s(&mut self) -> _PWMMR0SW {
_PWMMR0SW { w: self }
}
#[doc = "Bit 3 - Interrupt PWM1"]
#[inline]
pub fn pwmmr1i(&mut self) -> _PWMMR1IW {
_PWMMR1IW { w: self }
}
#[doc = "Bit 4 - Reset PWM1"]
#[inline]
pub fn pwmmr1r(&mut self) -> _PWMMR1RW {
_PWMMR1RW { w: self }
}
#[doc = "Bit 5 - Stop PWM1"]
#[inline]
pub fn pwmmr1s(&mut self) -> _PWMMR1SW {
_PWMMR1SW { w: self }
}
#[doc = "Bit 6 - Interrupt PWM0"]
#[inline]
pub fn pwmmr2i(&mut self) -> _PWMMR2IW {
_PWMMR2IW { w: self }
}
#[doc = "Bit 7 - Reset PWM0"]
#[inline]
pub fn pwmmr2r(&mut self) -> _PWMMR2RW {
_PWMMR2RW { w: self }
}
#[doc = "Bit 8 - Stop PWM0"]
#[inline]
pub fn pwmmr2s(&mut self) -> _PWMMR2SW {
_PWMMR2SW { w: self }
}
#[doc = "Bit 9 - Interrupt PWM3"]
#[inline]
pub fn pwmmr3i(&mut self) -> _PWMMR3IW {
_PWMMR3IW { w: self }
}
#[doc = "Bit 10 - Reset PWM3"]
#[inline]
pub fn pwmmr3r(&mut self) -> _PWMMR3RW {
_PWMMR3RW { w: self }
}
#[doc = "Bit 11 - Stop PWM0"]
#[inline]
pub fn pwmmr3s(&mut self) -> _PWMMR3SW {
_PWMMR3SW { w: self }
}
#[doc = "Bit 12 - Interrupt PWM4"]
#[inline]
pub fn pwmmr4i(&mut self) -> _PWMMR4IW {
_PWMMR4IW { w: self }
}
#[doc = "Bit 13 - Reset PWM4"]
#[inline]
pub fn pwmmr4r(&mut self) -> _PWMMR4RW {
_PWMMR4RW { w: self }
}
#[doc = "Bit 14 - Stop PWM4"]
#[inline]
pub fn pwmmr4s(&mut self) -> _PWMMR4SW {
_PWMMR4SW { w: self }
}
#[doc = "Bit 15 - Interrupt PWM5"]
#[inline]
pub fn pwmmr5i(&mut self) -> _PWMMR5IW {
_PWMMR5IW { w: self }
}
#[doc = "Bit 16 - Reset PWM5"]
#[inline]
pub fn pwmmr5r(&mut self) -> _PWMMR5RW {
_PWMMR5RW { w: self }
}
#[doc = "Bit 17 - Stop PWM5"]
#[inline]
pub fn pwmmr5s(&mut self) -> _PWMMR5SW {
_PWMMR5SW { w: self }
}
#[doc = "Bit 18 - Interrupt PWM6"]
#[inline]
pub fn pwmmr6i(&mut self) -> _PWMMR6IW {
_PWMMR6IW { w: self }
}
#[doc = "Bit 19 - Reset PWM6"]
#[inline]
pub fn pwmmr6r(&mut self) -> _PWMMR6RW {
_PWMMR6RW { w: self }
}
#[doc = "Bit 20 - Stop PWM6"]
#[inline]
pub fn pwmmr6s(&mut self) -> _PWMMR6SW {
_PWMMR6SW { w: self }
}
}
}
#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event."]
pub struct CCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event."]
pub mod ccr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CAP0_R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0_RR {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC."]
RISING_EDGE_A_SYNCH,
}
impl CAP0_RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP0_RR::DISABLED_THIS_FEATU => false,
CAP0_RR::RISING_EDGE_A_SYNCH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP0_RR {
match value {
false => CAP0_RR::DISABLED_THIS_FEATU,
true => CAP0_RR::RISING_EDGE_A_SYNCH,
}
}
#[doc = "Checks if the value of the field is `DISABLED_THIS_FEATU`"]
#[inline]
pub fn is_disabled_this_featu(&self) -> bool {
*self == CAP0_RR::DISABLED_THIS_FEATU
}
#[doc = "Checks if the value of the field is `RISING_EDGE_A_SYNCH`"]
#[inline]
pub fn is_rising_edge_a_synch(&self) -> bool {
*self == CAP0_RR::RISING_EDGE_A_SYNCH
}
}
#[doc = "Possible values of the field `CAP0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0_FR {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC."]
FALLING_EDGE_A_SYNC,
}
impl CAP0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP0_FR::DISABLED_THIS_FEATU => false,
CAP0_FR::FALLING_EDGE_A_SYNC => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP0_FR {
match value {
false => CAP0_FR::DISABLED_THIS_FEATU,
true => CAP0_FR::FALLING_EDGE_A_SYNC,
}
}
#[doc = "Checks if the value of the field is `DISABLED_THIS_FEATU`"]
#[inline]
pub fn is_disabled_this_featu(&self) -> bool {
*self == CAP0_FR::DISABLED_THIS_FEATU
}
#[doc = "Checks if the value of the field is `FALLING_EDGE_A_SYNC`"]
#[inline]
pub fn is_falling_edge_a_sync(&self) -> bool {
*self == CAP0_FR::FALLING_EDGE_A_SYNC
}
}
#[doc = "Possible values of the field `CAP0_I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP0_IR {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt."]
INTERRUPT_A_CR0_LOA,
}
impl CAP0_IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP0_IR::DISABLED_THIS_FEATU => false,
CAP0_IR::INTERRUPT_A_CR0_LOA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP0_IR {
match value {
false => CAP0_IR::DISABLED_THIS_FEATU,
true => CAP0_IR::INTERRUPT_A_CR0_LOA,
}
}
#[doc = "Checks if the value of the field is `DISABLED_THIS_FEATU`"]
#[inline]
pub fn is_disabled_this_featu(&self) -> bool {
*self == CAP0_IR::DISABLED_THIS_FEATU
}
#[doc = "Checks if the value of the field is `INTERRUPT_A_CR0_LOA`"]
#[inline]
pub fn is_interrupt_a_cr0_loa(&self) -> bool {
*self == CAP0_IR::INTERRUPT_A_CR0_LOA
}
}
#[doc = "Possible values of the field `CAP1_R`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1_RR {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC."]
RISING_EDGE_A_SYNCH,
}
impl CAP1_RR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP1_RR::DISABLED_THIS_FEATU => false,
CAP1_RR::RISING_EDGE_A_SYNCH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP1_RR {
match value {
false => CAP1_RR::DISABLED_THIS_FEATU,
true => CAP1_RR::RISING_EDGE_A_SYNCH,
}
}
#[doc = "Checks if the value of the field is `DISABLED_THIS_FEATU`"]
#[inline]
pub fn is_disabled_this_featu(&self) -> bool {
*self == CAP1_RR::DISABLED_THIS_FEATU
}
#[doc = "Checks if the value of the field is `RISING_EDGE_A_SYNCH`"]
#[inline]
pub fn is_rising_edge_a_synch(&self) -> bool {
*self == CAP1_RR::RISING_EDGE_A_SYNCH
}
}
#[doc = "Possible values of the field `CAP1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1_FR {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC."]
FALLING_EDGE_A_SYNC,
}
impl CAP1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP1_FR::DISABLED_THIS_FEATU => false,
CAP1_FR::FALLING_EDGE_A_SYNC => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP1_FR {
match value {
false => CAP1_FR::DISABLED_THIS_FEATU,
true => CAP1_FR::FALLING_EDGE_A_SYNC,
}
}
#[doc = "Checks if the value of the field is `DISABLED_THIS_FEATU`"]
#[inline]
pub fn is_disabled_this_featu(&self) -> bool {
*self == CAP1_FR::DISABLED_THIS_FEATU
}
#[doc = "Checks if the value of the field is `FALLING_EDGE_A_SYNC`"]
#[inline]
pub fn is_falling_edge_a_sync(&self) -> bool {
*self == CAP1_FR::FALLING_EDGE_A_SYNC
}
}
#[doc = "Possible values of the field `CAP1_I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CAP1_IR {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt."]
INTERRUPT_A_CR1_LOA,
}
impl CAP1_IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CAP1_IR::DISABLED_THIS_FEATU => false,
CAP1_IR::INTERRUPT_A_CR1_LOA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CAP1_IR {
match value {
false => CAP1_IR::DISABLED_THIS_FEATU,
true => CAP1_IR::INTERRUPT_A_CR1_LOA,
}
}
#[doc = "Checks if the value of the field is `DISABLED_THIS_FEATU`"]
#[inline]
pub fn is_disabled_this_featu(&self) -> bool {
*self == CAP1_IR::DISABLED_THIS_FEATU
}
#[doc = "Checks if the value of the field is `INTERRUPT_A_CR1_LOA`"]
#[inline]
pub fn is_interrupt_a_cr1_loa(&self) -> bool {
*self == CAP1_IR::INTERRUPT_A_CR1_LOA
}
}
#[doc = "Values that can be written to the field `CAP0_R`"]
pub enum CAP0_RW {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC."]
RISING_EDGE_A_SYNCH,
}
impl CAP0_RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP0_RW::DISABLED_THIS_FEATU => false,
CAP0_RW::RISING_EDGE_A_SYNCH => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP0_RW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0_RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP0_RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. This feature is disabled."]
#[inline]
pub fn disabled_this_featu(self) -> &'a mut W {
self.variant(CAP0_RW::DISABLED_THIS_FEATU)
}
#[doc = "Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC."]
#[inline]
pub fn rising_edge_a_synch(self) -> &'a mut W {
self.variant(CAP0_RW::RISING_EDGE_A_SYNCH)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP0_F`"]
pub enum CAP0_FW {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC."]
FALLING_EDGE_A_SYNC,
}
impl CAP0_FW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP0_FW::DISABLED_THIS_FEATU => false,
CAP0_FW::FALLING_EDGE_A_SYNC => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP0_FW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0_FW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP0_FW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. This feature is disabled."]
#[inline]
pub fn disabled_this_featu(self) -> &'a mut W {
self.variant(CAP0_FW::DISABLED_THIS_FEATU)
}
#[doc = "Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline]
pub fn falling_edge_a_sync(self) -> &'a mut W {
self.variant(CAP0_FW::FALLING_EDGE_A_SYNC)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP0_I`"]
pub enum CAP0_IW {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt."]
INTERRUPT_A_CR0_LOA,
}
impl CAP0_IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP0_IW::DISABLED_THIS_FEATU => false,
CAP0_IW::INTERRUPT_A_CR0_LOA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP0_IW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0_IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP0_IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. This feature is disabled."]
#[inline]
pub fn disabled_this_featu(self) -> &'a mut W {
self.variant(CAP0_IW::DISABLED_THIS_FEATU)
}
#[doc = "Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt."]
#[inline]
pub fn interrupt_a_cr0_loa(self) -> &'a mut W {
self.variant(CAP0_IW::INTERRUPT_A_CR0_LOA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP1_R`"]
pub enum CAP1_RW {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC."]
RISING_EDGE_A_SYNCH,
}
impl CAP1_RW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP1_RW::DISABLED_THIS_FEATU => false,
CAP1_RW::RISING_EDGE_A_SYNCH => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP1_RW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1_RW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP1_RW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. This feature is disabled."]
#[inline]
pub fn disabled_this_featu(self) -> &'a mut W {
self.variant(CAP1_RW::DISABLED_THIS_FEATU)
}
#[doc = "Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC."]
#[inline]
pub fn rising_edge_a_synch(self) -> &'a mut W {
self.variant(CAP1_RW::RISING_EDGE_A_SYNCH)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP1_F`"]
pub enum CAP1_FW {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC."]
FALLING_EDGE_A_SYNC,
}
impl CAP1_FW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP1_FW::DISABLED_THIS_FEATU => false,
CAP1_FW::FALLING_EDGE_A_SYNC => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP1_FW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1_FW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP1_FW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. This feature is disabled."]
#[inline]
pub fn disabled_this_featu(self) -> &'a mut W {
self.variant(CAP1_FW::DISABLED_THIS_FEATU)
}
#[doc = "Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline]
pub fn falling_edge_a_sync(self) -> &'a mut W {
self.variant(CAP1_FW::FALLING_EDGE_A_SYNC)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CAP1_I`"]
pub enum CAP1_IW {
#[doc = "Disabled. This feature is disabled."]
DISABLED_THIS_FEATU,
#[doc = "Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt."]
INTERRUPT_A_CR1_LOA,
}
impl CAP1_IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CAP1_IW::DISABLED_THIS_FEATU => false,
CAP1_IW::INTERRUPT_A_CR1_LOA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CAP1_IW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1_IW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CAP1_IW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. This feature is disabled."]
#[inline]
pub fn disabled_this_featu(self) -> &'a mut W {
self.variant(CAP1_IW::DISABLED_THIS_FEATU)
}
#[doc = "Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt."]
#[inline]
pub fn interrupt_a_cr1_loa(self) -> &'a mut W {
self.variant(CAP1_IW::INTERRUPT_A_CR1_LOA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Capture on PWMn_CAP0 rising edge"]
#[inline]
pub fn cap0_r(&self) -> CAP0_RR {
CAP0_RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Capture on PWMn_CAP0 falling edge"]
#[inline]
pub fn cap0_f(&self) -> CAP0_FR {
CAP0_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Interrupt on PWMn_CAP0 event"]
#[inline]
pub fn cap0_i(&self) -> CAP0_IR {
CAP0_IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Capture on PWMn_CAP1 rising edge. Reserved for PWM0."]
#[inline]
pub fn cap1_r(&self) -> CAP1_RR {
CAP1_RR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Capture on PWMn_CAP1 falling edge. Reserved for PWM0."]
#[inline]
pub fn cap1_f(&self) -> CAP1_FR {
CAP1_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Interrupt on PWMn_CAP1 event. Reserved for PWM0."]
#[inline]
pub fn cap1_i(&self) -> CAP1_IR {
CAP1_IR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Capture on PWMn_CAP0 rising edge"]
#[inline]
pub fn cap0_r(&mut self) -> _CAP0_RW {
_CAP0_RW { w: self }
}
#[doc = "Bit 1 - Capture on PWMn_CAP0 falling edge"]
#[inline]
pub fn cap0_f(&mut self) -> _CAP0_FW {
_CAP0_FW { w: self }
}
#[doc = "Bit 2 - Interrupt on PWMn_CAP0 event"]
#[inline]
pub fn cap0_i(&mut self) -> _CAP0_IW {
_CAP0_IW { w: self }
}
#[doc = "Bit 3 - Capture on PWMn_CAP1 rising edge. Reserved for PWM0."]
#[inline]
pub fn cap1_r(&mut self) -> _CAP1_RW {
_CAP1_RW { w: self }
}
#[doc = "Bit 4 - Capture on PWMn_CAP1 falling edge. Reserved for PWM0."]
#[inline]
pub fn cap1_f(&mut self) -> _CAP1_FW {
_CAP1_FW { w: self }
}
#[doc = "Bit 5 - Interrupt on PWMn_CAP1 event. Reserved for PWM0."]
#[inline]
pub fn cap1_i(&mut self) -> _CAP1_IW {
_CAP1_IW { w: self }
}
}
}
#[doc = "PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs."]
pub struct CR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs."]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `PWMSEL2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL2R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL2R::SINGLE_EDGE_CONTROLL => false,
PWMSEL2R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL2R {
match value {
false => PWMSEL2R::SINGLE_EDGE_CONTROLL,
true => PWMSEL2R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL2R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL2R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL3R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL3R::SINGLE_EDGE_CONTROLL => false,
PWMSEL3R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL3R {
match value {
false => PWMSEL3R::SINGLE_EDGE_CONTROLL,
true => PWMSEL3R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL3R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL3R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL4R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL4R::SINGLE_EDGE_CONTROLL => false,
PWMSEL4R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL4R {
match value {
false => PWMSEL4R::SINGLE_EDGE_CONTROLL,
true => PWMSEL4R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL4R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL4R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL5R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL5R::SINGLE_EDGE_CONTROLL => false,
PWMSEL5R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL5R {
match value {
false => PWMSEL5R::SINGLE_EDGE_CONTROLL,
true => PWMSEL5R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL5R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL5R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL6R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL6R::SINGLE_EDGE_CONTROLL => false,
PWMSEL6R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL6R {
match value {
false => PWMSEL6R::SINGLE_EDGE_CONTROLL,
true => PWMSEL6R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL6R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL6R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMENA1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA1R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA1R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA1R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA1R {
match value {
false => PWMENA1R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA1R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA1R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA1R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA2R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA2R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA2R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA2R {
match value {
false => PWMENA2R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA2R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA2R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA2R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA3R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA3R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA3R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA3R {
match value {
false => PWMENA3R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA3R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA3R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA3R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA4R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA4R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA4R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA4R {
match value {
false => PWMENA4R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA4R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA4R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA4R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA5R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA5R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA5R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA5R {
match value {
false => PWMENA5R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA5R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA5R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA5R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA6R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA6R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA6R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA6R {
match value {
false => PWMENA6R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA6R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA6R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA6R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Values that can be written to the field `PWMSEL2`"]
pub enum PWMSEL2W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL2W::SINGLE_EDGE_CONTROLL => false,
PWMSEL2W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL2W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL2W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL2W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL3`"]
pub enum PWMSEL3W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL3W::SINGLE_EDGE_CONTROLL => false,
PWMSEL3W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL3W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL3W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL3W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL4`"]
pub enum PWMSEL4W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL4W::SINGLE_EDGE_CONTROLL => false,
PWMSEL4W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL4W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL4W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL4W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL4W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL5`"]
pub enum PWMSEL5W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL5W::SINGLE_EDGE_CONTROLL => false,
PWMSEL5W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL5W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL5W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL5W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL5W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL6`"]
pub enum PWMSEL6W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL6W::SINGLE_EDGE_CONTROLL => false,
PWMSEL6W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL6W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL6W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL6W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA1`"]
pub enum PWMENA1W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA1W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA1W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA1W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA1W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA1W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA2`"]
pub enum PWMENA2W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA2W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA2W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA2W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA2W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA2W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA3`"]
pub enum PWMENA3W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA3W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA3W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA3W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA3W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA3W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA4`"]
pub enum PWMENA4W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA4W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA4W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA4W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA4W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA4W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA4W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA5`"]
pub enum PWMENA5W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA5W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA5W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA5W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA5W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA5W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA5W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA6`"]
pub enum PWMENA6W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA6W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA6W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA6W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA6W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA6W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 2 - PWM\\[2\\] output single/double edge mode control."]
#[inline]
pub fn pwmsel2(&self) -> PWMSEL2R {
PWMSEL2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - PWM\\[3\\] output edge control."]
#[inline]
pub fn pwmsel3(&self) -> PWMSEL3R {
PWMSEL3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - PWM\\[4\\] output edge control."]
#[inline]
pub fn pwmsel4(&self) -> PWMSEL4R {
PWMSEL4R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - PWM\\[5\\] output edge control."]
#[inline]
pub fn pwmsel5(&self) -> PWMSEL5R {
PWMSEL5R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - PWM\\[6\\] output edge control."]
#[inline]
pub fn pwmsel6(&self) -> PWMSEL6R {
PWMSEL6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - PWM\\[1\\] output enable control."]
#[inline]
pub fn pwmena1(&self) -> PWMENA1R {
PWMENA1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - PWM\\[2\\] output enable control."]
#[inline]
pub fn pwmena2(&self) -> PWMENA2R {
PWMENA2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - PWM\\[3\\] output enable control."]
#[inline]
pub fn pwmena3(&self) -> PWMENA3R {
PWMENA3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - PWM\\[4\\] output enable control."]
#[inline]
pub fn pwmena4(&self) -> PWMENA4R {
PWMENA4R::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - PWM\\[5\\] output enable control."]
#[inline]
pub fn pwmena5(&self) -> PWMENA5R {
PWMENA5R::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - PWM\\[6\\] output enable control. See PWMENA1 for details."]
#[inline]
pub fn pwmena6(&self) -> PWMENA6R {
PWMENA6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 2 - PWM\\[2\\] output single/double edge mode control."]
#[inline]
pub fn pwmsel2(&mut self) -> _PWMSEL2W {
_PWMSEL2W { w: self }
}
#[doc = "Bit 3 - PWM\\[3\\] output edge control."]
#[inline]
pub fn pwmsel3(&mut self) -> _PWMSEL3W {
_PWMSEL3W { w: self }
}
#[doc = "Bit 4 - PWM\\[4\\] output edge control."]
#[inline]
pub fn pwmsel4(&mut self) -> _PWMSEL4W {
_PWMSEL4W { w: self }
}
#[doc = "Bit 5 - PWM\\[5\\] output edge control."]
#[inline]
pub fn pwmsel5(&mut self) -> _PWMSEL5W {
_PWMSEL5W { w: self }
}
#[doc = "Bit 6 - PWM\\[6\\] output edge control."]
#[inline]
pub fn pwmsel6(&mut self) -> _PWMSEL6W {
_PWMSEL6W { w: self }
}
#[doc = "Bit 9 - PWM\\[1\\] output enable control."]
#[inline]
pub fn pwmena1(&mut self) -> _PWMENA1W {
_PWMENA1W { w: self }
}
#[doc = "Bit 10 - PWM\\[2\\] output enable control."]
#[inline]
pub fn pwmena2(&mut self) -> _PWMENA2W {
_PWMENA2W { w: self }
}
#[doc = "Bit 11 - PWM\\[3\\] output enable control."]
#[inline]
pub fn pwmena3(&mut self) -> _PWMENA3W {
_PWMENA3W { w: self }
}
#[doc = "Bit 12 - PWM\\[4\\] output enable control."]
#[inline]
pub fn pwmena4(&mut self) -> _PWMENA4W {
_PWMENA4W { w: self }
}
#[doc = "Bit 13 - PWM\\[5\\] output enable control."]
#[inline]
pub fn pwmena5(&mut self) -> _PWMENA5W {
_PWMENA5W { w: self }
}
#[doc = "Bit 14 - PWM\\[6\\] output enable control. See PWMENA1 for details."]
#[inline]
pub fn pwmena6(&mut self) -> _PWMENA6W {
_PWMENA6W { w: self }
}
}
}
#[doc = "Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges."]
pub struct MR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges."]
pub mod mr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MATCHR {
bits: u32,
}
impl MATCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MATCHW<'a> {
w: &'a mut W,
}
impl<'a> _MATCHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Timer counter match value."]
#[inline]
pub fn match_(&self) -> MATCHR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MATCHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Timer counter match value."]
#[inline]
pub fn match_(&mut self) -> _MATCHW {
_MATCHW { w: self }
}
}
}
#[doc = "PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs."]
pub struct PCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs."]
pub mod pcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `PWMSEL2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL2R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL2R::SINGLE_EDGE_CONTROLL => false,
PWMSEL2R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL2R {
match value {
false => PWMSEL2R::SINGLE_EDGE_CONTROLL,
true => PWMSEL2R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL2R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL2R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL3R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL3R::SINGLE_EDGE_CONTROLL => false,
PWMSEL3R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL3R {
match value {
false => PWMSEL3R::SINGLE_EDGE_CONTROLL,
true => PWMSEL3R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL3R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL3R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL4R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL4R::SINGLE_EDGE_CONTROLL => false,
PWMSEL4R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL4R {
match value {
false => PWMSEL4R::SINGLE_EDGE_CONTROLL,
true => PWMSEL4R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL4R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL4R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL5R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL5R::SINGLE_EDGE_CONTROLL => false,
PWMSEL5R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL5R {
match value {
false => PWMSEL5R::SINGLE_EDGE_CONTROLL,
true => PWMSEL5R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL5R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL5R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMSEL6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMSEL6R {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMSEL6R::SINGLE_EDGE_CONTROLL => false,
PWMSEL6R::DOUBLE_EDGE_CONTROLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMSEL6R {
match value {
false => PWMSEL6R::SINGLE_EDGE_CONTROLL,
true => PWMSEL6R::DOUBLE_EDGE_CONTROLL,
}
}
#[doc = "Checks if the value of the field is `SINGLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_single_edge_controll(&self) -> bool {
*self == PWMSEL6R::SINGLE_EDGE_CONTROLL
}
#[doc = "Checks if the value of the field is `DOUBLE_EDGE_CONTROLL`"]
#[inline]
pub fn is_double_edge_controll(&self) -> bool {
*self == PWMSEL6R::DOUBLE_EDGE_CONTROLL
}
}
#[doc = "Possible values of the field `PWMENA1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA1R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA1R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA1R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA1R {
match value {
false => PWMENA1R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA1R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA1R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA1R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA2R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA2R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA2R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA2R {
match value {
false => PWMENA2R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA2R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA2R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA2R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA3R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA3R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA3R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA3R {
match value {
false => PWMENA3R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA3R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA3R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA3R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA4R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA4R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA4R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA4R {
match value {
false => PWMENA4R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA4R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA4R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA4R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA5R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA5R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA5R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA5R {
match value {
false => PWMENA5R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA5R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA5R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA5R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Possible values of the field `PWMENA6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PWMENA6R {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PWMENA6R::THE_PWM_OUTPUT_IS_DI => false,
PWMENA6R::THE_PWM_OUTPUT_IS_EN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PWMENA6R {
match value {
false => PWMENA6R::THE_PWM_OUTPUT_IS_DI,
true => PWMENA6R::THE_PWM_OUTPUT_IS_EN,
}
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_DI`"]
#[inline]
pub fn is_the_pwm_output_is_di(&self) -> bool {
*self == PWMENA6R::THE_PWM_OUTPUT_IS_DI
}
#[doc = "Checks if the value of the field is `THE_PWM_OUTPUT_IS_EN`"]
#[inline]
pub fn is_the_pwm_output_is_en(&self) -> bool {
*self == PWMENA6R::THE_PWM_OUTPUT_IS_EN
}
}
#[doc = "Values that can be written to the field `PWMSEL2`"]
pub enum PWMSEL2W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL2W::SINGLE_EDGE_CONTROLL => false,
PWMSEL2W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL2W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL2W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL2W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL3`"]
pub enum PWMSEL3W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL3W::SINGLE_EDGE_CONTROLL => false,
PWMSEL3W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL3W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL3W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL3W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL4`"]
pub enum PWMSEL4W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL4W::SINGLE_EDGE_CONTROLL => false,
PWMSEL4W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL4W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL4W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL4W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL4W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL5`"]
pub enum PWMSEL5W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL5W::SINGLE_EDGE_CONTROLL => false,
PWMSEL5W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL5W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL5W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL5W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL5W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMSEL6`"]
pub enum PWMSEL6W {
#[doc = "Single edge controlled mode is selected."]
SINGLE_EDGE_CONTROLL,
#[doc = "Double edge controlled mode is selected."]
DOUBLE_EDGE_CONTROLL,
}
impl PWMSEL6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMSEL6W::SINGLE_EDGE_CONTROLL => false,
PWMSEL6W::DOUBLE_EDGE_CONTROLL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMSEL6W<'a> {
w: &'a mut W,
}
impl<'a> _PWMSEL6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMSEL6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single edge controlled mode is selected."]
#[inline]
pub fn single_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL6W::SINGLE_EDGE_CONTROLL)
}
#[doc = "Double edge controlled mode is selected."]
#[inline]
pub fn double_edge_controll(self) -> &'a mut W {
self.variant(PWMSEL6W::DOUBLE_EDGE_CONTROLL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA1`"]
pub enum PWMENA1W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA1W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA1W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA1W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA1W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA1W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA2`"]
pub enum PWMENA2W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA2W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA2W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA2W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA2W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA2W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA3`"]
pub enum PWMENA3W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA3W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA3W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA3W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA3W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA3W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA4`"]
pub enum PWMENA4W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA4W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA4W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA4W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA4W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA4W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA4W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA5`"]
pub enum PWMENA5W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA5W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA5W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA5W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA5W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA5W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA5W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PWMENA6`"]
pub enum PWMENA6W {
#[doc = "The PWM output is disabled."]
THE_PWM_OUTPUT_IS_DI,
#[doc = "The PWM output is enabled."]
THE_PWM_OUTPUT_IS_EN,
}
impl PWMENA6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PWMENA6W::THE_PWM_OUTPUT_IS_DI => false,
PWMENA6W::THE_PWM_OUTPUT_IS_EN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _PWMENA6W<'a> {
w: &'a mut W,
}
impl<'a> _PWMENA6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PWMENA6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The PWM output is disabled."]
#[inline]
pub fn the_pwm_output_is_di(self) -> &'a mut W {
self.variant(PWMENA6W::THE_PWM_OUTPUT_IS_DI)
}
#[doc = "The PWM output is enabled."]
#[inline]
pub fn the_pwm_output_is_en(self) -> &'a mut W {
self.variant(PWMENA6W::THE_PWM_OUTPUT_IS_EN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 2 - PWM\\[2\\] output single/double edge mode control."]
#[inline]
pub fn pwmsel2(&self) -> PWMSEL2R {
PWMSEL2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - PWM\\[3\\] output edge control."]
#[inline]
pub fn pwmsel3(&self) -> PWMSEL3R {
PWMSEL3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - PWM\\[4\\] output edge control."]
#[inline]
pub fn pwmsel4(&self) -> PWMSEL4R {
PWMSEL4R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - PWM\\[5\\] output edge control."]
#[inline]
pub fn pwmsel5(&self) -> PWMSEL5R {
PWMSEL5R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - PWM\\[6\\] output edge control."]
#[inline]
pub fn pwmsel6(&self) -> PWMSEL6R {
PWMSEL6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - PWM\\[1\\] output enable control."]
#[inline]
pub fn pwmena1(&self) -> PWMENA1R {
PWMENA1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - PWM\\[2\\] output enable control."]
#[inline]
pub fn pwmena2(&self) -> PWMENA2R {
PWMENA2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - PWM\\[3\\] output enable control."]
#[inline]
pub fn pwmena3(&self) -> PWMENA3R {
PWMENA3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - PWM\\[4\\] output enable control."]
#[inline]
pub fn pwmena4(&self) -> PWMENA4R {
PWMENA4R::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - PWM\\[5\\] output enable control."]
#[inline]
pub fn pwmena5(&self) -> PWMENA5R {
PWMENA5R::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - PWM\\[6\\] output enable control. See PWMENA1 for details."]
#[inline]
pub fn pwmena6(&self) -> PWMENA6R {
PWMENA6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 2 - PWM\\[2\\] output single/double edge mode control."]
#[inline]
pub fn pwmsel2(&mut self) -> _PWMSEL2W {
_PWMSEL2W { w: self }
}
#[doc = "Bit 3 - PWM\\[3\\] output edge control."]
#[inline]
pub fn pwmsel3(&mut self) -> _PWMSEL3W {
_PWMSEL3W { w: self }
}
#[doc = "Bit 4 - PWM\\[4\\] output edge control."]
#[inline]
pub fn pwmsel4(&mut self) -> _PWMSEL4W {
_PWMSEL4W { w: self }
}
#[doc = "Bit 5 - PWM\\[5\\] output edge control."]
#[inline]
pub fn pwmsel5(&mut self) -> _PWMSEL5W {
_PWMSEL5W { w: self }
}
#[doc = "Bit 6 - PWM\\[6\\] output edge control."]
#[inline]
pub fn pwmsel6(&mut self) -> _PWMSEL6W {
_PWMSEL6W { w: self }
}
#[doc = "Bit 9 - PWM\\[1\\] output enable control."]
#[inline]
pub fn pwmena1(&mut self) -> _PWMENA1W {
_PWMENA1W { w: self }
}
#[doc = "Bit 10 - PWM\\[2\\] output enable control."]
#[inline]
pub fn pwmena2(&mut self) -> _PWMENA2W {
_PWMENA2W { w: self }
}
#[doc = "Bit 11 - PWM\\[3\\] output enable control."]
#[inline]
pub fn pwmena3(&mut self) -> _PWMENA3W {
_PWMENA3W { w: self }
}
#[doc = "Bit 12 - PWM\\[4\\] output enable control."]
#[inline]
pub fn pwmena4(&mut self) -> _PWMENA4W {
_PWMENA4W { w: self }
}
#[doc = "Bit 13 - PWM\\[5\\] output enable control."]
#[inline]
pub fn pwmena5(&mut self) -> _PWMENA5W {
_PWMENA5W { w: self }
}
#[doc = "Bit 14 - PWM\\[6\\] output enable control. See PWMENA1 for details."]
#[inline]
pub fn pwmena6(&mut self) -> _PWMENA6W {
_PWMENA6W { w: self }
}
}
}
#[doc = "Load Enable Register. Enables use of updated PWM match values."]
pub struct LER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Load Enable Register. Enables use of updated PWM match values."]
pub mod ler {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::LER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MAT0LATCHENR {
bits: bool,
}
impl MAT0LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAT1LATCHENR {
bits: bool,
}
impl MAT1LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAT2LATCHENR {
bits: bool,
}
impl MAT2LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAT3LATCHENR {
bits: bool,
}
impl MAT3LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAT4LATCHENR {
bits: bool,
}
impl MAT4LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAT5LATCHENR {
bits: bool,
}
impl MAT5LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAT6LATCHENR {
bits: bool,
}
impl MAT6LATCHENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _MAT0LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT0LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAT1LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT1LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAT2LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT2LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAT3LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT3LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAT4LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT4LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAT5LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT5LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAT6LATCHENW<'a> {
w: &'a mut W,
}
impl<'a> _MAT6LATCHENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7."]
#[inline]
pub fn mat0latchen(&self) -> MAT0LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT0LATCHENR { bits }
}
#[doc = "Bit 1 - Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details."]
#[inline]
pub fn mat1latchen(&self) -> MAT1LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT1LATCHENR { bits }
}
#[doc = "Bit 2 - Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details."]
#[inline]
pub fn mat2latchen(&self) -> MAT2LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT2LATCHENR { bits }
}
#[doc = "Bit 3 - Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details."]
#[inline]
pub fn mat3latchen(&self) -> MAT3LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT3LATCHENR { bits }
}
#[doc = "Bit 4 - Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details."]
#[inline]
pub fn mat4latchen(&self) -> MAT4LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT4LATCHENR { bits }
}
#[doc = "Bit 5 - Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details."]
#[inline]
pub fn mat5latchen(&self) -> MAT5LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT5LATCHENR { bits }
}
#[doc = "Bit 6 - Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details."]
#[inline]
pub fn mat6latchen(&self) -> MAT6LATCHENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAT6LATCHENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7."]
#[inline]
pub fn mat0latchen(&mut self) -> _MAT0LATCHENW {
_MAT0LATCHENW { w: self }
}
#[doc = "Bit 1 - Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details."]
#[inline]
pub fn mat1latchen(&mut self) -> _MAT1LATCHENW {
_MAT1LATCHENW { w: self }
}
#[doc = "Bit 2 - Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details."]
#[inline]
pub fn mat2latchen(&mut self) -> _MAT2LATCHENW {
_MAT2LATCHENW { w: self }
}
#[doc = "Bit 3 - Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details."]
#[inline]
pub fn mat3latchen(&mut self) -> _MAT3LATCHENW {
_MAT3LATCHENW { w: self }
}
#[doc = "Bit 4 - Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details."]
#[inline]
pub fn mat4latchen(&mut self) -> _MAT4LATCHENW {
_MAT4LATCHENW { w: self }
}
#[doc = "Bit 5 - Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details."]
#[inline]
pub fn mat5latchen(&mut self) -> _MAT5LATCHENW {
_MAT5LATCHENW { w: self }
}
#[doc = "Bit 6 - Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details."]
#[inline]
pub fn mat6latchen(&mut self) -> _MAT6LATCHENW {
_MAT6LATCHENW { w: self }
}
}
}
#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub struct CTCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub mod ctcr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `MOD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MODR {
#[doc = "Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register."]
TIMER_MODE_THE_TC_I,
#[doc = "Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2."]
RISING_EDGE_COUNTER_,
#[doc = "Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2."]
FALLING_EDGE_COUNTER,
#[doc = "Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2."]
DUAL_EDGE_COUNTER_MO,
}
impl MODR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
MODR::TIMER_MODE_THE_TC_I => 0,
MODR::RISING_EDGE_COUNTER_ => 0x01,
MODR::FALLING_EDGE_COUNTER => 0x02,
MODR::DUAL_EDGE_COUNTER_MO => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> MODR {
match value {
0 => MODR::TIMER_MODE_THE_TC_I,
1 => MODR::RISING_EDGE_COUNTER_,
2 => MODR::FALLING_EDGE_COUNTER,
3 => MODR::DUAL_EDGE_COUNTER_MO,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TIMER_MODE_THE_TC_I`"]
#[inline]
pub fn is_timer_mode_the_tc_i(&self) -> bool {
*self == MODR::TIMER_MODE_THE_TC_I
}
#[doc = "Checks if the value of the field is `RISING_EDGE_COUNTER_`"]
#[inline]
pub fn is_rising_edge_counter_(&self) -> bool {
*self == MODR::RISING_EDGE_COUNTER_
}
#[doc = "Checks if the value of the field is `FALLING_EDGE_COUNTER`"]
#[inline]
pub fn is_falling_edge_counter(&self) -> bool {
*self == MODR::FALLING_EDGE_COUNTER
}
#[doc = "Checks if the value of the field is `DUAL_EDGE_COUNTER_MO`"]
#[inline]
pub fn is_dual_edge_counter_mo(&self) -> bool {
*self == MODR::DUAL_EDGE_COUNTER_MO
}
}
#[doc = "Possible values of the field `CIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CISR {
#[doc = "For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)"]
FOR_PWM0_00_EQ_PWM0_,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl CISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CISR::FOR_PWM0_00_EQ_PWM0_ => 0,
CISR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CISR {
match value {
0 => CISR::FOR_PWM0_00_EQ_PWM0_,
i => CISR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `FOR_PWM0_00_EQ_PWM0_`"]
#[inline]
pub fn is_for_pwm0_00_eq_pwm0_(&self) -> bool {
*self == CISR::FOR_PWM0_00_EQ_PWM0_
}
}
#[doc = "Values that can be written to the field `MOD`"]
pub enum MODW {
#[doc = "Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register."]
TIMER_MODE_THE_TC_I,
#[doc = "Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2."]
RISING_EDGE_COUNTER_,
#[doc = "Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2."]
FALLING_EDGE_COUNTER,
#[doc = "Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2."]
DUAL_EDGE_COUNTER_MO,
}
impl MODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
MODW::TIMER_MODE_THE_TC_I => 0,
MODW::RISING_EDGE_COUNTER_ => 1,
MODW::FALLING_EDGE_COUNTER => 2,
MODW::DUAL_EDGE_COUNTER_MO => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _MODW<'a> {
w: &'a mut W,
}
impl<'a> _MODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MODW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register."]
#[inline]
pub fn timer_mode_the_tc_i(self) -> &'a mut W {
self.variant(MODW::TIMER_MODE_THE_TC_I)
}
#[doc = "Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2."]
#[inline]
pub fn rising_edge_counter_(self) -> &'a mut W {
self.variant(MODW::RISING_EDGE_COUNTER_)
}
#[doc = "Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2."]
#[inline]
pub fn falling_edge_counter(self) -> &'a mut W {
self.variant(MODW::FALLING_EDGE_COUNTER)
}
#[doc = "Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2."]
#[inline]
pub fn dual_edge_counter_mo(self) -> &'a mut W {
self.variant(MODW::DUAL_EDGE_COUNTER_MO)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CIS`"]
pub enum CISW {
#[doc = "For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)"]
FOR_PWM0_00_EQ_PWM0_,
}
impl CISW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CISW::FOR_PWM0_00_EQ_PWM0_ => 0,
}
}
}
#[doc = r" Proxy"]
pub struct _CISW<'a> {
w: &'a mut W,
}
impl<'a> _CISW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CISW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)"]
#[inline]
pub fn for_pwm0_00_eq_pwm0_(self) -> &'a mut W {
self.variant(CISW::FOR_PWM0_00_EQ_PWM0_)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Counter/ Timer Mode"]
#[inline]
pub fn mod_(&self) -> MODR {
MODR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved."]
#[inline]
pub fn cis(&self) -> CISR {
CISR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Counter/ Timer Mode"]
#[inline]
pub fn mod_(&mut self) -> _MODW {
_MODW { w: self }
}
#[doc = "Bits 2:3 - Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved."]
#[inline]
pub fn cis(&mut self) -> _CISW {
_CISW { w: self }
}
}
}
}
#[doc = "I2C bus interface"]
pub struct I2C0 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C0 {}
impl I2C0 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const i2c0::RegisterBlock {
0x4001_c000 as *const _
}
}
impl Deref for I2C0 {
type Target = i2c0::RegisterBlock;
fn deref(&self) -> &i2c0::RegisterBlock {
unsafe { &*I2C0::ptr() }
}
}
#[doc = "I2C bus interface"]
pub mod i2c0 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub conset: CONSET,
#[doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub stat: STAT,
#[doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub dat: DAT,
#[doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub adr0: ADR0,
#[doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub sclh: SCLH,
#[doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub scll: SCLL,
#[doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub conclr: CONCLR,
#[doc = "0x1c - Monitor mode control register."]
pub mmctrl: MMCTRL,
#[doc = "0x20 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub adr1: ADR,
#[doc = "0x24 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub adr2: ADR,
#[doc = "0x28 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub adr3: ADR,
#[doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub data_buffer: DATA_BUFFER,
#[doc = "0x30 - I2C Slave address mask register"]
pub mask: [MASK; 4],
}
#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub struct CONSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conset {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CONSET {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct AAR {
bits: bool,
}
impl AAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SIR {
bits: bool,
}
impl SIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct STOR {
bits: bool,
}
impl STOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct STAR {
bits: bool,
}
impl STAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct I2ENR {
bits: bool,
}
impl I2ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _AAW<'a> {
w: &'a mut W,
}
impl<'a> _AAW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SIW<'a> {
w: &'a mut W,
}
impl<'a> _SIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STOW<'a> {
w: &'a mut W,
}
impl<'a> _STOW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STAW<'a> {
w: &'a mut W,
}
impl<'a> _STAW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _I2ENW<'a> {
w: &'a mut W,
}
impl<'a> _I2ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 2 - Assert acknowledge flag."]
#[inline]
pub fn aa(&self) -> AAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AAR { bits }
}
#[doc = "Bit 3 - I2C interrupt flag."]
#[inline]
pub fn si(&self) -> SIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SIR { bits }
}
#[doc = "Bit 4 - STOP flag."]
#[inline]
pub fn sto(&self) -> STOR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
STOR { bits }
}
#[doc = "Bit 5 - START flag."]
#[inline]
pub fn sta(&self) -> STAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
STAR { bits }
}
#[doc = "Bit 6 - I2C interface enable."]
#[inline]
pub fn i2en(&self) -> I2ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
I2ENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 2 - Assert acknowledge flag."]
#[inline]
pub fn aa(&mut self) -> _AAW {
_AAW { w: self }
}
#[doc = "Bit 3 - I2C interrupt flag."]
#[inline]
pub fn si(&mut self) -> _SIW {
_SIW { w: self }
}
#[doc = "Bit 4 - STOP flag."]
#[inline]
pub fn sto(&mut self) -> _STOW {
_STOW { w: self }
}
#[doc = "Bit 5 - START flag."]
#[inline]
pub fn sta(&mut self) -> _STAW {
_STAW { w: self }
}
#[doc = "Bit 6 - I2C interface enable."]
#[inline]
pub fn i2en(&mut self) -> _I2ENW {
_I2ENW { w: self }
}
}
}
#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub struct STAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub mod stat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct STATUSR {
bits: u8,
}
impl STATUSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 3:7 - These bits give the actual status information about the I 2C interface."]
#[inline]
pub fn status(&self) -> STATUSR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) as u8
};
STATUSR { bits }
}
}
}
#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub struct DAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub mod dat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DAT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATAR {
bits: u8,
}
impl DATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATAW<'a> {
w: &'a mut W,
}
impl<'a> _DATAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."]
#[inline]
pub fn data(&self) -> DATAR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."]
#[inline]
pub fn data(&mut self) -> _DATAW {
_DATAW { w: self }
}
}
}
#[doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub struct ADR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub mod adr0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADR0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct GCR {
bits: bool,
}
impl GCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ADDRESSR {
bits: u8,
}
impl ADDRESSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GCW<'a> {
w: &'a mut W,
}
impl<'a> _GCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ADDRESSW<'a> {
w: &'a mut W,
}
impl<'a> _ADDRESSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - General Call enable bit."]
#[inline]
pub fn gc(&self) -> GCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
GCR { bits }
}
#[doc = "Bits 1:7 - The I2C device address for slave mode."]
#[inline]
pub fn address(&self) -> ADDRESSR {
let bits = {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ADDRESSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - General Call enable bit."]
#[inline]
pub fn gc(&mut self) -> _GCW {
_GCW { w: self }
}
#[doc = "Bits 1:7 - The I2C device address for slave mode."]
#[inline]
pub fn address(&mut self) -> _ADDRESSW {
_ADDRESSW { w: self }
}
}
}
#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub struct SCLH {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub mod sclh {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCLH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SCLHR {
bits: u16,
}
impl SCLHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SCLHW<'a> {
w: &'a mut W,
}
impl<'a> _SCLHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Count for SCL HIGH time period selection."]
#[inline]
pub fn sclh(&self) -> SCLHR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
SCLHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x04 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Count for SCL HIGH time period selection."]
#[inline]
pub fn sclh(&mut self) -> _SCLHW {
_SCLHW { w: self }
}
}
}
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub struct SCLL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub mod scll {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCLL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SCLLR {
bits: u16,
}
impl SCLLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SCLLW<'a> {
w: &'a mut W,
}
impl<'a> _SCLLW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Count for SCL low time period selection."]
#[inline]
pub fn scll(&self) -> SCLLR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
SCLLR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x04 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Count for SCL low time period selection."]
#[inline]
pub fn scll(&mut self) -> _SCLLW {
_SCLLW { w: self }
}
}
}
#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub struct CONCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CONCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AACW<'a> {
w: &'a mut W,
}
impl<'a> _AACW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SICW<'a> {
w: &'a mut W,
}
impl<'a> _SICW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STACW<'a> {
w: &'a mut W,
}
impl<'a> _STACW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _I2ENCW<'a> {
w: &'a mut W,
}
impl<'a> _I2ENCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 2 - Assert acknowledge Clear bit."]
#[inline]
pub fn aac(&mut self) -> _AACW {
_AACW { w: self }
}
#[doc = "Bit 3 - I2C interrupt Clear bit."]
#[inline]
pub fn sic(&mut self) -> _SICW {
_SICW { w: self }
}
#[doc = "Bit 5 - START flag Clear bit."]
#[inline]
pub fn stac(&mut self) -> _STACW {
_STACW { w: self }
}
#[doc = "Bit 6 - I2C interface Disable bit."]
#[inline]
pub fn i2enc(&mut self) -> _I2ENCW {
_I2ENCW { w: self }
}
}
}
#[doc = "Monitor mode control register."]
pub struct MMCTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Monitor mode control register."]
pub mod mmctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MMCTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `MM_ENA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MM_ENAR {
#[doc = "Monitor mode disabled."]
MONITOR_MODE_DISABLE,
#[doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
THE_I_2C_MODULE_WILL,
}
impl MM_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MM_ENAR::MONITOR_MODE_DISABLE => false,
MM_ENAR::THE_I_2C_MODULE_WILL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MM_ENAR {
match value {
false => MM_ENAR::MONITOR_MODE_DISABLE,
true => MM_ENAR::THE_I_2C_MODULE_WILL,
}
}
#[doc = "Checks if the value of the field is `MONITOR_MODE_DISABLE`"]
#[inline]
pub fn is_monitor_mode_disable(&self) -> bool {
*self == MM_ENAR::MONITOR_MODE_DISABLE
}
#[doc = "Checks if the value of the field is `THE_I_2C_MODULE_WILL`"]
#[inline]
pub fn is_the_i_2c_module_will(&self) -> bool {
*self == MM_ENAR::THE_I_2C_MODULE_WILL
}
}
#[doc = "Possible values of the field `ENA_SCL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ENA_SCLR {
#[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
WHEN_THIS_BIT_IS_CLE,
#[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"]
WHEN_THIS_BIT_IS_SET,
}
impl ENA_SCLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ENA_SCLR::WHEN_THIS_BIT_IS_CLE => false,
ENA_SCLR::WHEN_THIS_BIT_IS_SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ENA_SCLR {
match value {
false => ENA_SCLR::WHEN_THIS_BIT_IS_CLE,
true => ENA_SCLR::WHEN_THIS_BIT_IS_SET,
}
}
#[doc = "Checks if the value of the field is `WHEN_THIS_BIT_IS_CLE`"]
#[inline]
pub fn is_when_this_bit_is_cle(&self) -> bool {
*self == ENA_SCLR::WHEN_THIS_BIT_IS_CLE
}
#[doc = "Checks if the value of the field is `WHEN_THIS_BIT_IS_SET`"]
#[inline]
pub fn is_when_this_bit_is_set(&self) -> bool {
*self == ENA_SCLR::WHEN_THIS_BIT_IS_SET
}
}
#[doc = "Possible values of the field `MATCH_ALL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MATCH_ALLR {
#[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
WHEN_THIS_BIT_IS_CLE,
#[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
WHEN_THIS_BIT_IS_SET,
}
impl MATCH_ALLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MATCH_ALLR::WHEN_THIS_BIT_IS_CLE => false,
MATCH_ALLR::WHEN_THIS_BIT_IS_SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MATCH_ALLR {
match value {
false => MATCH_ALLR::WHEN_THIS_BIT_IS_CLE,
true => MATCH_ALLR::WHEN_THIS_BIT_IS_SET,
}
}
#[doc = "Checks if the value of the field is `WHEN_THIS_BIT_IS_CLE`"]
#[inline]
pub fn is_when_this_bit_is_cle(&self) -> bool {
*self == MATCH_ALLR::WHEN_THIS_BIT_IS_CLE
}
#[doc = "Checks if the value of the field is `WHEN_THIS_BIT_IS_SET`"]
#[inline]
pub fn is_when_this_bit_is_set(&self) -> bool {
*self == MATCH_ALLR::WHEN_THIS_BIT_IS_SET
}
}
#[doc = "Values that can be written to the field `MM_ENA`"]
pub enum MM_ENAW {
#[doc = "Monitor mode disabled."]
MONITOR_MODE_DISABLE,
#[doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
THE_I_2C_MODULE_WILL,
}
impl MM_ENAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MM_ENAW::MONITOR_MODE_DISABLE => false,
MM_ENAW::THE_I_2C_MODULE_WILL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MM_ENAW<'a> {
w: &'a mut W,
}
impl<'a> _MM_ENAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MM_ENAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Monitor mode disabled."]
#[inline]
pub fn monitor_mode_disable(self) -> &'a mut W {
self.variant(MM_ENAW::MONITOR_MODE_DISABLE)
}
#[doc = "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
#[inline]
pub fn the_i_2c_module_will(self) -> &'a mut W {
self.variant(MM_ENAW::THE_I_2C_MODULE_WILL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ENA_SCL`"]
pub enum ENA_SCLW {
#[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
WHEN_THIS_BIT_IS_CLE,
#[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"]
WHEN_THIS_BIT_IS_SET,
}
impl ENA_SCLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ENA_SCLW::WHEN_THIS_BIT_IS_CLE => false,
ENA_SCLW::WHEN_THIS_BIT_IS_SET => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ENA_SCLW<'a> {
w: &'a mut W,
}
impl<'a> _ENA_SCLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ENA_SCLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
#[inline]
pub fn when_this_bit_is_cle(self) -> &'a mut W {
self.variant(ENA_SCLW::WHEN_THIS_BIT_IS_CLE)
}
#[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"]
#[inline]
pub fn when_this_bit_is_set(self) -> &'a mut W {
self.variant(ENA_SCLW::WHEN_THIS_BIT_IS_SET)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MATCH_ALL`"]
pub enum MATCH_ALLW {
#[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
WHEN_THIS_BIT_IS_CLE,
#[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
WHEN_THIS_BIT_IS_SET,
}
impl MATCH_ALLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MATCH_ALLW::WHEN_THIS_BIT_IS_CLE => false,
MATCH_ALLW::WHEN_THIS_BIT_IS_SET => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MATCH_ALLW<'a> {
w: &'a mut W,
}
impl<'a> _MATCH_ALLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MATCH_ALLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
#[inline]
pub fn when_this_bit_is_cle(self) -> &'a mut W {
self.variant(MATCH_ALLW::WHEN_THIS_BIT_IS_CLE)
}
#[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
#[inline]
pub fn when_this_bit_is_set(self) -> &'a mut W {
self.variant(MATCH_ALLW::WHEN_THIS_BIT_IS_SET)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Monitor mode enable."]
#[inline]
pub fn mm_ena(&self) -> MM_ENAR {
MM_ENAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - SCL output enable."]
#[inline]
pub fn ena_scl(&self) -> ENA_SCLR {
ENA_SCLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Select interrupt register match."]
#[inline]
pub fn match_all(&self) -> MATCH_ALLR {
MATCH_ALLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Monitor mode enable."]
#[inline]
pub fn mm_ena(&mut self) -> _MM_ENAW {
_MM_ENAW { w: self }
}
#[doc = "Bit 1 - SCL output enable."]
#[inline]
pub fn ena_scl(&mut self) -> _ENA_SCLW {
_ENA_SCLW { w: self }
}
#[doc = "Bit 2 - Select interrupt register match."]
#[inline]
pub fn match_all(&mut self) -> _MATCH_ALLW {
_MATCH_ALLW { w: self }
}
}
}
#[doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub struct ADR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub mod adr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct GCR {
bits: bool,
}
impl GCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ADDRESSR {
bits: u8,
}
impl ADDRESSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GCW<'a> {
w: &'a mut W,
}
impl<'a> _GCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ADDRESSW<'a> {
w: &'a mut W,
}
impl<'a> _ADDRESSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - General Call enable bit."]
#[inline]
pub fn gc(&self) -> GCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
GCR { bits }
}
#[doc = "Bits 1:7 - The I2C device address for slave mode."]
#[inline]
pub fn address(&self) -> ADDRESSR {
let bits = {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ADDRESSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - General Call enable bit."]
#[inline]
pub fn gc(&mut self) -> _GCW {
_GCW { w: self }
}
#[doc = "Bits 1:7 - The I2C device address for slave mode."]
#[inline]
pub fn address(&mut self) -> _ADDRESSW {
_ADDRESSW { w: self }
}
}
}
#[doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub struct DATA_BUFFER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub mod data_buffer {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DATA_BUFFER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DATAR {
bits: u8,
}
impl DATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - This register holds contents of the 8 MSBs of the DAT shift register."]
#[inline]
pub fn data(&self) -> DATAR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATAR { bits }
}
}
}
#[doc = "I2C Slave address mask register"]
pub struct MASK {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Slave address mask register"]
pub mod mask {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MASK {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MASKR {
bits: u8,
}
impl MASKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MASKW<'a> {
w: &'a mut W,
}
impl<'a> _MASKW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 1:7 - Mask bits."]
#[inline]
pub fn mask(&self) -> MASKR {
let bits = {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MASKR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 1:7 - Mask bits."]
#[inline]
pub fn mask(&mut self) -> _MASKW {
_MASKW { w: self }
}
}
}
}
#[doc = "SPI"]
pub struct SPI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI {}
impl SPI {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const spi::RegisterBlock {
0x4002_0000 as *const _
}
}
impl Deref for SPI {
type Target = spi::RegisterBlock;
fn deref(&self) -> &spi::RegisterBlock {
unsafe { &*SPI::ptr() }
}
}
#[doc = "SPI"]
pub mod spi {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - SPI Control Register. This register controls the operation of the SPI."]
pub cr: CR,
#[doc = "0x04 - SPI Status Register. This register shows the status of the SPI."]
pub sr: SR,
#[doc = "0x08 - SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register."]
pub dr: DR,
#[doc = "0x0c - SPI Clock Counter Register. This register controls the frequency of a master's SCK0."]
pub ccr: CCR,
_reserved4: [u8; 12usize],
#[doc = "0x1c - SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface."]
pub int: INT,
}
#[doc = "SPI Control Register. This register controls the operation of the SPI."]
pub struct CR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SPI Control Register. This register controls the operation of the SPI."]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `BITENABLE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BITENABLER {
#[doc = "The SPI controller sends and receives the number of bits selected by bits 11:8."]
THE_SPI_CONTROLLER_S,
#[doc = r" Reserved"]
_Reserved(bool),
}
impl BITENABLER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BITENABLER::THE_SPI_CONTROLLER_S => true,
BITENABLER::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BITENABLER {
match value {
true => BITENABLER::THE_SPI_CONTROLLER_S,
i => BITENABLER::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `THE_SPI_CONTROLLER_S`"]
#[inline]
pub fn is_the_spi_controller_s(&self) -> bool {
*self == BITENABLER::THE_SPI_CONTROLLER_S
}
}
#[doc = "Possible values of the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPHAR {
#[doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal."]
FIRST_EDGE,
#[doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active."]
SECOND_EDGE,
}
impl CPHAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CPHAR::FIRST_EDGE => false,
CPHAR::SECOND_EDGE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CPHAR {
match value {
false => CPHAR::FIRST_EDGE,
true => CPHAR::SECOND_EDGE,
}
}
#[doc = "Checks if the value of the field is `FIRST_EDGE`"]
#[inline]
pub fn is_first_edge(&self) -> bool {
*self == CPHAR::FIRST_EDGE
}
#[doc = "Checks if the value of the field is `SECOND_EDGE`"]
#[inline]
pub fn is_second_edge(&self) -> bool {
*self == CPHAR::SECOND_EDGE
}
}
#[doc = "Possible values of the field `CPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPOLR {
#[doc = "SCK is active high."]
SCK_IS_ACTIVE_HIGH_,
#[doc = "SCK is active low."]
SCK_IS_ACTIVE_LOW_,
}
impl CPOLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CPOLR::SCK_IS_ACTIVE_HIGH_ => false,
CPOLR::SCK_IS_ACTIVE_LOW_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CPOLR {
match value {
false => CPOLR::SCK_IS_ACTIVE_HIGH_,
true => CPOLR::SCK_IS_ACTIVE_LOW_,
}
}
#[doc = "Checks if the value of the field is `SCK_IS_ACTIVE_HIGH_`"]
#[inline]
pub fn is_sck_is_active_high_(&self) -> bool {
*self == CPOLR::SCK_IS_ACTIVE_HIGH_
}
#[doc = "Checks if the value of the field is `SCK_IS_ACTIVE_LOW_`"]
#[inline]
pub fn is_sck_is_active_low_(&self) -> bool {
*self == CPOLR::SCK_IS_ACTIVE_LOW_
}
}
#[doc = "Possible values of the field `MSTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MSTRR {
#[doc = "The SPI operates in Slave mode."]
SLAVE,
#[doc = "The SPI operates in Master mode."]
MASTER,
}
impl MSTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MSTRR::SLAVE => false,
MSTRR::MASTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MSTRR {
match value {
false => MSTRR::SLAVE,
true => MSTRR::MASTER,
}
}
#[doc = "Checks if the value of the field is `SLAVE`"]
#[inline]
pub fn is_slave(&self) -> bool {
*self == MSTRR::SLAVE
}
#[doc = "Checks if the value of the field is `MASTER`"]
#[inline]
pub fn is_master(&self) -> bool {
*self == MSTRR::MASTER
}
}
#[doc = "Possible values of the field `LSBF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LSBFR {
#[doc = "SPI data is transferred MSB (bit 7) first."]
MSB,
#[doc = "SPI data is transferred LSB (bit 0) first."]
LSB,
}
impl LSBFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LSBFR::MSB => false,
LSBFR::LSB => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LSBFR {
match value {
false => LSBFR::MSB,
true => LSBFR::LSB,
}
}
#[doc = "Checks if the value of the field is `MSB`"]
#[inline]
pub fn is_msb(&self) -> bool {
*self == LSBFR::MSB
}
#[doc = "Checks if the value of the field is `LSB`"]
#[inline]
pub fn is_lsb(&self) -> bool {
*self == LSBFR::LSB
}
}
#[doc = "Possible values of the field `SPIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPIER {
#[doc = "SPI interrupts are inhibited."]
INTBLOCK,
#[doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated."]
HWINT,
}
impl SPIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPIER::INTBLOCK => false,
SPIER::HWINT => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPIER {
match value {
false => SPIER::INTBLOCK,
true => SPIER::HWINT,
}
}
#[doc = "Checks if the value of the field is `INTBLOCK`"]
#[inline]
pub fn is_intblock(&self) -> bool {
*self == SPIER::INTBLOCK
}
#[doc = "Checks if the value of the field is `HWINT`"]
#[inline]
pub fn is_hwint(&self) -> bool {
*self == SPIER::HWINT
}
}
#[doc = "Possible values of the field `BITS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BITSR {
#[doc = "8 bits per transfer"]
_8_BITS_PER_TRANSFER,
#[doc = "9 bits per transfer"]
_9_BITS_PER_TRANSFER,
#[doc = "10 bits per transfer"]
_10_BITS_PER_TRANSFER,
#[doc = "11 bits per transfer"]
_11_BITS_PER_TRANSFER,
#[doc = "12 bits per transfer"]
_12_BITS_PER_TRANSFER,
#[doc = "13 bits per transfer"]
_13_BITS_PER_TRANSFER,
#[doc = "14 bits per transfer"]
_14_BITS_PER_TRANSFER,
#[doc = "15 bits per transfer"]
_15_BITS_PER_TRANSFER,
#[doc = "16 bits per transfer"]
_16_BITS_PER_TRANSFER,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl BITSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
BITSR::_8_BITS_PER_TRANSFER => 0x08,
BITSR::_9_BITS_PER_TRANSFER => 0x09,
BITSR::_10_BITS_PER_TRANSFER => 0x0a,
BITSR::_11_BITS_PER_TRANSFER => 0x0b,
BITSR::_12_BITS_PER_TRANSFER => 0x0c,
BITSR::_13_BITS_PER_TRANSFER => 0x0d,
BITSR::_14_BITS_PER_TRANSFER => 0x0e,
BITSR::_15_BITS_PER_TRANSFER => 0x0f,
BITSR::_16_BITS_PER_TRANSFER => 0,
BITSR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> BITSR {
match value {
8 => BITSR::_8_BITS_PER_TRANSFER,
9 => BITSR::_9_BITS_PER_TRANSFER,
10 => BITSR::_10_BITS_PER_TRANSFER,
11 => BITSR::_11_BITS_PER_TRANSFER,
12 => BITSR::_12_BITS_PER_TRANSFER,
13 => BITSR::_13_BITS_PER_TRANSFER,
14 => BITSR::_14_BITS_PER_TRANSFER,
15 => BITSR::_15_BITS_PER_TRANSFER,
0 => BITSR::_16_BITS_PER_TRANSFER,
i => BITSR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_8_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_8_bits_per_transfer(&self) -> bool {
*self == BITSR::_8_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_9_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_9_bits_per_transfer(&self) -> bool {
*self == BITSR::_9_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_10_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_10_bits_per_transfer(&self) -> bool {
*self == BITSR::_10_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_11_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_11_bits_per_transfer(&self) -> bool {
*self == BITSR::_11_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_12_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_12_bits_per_transfer(&self) -> bool {
*self == BITSR::_12_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_13_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_13_bits_per_transfer(&self) -> bool {
*self == BITSR::_13_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_14_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_14_bits_per_transfer(&self) -> bool {
*self == BITSR::_14_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_15_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_15_bits_per_transfer(&self) -> bool {
*self == BITSR::_15_BITS_PER_TRANSFER
}
#[doc = "Checks if the value of the field is `_16_BITS_PER_TRANSFER`"]
#[inline]
pub fn is_16_bits_per_transfer(&self) -> bool {
*self == BITSR::_16_BITS_PER_TRANSFER
}
}
#[doc = "Values that can be written to the field `BITENABLE`"]
pub enum BITENABLEW {
#[doc = "The SPI controller sends and receives the number of bits selected by bits 11:8."]
THE_SPI_CONTROLLER_S,
}
impl BITENABLEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BITENABLEW::THE_SPI_CONTROLLER_S => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BITENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _BITENABLEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BITENABLEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The SPI controller sends and receives the number of bits selected by bits 11:8."]
#[inline]
pub fn the_spi_controller_s(self) -> &'a mut W {
self.variant(BITENABLEW::THE_SPI_CONTROLLER_S)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CPHA`"]
pub enum CPHAW {
#[doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal."]
FIRST_EDGE,
#[doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active."]
SECOND_EDGE,
}
impl CPHAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CPHAW::FIRST_EDGE => false,
CPHAW::SECOND_EDGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CPHAW<'a> {
w: &'a mut W,
}
impl<'a> _CPHAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CPHAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal."]
#[inline]
pub fn first_edge(self) -> &'a mut W {
self.variant(CPHAW::FIRST_EDGE)
}
#[doc = "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active."]
#[inline]
pub fn second_edge(self) -> &'a mut W {
self.variant(CPHAW::SECOND_EDGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CPOL`"]
pub enum CPOLW {
#[doc = "SCK is active high."]
SCK_IS_ACTIVE_HIGH_,
#[doc = "SCK is active low."]
SCK_IS_ACTIVE_LOW_,
}
impl CPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CPOLW::SCK_IS_ACTIVE_HIGH_ => false,
CPOLW::SCK_IS_ACTIVE_LOW_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CPOLW<'a> {
w: &'a mut W,
}
impl<'a> _CPOLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CPOLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SCK is active high."]
#[inline]
pub fn sck_is_active_high_(self) -> &'a mut W {
self.variant(CPOLW::SCK_IS_ACTIVE_HIGH_)
}
#[doc = "SCK is active low."]
#[inline]
pub fn sck_is_active_low_(self) -> &'a mut W {
self.variant(CPOLW::SCK_IS_ACTIVE_LOW_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MSTR`"]
pub enum MSTRW {
#[doc = "The SPI operates in Slave mode."]
SLAVE,
#[doc = "The SPI operates in Master mode."]
MASTER,
}
impl MSTRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MSTRW::SLAVE => false,
MSTRW::MASTER => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MSTRW<'a> {
w: &'a mut W,
}
impl<'a> _MSTRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MSTRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The SPI operates in Slave mode."]
#[inline]
pub fn slave(self) -> &'a mut W {
self.variant(MSTRW::SLAVE)
}
#[doc = "The SPI operates in Master mode."]
#[inline]
pub fn master(self) -> &'a mut W {
self.variant(MSTRW::MASTER)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LSBF`"]
pub enum LSBFW {
#[doc = "SPI data is transferred MSB (bit 7) first."]
MSB,
#[doc = "SPI data is transferred LSB (bit 0) first."]
LSB,
}
impl LSBFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LSBFW::MSB => false,
LSBFW::LSB => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LSBFW<'a> {
w: &'a mut W,
}
impl<'a> _LSBFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LSBFW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SPI data is transferred MSB (bit 7) first."]
#[inline]
pub fn msb(self) -> &'a mut W {
self.variant(LSBFW::MSB)
}
#[doc = "SPI data is transferred LSB (bit 0) first."]
#[inline]
pub fn lsb(self) -> &'a mut W {
self.variant(LSBFW::LSB)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPIE`"]
pub enum SPIEW {
#[doc = "SPI interrupts are inhibited."]
INTBLOCK,
#[doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated."]
HWINT,
}
impl SPIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPIEW::INTBLOCK => false,
SPIEW::HWINT => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPIEW<'a> {
w: &'a mut W,
}
impl<'a> _SPIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SPI interrupts are inhibited."]
#[inline]
pub fn intblock(self) -> &'a mut W {
self.variant(SPIEW::INTBLOCK)
}
#[doc = "A hardware interrupt is generated each time the SPIF or MODF bits are activated."]
#[inline]
pub fn hwint(self) -> &'a mut W {
self.variant(SPIEW::HWINT)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BITS`"]
pub enum BITSW {
#[doc = "8 bits per transfer"]
_8_BITS_PER_TRANSFER,
#[doc = "9 bits per transfer"]
_9_BITS_PER_TRANSFER,
#[doc = "10 bits per transfer"]
_10_BITS_PER_TRANSFER,
#[doc = "11 bits per transfer"]
_11_BITS_PER_TRANSFER,
#[doc = "12 bits per transfer"]
_12_BITS_PER_TRANSFER,
#[doc = "13 bits per transfer"]
_13_BITS_PER_TRANSFER,
#[doc = "14 bits per transfer"]
_14_BITS_PER_TRANSFER,
#[doc = "15 bits per transfer"]
_15_BITS_PER_TRANSFER,
#[doc = "16 bits per transfer"]
_16_BITS_PER_TRANSFER,
}
impl BITSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
BITSW::_8_BITS_PER_TRANSFER => 8,
BITSW::_9_BITS_PER_TRANSFER => 9,
BITSW::_10_BITS_PER_TRANSFER => 10,
BITSW::_11_BITS_PER_TRANSFER => 11,
BITSW::_12_BITS_PER_TRANSFER => 12,
BITSW::_13_BITS_PER_TRANSFER => 13,
BITSW::_14_BITS_PER_TRANSFER => 14,
BITSW::_15_BITS_PER_TRANSFER => 15,
BITSW::_16_BITS_PER_TRANSFER => 0,
}
}
}
#[doc = r" Proxy"]
pub struct _BITSW<'a> {
w: &'a mut W,
}
impl<'a> _BITSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BITSW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "8 bits per transfer"]
#[inline]
pub fn _8_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_8_BITS_PER_TRANSFER)
}
#[doc = "9 bits per transfer"]
#[inline]
pub fn _9_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_9_BITS_PER_TRANSFER)
}
#[doc = "10 bits per transfer"]
#[inline]
pub fn _10_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_10_BITS_PER_TRANSFER)
}
#[doc = "11 bits per transfer"]
#[inline]
pub fn _11_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_11_BITS_PER_TRANSFER)
}
#[doc = "12 bits per transfer"]
#[inline]
pub fn _12_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_12_BITS_PER_TRANSFER)
}
#[doc = "13 bits per transfer"]
#[inline]
pub fn _13_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_13_BITS_PER_TRANSFER)
}
#[doc = "14 bits per transfer"]
#[inline]
pub fn _14_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_14_BITS_PER_TRANSFER)
}
#[doc = "15 bits per transfer"]
#[inline]
pub fn _15_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_15_BITS_PER_TRANSFER)
}
#[doc = "16 bits per transfer"]
#[inline]
pub fn _16_bits_per_transfer(self) -> &'a mut W {
self.variant(BITSW::_16_BITS_PER_TRANSFER)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 2 - The SPI controller sends and receives 8 bits of data per transfer."]
#[inline]
pub fn bitenable(&self) -> BITENABLER {
BITENABLER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."]
#[inline]
pub fn cpha(&self) -> CPHAR {
CPHAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Clock polarity control."]
#[inline]
pub fn cpol(&self) -> CPOLR {
CPOLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Master mode select."]
#[inline]
pub fn mstr(&self) -> MSTRR {
MSTRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - LSB First controls which direction each byte is shifted when transferred."]
#[inline]
pub fn lsbf(&self) -> LSBFR {
LSBFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Serial peripheral interrupt enable."]
#[inline]
pub fn spie(&self) -> SPIER {
SPIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer:"]
#[inline]
pub fn bits_(&self) -> BITSR {
BITSR::_from({
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 2 - The SPI controller sends and receives 8 bits of data per transfer."]
#[inline]
pub fn bitenable(&mut self) -> _BITENABLEW {
_BITENABLEW { w: self }
}
#[doc = "Bit 3 - Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending."]
#[inline]
pub fn cpha(&mut self) -> _CPHAW {
_CPHAW { w: self }
}
#[doc = "Bit 4 - Clock polarity control."]
#[inline]
pub fn cpol(&mut self) -> _CPOLW {
_CPOLW { w: self }
}
#[doc = "Bit 5 - Master mode select."]
#[inline]
pub fn mstr(&mut self) -> _MSTRW {
_MSTRW { w: self }
}
#[doc = "Bit 6 - LSB First controls which direction each byte is shifted when transferred."]
#[inline]
pub fn lsbf(&mut self) -> _LSBFW {
_LSBFW { w: self }
}
#[doc = "Bit 7 - Serial peripheral interrupt enable."]
#[inline]
pub fn spie(&mut self) -> _SPIEW {
_SPIEW { w: self }
}
#[doc = "Bits 8:11 - When bit 2 of this register is 1, this field controls the number of bits per transfer:"]
#[inline]
pub fn bits_(&mut self) -> _BITSW {
_BITSW { w: self }
}
}
}
#[doc = "SPI Status Register. This register shows the status of the SPI."]
pub struct SR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SPI Status Register. This register shows the status of the SPI."]
pub mod sr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::SR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct ABRTR {
bits: bool,
}
impl ABRTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MODFR {
bits: bool,
}
impl MODFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ROVRR {
bits: bool,
}
impl ROVRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WCOLR {
bits: bool,
}
impl WCOLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SPIFR {
bits: bool,
}
impl SPIFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 3 - Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register."]
#[inline]
pub fn abrt(&self) -> ABRTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABRTR { bits }
}
#[doc = "Bit 4 - Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register."]
#[inline]
pub fn modf(&self) -> MODFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MODFR { bits }
}
#[doc = "Bit 5 - Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register."]
#[inline]
pub fn rovr(&self) -> ROVRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ROVRR { bits }
}
#[doc = "Bit 6 - Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register."]
#[inline]
pub fn wcol(&self) -> WCOLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WCOLR { bits }
}
#[doc = "Bit 7 - SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register."]
#[inline]
pub fn spif(&self) -> SPIFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SPIFR { bits }
}
}
}
#[doc = "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register."]
pub struct DR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register."]
pub mod dr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATALOWR {
bits: u8,
}
impl DATALOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATAHIGHR {
bits: u8,
}
impl DATAHIGHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATALOWW<'a> {
w: &'a mut W,
}
impl<'a> _DATALOWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATAHIGHW<'a> {
w: &'a mut W,
}
impl<'a> _DATAHIGHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - SPI Bi-directional data port."]
#[inline]
pub fn datalow(&self) -> DATALOWR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATALOWR { bits }
}
#[doc = "Bits 8:15 - If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes."]
#[inline]
pub fn datahigh(&self) -> DATAHIGHR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATAHIGHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - SPI Bi-directional data port."]
#[inline]
pub fn datalow(&mut self) -> _DATALOWW {
_DATALOWW { w: self }
}
#[doc = "Bits 8:15 - If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes."]
#[inline]
pub fn datahigh(&mut self) -> _DATAHIGHW {
_DATAHIGHW { w: self }
}
}
}
#[doc = "SPI Clock Counter Register. This register controls the frequency of a master's SCK0."]
pub struct CCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SPI Clock Counter Register. This register controls the frequency of a master's SCK0."]
pub mod ccr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct COUNTERR {
bits: u8,
}
impl COUNTERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _COUNTERW<'a> {
w: &'a mut W,
}
impl<'a> _COUNTERW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - SPI0 Clock counter setting."]
#[inline]
pub fn counter(&self) -> COUNTERR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
COUNTERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - SPI0 Clock counter setting."]
#[inline]
pub fn counter(&mut self) -> _COUNTERW {
_COUNTERW { w: self }
}
}
}
#[doc = "SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface."]
pub struct INT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface."]
pub mod int {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SPIFR {
bits: bool,
}
impl SPIFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SPIFW<'a> {
w: &'a mut W,
}
impl<'a> _SPIFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software."]
#[inline]
pub fn spif(&self) -> SPIFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SPIFR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software."]
#[inline]
pub fn spif(&mut self) -> _SPIFW {
_SPIFW { w: self }
}
}
}
}
#[doc = "Real Time Clock (RTC)"]
pub struct RTC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RTC {}
impl RTC {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const rtc::RegisterBlock {
0x4002_4000 as *const _
}
}
impl Deref for RTC {
type Target = rtc::RegisterBlock;
fn deref(&self) -> &rtc::RegisterBlock {
unsafe { &*RTC::ptr() }
}
}
#[doc = "Real Time Clock (RTC)"]
pub mod rtc {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Interrupt Location Register"]
pub ilr: ILR,
_reserved1: [u8; 4usize],
#[doc = "0x08 - Clock Control Register"]
pub ccr: CCR,
#[doc = "0x0c - Counter Increment Interrupt Register"]
pub ciir: CIIR,
#[doc = "0x10 - Alarm Mask Register"]
pub amr: AMR,
#[doc = "0x14 - Consolidated Time Register 0"]
pub ctime0: CTIME0,
#[doc = "0x18 - Consolidated Time Register 1"]
pub ctime1: CTIME1,
#[doc = "0x1c - Consolidated Time Register 2"]
pub ctime2: CTIME2,
#[doc = "0x20 - Seconds Counter"]
pub sec: SEC,
#[doc = "0x24 - Minutes Register"]
pub min: MIN,
#[doc = "0x28 - Hours Register"]
pub hrs: HRS,
#[doc = "0x2c - Day of Month Register"]
pub dom: DOM,
#[doc = "0x30 - Day of Week Register"]
pub dow: DOW,
#[doc = "0x34 - Day of Year Register"]
pub doy: DOY,
#[doc = "0x38 - Months Register"]
pub month: MONTH,
#[doc = "0x3c - Years Register"]
pub year: YEAR,
#[doc = "0x40 - Calibration Value Register"]
pub calibration: CALIBRATION,
#[doc = "0x44 - General Purpose Register 0"]
pub gpreg: [GPREG; 5],
#[doc = "0x58 - RTC Auxiliary Enable register"]
pub rtc_auxen: RTC_AUXEN,
#[doc = "0x5c - RTC Auxiliary control register"]
pub rtc_aux: RTC_AUX,
#[doc = "0x60 - Alarm value for Seconds"]
pub asec: ASEC,
#[doc = "0x64 - Alarm value for Minutes"]
pub amin: AMIN,
#[doc = "0x68 - Alarm value for Hours"]
pub ahrs: AHRS,
#[doc = "0x6c - Alarm value for Day of Month"]
pub adom: ADOM,
#[doc = "0x70 - Alarm value for Day of Week"]
pub adow: ADOW,
#[doc = "0x74 - Alarm value for Day of Year"]
pub adoy: ADOY,
#[doc = "0x78 - Alarm value for Months"]
pub amon: AMON,
#[doc = "0x7c - Alarm value for Year"]
pub ayrs: AYRS,
}
#[doc = "Interrupt Location Register"]
pub struct ILR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Location Register"]
pub mod ilr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ILR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RTCCIFR {
bits: bool,
}
impl RTCCIFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RTCALFR {
bits: bool,
}
impl RTCALFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RTCCIFW<'a> {
w: &'a mut W,
}
impl<'a> _RTCCIFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTCALFW<'a> {
w: &'a mut W,
}
impl<'a> _RTCALFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt."]
#[inline]
pub fn rtccif(&self) -> RTCCIFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTCCIFR { bits }
}
#[doc = "Bit 1 - When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt."]
#[inline]
pub fn rtcalf(&self) -> RTCALFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTCALFR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt."]
#[inline]
pub fn rtccif(&mut self) -> _RTCCIFW {
_RTCCIFW { w: self }
}
#[doc = "Bit 1 - When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt."]
#[inline]
pub fn rtcalf(&mut self) -> _RTCALFW {
_RTCALFW { w: self }
}
}
}
#[doc = "Clock Control Register"]
pub struct CCR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clock Control Register"]
pub mod ccr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CLKEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKENR {
#[doc = "The time counters are enabled."]
THE_TIME_COUNTERS_ARE_ENABLED,
#[doc = "The time counters are disabled so that they may be initialized."]
THE_TIME_COUNTERS_ARE_DISABLED,
}
impl CLKENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CLKENR::THE_TIME_COUNTERS_ARE_ENABLED => true,
CLKENR::THE_TIME_COUNTERS_ARE_DISABLED => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CLKENR {
match value {
true => CLKENR::THE_TIME_COUNTERS_ARE_ENABLED,
false => CLKENR::THE_TIME_COUNTERS_ARE_DISABLED,
}
}
#[doc = "Checks if the value of the field is `THE_TIME_COUNTERS_ARE_ENABLED`"]
#[inline]
pub fn is_the_time_counters_are_enabled(&self) -> bool {
*self == CLKENR::THE_TIME_COUNTERS_ARE_ENABLED
}
#[doc = "Checks if the value of the field is `THE_TIME_COUNTERS_AR`"]
#[inline]
pub fn is_the_time_counters_are_disabled(&self) -> bool {
*self == CLKENR::THE_TIME_COUNTERS_ARE_DISABLED
}
}
#[doc = "Possible values of the field `CTCRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CTCRSTR {
#[doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR\\[1\\] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software."]
RESET,
#[doc = "No effect."]
NO_EFFECT_,
}
impl CTCRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CTCRSTR::RESET => true,
CTCRSTR::NO_EFFECT_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CTCRSTR {
match value {
true => CTCRSTR::RESET,
false => CTCRSTR::NO_EFFECT_,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == CTCRSTR::RESET
}
#[doc = "Checks if the value of the field is `NO_EFFECT_`"]
#[inline]
pub fn is_no_effect_(&self) -> bool {
*self == CTCRSTR::NO_EFFECT_
}
}
#[doc = "Possible values of the field `CCALEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCALENR {
#[doc = "The calibration counter is disabled and reset to zero."]
THE_CALIBRATION_COUNTER_IS_DISABLED,
#[doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5."]
THE_CALIBRATION_COUNTER_IS_ENABLED,
}
impl CCALENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCALENR::THE_CALIBRATION_COUNTER_IS_DISABLED => true,
CCALENR::THE_CALIBRATION_COUNTER_IS_ENABLED => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCALENR {
match value {
true => CCALENR::THE_CALIBRATION_COUNTER_IS_DISABLED,
false => CCALENR::THE_CALIBRATION_COUNTER_IS_ENABLED,
}
}
#[doc = "Checks if the value of the field is `THE_CALIBRATION_COUNTER_IS_DISABLED`"]
#[inline]
pub fn is_the_calibration_counter_disabled(&self) -> bool {
*self == CCALENR::THE_CALIBRATION_COUNTER_IS_DISABLED
}
#[doc = "Checks if the value of the field is `THE_CALIBRATION_COUNTER_IS_ENABLED`"]
#[inline]
pub fn is_the_calibration_counter_enabled(&self) -> bool {
*self == CCALENR::THE_CALIBRATION_COUNTER_IS_ENABLED
}
}
#[doc = "Values that can be written to the field `CLKEN`"]
pub enum CLKENW {
#[doc = "The time counters are enabled."]
THE_TIME_COUNTERS_ARE_ENABLED,
#[doc = "The time counters are disabled so that they may be initialized."]
THE_TIME_COUNTERS_ARE_DISABLED,
}
impl CLKENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CLKENW::THE_TIME_COUNTERS_ARE_ENABLED => true,
CLKENW::THE_TIME_COUNTERS_ARE_DISABLED => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CLKENW<'a> {
w: &'a mut W,
}
impl<'a> _CLKENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLKENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The time counters are enabled."]
#[inline]
pub fn the_time_counters_are_enabled(self) -> &'a mut W {
self.variant(CLKENW::THE_TIME_COUNTERS_ARE_ENABLED)
}
#[doc = "The time counters are disabled so that they may be initialized."]
#[inline]
pub fn the_time_counters_are_disabled(self) -> &'a mut W {
self.variant(CLKENW::THE_TIME_COUNTERS_ARE_DISABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CTCRST`"]
pub enum CTCRSTW {
#[doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR\\[1\\] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software."]
RESET,
#[doc = "No effect."]
NO_EFFECT_,
}
impl CTCRSTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CTCRSTW::RESET => true,
CTCRSTW::NO_EFFECT_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CTCRSTW<'a> {
w: &'a mut W,
}
impl<'a> _CTCRSTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CTCRSTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR\\[1\\] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software."]
#[inline]
pub fn reset(self) -> &'a mut W {
self.variant(CTCRSTW::RESET)
}
#[doc = "No effect."]
#[inline]
pub fn no_effect_(self) -> &'a mut W {
self.variant(CTCRSTW::NO_EFFECT_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CCALEN`"]
pub enum CCALENW {
#[doc = "The calibration counter is disabled and reset to zero."]
THE_CALIBRATION_COUNTER_IS_DISABLED,
#[doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5."]
THE_CALIBRATION_COUNTER_IS_ENABLED,
}
impl CCALENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCALENW::THE_CALIBRATION_COUNTER_IS_DISABLED => true,
CCALENW::THE_CALIBRATION_COUNTER_IS_ENABLED => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CCALENW<'a> {
w: &'a mut W,
}
impl<'a> _CCALENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCALENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The calibration counter is disabled and reset to zero."]
#[inline]
pub fn the_calibration_counter_is_disabled(self) -> &'a mut W {
self.variant(CCALENW::THE_CALIBRATION_COUNTER_IS_DISABLED)
}
#[doc = "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5."]
#[inline]
pub fn the_calibration_counter_is_enabled(self) -> &'a mut W {
self.variant(CCALENW::THE_CALIBRATION_COUNTER_IS_ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Clock Enable."]
#[inline]
pub fn clken(&self) -> CLKENR {
CLKENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - CTC Reset."]
#[inline]
pub fn ctcrst(&self) -> CTCRSTR {
CTCRSTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Calibration counter enable."]
#[inline]
pub fn ccalen(&self) -> CCALENR {
CCALENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clock Enable."]
#[inline]
pub fn clken(&mut self) -> _CLKENW {
_CLKENW { w: self }
}
#[doc = "Bit 1 - CTC Reset."]
#[inline]
pub fn ctcrst(&mut self) -> _CTCRSTW {
_CTCRSTW { w: self }
}
#[doc = "Bit 4 - Calibration counter enable."]
#[inline]
pub fn ccalen(&mut self) -> _CCALENW {
_CCALENW { w: self }
}
}
}
#[doc = "Counter Increment Interrupt Register"]
pub struct CIIR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Counter Increment Interrupt Register"]
pub mod ciir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CIIR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct IMSECR {
bits: bool,
}
impl IMSECR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMMINR {
bits: bool,
}
impl IMMINR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMHOURR {
bits: bool,
}
impl IMHOURR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMDOMR {
bits: bool,
}
impl IMDOMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMDOWR {
bits: bool,
}
impl IMDOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMDOYR {
bits: bool,
}
impl IMDOYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMMONR {
bits: bool,
}
impl IMMONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IMYEARR {
bits: bool,
}
impl IMYEARR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _IMSECW<'a> {
w: &'a mut W,
}
impl<'a> _IMSECW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMMINW<'a> {
w: &'a mut W,
}
impl<'a> _IMMINW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMHOURW<'a> {
w: &'a mut W,
}
impl<'a> _IMHOURW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMDOMW<'a> {
w: &'a mut W,
}
impl<'a> _IMDOMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMDOWW<'a> {
w: &'a mut W,
}
impl<'a> _IMDOWW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMDOYW<'a> {
w: &'a mut W,
}
impl<'a> _IMDOYW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMMONW<'a> {
w: &'a mut W,
}
impl<'a> _IMMONW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMYEARW<'a> {
w: &'a mut W,
}
impl<'a> _IMYEARW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, an increment of the Second value generates an interrupt."]
#[inline]
pub fn imsec(&self) -> IMSECR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMSECR { bits }
}
#[doc = "Bit 1 - When 1, an increment of the Minute value generates an interrupt."]
#[inline]
pub fn immin(&self) -> IMMINR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMMINR { bits }
}
#[doc = "Bit 2 - When 1, an increment of the Hour value generates an interrupt."]
#[inline]
pub fn imhour(&self) -> IMHOURR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMHOURR { bits }
}
#[doc = "Bit 3 - When 1, an increment of the Day of Month value generates an interrupt."]
#[inline]
pub fn imdom(&self) -> IMDOMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMDOMR { bits }
}
#[doc = "Bit 4 - When 1, an increment of the Day of Week value generates an interrupt."]
#[inline]
pub fn imdow(&self) -> IMDOWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMDOWR { bits }
}
#[doc = "Bit 5 - When 1, an increment of the Day of Year value generates an interrupt."]
#[inline]
pub fn imdoy(&self) -> IMDOYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMDOYR { bits }
}
#[doc = "Bit 6 - When 1, an increment of the Month value generates an interrupt."]
#[inline]
pub fn immon(&self) -> IMMONR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMMONR { bits }
}
#[doc = "Bit 7 - When 1, an increment of the Year value generates an interrupt."]
#[inline]
pub fn imyear(&self) -> IMYEARR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IMYEARR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When 1, an increment of the Second value generates an interrupt."]
#[inline]
pub fn imsec(&mut self) -> _IMSECW {
_IMSECW { w: self }
}
#[doc = "Bit 1 - When 1, an increment of the Minute value generates an interrupt."]
#[inline]
pub fn immin(&mut self) -> _IMMINW {
_IMMINW { w: self }
}
#[doc = "Bit 2 - When 1, an increment of the Hour value generates an interrupt."]
#[inline]
pub fn imhour(&mut self) -> _IMHOURW {
_IMHOURW { w: self }
}
#[doc = "Bit 3 - When 1, an increment of the Day of Month value generates an interrupt."]
#[inline]
pub fn imdom(&mut self) -> _IMDOMW {
_IMDOMW { w: self }
}
#[doc = "Bit 4 - When 1, an increment of the Day of Week value generates an interrupt."]
#[inline]
pub fn imdow(&mut self) -> _IMDOWW {
_IMDOWW { w: self }
}
#[doc = "Bit 5 - When 1, an increment of the Day of Year value generates an interrupt."]
#[inline]
pub fn imdoy(&mut self) -> _IMDOYW {
_IMDOYW { w: self }
}
#[doc = "Bit 6 - When 1, an increment of the Month value generates an interrupt."]
#[inline]
pub fn immon(&mut self) -> _IMMONW {
_IMMONW { w: self }
}
#[doc = "Bit 7 - When 1, an increment of the Year value generates an interrupt."]
#[inline]
pub fn imyear(&mut self) -> _IMYEARW {
_IMYEARW { w: self }
}
}
}
#[doc = "Alarm Mask Register"]
pub struct AMR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm Mask Register"]
pub mod amr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AMR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct AMRSECR {
bits: bool,
}
impl AMRSECR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRMINR {
bits: bool,
}
impl AMRMINR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRHOURR {
bits: bool,
}
impl AMRHOURR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRDOMR {
bits: bool,
}
impl AMRDOMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRDOWR {
bits: bool,
}
impl AMRDOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRDOYR {
bits: bool,
}
impl AMRDOYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRMONR {
bits: bool,
}
impl AMRMONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMRYEARR {
bits: bool,
}
impl AMRYEARR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _AMRSECW<'a> {
w: &'a mut W,
}
impl<'a> _AMRSECW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRMINW<'a> {
w: &'a mut W,
}
impl<'a> _AMRMINW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRHOURW<'a> {
w: &'a mut W,
}
impl<'a> _AMRHOURW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRDOMW<'a> {
w: &'a mut W,
}
impl<'a> _AMRDOMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRDOWW<'a> {
w: &'a mut W,
}
impl<'a> _AMRDOWW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRDOYW<'a> {
w: &'a mut W,
}
impl<'a> _AMRDOYW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRMONW<'a> {
w: &'a mut W,
}
impl<'a> _AMRMONW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMRYEARW<'a> {
w: &'a mut W,
}
impl<'a> _AMRYEARW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, the Second value is not compared for the alarm."]
#[inline]
pub fn amrsec(&self) -> AMRSECR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRSECR { bits }
}
#[doc = "Bit 1 - When 1, the Minutes value is not compared for the alarm."]
#[inline]
pub fn amrmin(&self) -> AMRMINR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRMINR { bits }
}
#[doc = "Bit 2 - When 1, the Hour value is not compared for the alarm."]
#[inline]
pub fn amrhour(&self) -> AMRHOURR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRHOURR { bits }
}
#[doc = "Bit 3 - When 1, the Day of Month value is not compared for the alarm."]
#[inline]
pub fn amrdom(&self) -> AMRDOMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRDOMR { bits }
}
#[doc = "Bit 4 - When 1, the Day of Week value is not compared for the alarm."]
#[inline]
pub fn amrdow(&self) -> AMRDOWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRDOWR { bits }
}
#[doc = "Bit 5 - When 1, the Day of Year value is not compared for the alarm."]
#[inline]
pub fn amrdoy(&self) -> AMRDOYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRDOYR { bits }
}
#[doc = "Bit 6 - When 1, the Month value is not compared for the alarm."]
#[inline]
pub fn amrmon(&self) -> AMRMONR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRMONR { bits }
}
#[doc = "Bit 7 - When 1, the Year value is not compared for the alarm."]
#[inline]
pub fn amryear(&self) -> AMRYEARR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMRYEARR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When 1, the Second value is not compared for the alarm."]
#[inline]
pub fn amrsec(&mut self) -> _AMRSECW {
_AMRSECW { w: self }
}
#[doc = "Bit 1 - When 1, the Minutes value is not compared for the alarm."]
#[inline]
pub fn amrmin(&mut self) -> _AMRMINW {
_AMRMINW { w: self }
}
#[doc = "Bit 2 - When 1, the Hour value is not compared for the alarm."]
#[inline]
pub fn amrhour(&mut self) -> _AMRHOURW {
_AMRHOURW { w: self }
}
#[doc = "Bit 3 - When 1, the Day of Month value is not compared for the alarm."]
#[inline]
pub fn amrdom(&mut self) -> _AMRDOMW {
_AMRDOMW { w: self }
}
#[doc = "Bit 4 - When 1, the Day of Week value is not compared for the alarm."]
#[inline]
pub fn amrdow(&mut self) -> _AMRDOWW {
_AMRDOWW { w: self }
}
#[doc = "Bit 5 - When 1, the Day of Year value is not compared for the alarm."]
#[inline]
pub fn amrdoy(&mut self) -> _AMRDOYW {
_AMRDOYW { w: self }
}
#[doc = "Bit 6 - When 1, the Month value is not compared for the alarm."]
#[inline]
pub fn amrmon(&mut self) -> _AMRMONW {
_AMRMONW { w: self }
}
#[doc = "Bit 7 - When 1, the Year value is not compared for the alarm."]
#[inline]
pub fn amryear(&mut self) -> _AMRYEARW {
_AMRYEARW { w: self }
}
}
}
#[doc = "Consolidated Time Register 0"]
pub struct CTIME0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Consolidated Time Register 0"]
pub mod ctime0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CTIME0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct SECONDSR {
bits: u8,
}
impl SECONDSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MINUTESR {
bits: u8,
}
impl MINUTESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct HOURSR {
bits: u8,
}
impl HOURSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DOWR {
bits: u8,
}
impl DOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - Seconds value in the range of 0 to 59"]
#[inline]
pub fn seconds(&self) -> SECONDSR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SECONDSR { bits }
}
#[doc = "Bits 8:13 - Minutes value in the range of 0 to 59"]
#[inline]
pub fn minutes(&self) -> MINUTESR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MINUTESR { bits }
}
#[doc = "Bits 16:20 - Hours value in the range of 0 to 23"]
#[inline]
pub fn hours(&self) -> HOURSR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
HOURSR { bits }
}
#[doc = "Bits 24:26 - Day of week value in the range of 0 to 6"]
#[inline]
pub fn dow(&self) -> DOWR {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DOWR { bits }
}
}
}
#[doc = "Consolidated Time Register 1"]
pub struct CTIME1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Consolidated Time Register 1"]
pub mod ctime1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CTIME1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DOMR {
bits: u8,
}
impl DOMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MONTHR {
bits: u8,
}
impl MONTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct YEARR {
bits: u16,
}
impl YEARR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
#[inline]
pub fn dom(&self) -> DOMR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DOMR { bits }
}
#[doc = "Bits 8:11 - Month value in the range of 1 to 12."]
#[inline]
pub fn month(&self) -> MONTHR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MONTHR { bits }
}
#[doc = "Bits 16:27 - Year value in the range of 0 to 4095."]
#[inline]
pub fn year(&self) -> YEARR {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u16
};
YEARR { bits }
}
}
}
#[doc = "Consolidated Time Register 2"]
pub struct CTIME2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Consolidated Time Register 2"]
pub mod ctime2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CTIME2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DOYR {
bits: u16,
}
impl DOYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Day of year value in the range of 1 to 365 (366 for leap years)."]
#[inline]
pub fn doy(&self) -> DOYR {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DOYR { bits }
}
}
}
#[doc = "Seconds Counter"]
pub struct SEC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Seconds Counter"]
pub mod sec {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SEC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SECONDSR {
bits: u8,
}
impl SECONDSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SECONDSW<'a> {
w: &'a mut W,
}
impl<'a> _SECONDSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - Seconds value in the range of 0 to 59"]
#[inline]
pub fn seconds(&self) -> SECONDSR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SECONDSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - Seconds value in the range of 0 to 59"]
#[inline]
pub fn seconds(&mut self) -> _SECONDSW {
_SECONDSW { w: self }
}
}
}
#[doc = "Minutes Register"]
pub struct MIN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Minutes Register"]
pub mod min {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MIN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MINUTESR {
bits: u8,
}
impl MINUTESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MINUTESW<'a> {
w: &'a mut W,
}
impl<'a> _MINUTESW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - Minutes value in the range of 0 to 59"]
#[inline]
pub fn minutes(&self) -> MINUTESR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MINUTESR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - Minutes value in the range of 0 to 59"]
#[inline]
pub fn minutes(&mut self) -> _MINUTESW {
_MINUTESW { w: self }
}
}
}
#[doc = "Hours Register"]
pub struct HRS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Hours Register"]
pub mod hrs {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::HRS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct HOURSR {
bits: u8,
}
impl HOURSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _HOURSW<'a> {
w: &'a mut W,
}
impl<'a> _HOURSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Hours value in the range of 0 to 23"]
#[inline]
pub fn hours(&self) -> HOURSR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
HOURSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Hours value in the range of 0 to 23"]
#[inline]
pub fn hours(&mut self) -> _HOURSW {
_HOURSW { w: self }
}
}
}
#[doc = "Day of Month Register"]
pub struct DOM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Day of Month Register"]
pub mod dom {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DOM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DOMR {
bits: u8,
}
impl DOMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DOMW<'a> {
w: &'a mut W,
}
impl<'a> _DOMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
#[inline]
pub fn dom(&self) -> DOMR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DOMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
#[inline]
pub fn dom(&mut self) -> _DOMW {
_DOMW { w: self }
}
}
}
#[doc = "Day of Week Register"]
pub struct DOW {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Day of Week Register"]
pub mod dow {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DOW {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DOWR {
bits: u8,
}
impl DOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DOWW<'a> {
w: &'a mut W,
}
impl<'a> _DOWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Day of week value in the range of 0 to 6."]
#[inline]
pub fn dow(&self) -> DOWR {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DOWR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Day of week value in the range of 0 to 6."]
#[inline]
pub fn dow(&mut self) -> _DOWW {
_DOWW { w: self }
}
}
}
#[doc = "Day of Year Register"]
pub struct DOY {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Day of Year Register"]
pub mod doy {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DOY {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DOYR {
bits: u16,
}
impl DOYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DOYW<'a> {
w: &'a mut W,
}
impl<'a> _DOYW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:8 - Day of year value in the range of 1 to 365 (366 for leap years)."]
#[inline]
pub fn doy(&self) -> DOYR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DOYR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:8 - Day of year value in the range of 1 to 365 (366 for leap years)."]
#[inline]
pub fn doy(&mut self) -> _DOYW {
_DOYW { w: self }
}
}
}
#[doc = "Months Register"]
pub struct MONTH {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Months Register"]
pub mod month {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MONTH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MONTHR {
bits: u8,
}
impl MONTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MONTHW<'a> {
w: &'a mut W,
}
impl<'a> _MONTHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Month value in the range of 1 to 12."]
#[inline]
pub fn month(&self) -> MONTHR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MONTHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Month value in the range of 1 to 12."]
#[inline]
pub fn month(&mut self) -> _MONTHW {
_MONTHW { w: self }
}
}
}
#[doc = "Years Register"]
pub struct YEAR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Years Register"]
pub mod year {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::YEAR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct YEARR {
bits: u16,
}
impl YEARR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _YEARW<'a> {
w: &'a mut W,
}
impl<'a> _YEARW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Year value in the range of 0 to 4095."]
#[inline]
pub fn year(&self) -> YEARR {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
YEARR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - Year value in the range of 0 to 4095."]
#[inline]
pub fn year(&mut self) -> _YEARW {
_YEARW { w: self }
}
}
}
#[doc = "Calibration Value Register"]
pub struct CALIBRATION {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Calibration Value Register"]
pub mod calibration {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CALIBRATION {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CALVALR {
bits: u32,
}
impl CALVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = "Possible values of the field `CALDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CALDIRR {
#[doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second."]
BACKWARD_CALIBRATION,
#[doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds."]
FORWARD_CALIBRATION_,
}
impl CALDIRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CALDIRR::BACKWARD_CALIBRATION => true,
CALDIRR::FORWARD_CALIBRATION_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CALDIRR {
match value {
true => CALDIRR::BACKWARD_CALIBRATION,
false => CALDIRR::FORWARD_CALIBRATION_,
}
}
#[doc = "Checks if the value of the field is `BACKWARD_CALIBRATION`"]
#[inline]
pub fn is_backward_calibration(&self) -> bool {
*self == CALDIRR::BACKWARD_CALIBRATION
}
#[doc = "Checks if the value of the field is `FORWARD_CALIBRATION_`"]
#[inline]
pub fn is_forward_calibration_(&self) -> bool {
*self == CALDIRR::FORWARD_CALIBRATION_
}
}
#[doc = r" Proxy"]
pub struct _CALVALW<'a> {
w: &'a mut W,
}
impl<'a> _CALVALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x0001_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CALDIR`"]
pub enum CALDIRW {
#[doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second."]
BACKWARD_CALIBRATION,
#[doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds."]
FORWARD_CALIBRATION_,
}
impl CALDIRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CALDIRW::BACKWARD_CALIBRATION => true,
CALDIRW::FORWARD_CALIBRATION_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _CALDIRW<'a> {
w: &'a mut W,
}
impl<'a> _CALDIRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CALDIRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second."]
#[inline]
pub fn backward_calibration(self) -> &'a mut W {
self.variant(CALDIRW::BACKWARD_CALIBRATION)
}
#[doc = "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds."]
#[inline]
pub fn forward_calibration_(self) -> &'a mut W {
self.variant(CALDIRW::FORWARD_CALIBRATION_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:16 - If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0."]
#[inline]
pub fn calval(&self) -> CALVALR {
let bits = {
const MASK: u32 = 0x0001_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
CALVALR { bits }
}
#[doc = "Bit 17 - Calibration direction"]
#[inline]
pub fn caldir(&self) -> CALDIRR {
CALDIRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:16 - If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0."]
#[inline]
pub fn calval(&mut self) -> _CALVALW {
_CALVALW { w: self }
}
#[doc = "Bit 17 - Calibration direction"]
#[inline]
pub fn caldir(&mut self) -> _CALDIRW {
_CALDIRW { w: self }
}
}
}
#[doc = "General Purpose Register 0"]
pub struct GPREG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "General Purpose Register 0"]
pub mod gpreg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::GPREG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct GPR {
bits: u32,
}
impl GPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GPW<'a> {
w: &'a mut W,
}
impl<'a> _GPW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - General purpose storage."]
#[inline]
pub fn gp(&self) -> GPR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
GPR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - General purpose storage."]
#[inline]
pub fn gp(&mut self) -> _GPW {
_GPW { w: self }
}
}
}
#[doc = "RTC Auxiliary control register"]
pub struct RTC_AUX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RTC Auxiliary control register"]
pub mod rtc_aux {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RTC_AUX {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RTC_OSCFR {
bits: bool,
}
impl RTC_OSCFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RTC_PDOUTR {
bits: bool,
}
impl RTC_PDOUTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RTC_OSCFW<'a> {
w: &'a mut W,
}
impl<'a> _RTC_OSCFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTC_PDOUTW<'a> {
w: &'a mut W,
}
impl<'a> _RTC_PDOUTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 4 - RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag."]
#[inline]
pub fn rtc_oscf(&self) -> RTC_OSCFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTC_OSCFR { bits }
}
#[doc = "Bit 6 - When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode."]
#[inline]
pub fn rtc_pdout(&self) -> RTC_PDOUTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTC_PDOUTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x10 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 4 - RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag."]
#[inline]
pub fn rtc_oscf(&mut self) -> _RTC_OSCFW {
_RTC_OSCFW { w: self }
}
#[doc = "Bit 6 - When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode."]
#[inline]
pub fn rtc_pdout(&mut self) -> _RTC_PDOUTW {
_RTC_PDOUTW { w: self }
}
}
}
#[doc = "RTC Auxiliary Enable register"]
pub struct RTC_AUXEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "RTC Auxiliary Enable register"]
pub mod rtc_auxen {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RTC_AUXEN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RTC_OSCFENR {
bits: bool,
}
impl RTC_OSCFENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RTC_OSCFENW<'a> {
w: &'a mut W,
}
impl<'a> _RTC_OSCFENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 4 - Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5."]
#[inline]
pub fn rtc_oscfen(&self) -> RTC_OSCFENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTC_OSCFENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 4 - Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5."]
#[inline]
pub fn rtc_oscfen(&mut self) -> _RTC_OSCFENW {
_RTC_OSCFENW { w: self }
}
}
}
#[doc = "Alarm value for Seconds"]
pub struct ASEC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Seconds"]
pub mod asec {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ASEC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SECONDSR {
bits: u8,
}
impl SECONDSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SECONDSW<'a> {
w: &'a mut W,
}
impl<'a> _SECONDSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - Seconds value in the range of 0 to 59"]
#[inline]
pub fn seconds(&self) -> SECONDSR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SECONDSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - Seconds value in the range of 0 to 59"]
#[inline]
pub fn seconds(&mut self) -> _SECONDSW {
_SECONDSW { w: self }
}
}
}
#[doc = "Alarm value for Minutes"]
pub struct AMIN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Minutes"]
pub mod amin {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AMIN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MINUTESR {
bits: u8,
}
impl MINUTESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MINUTESW<'a> {
w: &'a mut W,
}
impl<'a> _MINUTESW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - Minutes value in the range of 0 to 59"]
#[inline]
pub fn minutes(&self) -> MINUTESR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MINUTESR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - Minutes value in the range of 0 to 59"]
#[inline]
pub fn minutes(&mut self) -> _MINUTESW {
_MINUTESW { w: self }
}
}
}
#[doc = "Alarm value for Hours"]
pub struct AHRS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Hours"]
pub mod ahrs {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AHRS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct HOURSR {
bits: u8,
}
impl HOURSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _HOURSW<'a> {
w: &'a mut W,
}
impl<'a> _HOURSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Hours value in the range of 0 to 23"]
#[inline]
pub fn hours(&self) -> HOURSR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
HOURSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Hours value in the range of 0 to 23"]
#[inline]
pub fn hours(&mut self) -> _HOURSW {
_HOURSW { w: self }
}
}
}
#[doc = "Alarm value for Day of Month"]
pub struct ADOM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Day of Month"]
pub mod adom {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADOM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DOMR {
bits: u8,
}
impl DOMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DOMW<'a> {
w: &'a mut W,
}
impl<'a> _DOMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
#[inline]
pub fn dom(&self) -> DOMR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DOMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)."]
#[inline]
pub fn dom(&mut self) -> _DOMW {
_DOMW { w: self }
}
}
}
#[doc = "Alarm value for Day of Week"]
pub struct ADOW {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Day of Week"]
pub mod adow {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADOW {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DOWR {
bits: u8,
}
impl DOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DOWW<'a> {
w: &'a mut W,
}
impl<'a> _DOWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Day of week value in the range of 0 to 6."]
#[inline]
pub fn dow(&self) -> DOWR {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DOWR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Day of week value in the range of 0 to 6."]
#[inline]
pub fn dow(&mut self) -> _DOWW {
_DOWW { w: self }
}
}
}
#[doc = "Alarm value for Day of Year"]
pub struct ADOY {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Day of Year"]
pub mod adoy {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ADOY {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DOYR {
bits: u16,
}
impl DOYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DOYW<'a> {
w: &'a mut W,
}
impl<'a> _DOYW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:8 - Day of year value in the range of 1 to 365 (366 for leap years)."]
#[inline]
pub fn doy(&self) -> DOYR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DOYR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:8 - Day of year value in the range of 1 to 365 (366 for leap years)."]
#[inline]
pub fn doy(&mut self) -> _DOYW {
_DOYW { w: self }
}
}
}
#[doc = "Alarm value for Months"]
pub struct AMON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Months"]
pub mod amon {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AMON {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MONTHR {
bits: u8,
}
impl MONTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MONTHW<'a> {
w: &'a mut W,
}
impl<'a> _MONTHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Month value in the range of 1 to 12."]
#[inline]
pub fn month(&self) -> MONTHR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MONTHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Month value in the range of 1 to 12."]
#[inline]
pub fn month(&mut self) -> _MONTHW {
_MONTHW { w: self }
}
}
}
#[doc = "Alarm value for Year"]
pub struct AYRS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Alarm value for Year"]
pub mod ayrs {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AYRS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct YEARR {
bits: u16,
}
impl YEARR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _YEARW<'a> {
w: &'a mut W,
}
impl<'a> _YEARW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Year value in the range of 0 to 4095."]
#[inline]
pub fn year(&self) -> YEARR {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
YEARR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - Year value in the range of 0 to 4095."]
#[inline]
pub fn year(&mut self) -> _YEARW {
_YEARW { w: self }
}
}
}
}
#[doc = "GPIO"]
pub struct GPIOINT {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOINT {}
impl GPIOINT {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const gpioint::RegisterBlock {
0x4002_8080 as *const _
}
}
impl Deref for GPIOINT {
type Target = gpioint::RegisterBlock;
fn deref(&self) -> &gpioint::RegisterBlock {
unsafe { &*GPIOINT::ptr() }
}
}
#[doc = "GPIO"]
pub mod gpioint {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - GPIO overall Interrupt Status."]
pub status: STATUS,
#[doc = "0x04 - GPIO Interrupt Status for Rising edge for Port 0."]
pub statr0: STATR0,
#[doc = "0x08 - GPIO Interrupt Status for Falling edge for Port 0."]
pub statf0: STATF0,
#[doc = "0x0c - GPIO Interrupt Clear."]
pub clr0: CLR0,
#[doc = "0x10 - GPIO Interrupt Enable for Rising edge for Port 0."]
pub enr0: ENR0,
#[doc = "0x14 - GPIO Interrupt Enable for Falling edge for Port 0."]
pub enf0: ENF0,
_reserved6: [u8; 12usize],
#[doc = "0x24 - GPIO Interrupt Status for Rising edge for Port 0."]
pub statr2: STATR2,
#[doc = "0x28 - GPIO Interrupt Status for Falling edge for Port 0."]
pub statf2: STATF2,
#[doc = "0x2c - GPIO Interrupt Clear."]
pub clr2: CLR2,
#[doc = "0x30 - GPIO Interrupt Enable for Rising edge for Port 0."]
pub enr2: ENR2,
#[doc = "0x34 - GPIO Interrupt Enable for Falling edge for Port 0."]
pub enf2: ENF2,
}
#[doc = "GPIO overall Interrupt Status."]
pub struct STATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO overall Interrupt Status."]
pub mod status {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATUS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `P0INT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0INTR {
#[doc = "No pending interrupts on Port 0."]
NO_PENDING_INTERRUPT,
#[doc = "At least one pending interrupt on Port 0."]
AT_LEAST_ONE_PENDING,
}
impl P0INTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0INTR::NO_PENDING_INTERRUPT => false,
P0INTR::AT_LEAST_ONE_PENDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0INTR {
match value {
false => P0INTR::NO_PENDING_INTERRUPT,
true => P0INTR::AT_LEAST_ONE_PENDING,
}
}
#[doc = "Checks if the value of the field is `NO_PENDING_INTERRUPT`"]
#[inline]
pub fn is_no_pending_interrupt(&self) -> bool {
*self == P0INTR::NO_PENDING_INTERRUPT
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_PENDING`"]
#[inline]
pub fn is_at_least_one_pending(&self) -> bool {
*self == P0INTR::AT_LEAST_ONE_PENDING
}
}
#[doc = "Possible values of the field `P2INT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2INTR {
#[doc = "No pending interrupts on Port 2."]
NO_PENDING_INTERRUPT,
#[doc = "At least one pending interrupt on Port 2."]
AT_LEAST_ONE_PENDING,
}
impl P2INTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2INTR::NO_PENDING_INTERRUPT => false,
P2INTR::AT_LEAST_ONE_PENDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2INTR {
match value {
false => P2INTR::NO_PENDING_INTERRUPT,
true => P2INTR::AT_LEAST_ONE_PENDING,
}
}
#[doc = "Checks if the value of the field is `NO_PENDING_INTERRUPT`"]
#[inline]
pub fn is_no_pending_interrupt(&self) -> bool {
*self == P2INTR::NO_PENDING_INTERRUPT
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_PENDING`"]
#[inline]
pub fn is_at_least_one_pending(&self) -> bool {
*self == P2INTR::AT_LEAST_ONE_PENDING
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Port 0 GPIO interrupt pending."]
#[inline]
pub fn p0int(&self) -> P0INTR {
P0INTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Port 2 GPIO interrupt pending."]
#[inline]
pub fn p2int(&self) -> P2INTR {
P2INTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "GPIO Interrupt Status for Rising edge for Port 0."]
pub struct STATR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Status for Rising edge for Port 0."]
pub mod statr0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATR0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct P0_0REIR {
bits: bool,
}
impl P0_0REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_1REIR {
bits: bool,
}
impl P0_1REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_2REIR {
bits: bool,
}
impl P0_2REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_3REIR {
bits: bool,
}
impl P0_3REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_4REIR {
bits: bool,
}
impl P0_4REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_5REIR {
bits: bool,
}
impl P0_5REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_6REIR {
bits: bool,
}
impl P0_6REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_7REIR {
bits: bool,
}
impl P0_7REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_8REIR {
bits: bool,
}
impl P0_8REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_9REIR {
bits: bool,
}
impl P0_9REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_10REIR {
bits: bool,
}
impl P0_10REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_11REIR {
bits: bool,
}
impl P0_11REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_12REIR {
bits: bool,
}
impl P0_12REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_13REIR {
bits: bool,
}
impl P0_13REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_14REIR {
bits: bool,
}
impl P0_14REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_15REIR {
bits: bool,
}
impl P0_15REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_16REIR {
bits: bool,
}
impl P0_16REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_17REIR {
bits: bool,
}
impl P0_17REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_18REIR {
bits: bool,
}
impl P0_18REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_19REIR {
bits: bool,
}
impl P0_19REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_20REIR {
bits: bool,
}
impl P0_20REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_21REIR {
bits: bool,
}
impl P0_21REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_22REIR {
bits: bool,
}
impl P0_22REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_23REIR {
bits: bool,
}
impl P0_23REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_24REIR {
bits: bool,
}
impl P0_24REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_25REIR {
bits: bool,
}
impl P0_25REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_26REIR {
bits: bool,
}
impl P0_26REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_27REIR {
bits: bool,
}
impl P0_27REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_28REIR {
bits: bool,
}
impl P0_28REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_29REIR {
bits: bool,
}
impl P0_29REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_30REIR {
bits: bool,
}
impl P0_30REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of Rising Edge Interrupt for P0\\[0\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_0rei(&self) -> P0_0REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_0REIR { bits }
}
#[doc = "Bit 1 - Status of Rising Edge Interrupt for P0\\[1\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_1rei(&self) -> P0_1REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_1REIR { bits }
}
#[doc = "Bit 2 - Status of Rising Edge Interrupt for P0\\[2\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_2rei(&self) -> P0_2REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_2REIR { bits }
}
#[doc = "Bit 3 - Status of Rising Edge Interrupt for P0\\[3\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_3rei(&self) -> P0_3REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_3REIR { bits }
}
#[doc = "Bit 4 - Status of Rising Edge Interrupt for P0\\[4\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_4rei(&self) -> P0_4REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_4REIR { bits }
}
#[doc = "Bit 5 - Status of Rising Edge Interrupt for P0\\[5\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_5rei(&self) -> P0_5REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_5REIR { bits }
}
#[doc = "Bit 6 - Status of Rising Edge Interrupt for P0\\[6\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_6rei(&self) -> P0_6REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_6REIR { bits }
}
#[doc = "Bit 7 - Status of Rising Edge Interrupt for P0\\[7\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_7rei(&self) -> P0_7REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_7REIR { bits }
}
#[doc = "Bit 8 - Status of Rising Edge Interrupt for P0\\[8\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_8rei(&self) -> P0_8REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_8REIR { bits }
}
#[doc = "Bit 9 - Status of Rising Edge Interrupt for P0\\[9\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_9rei(&self) -> P0_9REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_9REIR { bits }
}
#[doc = "Bit 10 - Status of Rising Edge Interrupt for P0\\[10\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_10rei(&self) -> P0_10REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_10REIR { bits }
}
#[doc = "Bit 11 - Status of Rising Edge Interrupt for P0\\[11\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_11rei(&self) -> P0_11REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_11REIR { bits }
}
#[doc = "Bit 12 - Status of Rising Edge Interrupt for P0\\[12\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_12rei(&self) -> P0_12REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_12REIR { bits }
}
#[doc = "Bit 13 - Status of Rising Edge Interrupt for P0\\[13\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_13rei(&self) -> P0_13REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_13REIR { bits }
}
#[doc = "Bit 14 - Status of Rising Edge Interrupt for P0\\[14\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_14rei(&self) -> P0_14REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_14REIR { bits }
}
#[doc = "Bit 15 - Status of Rising Edge Interrupt for P0\\[15\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_15rei(&self) -> P0_15REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_15REIR { bits }
}
#[doc = "Bit 16 - Status of Rising Edge Interrupt for P0\\[16\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_16rei(&self) -> P0_16REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_16REIR { bits }
}
#[doc = "Bit 17 - Status of Rising Edge Interrupt for P0\\[17\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_17rei(&self) -> P0_17REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_17REIR { bits }
}
#[doc = "Bit 18 - Status of Rising Edge Interrupt for P0\\[18\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_18rei(&self) -> P0_18REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_18REIR { bits }
}
#[doc = "Bit 19 - Status of Rising Edge Interrupt for P0\\[19\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_19rei(&self) -> P0_19REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_19REIR { bits }
}
#[doc = "Bit 20 - Status of Rising Edge Interrupt for P0\\[20\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_20rei(&self) -> P0_20REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_20REIR { bits }
}
#[doc = "Bit 21 - Status of Rising Edge Interrupt for P0\\[21\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_21rei(&self) -> P0_21REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_21REIR { bits }
}
#[doc = "Bit 22 - Status of Rising Edge Interrupt for P0\\[22\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_22rei(&self) -> P0_22REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_22REIR { bits }
}
#[doc = "Bit 23 - Status of Rising Edge Interrupt for P0\\[23\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_23rei(&self) -> P0_23REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_23REIR { bits }
}
#[doc = "Bit 24 - Status of Rising Edge Interrupt for P0\\[24\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_24rei(&self) -> P0_24REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_24REIR { bits }
}
#[doc = "Bit 25 - Status of Rising Edge Interrupt for P0\\[25\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_25rei(&self) -> P0_25REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_25REIR { bits }
}
#[doc = "Bit 26 - Status of Rising Edge Interrupt for P0\\[26\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_26rei(&self) -> P0_26REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_26REIR { bits }
}
#[doc = "Bit 27 - Status of Rising Edge Interrupt for P0\\[27\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_27rei(&self) -> P0_27REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_27REIR { bits }
}
#[doc = "Bit 28 - Status of Rising Edge Interrupt for P0\\[28\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_28rei(&self) -> P0_28REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_28REIR { bits }
}
#[doc = "Bit 29 - Status of Rising Edge Interrupt for P0\\[29\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_29rei(&self) -> P0_29REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_29REIR { bits }
}
#[doc = "Bit 30 - Status of Rising Edge Interrupt for P0\\[30\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p0_30rei(&self) -> P0_30REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_30REIR { bits }
}
}
}
#[doc = "GPIO Interrupt Status for Falling edge for Port 0."]
pub struct STATF0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Status for Falling edge for Port 0."]
pub mod statf0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATF0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct P0_0FEIR {
bits: bool,
}
impl P0_0FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_1FEIR {
bits: bool,
}
impl P0_1FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_2FEIR {
bits: bool,
}
impl P0_2FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_3FEIR {
bits: bool,
}
impl P0_3FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_4FEIR {
bits: bool,
}
impl P0_4FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_5FEIR {
bits: bool,
}
impl P0_5FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_6FEIR {
bits: bool,
}
impl P0_6FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_7FEIR {
bits: bool,
}
impl P0_7FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_8FEIR {
bits: bool,
}
impl P0_8FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_9FEIR {
bits: bool,
}
impl P0_9FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_10FEIR {
bits: bool,
}
impl P0_10FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_11FEIR {
bits: bool,
}
impl P0_11FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_12FEIR {
bits: bool,
}
impl P0_12FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_13FEIR {
bits: bool,
}
impl P0_13FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_14FEIR {
bits: bool,
}
impl P0_14FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_15FEIR {
bits: bool,
}
impl P0_15FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_16FEIR {
bits: bool,
}
impl P0_16FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_17FEIR {
bits: bool,
}
impl P0_17FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_18FEIR {
bits: bool,
}
impl P0_18FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_19FEIR {
bits: bool,
}
impl P0_19FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_20FEIR {
bits: bool,
}
impl P0_20FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_21FEIR {
bits: bool,
}
impl P0_21FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_22FEIR {
bits: bool,
}
impl P0_22FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_23FEIR {
bits: bool,
}
impl P0_23FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_24FEIR {
bits: bool,
}
impl P0_24FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_25FEIR {
bits: bool,
}
impl P0_25FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_26FEIR {
bits: bool,
}
impl P0_26FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_27FEIR {
bits: bool,
}
impl P0_27FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_28FEIR {
bits: bool,
}
impl P0_28FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_29FEIR {
bits: bool,
}
impl P0_29FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_30FEIR {
bits: bool,
}
impl P0_30FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of Falling Edge Interrupt for P0\\[0\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_0fei(&self) -> P0_0FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_0FEIR { bits }
}
#[doc = "Bit 1 - Status of Falling Edge Interrupt for P0\\[1\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_1fei(&self) -> P0_1FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_1FEIR { bits }
}
#[doc = "Bit 2 - Status of Falling Edge Interrupt for P0\\[2\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_2fei(&self) -> P0_2FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_2FEIR { bits }
}
#[doc = "Bit 3 - Status of Falling Edge Interrupt for P0\\[3\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_3fei(&self) -> P0_3FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_3FEIR { bits }
}
#[doc = "Bit 4 - Status of Falling Edge Interrupt for P0\\[4\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_4fei(&self) -> P0_4FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_4FEIR { bits }
}
#[doc = "Bit 5 - Status of Falling Edge Interrupt for P0\\[5\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_5fei(&self) -> P0_5FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_5FEIR { bits }
}
#[doc = "Bit 6 - Status of Falling Edge Interrupt for P0\\[6\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_6fei(&self) -> P0_6FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_6FEIR { bits }
}
#[doc = "Bit 7 - Status of Falling Edge Interrupt for P0\\[7\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_7fei(&self) -> P0_7FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_7FEIR { bits }
}
#[doc = "Bit 8 - Status of Falling Edge Interrupt for P0\\[8\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_8fei(&self) -> P0_8FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_8FEIR { bits }
}
#[doc = "Bit 9 - Status of Falling Edge Interrupt for P0\\[9\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_9fei(&self) -> P0_9FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_9FEIR { bits }
}
#[doc = "Bit 10 - Status of Falling Edge Interrupt for P0\\[10\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_10fei(&self) -> P0_10FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_10FEIR { bits }
}
#[doc = "Bit 11 - Status of Falling Edge Interrupt for P0\\[11\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_11fei(&self) -> P0_11FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_11FEIR { bits }
}
#[doc = "Bit 12 - Status of Falling Edge Interrupt for P0\\[12\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_12fei(&self) -> P0_12FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_12FEIR { bits }
}
#[doc = "Bit 13 - Status of Falling Edge Interrupt for P0\\[13\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_13fei(&self) -> P0_13FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_13FEIR { bits }
}
#[doc = "Bit 14 - Status of Falling Edge Interrupt for P0\\[14\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_14fei(&self) -> P0_14FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_14FEIR { bits }
}
#[doc = "Bit 15 - Status of Falling Edge Interrupt for P0\\[15\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_15fei(&self) -> P0_15FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_15FEIR { bits }
}
#[doc = "Bit 16 - Status of Falling Edge Interrupt for P0\\[16\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_16fei(&self) -> P0_16FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_16FEIR { bits }
}
#[doc = "Bit 17 - Status of Falling Edge Interrupt for P0\\[17\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_17fei(&self) -> P0_17FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_17FEIR { bits }
}
#[doc = "Bit 18 - Status of Falling Edge Interrupt for P0\\[18\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_18fei(&self) -> P0_18FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_18FEIR { bits }
}
#[doc = "Bit 19 - Status of Falling Edge Interrupt for P0\\[19\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_19fei(&self) -> P0_19FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_19FEIR { bits }
}
#[doc = "Bit 20 - Status of Falling Edge Interrupt for P0\\[20\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_20fei(&self) -> P0_20FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_20FEIR { bits }
}
#[doc = "Bit 21 - Status of Falling Edge Interrupt for P0\\[21\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_21fei(&self) -> P0_21FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_21FEIR { bits }
}
#[doc = "Bit 22 - Status of Falling Edge Interrupt for P0\\[22\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_22fei(&self) -> P0_22FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_22FEIR { bits }
}
#[doc = "Bit 23 - Status of Falling Edge Interrupt for P0\\[23\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_23fei(&self) -> P0_23FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_23FEIR { bits }
}
#[doc = "Bit 24 - Status of Falling Edge Interrupt for P0\\[24\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_24fei(&self) -> P0_24FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_24FEIR { bits }
}
#[doc = "Bit 25 - Status of Falling Edge Interrupt for P0\\[25\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_25fei(&self) -> P0_25FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_25FEIR { bits }
}
#[doc = "Bit 26 - Status of Falling Edge Interrupt for P0\\[26\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_26fei(&self) -> P0_26FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_26FEIR { bits }
}
#[doc = "Bit 27 - Status of Falling Edge Interrupt for P0\\[27\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_27fei(&self) -> P0_27FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_27FEIR { bits }
}
#[doc = "Bit 28 - Status of Falling Edge Interrupt for P0\\[28\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_28fei(&self) -> P0_28FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_28FEIR { bits }
}
#[doc = "Bit 29 - Status of Falling Edge Interrupt for P0\\[29\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_29fei(&self) -> P0_29FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_29FEIR { bits }
}
#[doc = "Bit 30 - Status of Falling Edge Interrupt for P0\\[30\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p0_30fei(&self) -> P0_30FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_30FEIR { bits }
}
}
}
#[doc = "GPIO Interrupt Clear."]
pub struct CLR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Clear."]
pub mod clr0 {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLR0 {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _P0_0CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_0CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_1CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_1CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_2CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_2CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_3CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_3CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_4CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_4CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_5CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_5CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_6CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_6CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_7CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_7CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_8CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_8CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_9CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_9CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_10CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_10CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_11CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_11CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_12CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_12CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_13CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_13CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_14CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_14CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_15CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_15CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_16CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_16CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_17CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_17CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_18CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_18CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_19CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_19CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_20CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_20CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_21CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_21CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_22CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_22CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_23CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_23CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_24CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_24CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_25CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_25CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_26CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_26CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_27CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_27CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_28CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_28CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_29CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_29CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_30CIW<'a> {
w: &'a mut W,
}
impl<'a> _P0_30CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clear GPIO port Interrupts for P0\\[0\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_0ci(&mut self) -> _P0_0CIW {
_P0_0CIW { w: self }
}
#[doc = "Bit 1 - Clear GPIO port Interrupts for P0\\[1\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_1ci(&mut self) -> _P0_1CIW {
_P0_1CIW { w: self }
}
#[doc = "Bit 2 - Clear GPIO port Interrupts for P0\\[2\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_2ci(&mut self) -> _P0_2CIW {
_P0_2CIW { w: self }
}
#[doc = "Bit 3 - Clear GPIO port Interrupts for P0\\[3\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_3ci(&mut self) -> _P0_3CIW {
_P0_3CIW { w: self }
}
#[doc = "Bit 4 - Clear GPIO port Interrupts for P0\\[4\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_4ci(&mut self) -> _P0_4CIW {
_P0_4CIW { w: self }
}
#[doc = "Bit 5 - Clear GPIO port Interrupts for P0\\[5\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_5ci(&mut self) -> _P0_5CIW {
_P0_5CIW { w: self }
}
#[doc = "Bit 6 - Clear GPIO port Interrupts for P0\\[6\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_6ci(&mut self) -> _P0_6CIW {
_P0_6CIW { w: self }
}
#[doc = "Bit 7 - Clear GPIO port Interrupts for P0\\[7\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_7ci(&mut self) -> _P0_7CIW {
_P0_7CIW { w: self }
}
#[doc = "Bit 8 - Clear GPIO port Interrupts for P0\\[8\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_8ci(&mut self) -> _P0_8CIW {
_P0_8CIW { w: self }
}
#[doc = "Bit 9 - Clear GPIO port Interrupts for P0\\[9\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_9ci(&mut self) -> _P0_9CIW {
_P0_9CIW { w: self }
}
#[doc = "Bit 10 - Clear GPIO port Interrupts for P0\\[10\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_10ci(&mut self) -> _P0_10CIW {
_P0_10CIW { w: self }
}
#[doc = "Bit 11 - Clear GPIO port Interrupts for P0\\[11\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_11ci(&mut self) -> _P0_11CIW {
_P0_11CIW { w: self }
}
#[doc = "Bit 12 - Clear GPIO port Interrupts for P0\\[12\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_12ci(&mut self) -> _P0_12CIW {
_P0_12CIW { w: self }
}
#[doc = "Bit 13 - Clear GPIO port Interrupts for P0\\[13\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_13ci(&mut self) -> _P0_13CIW {
_P0_13CIW { w: self }
}
#[doc = "Bit 14 - Clear GPIO port Interrupts for P0\\[14\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_14ci(&mut self) -> _P0_14CIW {
_P0_14CIW { w: self }
}
#[doc = "Bit 15 - Clear GPIO port Interrupts for P0\\[15\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_15ci(&mut self) -> _P0_15CIW {
_P0_15CIW { w: self }
}
#[doc = "Bit 16 - Clear GPIO port Interrupts for P0\\[16\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_16ci(&mut self) -> _P0_16CIW {
_P0_16CIW { w: self }
}
#[doc = "Bit 17 - Clear GPIO port Interrupts for P0\\[17\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_17ci(&mut self) -> _P0_17CIW {
_P0_17CIW { w: self }
}
#[doc = "Bit 18 - Clear GPIO port Interrupts for P0\\[18\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_18ci(&mut self) -> _P0_18CIW {
_P0_18CIW { w: self }
}
#[doc = "Bit 19 - Clear GPIO port Interrupts for P0\\[19\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_19ci(&mut self) -> _P0_19CIW {
_P0_19CIW { w: self }
}
#[doc = "Bit 20 - Clear GPIO port Interrupts for P0\\[20\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_20ci(&mut self) -> _P0_20CIW {
_P0_20CIW { w: self }
}
#[doc = "Bit 21 - Clear GPIO port Interrupts for P0\\[21\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_21ci(&mut self) -> _P0_21CIW {
_P0_21CIW { w: self }
}
#[doc = "Bit 22 - Clear GPIO port Interrupts for P0\\[22\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_22ci(&mut self) -> _P0_22CIW {
_P0_22CIW { w: self }
}
#[doc = "Bit 23 - Clear GPIO port Interrupts for P0\\[23\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_23ci(&mut self) -> _P0_23CIW {
_P0_23CIW { w: self }
}
#[doc = "Bit 24 - Clear GPIO port Interrupts for P0\\[24\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_24ci(&mut self) -> _P0_24CIW {
_P0_24CIW { w: self }
}
#[doc = "Bit 25 - Clear GPIO port Interrupts for P0\\[25\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_25ci(&mut self) -> _P0_25CIW {
_P0_25CIW { w: self }
}
#[doc = "Bit 26 - Clear GPIO port Interrupts for P0\\[26\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_26ci(&mut self) -> _P0_26CIW {
_P0_26CIW { w: self }
}
#[doc = "Bit 27 - Clear GPIO port Interrupts for P0\\[27\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_27ci(&mut self) -> _P0_27CIW {
_P0_27CIW { w: self }
}
#[doc = "Bit 28 - Clear GPIO port Interrupts for P0\\[28\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_28ci(&mut self) -> _P0_28CIW {
_P0_28CIW { w: self }
}
#[doc = "Bit 29 - Clear GPIO port Interrupts for P0\\[29\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_29ci(&mut self) -> _P0_29CIW {
_P0_29CIW { w: self }
}
#[doc = "Bit 30 - Clear GPIO port Interrupts for P0\\[30\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p0_30ci(&mut self) -> _P0_30CIW {
_P0_30CIW { w: self }
}
}
}
#[doc = "GPIO Interrupt Enable for Rising edge for Port 0."]
pub struct ENR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Enable for Rising edge for Port 0."]
pub mod enr0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ENR0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct P0_0ERR {
bits: bool,
}
impl P0_0ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_1ERR {
bits: bool,
}
impl P0_1ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_2ERR {
bits: bool,
}
impl P0_2ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_3ERR {
bits: bool,
}
impl P0_3ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_4ERR {
bits: bool,
}
impl P0_4ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_5ERR {
bits: bool,
}
impl P0_5ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_6ERR {
bits: bool,
}
impl P0_6ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_7ERR {
bits: bool,
}
impl P0_7ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_8ERR {
bits: bool,
}
impl P0_8ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_9ERR {
bits: bool,
}
impl P0_9ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_10ERR {
bits: bool,
}
impl P0_10ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_11ERR {
bits: bool,
}
impl P0_11ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_12ERR {
bits: bool,
}
impl P0_12ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_13ERR {
bits: bool,
}
impl P0_13ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_14ERR {
bits: bool,
}
impl P0_14ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_15ERR {
bits: bool,
}
impl P0_15ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_16ERR {
bits: bool,
}
impl P0_16ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_17ERR {
bits: bool,
}
impl P0_17ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_18ERR {
bits: bool,
}
impl P0_18ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_19ERR {
bits: bool,
}
impl P0_19ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_20ERR {
bits: bool,
}
impl P0_20ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_21ERR {
bits: bool,
}
impl P0_21ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_22ERR {
bits: bool,
}
impl P0_22ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_23ERR {
bits: bool,
}
impl P0_23ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_24ERR {
bits: bool,
}
impl P0_24ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_25ERR {
bits: bool,
}
impl P0_25ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_26ERR {
bits: bool,
}
impl P0_26ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_27ERR {
bits: bool,
}
impl P0_27ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_28ERR {
bits: bool,
}
impl P0_28ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_29ERR {
bits: bool,
}
impl P0_29ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_30ERR {
bits: bool,
}
impl P0_30ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _P0_0ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_0ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_1ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_1ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_2ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_2ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_3ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_3ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_4ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_4ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_5ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_5ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_6ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_6ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_7ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_7ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_8ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_8ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_9ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_9ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_10ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_10ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_11ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_11ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_12ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_12ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_13ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_13ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_14ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_14ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_15ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_15ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_16ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_16ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_17ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_17ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_18ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_18ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_19ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_19ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_20ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_20ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_21ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_21ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_22ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_22ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_23ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_23ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_24ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_24ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_25ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_25ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_26ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_26ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_27ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_27ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_28ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_28ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_29ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_29ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_30ERW<'a> {
w: &'a mut W,
}
impl<'a> _P0_30ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable rising edge interrupt for P0\\[0\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_0er(&self) -> P0_0ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_0ERR { bits }
}
#[doc = "Bit 1 - Enable rising edge interrupt for P0\\[1\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_1er(&self) -> P0_1ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_1ERR { bits }
}
#[doc = "Bit 2 - Enable rising edge interrupt for P0\\[2\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_2er(&self) -> P0_2ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_2ERR { bits }
}
#[doc = "Bit 3 - Enable rising edge interrupt for P0\\[3\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_3er(&self) -> P0_3ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_3ERR { bits }
}
#[doc = "Bit 4 - Enable rising edge interrupt for P0\\[4\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_4er(&self) -> P0_4ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_4ERR { bits }
}
#[doc = "Bit 5 - Enable rising edge interrupt for P0\\[5\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_5er(&self) -> P0_5ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_5ERR { bits }
}
#[doc = "Bit 6 - Enable rising edge interrupt for P0\\[6\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_6er(&self) -> P0_6ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_6ERR { bits }
}
#[doc = "Bit 7 - Enable rising edge interrupt for P0\\[7\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_7er(&self) -> P0_7ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_7ERR { bits }
}
#[doc = "Bit 8 - Enable rising edge interrupt for P0\\[8\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_8er(&self) -> P0_8ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_8ERR { bits }
}
#[doc = "Bit 9 - Enable rising edge interrupt for P0\\[9\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_9er(&self) -> P0_9ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_9ERR { bits }
}
#[doc = "Bit 10 - Enable rising edge interrupt for P0\\[10\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_10er(&self) -> P0_10ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_10ERR { bits }
}
#[doc = "Bit 11 - Enable rising edge interrupt for P0\\[11\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_11er(&self) -> P0_11ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_11ERR { bits }
}
#[doc = "Bit 12 - Enable rising edge interrupt for P0\\[12\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_12er(&self) -> P0_12ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_12ERR { bits }
}
#[doc = "Bit 13 - Enable rising edge interrupt for P0\\[13\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_13er(&self) -> P0_13ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_13ERR { bits }
}
#[doc = "Bit 14 - Enable rising edge interrupt for P0\\[14\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_14er(&self) -> P0_14ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_14ERR { bits }
}
#[doc = "Bit 15 - Enable rising edge interrupt for P0\\[15\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_15er(&self) -> P0_15ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_15ERR { bits }
}
#[doc = "Bit 16 - Enable rising edge interrupt for P0\\[16\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_16er(&self) -> P0_16ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_16ERR { bits }
}
#[doc = "Bit 17 - Enable rising edge interrupt for P0\\[17\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_17er(&self) -> P0_17ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_17ERR { bits }
}
#[doc = "Bit 18 - Enable rising edge interrupt for P0\\[18\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_18er(&self) -> P0_18ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_18ERR { bits }
}
#[doc = "Bit 19 - Enable rising edge interrupt for P0\\[19\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_19er(&self) -> P0_19ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_19ERR { bits }
}
#[doc = "Bit 20 - Enable rising edge interrupt for P0\\[20\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_20er(&self) -> P0_20ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_20ERR { bits }
}
#[doc = "Bit 21 - Enable rising edge interrupt for P0\\[21\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_21er(&self) -> P0_21ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_21ERR { bits }
}
#[doc = "Bit 22 - Enable rising edge interrupt for P0\\[22\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_22er(&self) -> P0_22ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_22ERR { bits }
}
#[doc = "Bit 23 - Enable rising edge interrupt for P0\\[23\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_23er(&self) -> P0_23ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_23ERR { bits }
}
#[doc = "Bit 24 - Enable rising edge interrupt for P0\\[24\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_24er(&self) -> P0_24ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_24ERR { bits }
}
#[doc = "Bit 25 - Enable rising edge interrupt for P0\\[25\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_25er(&self) -> P0_25ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_25ERR { bits }
}
#[doc = "Bit 26 - Enable rising edge interrupt for P0\\[26\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_26er(&self) -> P0_26ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_26ERR { bits }
}
#[doc = "Bit 27 - Enable rising edge interrupt for P0\\[27\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_27er(&self) -> P0_27ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_27ERR { bits }
}
#[doc = "Bit 28 - Enable rising edge interrupt for P0\\[28\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_28er(&self) -> P0_28ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_28ERR { bits }
}
#[doc = "Bit 29 - Enable rising edge interrupt for P0\\[29\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_29er(&self) -> P0_29ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_29ERR { bits }
}
#[doc = "Bit 30 - Enable rising edge interrupt for P0\\[30\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_30er(&self) -> P0_30ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_30ERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable rising edge interrupt for P0\\[0\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_0er(&mut self) -> _P0_0ERW {
_P0_0ERW { w: self }
}
#[doc = "Bit 1 - Enable rising edge interrupt for P0\\[1\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_1er(&mut self) -> _P0_1ERW {
_P0_1ERW { w: self }
}
#[doc = "Bit 2 - Enable rising edge interrupt for P0\\[2\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_2er(&mut self) -> _P0_2ERW {
_P0_2ERW { w: self }
}
#[doc = "Bit 3 - Enable rising edge interrupt for P0\\[3\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_3er(&mut self) -> _P0_3ERW {
_P0_3ERW { w: self }
}
#[doc = "Bit 4 - Enable rising edge interrupt for P0\\[4\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_4er(&mut self) -> _P0_4ERW {
_P0_4ERW { w: self }
}
#[doc = "Bit 5 - Enable rising edge interrupt for P0\\[5\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_5er(&mut self) -> _P0_5ERW {
_P0_5ERW { w: self }
}
#[doc = "Bit 6 - Enable rising edge interrupt for P0\\[6\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_6er(&mut self) -> _P0_6ERW {
_P0_6ERW { w: self }
}
#[doc = "Bit 7 - Enable rising edge interrupt for P0\\[7\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_7er(&mut self) -> _P0_7ERW {
_P0_7ERW { w: self }
}
#[doc = "Bit 8 - Enable rising edge interrupt for P0\\[8\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_8er(&mut self) -> _P0_8ERW {
_P0_8ERW { w: self }
}
#[doc = "Bit 9 - Enable rising edge interrupt for P0\\[9\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_9er(&mut self) -> _P0_9ERW {
_P0_9ERW { w: self }
}
#[doc = "Bit 10 - Enable rising edge interrupt for P0\\[10\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_10er(&mut self) -> _P0_10ERW {
_P0_10ERW { w: self }
}
#[doc = "Bit 11 - Enable rising edge interrupt for P0\\[11\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_11er(&mut self) -> _P0_11ERW {
_P0_11ERW { w: self }
}
#[doc = "Bit 12 - Enable rising edge interrupt for P0\\[12\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_12er(&mut self) -> _P0_12ERW {
_P0_12ERW { w: self }
}
#[doc = "Bit 13 - Enable rising edge interrupt for P0\\[13\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_13er(&mut self) -> _P0_13ERW {
_P0_13ERW { w: self }
}
#[doc = "Bit 14 - Enable rising edge interrupt for P0\\[14\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_14er(&mut self) -> _P0_14ERW {
_P0_14ERW { w: self }
}
#[doc = "Bit 15 - Enable rising edge interrupt for P0\\[15\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_15er(&mut self) -> _P0_15ERW {
_P0_15ERW { w: self }
}
#[doc = "Bit 16 - Enable rising edge interrupt for P0\\[16\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_16er(&mut self) -> _P0_16ERW {
_P0_16ERW { w: self }
}
#[doc = "Bit 17 - Enable rising edge interrupt for P0\\[17\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_17er(&mut self) -> _P0_17ERW {
_P0_17ERW { w: self }
}
#[doc = "Bit 18 - Enable rising edge interrupt for P0\\[18\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_18er(&mut self) -> _P0_18ERW {
_P0_18ERW { w: self }
}
#[doc = "Bit 19 - Enable rising edge interrupt for P0\\[19\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_19er(&mut self) -> _P0_19ERW {
_P0_19ERW { w: self }
}
#[doc = "Bit 20 - Enable rising edge interrupt for P0\\[20\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_20er(&mut self) -> _P0_20ERW {
_P0_20ERW { w: self }
}
#[doc = "Bit 21 - Enable rising edge interrupt for P0\\[21\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_21er(&mut self) -> _P0_21ERW {
_P0_21ERW { w: self }
}
#[doc = "Bit 22 - Enable rising edge interrupt for P0\\[22\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_22er(&mut self) -> _P0_22ERW {
_P0_22ERW { w: self }
}
#[doc = "Bit 23 - Enable rising edge interrupt for P0\\[23\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_23er(&mut self) -> _P0_23ERW {
_P0_23ERW { w: self }
}
#[doc = "Bit 24 - Enable rising edge interrupt for P0\\[24\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_24er(&mut self) -> _P0_24ERW {
_P0_24ERW { w: self }
}
#[doc = "Bit 25 - Enable rising edge interrupt for P0\\[25\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_25er(&mut self) -> _P0_25ERW {
_P0_25ERW { w: self }
}
#[doc = "Bit 26 - Enable rising edge interrupt for P0\\[26\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_26er(&mut self) -> _P0_26ERW {
_P0_26ERW { w: self }
}
#[doc = "Bit 27 - Enable rising edge interrupt for P0\\[27\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_27er(&mut self) -> _P0_27ERW {
_P0_27ERW { w: self }
}
#[doc = "Bit 28 - Enable rising edge interrupt for P0\\[28\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_28er(&mut self) -> _P0_28ERW {
_P0_28ERW { w: self }
}
#[doc = "Bit 29 - Enable rising edge interrupt for P0\\[29\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_29er(&mut self) -> _P0_29ERW {
_P0_29ERW { w: self }
}
#[doc = "Bit 30 - Enable rising edge interrupt for P0\\[30\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p0_30er(&mut self) -> _P0_30ERW {
_P0_30ERW { w: self }
}
}
}
#[doc = "GPIO Interrupt Enable for Falling edge for Port 0."]
pub struct ENF0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Enable for Falling edge for Port 0."]
pub mod enf0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ENF0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct P0_0EFR {
bits: bool,
}
impl P0_0EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_1EFR {
bits: bool,
}
impl P0_1EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_2EFR {
bits: bool,
}
impl P0_2EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_3EFR {
bits: bool,
}
impl P0_3EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_4EFR {
bits: bool,
}
impl P0_4EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_5EFR {
bits: bool,
}
impl P0_5EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_6EFR {
bits: bool,
}
impl P0_6EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_7EFR {
bits: bool,
}
impl P0_7EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_8EFR {
bits: bool,
}
impl P0_8EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_9EFR {
bits: bool,
}
impl P0_9EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_10EFR {
bits: bool,
}
impl P0_10EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_11EFR {
bits: bool,
}
impl P0_11EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_12EFR {
bits: bool,
}
impl P0_12EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_13EFR {
bits: bool,
}
impl P0_13EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_14EFR {
bits: bool,
}
impl P0_14EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_15EFR {
bits: bool,
}
impl P0_15EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_16EFR {
bits: bool,
}
impl P0_16EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_17EFR {
bits: bool,
}
impl P0_17EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_18EFR {
bits: bool,
}
impl P0_18EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_19EFR {
bits: bool,
}
impl P0_19EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_20EFR {
bits: bool,
}
impl P0_20EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_21EFR {
bits: bool,
}
impl P0_21EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_22EFR {
bits: bool,
}
impl P0_22EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_23EFR {
bits: bool,
}
impl P0_23EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_24EFR {
bits: bool,
}
impl P0_24EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_25EFR {
bits: bool,
}
impl P0_25EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_26EFR {
bits: bool,
}
impl P0_26EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_27EFR {
bits: bool,
}
impl P0_27EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_28EFR {
bits: bool,
}
impl P0_28EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_29EFR {
bits: bool,
}
impl P0_29EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P0_30EFR {
bits: bool,
}
impl P0_30EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _P0_0EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_0EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_1EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_1EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_2EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_2EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_3EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_3EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_4EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_4EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_5EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_5EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_6EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_6EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_7EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_7EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_8EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_8EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_9EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_9EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_10EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_10EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_11EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_11EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_12EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_12EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_13EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_13EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_14EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_14EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_15EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_15EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_16EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_16EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_17EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_17EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_18EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_18EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_19EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_19EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_20EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_20EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_21EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_21EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_22EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_22EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_23EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_23EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_24EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_24EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_25EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_25EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_26EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_26EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_27EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_27EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_28EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_28EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_29EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_29EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P0_30EFW<'a> {
w: &'a mut W,
}
impl<'a> _P0_30EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable falling edge interrupt for P0\\[0\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_0ef(&self) -> P0_0EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_0EFR { bits }
}
#[doc = "Bit 1 - Enable falling edge interrupt for P0\\[1\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_1ef(&self) -> P0_1EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_1EFR { bits }
}
#[doc = "Bit 2 - Enable falling edge interrupt for P0\\[2\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_2ef(&self) -> P0_2EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_2EFR { bits }
}
#[doc = "Bit 3 - Enable falling edge interrupt for P0\\[3\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_3ef(&self) -> P0_3EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_3EFR { bits }
}
#[doc = "Bit 4 - Enable falling edge interrupt for P0\\[4\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_4ef(&self) -> P0_4EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_4EFR { bits }
}
#[doc = "Bit 5 - Enable falling edge interrupt for P0\\[5\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_5ef(&self) -> P0_5EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_5EFR { bits }
}
#[doc = "Bit 6 - Enable falling edge interrupt for P0\\[6\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_6ef(&self) -> P0_6EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_6EFR { bits }
}
#[doc = "Bit 7 - Enable falling edge interrupt for P0\\[7\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_7ef(&self) -> P0_7EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_7EFR { bits }
}
#[doc = "Bit 8 - Enable falling edge interrupt for P0\\[8\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_8ef(&self) -> P0_8EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_8EFR { bits }
}
#[doc = "Bit 9 - Enable falling edge interrupt for P0\\[9\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_9ef(&self) -> P0_9EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_9EFR { bits }
}
#[doc = "Bit 10 - Enable falling edge interrupt for P0\\[10\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_10ef(&self) -> P0_10EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_10EFR { bits }
}
#[doc = "Bit 11 - Enable falling edge interrupt for P0\\[11\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_11ef(&self) -> P0_11EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_11EFR { bits }
}
#[doc = "Bit 12 - Enable falling edge interrupt for P0\\[12\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_12ef(&self) -> P0_12EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_12EFR { bits }
}
#[doc = "Bit 13 - Enable falling edge interrupt for P0\\[13\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_13ef(&self) -> P0_13EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_13EFR { bits }
}
#[doc = "Bit 14 - Enable falling edge interrupt for P0\\[14\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_14ef(&self) -> P0_14EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_14EFR { bits }
}
#[doc = "Bit 15 - Enable falling edge interrupt for P0\\[15\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_15ef(&self) -> P0_15EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_15EFR { bits }
}
#[doc = "Bit 16 - Enable falling edge interrupt for P0\\[16\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_16ef(&self) -> P0_16EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_16EFR { bits }
}
#[doc = "Bit 17 - Enable falling edge interrupt for P0\\[17\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_17ef(&self) -> P0_17EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_17EFR { bits }
}
#[doc = "Bit 18 - Enable falling edge interrupt for P0\\[18\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_18ef(&self) -> P0_18EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_18EFR { bits }
}
#[doc = "Bit 19 - Enable falling edge interrupt for P0\\[19\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_19ef(&self) -> P0_19EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_19EFR { bits }
}
#[doc = "Bit 20 - Enable falling edge interrupt for P0\\[20\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_20ef(&self) -> P0_20EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_20EFR { bits }
}
#[doc = "Bit 21 - Enable falling edge interrupt for P0\\[21\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_21ef(&self) -> P0_21EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_21EFR { bits }
}
#[doc = "Bit 22 - Enable falling edge interrupt for P0\\[22\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_22ef(&self) -> P0_22EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_22EFR { bits }
}
#[doc = "Bit 23 - Enable falling edge interrupt for P0\\[23\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_23ef(&self) -> P0_23EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_23EFR { bits }
}
#[doc = "Bit 24 - Enable falling edge interrupt for P0\\[24\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_24ef(&self) -> P0_24EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_24EFR { bits }
}
#[doc = "Bit 25 - Enable falling edge interrupt for P0\\[25\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_25ef(&self) -> P0_25EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_25EFR { bits }
}
#[doc = "Bit 26 - Enable falling edge interrupt for P0\\[26\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_26ef(&self) -> P0_26EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_26EFR { bits }
}
#[doc = "Bit 27 - Enable falling edge interrupt for P0\\[27\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_27ef(&self) -> P0_27EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_27EFR { bits }
}
#[doc = "Bit 28 - Enable falling edge interrupt for P0\\[28\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_28ef(&self) -> P0_28EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_28EFR { bits }
}
#[doc = "Bit 29 - Enable falling edge interrupt for P0\\[29\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_29ef(&self) -> P0_29EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_29EFR { bits }
}
#[doc = "Bit 30 - Enable falling edge interrupt for P0\\[30\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_30ef(&self) -> P0_30EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P0_30EFR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable falling edge interrupt for P0\\[0\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_0ef(&mut self) -> _P0_0EFW {
_P0_0EFW { w: self }
}
#[doc = "Bit 1 - Enable falling edge interrupt for P0\\[1\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_1ef(&mut self) -> _P0_1EFW {
_P0_1EFW { w: self }
}
#[doc = "Bit 2 - Enable falling edge interrupt for P0\\[2\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_2ef(&mut self) -> _P0_2EFW {
_P0_2EFW { w: self }
}
#[doc = "Bit 3 - Enable falling edge interrupt for P0\\[3\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_3ef(&mut self) -> _P0_3EFW {
_P0_3EFW { w: self }
}
#[doc = "Bit 4 - Enable falling edge interrupt for P0\\[4\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_4ef(&mut self) -> _P0_4EFW {
_P0_4EFW { w: self }
}
#[doc = "Bit 5 - Enable falling edge interrupt for P0\\[5\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_5ef(&mut self) -> _P0_5EFW {
_P0_5EFW { w: self }
}
#[doc = "Bit 6 - Enable falling edge interrupt for P0\\[6\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_6ef(&mut self) -> _P0_6EFW {
_P0_6EFW { w: self }
}
#[doc = "Bit 7 - Enable falling edge interrupt for P0\\[7\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_7ef(&mut self) -> _P0_7EFW {
_P0_7EFW { w: self }
}
#[doc = "Bit 8 - Enable falling edge interrupt for P0\\[8\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_8ef(&mut self) -> _P0_8EFW {
_P0_8EFW { w: self }
}
#[doc = "Bit 9 - Enable falling edge interrupt for P0\\[9\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_9ef(&mut self) -> _P0_9EFW {
_P0_9EFW { w: self }
}
#[doc = "Bit 10 - Enable falling edge interrupt for P0\\[10\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_10ef(&mut self) -> _P0_10EFW {
_P0_10EFW { w: self }
}
#[doc = "Bit 11 - Enable falling edge interrupt for P0\\[11\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_11ef(&mut self) -> _P0_11EFW {
_P0_11EFW { w: self }
}
#[doc = "Bit 12 - Enable falling edge interrupt for P0\\[12\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_12ef(&mut self) -> _P0_12EFW {
_P0_12EFW { w: self }
}
#[doc = "Bit 13 - Enable falling edge interrupt for P0\\[13\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_13ef(&mut self) -> _P0_13EFW {
_P0_13EFW { w: self }
}
#[doc = "Bit 14 - Enable falling edge interrupt for P0\\[14\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_14ef(&mut self) -> _P0_14EFW {
_P0_14EFW { w: self }
}
#[doc = "Bit 15 - Enable falling edge interrupt for P0\\[15\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_15ef(&mut self) -> _P0_15EFW {
_P0_15EFW { w: self }
}
#[doc = "Bit 16 - Enable falling edge interrupt for P0\\[16\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_16ef(&mut self) -> _P0_16EFW {
_P0_16EFW { w: self }
}
#[doc = "Bit 17 - Enable falling edge interrupt for P0\\[17\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_17ef(&mut self) -> _P0_17EFW {
_P0_17EFW { w: self }
}
#[doc = "Bit 18 - Enable falling edge interrupt for P0\\[18\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_18ef(&mut self) -> _P0_18EFW {
_P0_18EFW { w: self }
}
#[doc = "Bit 19 - Enable falling edge interrupt for P0\\[19\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_19ef(&mut self) -> _P0_19EFW {
_P0_19EFW { w: self }
}
#[doc = "Bit 20 - Enable falling edge interrupt for P0\\[20\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_20ef(&mut self) -> _P0_20EFW {
_P0_20EFW { w: self }
}
#[doc = "Bit 21 - Enable falling edge interrupt for P0\\[21\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_21ef(&mut self) -> _P0_21EFW {
_P0_21EFW { w: self }
}
#[doc = "Bit 22 - Enable falling edge interrupt for P0\\[22\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_22ef(&mut self) -> _P0_22EFW {
_P0_22EFW { w: self }
}
#[doc = "Bit 23 - Enable falling edge interrupt for P0\\[23\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_23ef(&mut self) -> _P0_23EFW {
_P0_23EFW { w: self }
}
#[doc = "Bit 24 - Enable falling edge interrupt for P0\\[24\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_24ef(&mut self) -> _P0_24EFW {
_P0_24EFW { w: self }
}
#[doc = "Bit 25 - Enable falling edge interrupt for P0\\[25\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_25ef(&mut self) -> _P0_25EFW {
_P0_25EFW { w: self }
}
#[doc = "Bit 26 - Enable falling edge interrupt for P0\\[26\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_26ef(&mut self) -> _P0_26EFW {
_P0_26EFW { w: self }
}
#[doc = "Bit 27 - Enable falling edge interrupt for P0\\[27\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_27ef(&mut self) -> _P0_27EFW {
_P0_27EFW { w: self }
}
#[doc = "Bit 28 - Enable falling edge interrupt for P0\\[28\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_28ef(&mut self) -> _P0_28EFW {
_P0_28EFW { w: self }
}
#[doc = "Bit 29 - Enable falling edge interrupt for P0\\[29\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_29ef(&mut self) -> _P0_29EFW {
_P0_29EFW { w: self }
}
#[doc = "Bit 30 - Enable falling edge interrupt for P0\\[30\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p0_30ef(&mut self) -> _P0_30EFW {
_P0_30EFW { w: self }
}
}
}
#[doc = "GPIO Interrupt Status for Rising edge for Port 0."]
pub struct STATR2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Status for Rising edge for Port 0."]
pub mod statr2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATR2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct P2_0REIR {
bits: bool,
}
impl P2_0REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_1REIR {
bits: bool,
}
impl P2_1REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_2REIR {
bits: bool,
}
impl P2_2REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_3REIR {
bits: bool,
}
impl P2_3REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_4REIR {
bits: bool,
}
impl P2_4REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_5REIR {
bits: bool,
}
impl P2_5REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_6REIR {
bits: bool,
}
impl P2_6REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_7REIR {
bits: bool,
}
impl P2_7REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_8REIR {
bits: bool,
}
impl P2_8REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_9REIR {
bits: bool,
}
impl P2_9REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_10REIR {
bits: bool,
}
impl P2_10REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_11REIR {
bits: bool,
}
impl P2_11REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_12REIR {
bits: bool,
}
impl P2_12REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_13REIR {
bits: bool,
}
impl P2_13REIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of Rising Edge Interrupt for P2\\[0\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_0rei(&self) -> P2_0REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_0REIR { bits }
}
#[doc = "Bit 1 - Status of Rising Edge Interrupt for P2\\[1\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_1rei(&self) -> P2_1REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_1REIR { bits }
}
#[doc = "Bit 2 - Status of Rising Edge Interrupt for P2\\[2\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_2rei(&self) -> P2_2REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_2REIR { bits }
}
#[doc = "Bit 3 - Status of Rising Edge Interrupt for P2\\[3\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_3rei(&self) -> P2_3REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_3REIR { bits }
}
#[doc = "Bit 4 - Status of Rising Edge Interrupt for P2\\[4\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_4rei(&self) -> P2_4REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_4REIR { bits }
}
#[doc = "Bit 5 - Status of Rising Edge Interrupt for P2\\[5\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_5rei(&self) -> P2_5REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_5REIR { bits }
}
#[doc = "Bit 6 - Status of Rising Edge Interrupt for P2\\[6\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_6rei(&self) -> P2_6REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_6REIR { bits }
}
#[doc = "Bit 7 - Status of Rising Edge Interrupt for P2\\[7\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_7rei(&self) -> P2_7REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_7REIR { bits }
}
#[doc = "Bit 8 - Status of Rising Edge Interrupt for P2\\[8\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_8rei(&self) -> P2_8REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_8REIR { bits }
}
#[doc = "Bit 9 - Status of Rising Edge Interrupt for P2\\[9\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_9rei(&self) -> P2_9REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_9REIR { bits }
}
#[doc = "Bit 10 - Status of Rising Edge Interrupt for P2\\[10\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_10rei(&self) -> P2_10REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_10REIR { bits }
}
#[doc = "Bit 11 - Status of Rising Edge Interrupt for P2\\[11\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_11rei(&self) -> P2_11REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_11REIR { bits }
}
#[doc = "Bit 12 - Status of Rising Edge Interrupt for P2\\[12\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_12rei(&self) -> P2_12REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_12REIR { bits }
}
#[doc = "Bit 13 - Status of Rising Edge Interrupt for P2\\[13\\]. 0 = No rising edge detected. 1 = Rising edge interrupt generated."]
#[inline]
pub fn p2_13rei(&self) -> P2_13REIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_13REIR { bits }
}
}
}
#[doc = "GPIO Interrupt Status for Falling edge for Port 0."]
pub struct STATF2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Status for Falling edge for Port 0."]
pub mod statf2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATF2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct P2_0FEIR {
bits: bool,
}
impl P2_0FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_1FEIR {
bits: bool,
}
impl P2_1FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_2FEIR {
bits: bool,
}
impl P2_2FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_3FEIR {
bits: bool,
}
impl P2_3FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_4FEIR {
bits: bool,
}
impl P2_4FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_5FEIR {
bits: bool,
}
impl P2_5FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_6FEIR {
bits: bool,
}
impl P2_6FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_7FEIR {
bits: bool,
}
impl P2_7FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_8FEIR {
bits: bool,
}
impl P2_8FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_9FEIR {
bits: bool,
}
impl P2_9FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_10FEIR {
bits: bool,
}
impl P2_10FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_11FEIR {
bits: bool,
}
impl P2_11FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_12FEIR {
bits: bool,
}
impl P2_12FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_13FEIR {
bits: bool,
}
impl P2_13FEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of Falling Edge Interrupt for P2\\[0\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_0fei(&self) -> P2_0FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_0FEIR { bits }
}
#[doc = "Bit 1 - Status of Falling Edge Interrupt for P2\\[1\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_1fei(&self) -> P2_1FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_1FEIR { bits }
}
#[doc = "Bit 2 - Status of Falling Edge Interrupt for P2\\[2\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_2fei(&self) -> P2_2FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_2FEIR { bits }
}
#[doc = "Bit 3 - Status of Falling Edge Interrupt for P2\\[3\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_3fei(&self) -> P2_3FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_3FEIR { bits }
}
#[doc = "Bit 4 - Status of Falling Edge Interrupt for P2\\[4\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_4fei(&self) -> P2_4FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_4FEIR { bits }
}
#[doc = "Bit 5 - Status of Falling Edge Interrupt for P2\\[5\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_5fei(&self) -> P2_5FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_5FEIR { bits }
}
#[doc = "Bit 6 - Status of Falling Edge Interrupt for P2\\[6\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_6fei(&self) -> P2_6FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_6FEIR { bits }
}
#[doc = "Bit 7 - Status of Falling Edge Interrupt for P2\\[7\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_7fei(&self) -> P2_7FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_7FEIR { bits }
}
#[doc = "Bit 8 - Status of Falling Edge Interrupt for P2\\[8\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_8fei(&self) -> P2_8FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_8FEIR { bits }
}
#[doc = "Bit 9 - Status of Falling Edge Interrupt for P2\\[9\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_9fei(&self) -> P2_9FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_9FEIR { bits }
}
#[doc = "Bit 10 - Status of Falling Edge Interrupt for P2\\[10\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_10fei(&self) -> P2_10FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_10FEIR { bits }
}
#[doc = "Bit 11 - Status of Falling Edge Interrupt for P2\\[11\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_11fei(&self) -> P2_11FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_11FEIR { bits }
}
#[doc = "Bit 12 - Status of Falling Edge Interrupt for P2\\[12\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_12fei(&self) -> P2_12FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_12FEIR { bits }
}
#[doc = "Bit 13 - Status of Falling Edge Interrupt for P2\\[13\\]. 0 = No falling edge detected. 1 = Falling edge interrupt generated."]
#[inline]
pub fn p2_13fei(&self) -> P2_13FEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_13FEIR { bits }
}
}
}
#[doc = "GPIO Interrupt Clear."]
pub struct CLR2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Clear."]
pub mod clr2 {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLR2 {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _P2_0CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_0CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_1CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_1CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_2CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_2CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_3CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_3CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_4CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_4CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_5CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_5CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_6CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_6CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_7CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_7CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_8CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_8CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_9CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_9CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_10CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_10CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_11CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_11CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_12CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_12CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_13CIW<'a> {
w: &'a mut W,
}
impl<'a> _P2_13CIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clear GPIO port Interrupts for P2\\[0\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_0ci(&mut self) -> _P2_0CIW {
_P2_0CIW { w: self }
}
#[doc = "Bit 1 - Clear GPIO port Interrupts for P2\\[1\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_1ci(&mut self) -> _P2_1CIW {
_P2_1CIW { w: self }
}
#[doc = "Bit 2 - Clear GPIO port Interrupts for P2\\[2\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_2ci(&mut self) -> _P2_2CIW {
_P2_2CIW { w: self }
}
#[doc = "Bit 3 - Clear GPIO port Interrupts for P2\\[3\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_3ci(&mut self) -> _P2_3CIW {
_P2_3CIW { w: self }
}
#[doc = "Bit 4 - Clear GPIO port Interrupts for P2\\[4\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_4ci(&mut self) -> _P2_4CIW {
_P2_4CIW { w: self }
}
#[doc = "Bit 5 - Clear GPIO port Interrupts for P2\\[5\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_5ci(&mut self) -> _P2_5CIW {
_P2_5CIW { w: self }
}
#[doc = "Bit 6 - Clear GPIO port Interrupts for P2\\[6\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_6ci(&mut self) -> _P2_6CIW {
_P2_6CIW { w: self }
}
#[doc = "Bit 7 - Clear GPIO port Interrupts for P2\\[7\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_7ci(&mut self) -> _P2_7CIW {
_P2_7CIW { w: self }
}
#[doc = "Bit 8 - Clear GPIO port Interrupts for P2\\[8\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_8ci(&mut self) -> _P2_8CIW {
_P2_8CIW { w: self }
}
#[doc = "Bit 9 - Clear GPIO port Interrupts for P2\\[9\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_9ci(&mut self) -> _P2_9CIW {
_P2_9CIW { w: self }
}
#[doc = "Bit 10 - Clear GPIO port Interrupts for P2\\[10\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_10ci(&mut self) -> _P2_10CIW {
_P2_10CIW { w: self }
}
#[doc = "Bit 11 - Clear GPIO port Interrupts for P2\\[11\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_11ci(&mut self) -> _P2_11CIW {
_P2_11CIW { w: self }
}
#[doc = "Bit 12 - Clear GPIO port Interrupts for P2\\[12\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_12ci(&mut self) -> _P2_12CIW {
_P2_12CIW { w: self }
}
#[doc = "Bit 13 - Clear GPIO port Interrupts for P2\\[13\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
#[inline]
pub fn p2_13ci(&mut self) -> _P2_13CIW {
_P2_13CIW { w: self }
}
}
}
#[doc = "GPIO Interrupt Enable for Rising edge for Port 0."]
pub struct ENR2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Enable for Rising edge for Port 0."]
pub mod enr2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ENR2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct P2_0ERR {
bits: bool,
}
impl P2_0ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_1ERR {
bits: bool,
}
impl P2_1ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_2ERR {
bits: bool,
}
impl P2_2ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_3ERR {
bits: bool,
}
impl P2_3ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_4ERR {
bits: bool,
}
impl P2_4ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_5ERR {
bits: bool,
}
impl P2_5ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_6ERR {
bits: bool,
}
impl P2_6ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_7ERR {
bits: bool,
}
impl P2_7ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_8ERR {
bits: bool,
}
impl P2_8ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_9ERR {
bits: bool,
}
impl P2_9ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_10ERR {
bits: bool,
}
impl P2_10ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_11ERR {
bits: bool,
}
impl P2_11ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_12ERR {
bits: bool,
}
impl P2_12ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_13ERR {
bits: bool,
}
impl P2_13ERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _P2_0ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_0ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_1ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_1ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_2ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_2ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_3ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_3ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_4ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_4ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_5ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_5ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_6ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_6ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_7ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_7ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_8ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_8ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_9ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_9ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_10ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_10ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_11ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_11ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_12ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_12ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_13ERW<'a> {
w: &'a mut W,
}
impl<'a> _P2_13ERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable rising edge interrupt for P2\\[0\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_0er(&self) -> P2_0ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_0ERR { bits }
}
#[doc = "Bit 1 - Enable rising edge interrupt for P2\\[1\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_1er(&self) -> P2_1ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_1ERR { bits }
}
#[doc = "Bit 2 - Enable rising edge interrupt for P2\\[2\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_2er(&self) -> P2_2ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_2ERR { bits }
}
#[doc = "Bit 3 - Enable rising edge interrupt for P2\\[3\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_3er(&self) -> P2_3ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_3ERR { bits }
}
#[doc = "Bit 4 - Enable rising edge interrupt for P2\\[4\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_4er(&self) -> P2_4ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_4ERR { bits }
}
#[doc = "Bit 5 - Enable rising edge interrupt for P2\\[5\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_5er(&self) -> P2_5ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_5ERR { bits }
}
#[doc = "Bit 6 - Enable rising edge interrupt for P2\\[6\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_6er(&self) -> P2_6ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_6ERR { bits }
}
#[doc = "Bit 7 - Enable rising edge interrupt for P2\\[7\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_7er(&self) -> P2_7ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_7ERR { bits }
}
#[doc = "Bit 8 - Enable rising edge interrupt for P2\\[8\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_8er(&self) -> P2_8ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_8ERR { bits }
}
#[doc = "Bit 9 - Enable rising edge interrupt for P2\\[9\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_9er(&self) -> P2_9ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_9ERR { bits }
}
#[doc = "Bit 10 - Enable rising edge interrupt for P2\\[10\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_10er(&self) -> P2_10ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_10ERR { bits }
}
#[doc = "Bit 11 - Enable rising edge interrupt for P2\\[11\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_11er(&self) -> P2_11ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_11ERR { bits }
}
#[doc = "Bit 12 - Enable rising edge interrupt for P2\\[12\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_12er(&self) -> P2_12ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_12ERR { bits }
}
#[doc = "Bit 13 - Enable rising edge interrupt for P2\\[13\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_13er(&self) -> P2_13ERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_13ERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable rising edge interrupt for P2\\[0\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_0er(&mut self) -> _P2_0ERW {
_P2_0ERW { w: self }
}
#[doc = "Bit 1 - Enable rising edge interrupt for P2\\[1\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_1er(&mut self) -> _P2_1ERW {
_P2_1ERW { w: self }
}
#[doc = "Bit 2 - Enable rising edge interrupt for P2\\[2\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_2er(&mut self) -> _P2_2ERW {
_P2_2ERW { w: self }
}
#[doc = "Bit 3 - Enable rising edge interrupt for P2\\[3\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_3er(&mut self) -> _P2_3ERW {
_P2_3ERW { w: self }
}
#[doc = "Bit 4 - Enable rising edge interrupt for P2\\[4\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_4er(&mut self) -> _P2_4ERW {
_P2_4ERW { w: self }
}
#[doc = "Bit 5 - Enable rising edge interrupt for P2\\[5\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_5er(&mut self) -> _P2_5ERW {
_P2_5ERW { w: self }
}
#[doc = "Bit 6 - Enable rising edge interrupt for P2\\[6\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_6er(&mut self) -> _P2_6ERW {
_P2_6ERW { w: self }
}
#[doc = "Bit 7 - Enable rising edge interrupt for P2\\[7\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_7er(&mut self) -> _P2_7ERW {
_P2_7ERW { w: self }
}
#[doc = "Bit 8 - Enable rising edge interrupt for P2\\[8\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_8er(&mut self) -> _P2_8ERW {
_P2_8ERW { w: self }
}
#[doc = "Bit 9 - Enable rising edge interrupt for P2\\[9\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_9er(&mut self) -> _P2_9ERW {
_P2_9ERW { w: self }
}
#[doc = "Bit 10 - Enable rising edge interrupt for P2\\[10\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_10er(&mut self) -> _P2_10ERW {
_P2_10ERW { w: self }
}
#[doc = "Bit 11 - Enable rising edge interrupt for P2\\[11\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_11er(&mut self) -> _P2_11ERW {
_P2_11ERW { w: self }
}
#[doc = "Bit 12 - Enable rising edge interrupt for P2\\[12\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_12er(&mut self) -> _P2_12ERW {
_P2_12ERW { w: self }
}
#[doc = "Bit 13 - Enable rising edge interrupt for P2\\[13\\]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt."]
#[inline]
pub fn p2_13er(&mut self) -> _P2_13ERW {
_P2_13ERW { w: self }
}
}
}
#[doc = "GPIO Interrupt Enable for Falling edge for Port 0."]
pub struct ENF2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Interrupt Enable for Falling edge for Port 0."]
pub mod enf2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ENF2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct P2_0EFR {
bits: bool,
}
impl P2_0EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_1EFR {
bits: bool,
}
impl P2_1EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_2EFR {
bits: bool,
}
impl P2_2EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_3EFR {
bits: bool,
}
impl P2_3EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_4EFR {
bits: bool,
}
impl P2_4EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_5EFR {
bits: bool,
}
impl P2_5EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_6EFR {
bits: bool,
}
impl P2_6EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_7EFR {
bits: bool,
}
impl P2_7EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_8EFR {
bits: bool,
}
impl P2_8EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_9EFR {
bits: bool,
}
impl P2_9EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_10EFR {
bits: bool,
}
impl P2_10EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_11EFR {
bits: bool,
}
impl P2_11EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_12EFR {
bits: bool,
}
impl P2_12EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct P2_13EFR {
bits: bool,
}
impl P2_13EFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _P2_0EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_0EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_1EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_1EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_2EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_2EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_3EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_3EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_4EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_4EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_5EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_5EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_6EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_6EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_7EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_7EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_8EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_8EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_9EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_9EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_10EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_10EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_11EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_11EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_12EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_12EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P2_13EFW<'a> {
w: &'a mut W,
}
impl<'a> _P2_13EFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable falling edge interrupt for P2\\[0\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_0ef(&self) -> P2_0EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_0EFR { bits }
}
#[doc = "Bit 1 - Enable falling edge interrupt for P2\\[1\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_1ef(&self) -> P2_1EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_1EFR { bits }
}
#[doc = "Bit 2 - Enable falling edge interrupt for P2\\[2\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_2ef(&self) -> P2_2EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_2EFR { bits }
}
#[doc = "Bit 3 - Enable falling edge interrupt for P2\\[3\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_3ef(&self) -> P2_3EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_3EFR { bits }
}
#[doc = "Bit 4 - Enable falling edge interrupt for P2\\[4\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_4ef(&self) -> P2_4EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_4EFR { bits }
}
#[doc = "Bit 5 - Enable falling edge interrupt for P2\\[5\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_5ef(&self) -> P2_5EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_5EFR { bits }
}
#[doc = "Bit 6 - Enable falling edge interrupt for P2\\[6\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_6ef(&self) -> P2_6EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_6EFR { bits }
}
#[doc = "Bit 7 - Enable falling edge interrupt for P2\\[7\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_7ef(&self) -> P2_7EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_7EFR { bits }
}
#[doc = "Bit 8 - Enable falling edge interrupt for P2\\[8\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_8ef(&self) -> P2_8EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_8EFR { bits }
}
#[doc = "Bit 9 - Enable falling edge interrupt for P2\\[9\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_9ef(&self) -> P2_9EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_9EFR { bits }
}
#[doc = "Bit 10 - Enable falling edge interrupt for P2\\[10\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_10ef(&self) -> P2_10EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_10EFR { bits }
}
#[doc = "Bit 11 - Enable falling edge interrupt for P2\\[11\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_11ef(&self) -> P2_11EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_11EFR { bits }
}
#[doc = "Bit 12 - Enable falling edge interrupt for P2\\[12\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_12ef(&self) -> P2_12EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_12EFR { bits }
}
#[doc = "Bit 13 - Enable falling edge interrupt for P2\\[13\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_13ef(&self) -> P2_13EFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P2_13EFR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable falling edge interrupt for P2\\[0\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_0ef(&mut self) -> _P2_0EFW {
_P2_0EFW { w: self }
}
#[doc = "Bit 1 - Enable falling edge interrupt for P2\\[1\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_1ef(&mut self) -> _P2_1EFW {
_P2_1EFW { w: self }
}
#[doc = "Bit 2 - Enable falling edge interrupt for P2\\[2\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_2ef(&mut self) -> _P2_2EFW {
_P2_2EFW { w: self }
}
#[doc = "Bit 3 - Enable falling edge interrupt for P2\\[3\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_3ef(&mut self) -> _P2_3EFW {
_P2_3EFW { w: self }
}
#[doc = "Bit 4 - Enable falling edge interrupt for P2\\[4\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_4ef(&mut self) -> _P2_4EFW {
_P2_4EFW { w: self }
}
#[doc = "Bit 5 - Enable falling edge interrupt for P2\\[5\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_5ef(&mut self) -> _P2_5EFW {
_P2_5EFW { w: self }
}
#[doc = "Bit 6 - Enable falling edge interrupt for P2\\[6\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_6ef(&mut self) -> _P2_6EFW {
_P2_6EFW { w: self }
}
#[doc = "Bit 7 - Enable falling edge interrupt for P2\\[7\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_7ef(&mut self) -> _P2_7EFW {
_P2_7EFW { w: self }
}
#[doc = "Bit 8 - Enable falling edge interrupt for P2\\[8\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_8ef(&mut self) -> _P2_8EFW {
_P2_8EFW { w: self }
}
#[doc = "Bit 9 - Enable falling edge interrupt for P2\\[9\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_9ef(&mut self) -> _P2_9EFW {
_P2_9EFW { w: self }
}
#[doc = "Bit 10 - Enable falling edge interrupt for P2\\[10\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_10ef(&mut self) -> _P2_10EFW {
_P2_10EFW { w: self }
}
#[doc = "Bit 11 - Enable falling edge interrupt for P2\\[11\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_11ef(&mut self) -> _P2_11EFW {
_P2_11EFW { w: self }
}
#[doc = "Bit 12 - Enable falling edge interrupt for P2\\[12\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_12ef(&mut self) -> _P2_12EFW {
_P2_12EFW { w: self }
}
#[doc = "Bit 13 - Enable falling edge interrupt for P2\\[13\\]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt."]
#[inline]
pub fn p2_13ef(&mut self) -> _P2_13EFW {
_P2_13EFW { w: self }
}
}
}
}
#[doc = "Pin connect block"]
pub struct PINCONNECT {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for PINCONNECT {}
impl PINCONNECT {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const pinconnect::RegisterBlock {
0x4002_c000 as *const _
}
}
impl Deref for PINCONNECT {
type Target = pinconnect::RegisterBlock;
fn deref(&self) -> &pinconnect::RegisterBlock {
unsafe { &*PINCONNECT::ptr() }
}
}
#[doc = "Pin connect block"]
pub mod pinconnect {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Pin function select register 0."]
pub pinsel0: PINSEL0,
#[doc = "0x04 - Pin function select register 1."]
pub pinsel1: PINSEL1,
#[doc = "0x08 - Pin function select register 2."]
pub pinsel2: PINSEL2,
#[doc = "0x0c - Pin function select register 3."]
pub pinsel3: PINSEL3,
#[doc = "0x10 - Pin function select register 4"]
pub pinsel4: PINSEL4,
_reserved5: [u8; 8usize],
#[doc = "0x1c - Pin function select register 7"]
pub pinsel7: PINSEL7,
_reserved6: [u8; 4usize],
#[doc = "0x24 - Pin function select register 9"]
pub pinsel9: PINSEL9,
#[doc = "0x28 - Pin function select register 10"]
pub pinsel10: PINSEL10,
_reserved8: [u8; 20usize],
#[doc = "0x40 - Pin mode select register 0"]
pub pinmode0: PINMODE0,
#[doc = "0x44 - Pin mode select register 1"]
pub pinmode1: PINMODE1,
#[doc = "0x48 - Pin mode select register 2"]
pub pinmode2: PINMODE2,
#[doc = "0x4c - Pin mode select register 3."]
pub pinmode3: PINMODE3,
#[doc = "0x50 - Pin mode select register 4"]
pub pinmode4: PINMODE4,
_reserved13: [u8; 8usize],
#[doc = "0x5c - Pin mode select register 7"]
pub pinmode7: PINMODE7,
_reserved14: [u8; 4usize],
#[doc = "0x64 - Pin mode select register 9"]
pub pinmode9: PINMODE9,
#[doc = "0x68 - Open drain mode control register 0"]
pub pinmode_od0: PINMODE_OD0,
#[doc = "0x6c - Open drain mode control register 1"]
pub pinmode_od1: PINMODE_OD1,
#[doc = "0x70 - Open drain mode control register 2"]
pub pinmode_od2: PINMODE_OD2,
#[doc = "0x74 - Open drain mode control register 3"]
pub pinmode_od3: PINMODE_OD3,
#[doc = "0x78 - Open drain mode control register 4"]
pub pinmode_od4: PINMODE_OD4,
#[doc = "0x7c - I2C Pin Configuration register"]
pub i2cpadcfg: I2CPADCFG,
}
#[doc = "Pin function select register 0."]
pub struct PINSEL0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 0."]
pub mod pinsel0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P0_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_0R {
#[doc = "GPIO P0.0"]
GPIO_P0,
#[doc = "RD1"]
RD1,
#[doc = "TXD3"]
TXD3,
#[doc = "SDA1"]
SDA1,
}
impl P0_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_0R::GPIO_P0 => 0,
P0_0R::RD1 => 0x01,
P0_0R::TXD3 => 0x02,
P0_0R::SDA1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_0R {
match value {
0 => P0_0R::GPIO_P0,
1 => P0_0R::RD1,
2 => P0_0R::TXD3,
3 => P0_0R::SDA1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_0R::GPIO_P0
}
#[doc = "Checks if the value of the field is `RD1`"]
#[inline]
pub fn is_rd1(&self) -> bool {
*self == P0_0R::RD1
}
#[doc = "Checks if the value of the field is `TXD3`"]
#[inline]
pub fn is_txd3(&self) -> bool {
*self == P0_0R::TXD3
}
#[doc = "Checks if the value of the field is `SDA1`"]
#[inline]
pub fn is_sda1(&self) -> bool {
*self == P0_0R::SDA1
}
}
#[doc = "Possible values of the field `P0_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_1R {
#[doc = "GPIO P0.1"]
GPIO_P0,
#[doc = "TD1"]
TD1,
#[doc = "RXD3"]
RXD3,
#[doc = "SCL1"]
SCL1,
}
impl P0_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_1R::GPIO_P0 => 0,
P0_1R::TD1 => 0x01,
P0_1R::RXD3 => 0x02,
P0_1R::SCL1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_1R {
match value {
0 => P0_1R::GPIO_P0,
1 => P0_1R::TD1,
2 => P0_1R::RXD3,
3 => P0_1R::SCL1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_1R::GPIO_P0
}
#[doc = "Checks if the value of the field is `TD1`"]
#[inline]
pub fn is_td1(&self) -> bool {
*self == P0_1R::TD1
}
#[doc = "Checks if the value of the field is `RXD3`"]
#[inline]
pub fn is_rxd3(&self) -> bool {
*self == P0_1R::RXD3
}
#[doc = "Checks if the value of the field is `SCL1`"]
#[inline]
pub fn is_scl1(&self) -> bool {
*self == P0_1R::SCL1
}
}
#[doc = "Possible values of the field `P0_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_2R {
#[doc = "GPIO P0.2"]
GPIO_P0,
#[doc = "TXD0"]
TXD0,
#[doc = "AD0.7"]
AD0,
}
impl P0_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_2R::GPIO_P0 => 0,
P0_2R::TXD0 => 0x01,
P0_2R::AD0 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_2R {
match value {
0 => P0_2R::GPIO_P0,
1 => P0_2R::TXD0,
2 => P0_2R::AD0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_2R::GPIO_P0
}
#[doc = "Checks if the value of the field is `TXD0`"]
#[inline]
pub fn is_txd0(&self) -> bool {
*self == P0_2R::TXD0
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P0_2R::AD0
}
}
#[doc = "Possible values of the field `P0_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_3R {
#[doc = "GPIO P0.3."]
GPIO_P0,
#[doc = "RXD0"]
RXD0,
#[doc = "AD0.6"]
AD0,
}
impl P0_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_3R::GPIO_P0 => 0,
P0_3R::RXD0 => 0x01,
P0_3R::AD0 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_3R {
match value {
0 => P0_3R::GPIO_P0,
1 => P0_3R::RXD0,
2 => P0_3R::AD0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_3R::GPIO_P0
}
#[doc = "Checks if the value of the field is `RXD0`"]
#[inline]
pub fn is_rxd0(&self) -> bool {
*self == P0_3R::RXD0
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P0_3R::AD0
}
}
#[doc = "Possible values of the field `P0_4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_4R {
#[doc = "GPIO P0.4."]
GPIO_P0,
#[doc = "I2SRX_CLK"]
I2SRX_CLK,
#[doc = "RD2"]
RD2,
#[doc = "CAP2.0"]
CAP2,
}
impl P0_4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_4R::GPIO_P0 => 0,
P0_4R::I2SRX_CLK => 0x01,
P0_4R::RD2 => 0x02,
P0_4R::CAP2 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_4R {
match value {
0 => P0_4R::GPIO_P0,
1 => P0_4R::I2SRX_CLK,
2 => P0_4R::RD2,
3 => P0_4R::CAP2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_4R::GPIO_P0
}
#[doc = "Checks if the value of the field is `I2SRX_CLK`"]
#[inline]
pub fn is_i2srx_clk(&self) -> bool {
*self == P0_4R::I2SRX_CLK
}
#[doc = "Checks if the value of the field is `RD2`"]
#[inline]
pub fn is_rd2(&self) -> bool {
*self == P0_4R::RD2
}
#[doc = "Checks if the value of the field is `CAP2`"]
#[inline]
pub fn is_cap2(&self) -> bool {
*self == P0_4R::CAP2
}
}
#[doc = "Possible values of the field `P0_5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_5R {
#[doc = "GPIO P0.5."]
GPIO_P0,
#[doc = "I2SRX_WS"]
I2SRX_WS,
#[doc = "TD2"]
TD2,
#[doc = "CAP2.1"]
CAP2,
}
impl P0_5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_5R::GPIO_P0 => 0,
P0_5R::I2SRX_WS => 0x01,
P0_5R::TD2 => 0x02,
P0_5R::CAP2 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_5R {
match value {
0 => P0_5R::GPIO_P0,
1 => P0_5R::I2SRX_WS,
2 => P0_5R::TD2,
3 => P0_5R::CAP2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_5R::GPIO_P0
}
#[doc = "Checks if the value of the field is `I2SRX_WS`"]
#[inline]
pub fn is_i2srx_ws(&self) -> bool {
*self == P0_5R::I2SRX_WS
}
#[doc = "Checks if the value of the field is `TD2`"]
#[inline]
pub fn is_td2(&self) -> bool {
*self == P0_5R::TD2
}
#[doc = "Checks if the value of the field is `CAP2`"]
#[inline]
pub fn is_cap2(&self) -> bool {
*self == P0_5R::CAP2
}
}
#[doc = "Possible values of the field `P0_6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_6R {
#[doc = "GPIO P0.6."]
GPIO_P0,
#[doc = "I2SRX_SDA"]
I2SRX_SDA,
#[doc = "SSEL1"]
SSEL1,
#[doc = "MAT2.0"]
MAT2,
}
impl P0_6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_6R::GPIO_P0 => 0,
P0_6R::I2SRX_SDA => 0x01,
P0_6R::SSEL1 => 0x02,
P0_6R::MAT2 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_6R {
match value {
0 => P0_6R::GPIO_P0,
1 => P0_6R::I2SRX_SDA,
2 => P0_6R::SSEL1,
3 => P0_6R::MAT2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_6R::GPIO_P0
}
#[doc = "Checks if the value of the field is `I2SRX_SDA`"]
#[inline]
pub fn is_i2srx_sda(&self) -> bool {
*self == P0_6R::I2SRX_SDA
}
#[doc = "Checks if the value of the field is `SSEL1`"]
#[inline]
pub fn is_ssel1(&self) -> bool {
*self == P0_6R::SSEL1
}
#[doc = "Checks if the value of the field is `MAT2`"]
#[inline]
pub fn is_mat2(&self) -> bool {
*self == P0_6R::MAT2
}
}
#[doc = "Possible values of the field `P0_7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_7R {
#[doc = "GPIO P0.7."]
GPIO_P0,
#[doc = "I2STX_CLK"]
I2STX_CLK,
#[doc = "SCK1"]
SCK1,
#[doc = "MAT2.1"]
MAT2,
}
impl P0_7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_7R::GPIO_P0 => 0,
P0_7R::I2STX_CLK => 0x01,
P0_7R::SCK1 => 0x02,
P0_7R::MAT2 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_7R {
match value {
0 => P0_7R::GPIO_P0,
1 => P0_7R::I2STX_CLK,
2 => P0_7R::SCK1,
3 => P0_7R::MAT2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_7R::GPIO_P0
}
#[doc = "Checks if the value of the field is `I2STX_CLK`"]
#[inline]
pub fn is_i2stx_clk(&self) -> bool {
*self == P0_7R::I2STX_CLK
}
#[doc = "Checks if the value of the field is `SCK1`"]
#[inline]
pub fn is_sck1(&self) -> bool {
*self == P0_7R::SCK1
}
#[doc = "Checks if the value of the field is `MAT2`"]
#[inline]
pub fn is_mat2(&self) -> bool {
*self == P0_7R::MAT2
}
}
#[doc = "Possible values of the field `P0_8`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_8R {
#[doc = "GPIO P0.8."]
GPIO_P0,
#[doc = "I2STX_WS"]
I2STX_WS,
#[doc = "MISO1"]
MISO1,
#[doc = "MAT2.2"]
MAT2,
}
impl P0_8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_8R::GPIO_P0 => 0,
P0_8R::I2STX_WS => 0x01,
P0_8R::MISO1 => 0x02,
P0_8R::MAT2 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_8R {
match value {
0 => P0_8R::GPIO_P0,
1 => P0_8R::I2STX_WS,
2 => P0_8R::MISO1,
3 => P0_8R::MAT2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_8R::GPIO_P0
}
#[doc = "Checks if the value of the field is `I2STX_WS`"]
#[inline]
pub fn is_i2stx_ws(&self) -> bool {
*self == P0_8R::I2STX_WS
}
#[doc = "Checks if the value of the field is `MISO1`"]
#[inline]
pub fn is_miso1(&self) -> bool {
*self == P0_8R::MISO1
}
#[doc = "Checks if the value of the field is `MAT2`"]
#[inline]
pub fn is_mat2(&self) -> bool {
*self == P0_8R::MAT2
}
}
#[doc = "Possible values of the field `P0_9`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_9R {
#[doc = "GPIO P0.9"]
GPIO_P0,
#[doc = "I2STX_SDA"]
I2STX_SDA,
#[doc = "MOSI1"]
MOSI1,
#[doc = "MAT2.3"]
MAT2,
}
impl P0_9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_9R::GPIO_P0 => 0,
P0_9R::I2STX_SDA => 0x01,
P0_9R::MOSI1 => 0x02,
P0_9R::MAT2 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_9R {
match value {
0 => P0_9R::GPIO_P0,
1 => P0_9R::I2STX_SDA,
2 => P0_9R::MOSI1,
3 => P0_9R::MAT2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_9R::GPIO_P0
}
#[doc = "Checks if the value of the field is `I2STX_SDA`"]
#[inline]
pub fn is_i2stx_sda(&self) -> bool {
*self == P0_9R::I2STX_SDA
}
#[doc = "Checks if the value of the field is `MOSI1`"]
#[inline]
pub fn is_mosi1(&self) -> bool {
*self == P0_9R::MOSI1
}
#[doc = "Checks if the value of the field is `MAT2`"]
#[inline]
pub fn is_mat2(&self) -> bool {
*self == P0_9R::MAT2
}
}
#[doc = "Possible values of the field `P0_10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_10R {
#[doc = "GPIO P0.10"]
GPIO_P0,
#[doc = "TXD2"]
TXD2,
#[doc = "SDA2"]
SDA2,
#[doc = "MAT3.0"]
MAT3,
}
impl P0_10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_10R::GPIO_P0 => 0,
P0_10R::TXD2 => 0x01,
P0_10R::SDA2 => 0x02,
P0_10R::MAT3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_10R {
match value {
0 => P0_10R::GPIO_P0,
1 => P0_10R::TXD2,
2 => P0_10R::SDA2,
3 => P0_10R::MAT3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_10R::GPIO_P0
}
#[doc = "Checks if the value of the field is `TXD2`"]
#[inline]
pub fn is_txd2(&self) -> bool {
*self == P0_10R::TXD2
}
#[doc = "Checks if the value of the field is `SDA2`"]
#[inline]
pub fn is_sda2(&self) -> bool {
*self == P0_10R::SDA2
}
#[doc = "Checks if the value of the field is `MAT3`"]
#[inline]
pub fn is_mat3(&self) -> bool {
*self == P0_10R::MAT3
}
}
#[doc = "Possible values of the field `P0_11`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_11R {
#[doc = "GPIO P0.11"]
GPIO_P0,
#[doc = "RXD2"]
RXD2,
#[doc = "SCL2"]
SCL2,
#[doc = "MAT3.1"]
MAT3,
}
impl P0_11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_11R::GPIO_P0 => 0,
P0_11R::RXD2 => 0x01,
P0_11R::SCL2 => 0x02,
P0_11R::MAT3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_11R {
match value {
0 => P0_11R::GPIO_P0,
1 => P0_11R::RXD2,
2 => P0_11R::SCL2,
3 => P0_11R::MAT3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_11R::GPIO_P0
}
#[doc = "Checks if the value of the field is `RXD2`"]
#[inline]
pub fn is_rxd2(&self) -> bool {
*self == P0_11R::RXD2
}
#[doc = "Checks if the value of the field is `SCL2`"]
#[inline]
pub fn is_scl2(&self) -> bool {
*self == P0_11R::SCL2
}
#[doc = "Checks if the value of the field is `MAT3`"]
#[inline]
pub fn is_mat3(&self) -> bool {
*self == P0_11R::MAT3
}
}
#[doc = "Possible values of the field `P0_15`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_15R {
#[doc = "GPIO P0.15"]
GPIO_P0,
#[doc = "TXD1"]
TXD1,
#[doc = "SCK0"]
SCK0,
#[doc = "SCK"]
SCK,
}
impl P0_15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_15R::GPIO_P0 => 0,
P0_15R::TXD1 => 0x01,
P0_15R::SCK0 => 0x02,
P0_15R::SCK => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_15R {
match value {
0 => P0_15R::GPIO_P0,
1 => P0_15R::TXD1,
2 => P0_15R::SCK0,
3 => P0_15R::SCK,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_15R::GPIO_P0
}
#[doc = "Checks if the value of the field is `TXD1`"]
#[inline]
pub fn is_txd1(&self) -> bool {
*self == P0_15R::TXD1
}
#[doc = "Checks if the value of the field is `SCK0`"]
#[inline]
pub fn is_sck0(&self) -> bool {
*self == P0_15R::SCK0
}
#[doc = "Checks if the value of the field is `SCK`"]
#[inline]
pub fn is_sck(&self) -> bool {
*self == P0_15R::SCK
}
}
#[doc = "Values that can be written to the field `P0_0`"]
pub enum P0_0W {
#[doc = "GPIO P0.0"]
GPIO_P0,
#[doc = "RD1"]
RD1,
#[doc = "TXD3"]
TXD3,
#[doc = "SDA1"]
SDA1,
}
impl P0_0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_0W::GPIO_P0 => 0,
P0_0W::RD1 => 1,
P0_0W::TXD3 => 2,
P0_0W::SDA1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_0W<'a> {
w: &'a mut W,
}
impl<'a> _P0_0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.0"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_0W::GPIO_P0)
}
#[doc = "RD1"]
#[inline]
pub fn rd1(self) -> &'a mut W {
self.variant(P0_0W::RD1)
}
#[doc = "TXD3"]
#[inline]
pub fn txd3(self) -> &'a mut W {
self.variant(P0_0W::TXD3)
}
#[doc = "SDA1"]
#[inline]
pub fn sda1(self) -> &'a mut W {
self.variant(P0_0W::SDA1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_1`"]
pub enum P0_1W {
#[doc = "GPIO P0.1"]
GPIO_P0,
#[doc = "TD1"]
TD1,
#[doc = "RXD3"]
RXD3,
#[doc = "SCL1"]
SCL1,
}
impl P0_1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_1W::GPIO_P0 => 0,
P0_1W::TD1 => 1,
P0_1W::RXD3 => 2,
P0_1W::SCL1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_1W<'a> {
w: &'a mut W,
}
impl<'a> _P0_1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.1"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_1W::GPIO_P0)
}
#[doc = "TD1"]
#[inline]
pub fn td1(self) -> &'a mut W {
self.variant(P0_1W::TD1)
}
#[doc = "RXD3"]
#[inline]
pub fn rxd3(self) -> &'a mut W {
self.variant(P0_1W::RXD3)
}
#[doc = "SCL1"]
#[inline]
pub fn scl1(self) -> &'a mut W {
self.variant(P0_1W::SCL1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_2`"]
pub enum P0_2W {
#[doc = "GPIO P0.2"]
GPIO_P0,
#[doc = "TXD0"]
TXD0,
#[doc = "AD0.7"]
AD0,
}
impl P0_2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_2W::GPIO_P0 => 0,
P0_2W::TXD0 => 1,
P0_2W::AD0 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_2W<'a> {
w: &'a mut W,
}
impl<'a> _P0_2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_2W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.2"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_2W::GPIO_P0)
}
#[doc = "TXD0"]
#[inline]
pub fn txd0(self) -> &'a mut W {
self.variant(P0_2W::TXD0)
}
#[doc = "AD0.7"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P0_2W::AD0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_3`"]
pub enum P0_3W {
#[doc = "GPIO P0.3."]
GPIO_P0,
#[doc = "RXD0"]
RXD0,
#[doc = "AD0.6"]
AD0,
}
impl P0_3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_3W::GPIO_P0 => 0,
P0_3W::RXD0 => 1,
P0_3W::AD0 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_3W<'a> {
w: &'a mut W,
}
impl<'a> _P0_3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_3W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.3."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_3W::GPIO_P0)
}
#[doc = "RXD0"]
#[inline]
pub fn rxd0(self) -> &'a mut W {
self.variant(P0_3W::RXD0)
}
#[doc = "AD0.6"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P0_3W::AD0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_4`"]
pub enum P0_4W {
#[doc = "GPIO P0.4."]
GPIO_P0,
#[doc = "I2SRX_CLK"]
I2SRX_CLK,
#[doc = "RD2"]
RD2,
#[doc = "CAP2.0"]
CAP2,
}
impl P0_4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_4W::GPIO_P0 => 0,
P0_4W::I2SRX_CLK => 1,
P0_4W::RD2 => 2,
P0_4W::CAP2 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_4W<'a> {
w: &'a mut W,
}
impl<'a> _P0_4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_4W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.4."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_4W::GPIO_P0)
}
#[doc = "I2SRX_CLK"]
#[inline]
pub fn i2srx_clk(self) -> &'a mut W {
self.variant(P0_4W::I2SRX_CLK)
}
#[doc = "RD2"]
#[inline]
pub fn rd2(self) -> &'a mut W {
self.variant(P0_4W::RD2)
}
#[doc = "CAP2.0"]
#[inline]
pub fn cap2(self) -> &'a mut W {
self.variant(P0_4W::CAP2)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_5`"]
pub enum P0_5W {
#[doc = "GPIO P0.5."]
GPIO_P0,
#[doc = "I2SRX_WS"]
I2SRX_WS,
#[doc = "TD2"]
TD2,
#[doc = "CAP2.1"]
CAP2,
}
impl P0_5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_5W::GPIO_P0 => 0,
P0_5W::I2SRX_WS => 1,
P0_5W::TD2 => 2,
P0_5W::CAP2 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_5W<'a> {
w: &'a mut W,
}
impl<'a> _P0_5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_5W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.5."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_5W::GPIO_P0)
}
#[doc = "I2SRX_WS"]
#[inline]
pub fn i2srx_ws(self) -> &'a mut W {
self.variant(P0_5W::I2SRX_WS)
}
#[doc = "TD2"]
#[inline]
pub fn td2(self) -> &'a mut W {
self.variant(P0_5W::TD2)
}
#[doc = "CAP2.1"]
#[inline]
pub fn cap2(self) -> &'a mut W {
self.variant(P0_5W::CAP2)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_6`"]
pub enum P0_6W {
#[doc = "GPIO P0.6."]
GPIO_P0,
#[doc = "I2SRX_SDA"]
I2SRX_SDA,
#[doc = "SSEL1"]
SSEL1,
#[doc = "MAT2.0"]
MAT2,
}
impl P0_6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_6W::GPIO_P0 => 0,
P0_6W::I2SRX_SDA => 1,
P0_6W::SSEL1 => 2,
P0_6W::MAT2 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_6W<'a> {
w: &'a mut W,
}
impl<'a> _P0_6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_6W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.6."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_6W::GPIO_P0)
}
#[doc = "I2SRX_SDA"]
#[inline]
pub fn i2srx_sda(self) -> &'a mut W {
self.variant(P0_6W::I2SRX_SDA)
}
#[doc = "SSEL1"]
#[inline]
pub fn ssel1(self) -> &'a mut W {
self.variant(P0_6W::SSEL1)
}
#[doc = "MAT2.0"]
#[inline]
pub fn mat2(self) -> &'a mut W {
self.variant(P0_6W::MAT2)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_7`"]
pub enum P0_7W {
#[doc = "GPIO P0.7."]
GPIO_P0,
#[doc = "I2STX_CLK"]
I2STX_CLK,
#[doc = "SCK1"]
SCK1,
#[doc = "MAT2.1"]
MAT2,
}
impl P0_7W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_7W::GPIO_P0 => 0,
P0_7W::I2STX_CLK => 1,
P0_7W::SCK1 => 2,
P0_7W::MAT2 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_7W<'a> {
w: &'a mut W,
}
impl<'a> _P0_7W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_7W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.7."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_7W::GPIO_P0)
}
#[doc = "I2STX_CLK"]
#[inline]
pub fn i2stx_clk(self) -> &'a mut W {
self.variant(P0_7W::I2STX_CLK)
}
#[doc = "SCK1"]
#[inline]
pub fn sck1(self) -> &'a mut W {
self.variant(P0_7W::SCK1)
}
#[doc = "MAT2.1"]
#[inline]
pub fn mat2(self) -> &'a mut W {
self.variant(P0_7W::MAT2)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_8`"]
pub enum P0_8W {
#[doc = "GPIO P0.8."]
GPIO_P0,
#[doc = "I2STX_WS"]
I2STX_WS,
#[doc = "MISO1"]
MISO1,
#[doc = "MAT2.2"]
MAT2,
}
impl P0_8W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_8W::GPIO_P0 => 0,
P0_8W::I2STX_WS => 1,
P0_8W::MISO1 => 2,
P0_8W::MAT2 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_8W<'a> {
w: &'a mut W,
}
impl<'a> _P0_8W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_8W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.8."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_8W::GPIO_P0)
}
#[doc = "I2STX_WS"]
#[inline]
pub fn i2stx_ws(self) -> &'a mut W {
self.variant(P0_8W::I2STX_WS)
}
#[doc = "MISO1"]
#[inline]
pub fn miso1(self) -> &'a mut W {
self.variant(P0_8W::MISO1)
}
#[doc = "MAT2.2"]
#[inline]
pub fn mat2(self) -> &'a mut W {
self.variant(P0_8W::MAT2)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_9`"]
pub enum P0_9W {
#[doc = "GPIO P0.9"]
GPIO_P0,
#[doc = "I2STX_SDA"]
I2STX_SDA,
#[doc = "MOSI1"]
MOSI1,
#[doc = "MAT2.3"]
MAT2,
}
impl P0_9W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_9W::GPIO_P0 => 0,
P0_9W::I2STX_SDA => 1,
P0_9W::MOSI1 => 2,
P0_9W::MAT2 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_9W<'a> {
w: &'a mut W,
}
impl<'a> _P0_9W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_9W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.9"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_9W::GPIO_P0)
}
#[doc = "I2STX_SDA"]
#[inline]
pub fn i2stx_sda(self) -> &'a mut W {
self.variant(P0_9W::I2STX_SDA)
}
#[doc = "MOSI1"]
#[inline]
pub fn mosi1(self) -> &'a mut W {
self.variant(P0_9W::MOSI1)
}
#[doc = "MAT2.3"]
#[inline]
pub fn mat2(self) -> &'a mut W {
self.variant(P0_9W::MAT2)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_10`"]
pub enum P0_10W {
#[doc = "GPIO P0.10"]
GPIO_P0,
#[doc = "TXD2"]
TXD2,
#[doc = "SDA2"]
SDA2,
#[doc = "MAT3.0"]
MAT3,
}
impl P0_10W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_10W::GPIO_P0 => 0,
P0_10W::TXD2 => 1,
P0_10W::SDA2 => 2,
P0_10W::MAT3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_10W<'a> {
w: &'a mut W,
}
impl<'a> _P0_10W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_10W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.10"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_10W::GPIO_P0)
}
#[doc = "TXD2"]
#[inline]
pub fn txd2(self) -> &'a mut W {
self.variant(P0_10W::TXD2)
}
#[doc = "SDA2"]
#[inline]
pub fn sda2(self) -> &'a mut W {
self.variant(P0_10W::SDA2)
}
#[doc = "MAT3.0"]
#[inline]
pub fn mat3(self) -> &'a mut W {
self.variant(P0_10W::MAT3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_11`"]
pub enum P0_11W {
#[doc = "GPIO P0.11"]
GPIO_P0,
#[doc = "RXD2"]
RXD2,
#[doc = "SCL2"]
SCL2,
#[doc = "MAT3.1"]
MAT3,
}
impl P0_11W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_11W::GPIO_P0 => 0,
P0_11W::RXD2 => 1,
P0_11W::SCL2 => 2,
P0_11W::MAT3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_11W<'a> {
w: &'a mut W,
}
impl<'a> _P0_11W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_11W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.11"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_11W::GPIO_P0)
}
#[doc = "RXD2"]
#[inline]
pub fn rxd2(self) -> &'a mut W {
self.variant(P0_11W::RXD2)
}
#[doc = "SCL2"]
#[inline]
pub fn scl2(self) -> &'a mut W {
self.variant(P0_11W::SCL2)
}
#[doc = "MAT3.1"]
#[inline]
pub fn mat3(self) -> &'a mut W {
self.variant(P0_11W::MAT3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_15`"]
pub enum P0_15W {
#[doc = "GPIO P0.15"]
GPIO_P0,
#[doc = "TXD1"]
TXD1,
#[doc = "SCK0"]
SCK0,
#[doc = "SCK"]
SCK,
}
impl P0_15W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_15W::GPIO_P0 => 0,
P0_15W::TXD1 => 1,
P0_15W::SCK0 => 2,
P0_15W::SCK => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_15W<'a> {
w: &'a mut W,
}
impl<'a> _P0_15W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_15W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.15"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_15W::GPIO_P0)
}
#[doc = "TXD1"]
#[inline]
pub fn txd1(self) -> &'a mut W {
self.variant(P0_15W::TXD1)
}
#[doc = "SCK0"]
#[inline]
pub fn sck0(self) -> &'a mut W {
self.variant(P0_15W::SCK0)
}
#[doc = "SCK"]
#[inline]
pub fn sck(self) -> &'a mut W {
self.variant(P0_15W::SCK)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Pin function select P0.0."]
#[inline]
pub fn p0_0(&self) -> P0_0R {
P0_0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Pin function select P0.1."]
#[inline]
pub fn p0_1(&self) -> P0_1R {
P0_1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Pin function select P0.2."]
#[inline]
pub fn p0_2(&self) -> P0_2R {
P0_2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Pin function select P0.3."]
#[inline]
pub fn p0_3(&self) -> P0_3R {
P0_3R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Pin function select P0.4."]
#[inline]
pub fn p0_4(&self) -> P0_4R {
P0_4R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Pin function select P0.5."]
#[inline]
pub fn p0_5(&self) -> P0_5R {
P0_5R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Pin function select P0.6."]
#[inline]
pub fn p0_6(&self) -> P0_6R {
P0_6R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Pin function select P0.7."]
#[inline]
pub fn p0_7(&self) -> P0_7R {
P0_7R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Pin function select P0.8."]
#[inline]
pub fn p0_8(&self) -> P0_8R {
P0_8R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Pin function select P0.9."]
#[inline]
pub fn p0_9(&self) -> P0_9R {
P0_9R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Pin function select P0.10."]
#[inline]
pub fn p0_10(&self) -> P0_10R {
P0_10R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Pin function select P0.11."]
#[inline]
pub fn p0_11(&self) -> P0_11R {
P0_11R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Pin function select P0.15."]
#[inline]
pub fn p0_15(&self) -> P0_15R {
P0_15R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Pin function select P0.0."]
#[inline]
pub fn p0_0(&mut self) -> _P0_0W {
_P0_0W { w: self }
}
#[doc = "Bits 2:3 - Pin function select P0.1."]
#[inline]
pub fn p0_1(&mut self) -> _P0_1W {
_P0_1W { w: self }
}
#[doc = "Bits 4:5 - Pin function select P0.2."]
#[inline]
pub fn p0_2(&mut self) -> _P0_2W {
_P0_2W { w: self }
}
#[doc = "Bits 6:7 - Pin function select P0.3."]
#[inline]
pub fn p0_3(&mut self) -> _P0_3W {
_P0_3W { w: self }
}
#[doc = "Bits 8:9 - Pin function select P0.4."]
#[inline]
pub fn p0_4(&mut self) -> _P0_4W {
_P0_4W { w: self }
}
#[doc = "Bits 10:11 - Pin function select P0.5."]
#[inline]
pub fn p0_5(&mut self) -> _P0_5W {
_P0_5W { w: self }
}
#[doc = "Bits 12:13 - Pin function select P0.6."]
#[inline]
pub fn p0_6(&mut self) -> _P0_6W {
_P0_6W { w: self }
}
#[doc = "Bits 14:15 - Pin function select P0.7."]
#[inline]
pub fn p0_7(&mut self) -> _P0_7W {
_P0_7W { w: self }
}
#[doc = "Bits 16:17 - Pin function select P0.8."]
#[inline]
pub fn p0_8(&mut self) -> _P0_8W {
_P0_8W { w: self }
}
#[doc = "Bits 18:19 - Pin function select P0.9."]
#[inline]
pub fn p0_9(&mut self) -> _P0_9W {
_P0_9W { w: self }
}
#[doc = "Bits 20:21 - Pin function select P0.10."]
#[inline]
pub fn p0_10(&mut self) -> _P0_10W {
_P0_10W { w: self }
}
#[doc = "Bits 22:23 - Pin function select P0.11."]
#[inline]
pub fn p0_11(&mut self) -> _P0_11W {
_P0_11W { w: self }
}
#[doc = "Bits 30:31 - Pin function select P0.15."]
#[inline]
pub fn p0_15(&mut self) -> _P0_15W {
_P0_15W { w: self }
}
}
}
#[doc = "Pin function select register 1."]
pub struct PINSEL1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 1."]
pub mod pinsel1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P0_16`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_16R {
#[doc = "GPIO P0.16"]
GPIO_P0,
#[doc = "RXD1"]
RXD1,
#[doc = "SSEL0"]
SSEL0,
#[doc = "SSEL"]
SSEL,
}
impl P0_16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_16R::GPIO_P0 => 0,
P0_16R::RXD1 => 0x01,
P0_16R::SSEL0 => 0x02,
P0_16R::SSEL => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_16R {
match value {
0 => P0_16R::GPIO_P0,
1 => P0_16R::RXD1,
2 => P0_16R::SSEL0,
3 => P0_16R::SSEL,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_16R::GPIO_P0
}
#[doc = "Checks if the value of the field is `RXD1`"]
#[inline]
pub fn is_rxd1(&self) -> bool {
*self == P0_16R::RXD1
}
#[doc = "Checks if the value of the field is `SSEL0`"]
#[inline]
pub fn is_ssel0(&self) -> bool {
*self == P0_16R::SSEL0
}
#[doc = "Checks if the value of the field is `SSEL`"]
#[inline]
pub fn is_ssel(&self) -> bool {
*self == P0_16R::SSEL
}
}
#[doc = "Possible values of the field `P0_17`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_17R {
#[doc = "GPIO P0.17"]
GPIO_P0,
#[doc = "CTS1"]
CTS1,
#[doc = "MISO0"]
MISO0,
#[doc = "MISO"]
MISO,
}
impl P0_17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_17R::GPIO_P0 => 0,
P0_17R::CTS1 => 0x01,
P0_17R::MISO0 => 0x02,
P0_17R::MISO => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_17R {
match value {
0 => P0_17R::GPIO_P0,
1 => P0_17R::CTS1,
2 => P0_17R::MISO0,
3 => P0_17R::MISO,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_17R::GPIO_P0
}
#[doc = "Checks if the value of the field is `CTS1`"]
#[inline]
pub fn is_cts1(&self) -> bool {
*self == P0_17R::CTS1
}
#[doc = "Checks if the value of the field is `MISO0`"]
#[inline]
pub fn is_miso0(&self) -> bool {
*self == P0_17R::MISO0
}
#[doc = "Checks if the value of the field is `MISO`"]
#[inline]
pub fn is_miso(&self) -> bool {
*self == P0_17R::MISO
}
}
#[doc = "Possible values of the field `P0_18`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_18R {
#[doc = "GPIO P0.18"]
GPIO_P0,
#[doc = "DCD1"]
DCD1,
#[doc = "MOSI0"]
MOSI0,
#[doc = "MOSI"]
MOSI,
}
impl P0_18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_18R::GPIO_P0 => 0,
P0_18R::DCD1 => 0x01,
P0_18R::MOSI0 => 0x02,
P0_18R::MOSI => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_18R {
match value {
0 => P0_18R::GPIO_P0,
1 => P0_18R::DCD1,
2 => P0_18R::MOSI0,
3 => P0_18R::MOSI,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_18R::GPIO_P0
}
#[doc = "Checks if the value of the field is `DCD1`"]
#[inline]
pub fn is_dcd1(&self) -> bool {
*self == P0_18R::DCD1
}
#[doc = "Checks if the value of the field is `MOSI0`"]
#[inline]
pub fn is_mosi0(&self) -> bool {
*self == P0_18R::MOSI0
}
#[doc = "Checks if the value of the field is `MOSI`"]
#[inline]
pub fn is_mosi(&self) -> bool {
*self == P0_18R::MOSI
}
}
#[doc = "Possible values of the field `P0_19`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_19R {
#[doc = "GPIO P0.19."]
GPIO_P0,
#[doc = "DSR1"]
DSR1,
#[doc = "SDA1"]
SDA1,
}
impl P0_19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_19R::GPIO_P0 => 0,
P0_19R::DSR1 => 0x01,
P0_19R::SDA1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_19R {
match value {
0 => P0_19R::GPIO_P0,
1 => P0_19R::DSR1,
3 => P0_19R::SDA1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_19R::GPIO_P0
}
#[doc = "Checks if the value of the field is `DSR1`"]
#[inline]
pub fn is_dsr1(&self) -> bool {
*self == P0_19R::DSR1
}
#[doc = "Checks if the value of the field is `SDA1`"]
#[inline]
pub fn is_sda1(&self) -> bool {
*self == P0_19R::SDA1
}
}
#[doc = "Possible values of the field `P0_20`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_20R {
#[doc = "GPIO P0.20."]
GPIO_P0,
#[doc = "DTR1"]
DTR1,
#[doc = "SCL1"]
SCL1,
}
impl P0_20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_20R::GPIO_P0 => 0,
P0_20R::DTR1 => 0x01,
P0_20R::SCL1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_20R {
match value {
0 => P0_20R::GPIO_P0,
1 => P0_20R::DTR1,
3 => P0_20R::SCL1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_20R::GPIO_P0
}
#[doc = "Checks if the value of the field is `DTR1`"]
#[inline]
pub fn is_dtr1(&self) -> bool {
*self == P0_20R::DTR1
}
#[doc = "Checks if the value of the field is `SCL1`"]
#[inline]
pub fn is_scl1(&self) -> bool {
*self == P0_20R::SCL1
}
}
#[doc = "Possible values of the field `P0_21`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_21R {
#[doc = "GPIO Port 0.21."]
GPIO_PORT_0,
#[doc = "RI1"]
RI1,
#[doc = "RD1"]
RD1,
}
impl P0_21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_21R::GPIO_PORT_0 => 0,
P0_21R::RI1 => 0x01,
P0_21R::RD1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_21R {
match value {
0 => P0_21R::GPIO_PORT_0,
1 => P0_21R::RI1,
3 => P0_21R::RD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_PORT_0`"]
#[inline]
pub fn is_gpio_port_0(&self) -> bool {
*self == P0_21R::GPIO_PORT_0
}
#[doc = "Checks if the value of the field is `RI1`"]
#[inline]
pub fn is_ri1(&self) -> bool {
*self == P0_21R::RI1
}
#[doc = "Checks if the value of the field is `RD1`"]
#[inline]
pub fn is_rd1(&self) -> bool {
*self == P0_21R::RD1
}
}
#[doc = "Possible values of the field `P0_22`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_22R {
#[doc = "GPIO P0.22."]
GPIO_P0,
#[doc = "RTS1"]
RTS1,
#[doc = "TD1"]
TD1,
}
impl P0_22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_22R::GPIO_P0 => 0,
P0_22R::RTS1 => 0x01,
P0_22R::TD1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_22R {
match value {
0 => P0_22R::GPIO_P0,
1 => P0_22R::RTS1,
3 => P0_22R::TD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_22R::GPIO_P0
}
#[doc = "Checks if the value of the field is `RTS1`"]
#[inline]
pub fn is_rts1(&self) -> bool {
*self == P0_22R::RTS1
}
#[doc = "Checks if the value of the field is `TD1`"]
#[inline]
pub fn is_td1(&self) -> bool {
*self == P0_22R::TD1
}
}
#[doc = "Possible values of the field `P0_23`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_23R {
#[doc = "GPIO P0.23."]
GPIO_P0,
#[doc = "AD0.0"]
AD0,
#[doc = "I2SRX_CLK"]
I2SRX_CLK,
#[doc = "CAP3.0"]
CAP3,
}
impl P0_23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_23R::GPIO_P0 => 0,
P0_23R::AD0 => 0x01,
P0_23R::I2SRX_CLK => 0x02,
P0_23R::CAP3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_23R {
match value {
0 => P0_23R::GPIO_P0,
1 => P0_23R::AD0,
2 => P0_23R::I2SRX_CLK,
3 => P0_23R::CAP3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_23R::GPIO_P0
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P0_23R::AD0
}
#[doc = "Checks if the value of the field is `I2SRX_CLK`"]
#[inline]
pub fn is_i2srx_clk(&self) -> bool {
*self == P0_23R::I2SRX_CLK
}
#[doc = "Checks if the value of the field is `CAP3`"]
#[inline]
pub fn is_cap3(&self) -> bool {
*self == P0_23R::CAP3
}
}
#[doc = "Possible values of the field `P0_24`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_24R {
#[doc = "GPIO P0.24."]
GPIO_P0,
#[doc = "AD0.1"]
AD0,
#[doc = "I2SRX_WS"]
I2SRX_WS,
#[doc = "CAP3.1"]
CAP3,
}
impl P0_24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_24R::GPIO_P0 => 0,
P0_24R::AD0 => 0x01,
P0_24R::I2SRX_WS => 0x02,
P0_24R::CAP3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_24R {
match value {
0 => P0_24R::GPIO_P0,
1 => P0_24R::AD0,
2 => P0_24R::I2SRX_WS,
3 => P0_24R::CAP3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_24R::GPIO_P0
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P0_24R::AD0
}
#[doc = "Checks if the value of the field is `I2SRX_WS`"]
#[inline]
pub fn is_i2srx_ws(&self) -> bool {
*self == P0_24R::I2SRX_WS
}
#[doc = "Checks if the value of the field is `CAP3`"]
#[inline]
pub fn is_cap3(&self) -> bool {
*self == P0_24R::CAP3
}
}
#[doc = "Possible values of the field `P0_25`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_25R {
#[doc = "GPIO P0.25"]
GPIO_P0,
#[doc = "AD0.2"]
AD0,
#[doc = "I2SRX_SDA"]
I2SRX_SDA,
#[doc = "TXD3"]
TXD3,
}
impl P0_25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_25R::GPIO_P0 => 0,
P0_25R::AD0 => 0x01,
P0_25R::I2SRX_SDA => 0x02,
P0_25R::TXD3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_25R {
match value {
0 => P0_25R::GPIO_P0,
1 => P0_25R::AD0,
2 => P0_25R::I2SRX_SDA,
3 => P0_25R::TXD3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_25R::GPIO_P0
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P0_25R::AD0
}
#[doc = "Checks if the value of the field is `I2SRX_SDA`"]
#[inline]
pub fn is_i2srx_sda(&self) -> bool {
*self == P0_25R::I2SRX_SDA
}
#[doc = "Checks if the value of the field is `TXD3`"]
#[inline]
pub fn is_txd3(&self) -> bool {
*self == P0_25R::TXD3
}
}
#[doc = "Possible values of the field `P0_26`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_26R {
#[doc = "GPIO P0.26"]
GPIO_P0,
#[doc = "AD0.3"]
AD0,
#[doc = "AOUT"]
AOUT,
#[doc = "RXD3"]
RXD3,
}
impl P0_26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_26R::GPIO_P0 => 0,
P0_26R::AD0 => 0x01,
P0_26R::AOUT => 0x02,
P0_26R::RXD3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_26R {
match value {
0 => P0_26R::GPIO_P0,
1 => P0_26R::AD0,
2 => P0_26R::AOUT,
3 => P0_26R::RXD3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_26R::GPIO_P0
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P0_26R::AD0
}
#[doc = "Checks if the value of the field is `AOUT`"]
#[inline]
pub fn is_aout(&self) -> bool {
*self == P0_26R::AOUT
}
#[doc = "Checks if the value of the field is `RXD3`"]
#[inline]
pub fn is_rxd3(&self) -> bool {
*self == P0_26R::RXD3
}
}
#[doc = "Possible values of the field `P0_27`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_27R {
#[doc = "GPIO P0.27"]
GPIO_P0,
#[doc = "SDA0"]
SDA0,
#[doc = "USB_SDA"]
USB_SDA,
}
impl P0_27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_27R::GPIO_P0 => 0,
P0_27R::SDA0 => 0x01,
P0_27R::USB_SDA => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_27R {
match value {
0 => P0_27R::GPIO_P0,
1 => P0_27R::SDA0,
2 => P0_27R::USB_SDA,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_27R::GPIO_P0
}
#[doc = "Checks if the value of the field is `SDA0`"]
#[inline]
pub fn is_sda0(&self) -> bool {
*self == P0_27R::SDA0
}
#[doc = "Checks if the value of the field is `USB_SDA`"]
#[inline]
pub fn is_usb_sda(&self) -> bool {
*self == P0_27R::USB_SDA
}
}
#[doc = "Possible values of the field `P0_28`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_28R {
#[doc = "GPIO P0.28"]
GPIO_P0,
#[doc = "SCL0"]
SCL0,
#[doc = "USB_SCL"]
USB_SCL,
}
impl P0_28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_28R::GPIO_P0 => 0,
P0_28R::SCL0 => 0x01,
P0_28R::USB_SCL => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_28R {
match value {
0 => P0_28R::GPIO_P0,
1 => P0_28R::SCL0,
2 => P0_28R::USB_SCL,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_28R::GPIO_P0
}
#[doc = "Checks if the value of the field is `SCL0`"]
#[inline]
pub fn is_scl0(&self) -> bool {
*self == P0_28R::SCL0
}
#[doc = "Checks if the value of the field is `USB_SCL`"]
#[inline]
pub fn is_usb_scl(&self) -> bool {
*self == P0_28R::USB_SCL
}
}
#[doc = "Possible values of the field `P0_29`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_29R {
#[doc = "GPIO P0.29"]
GPIO_P0,
#[doc = "USB_D+"]
USB_DP,
}
impl P0_29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_29R::GPIO_P0 => 0,
P0_29R::USB_DP => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_29R {
match value {
0 => P0_29R::GPIO_P0,
1 => P0_29R::USB_DP,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_29R::GPIO_P0
}
#[doc = "Checks if the value of the field is `USB_DP`"]
#[inline]
pub fn is_usb_dp(&self) -> bool {
*self == P0_29R::USB_DP
}
}
#[doc = "Possible values of the field `P0_30`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_30R {
#[doc = "GPIO P0.30"]
GPIO_P0,
#[doc = "USB_D-"]
USB_DM,
}
impl P0_30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_30R::GPIO_P0 => 0,
P0_30R::USB_DM => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_30R {
match value {
0 => P0_30R::GPIO_P0,
1 => P0_30R::USB_DM,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P0`"]
#[inline]
pub fn is_gpio_p0(&self) -> bool {
*self == P0_30R::GPIO_P0
}
#[doc = "Checks if the value of the field is `USB_DM`"]
#[inline]
pub fn is_usb_dm(&self) -> bool {
*self == P0_30R::USB_DM
}
}
#[doc = "Values that can be written to the field `P0_16`"]
pub enum P0_16W {
#[doc = "GPIO P0.16"]
GPIO_P0,
#[doc = "RXD1"]
RXD1,
#[doc = "SSEL0"]
SSEL0,
#[doc = "SSEL"]
SSEL,
}
impl P0_16W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_16W::GPIO_P0 => 0,
P0_16W::RXD1 => 1,
P0_16W::SSEL0 => 2,
P0_16W::SSEL => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_16W<'a> {
w: &'a mut W,
}
impl<'a> _P0_16W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_16W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.16"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_16W::GPIO_P0)
}
#[doc = "RXD1"]
#[inline]
pub fn rxd1(self) -> &'a mut W {
self.variant(P0_16W::RXD1)
}
#[doc = "SSEL0"]
#[inline]
pub fn ssel0(self) -> &'a mut W {
self.variant(P0_16W::SSEL0)
}
#[doc = "SSEL"]
#[inline]
pub fn ssel(self) -> &'a mut W {
self.variant(P0_16W::SSEL)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_17`"]
pub enum P0_17W {
#[doc = "GPIO P0.17"]
GPIO_P0,
#[doc = "CTS1"]
CTS1,
#[doc = "MISO0"]
MISO0,
#[doc = "MISO"]
MISO,
}
impl P0_17W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_17W::GPIO_P0 => 0,
P0_17W::CTS1 => 1,
P0_17W::MISO0 => 2,
P0_17W::MISO => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_17W<'a> {
w: &'a mut W,
}
impl<'a> _P0_17W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_17W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.17"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_17W::GPIO_P0)
}
#[doc = "CTS1"]
#[inline]
pub fn cts1(self) -> &'a mut W {
self.variant(P0_17W::CTS1)
}
#[doc = "MISO0"]
#[inline]
pub fn miso0(self) -> &'a mut W {
self.variant(P0_17W::MISO0)
}
#[doc = "MISO"]
#[inline]
pub fn miso(self) -> &'a mut W {
self.variant(P0_17W::MISO)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_18`"]
pub enum P0_18W {
#[doc = "GPIO P0.18"]
GPIO_P0,
#[doc = "DCD1"]
DCD1,
#[doc = "MOSI0"]
MOSI0,
#[doc = "MOSI"]
MOSI,
}
impl P0_18W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_18W::GPIO_P0 => 0,
P0_18W::DCD1 => 1,
P0_18W::MOSI0 => 2,
P0_18W::MOSI => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_18W<'a> {
w: &'a mut W,
}
impl<'a> _P0_18W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_18W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.18"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_18W::GPIO_P0)
}
#[doc = "DCD1"]
#[inline]
pub fn dcd1(self) -> &'a mut W {
self.variant(P0_18W::DCD1)
}
#[doc = "MOSI0"]
#[inline]
pub fn mosi0(self) -> &'a mut W {
self.variant(P0_18W::MOSI0)
}
#[doc = "MOSI"]
#[inline]
pub fn mosi(self) -> &'a mut W {
self.variant(P0_18W::MOSI)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_19`"]
pub enum P0_19W {
#[doc = "GPIO P0.19."]
GPIO_P0,
#[doc = "DSR1"]
DSR1,
#[doc = "SDA1"]
SDA1,
}
impl P0_19W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_19W::GPIO_P0 => 0,
P0_19W::DSR1 => 1,
P0_19W::SDA1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_19W<'a> {
w: &'a mut W,
}
impl<'a> _P0_19W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_19W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.19."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_19W::GPIO_P0)
}
#[doc = "DSR1"]
#[inline]
pub fn dsr1(self) -> &'a mut W {
self.variant(P0_19W::DSR1)
}
#[doc = "SDA1"]
#[inline]
pub fn sda1(self) -> &'a mut W {
self.variant(P0_19W::SDA1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_20`"]
pub enum P0_20W {
#[doc = "GPIO P0.20."]
GPIO_P0,
#[doc = "DTR1"]
DTR1,
#[doc = "SCL1"]
SCL1,
}
impl P0_20W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_20W::GPIO_P0 => 0,
P0_20W::DTR1 => 1,
P0_20W::SCL1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_20W<'a> {
w: &'a mut W,
}
impl<'a> _P0_20W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_20W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.20."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_20W::GPIO_P0)
}
#[doc = "DTR1"]
#[inline]
pub fn dtr1(self) -> &'a mut W {
self.variant(P0_20W::DTR1)
}
#[doc = "SCL1"]
#[inline]
pub fn scl1(self) -> &'a mut W {
self.variant(P0_20W::SCL1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_21`"]
pub enum P0_21W {
#[doc = "GPIO Port 0.21."]
GPIO_PORT_0,
#[doc = "RI1"]
RI1,
#[doc = "RD1"]
RD1,
}
impl P0_21W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_21W::GPIO_PORT_0 => 0,
P0_21W::RI1 => 1,
P0_21W::RD1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_21W<'a> {
w: &'a mut W,
}
impl<'a> _P0_21W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_21W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO Port 0.21."]
#[inline]
pub fn gpio_port_0(self) -> &'a mut W {
self.variant(P0_21W::GPIO_PORT_0)
}
#[doc = "RI1"]
#[inline]
pub fn ri1(self) -> &'a mut W {
self.variant(P0_21W::RI1)
}
#[doc = "RD1"]
#[inline]
pub fn rd1(self) -> &'a mut W {
self.variant(P0_21W::RD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_22`"]
pub enum P0_22W {
#[doc = "GPIO P0.22."]
GPIO_P0,
#[doc = "RTS1"]
RTS1,
#[doc = "TD1"]
TD1,
}
impl P0_22W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_22W::GPIO_P0 => 0,
P0_22W::RTS1 => 1,
P0_22W::TD1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_22W<'a> {
w: &'a mut W,
}
impl<'a> _P0_22W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_22W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.22."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_22W::GPIO_P0)
}
#[doc = "RTS1"]
#[inline]
pub fn rts1(self) -> &'a mut W {
self.variant(P0_22W::RTS1)
}
#[doc = "TD1"]
#[inline]
pub fn td1(self) -> &'a mut W {
self.variant(P0_22W::TD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_23`"]
pub enum P0_23W {
#[doc = "GPIO P0.23."]
GPIO_P0,
#[doc = "AD0.0"]
AD0,
#[doc = "I2SRX_CLK"]
I2SRX_CLK,
#[doc = "CAP3.0"]
CAP3,
}
impl P0_23W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_23W::GPIO_P0 => 0,
P0_23W::AD0 => 1,
P0_23W::I2SRX_CLK => 2,
P0_23W::CAP3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_23W<'a> {
w: &'a mut W,
}
impl<'a> _P0_23W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_23W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.23."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_23W::GPIO_P0)
}
#[doc = "AD0.0"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P0_23W::AD0)
}
#[doc = "I2SRX_CLK"]
#[inline]
pub fn i2srx_clk(self) -> &'a mut W {
self.variant(P0_23W::I2SRX_CLK)
}
#[doc = "CAP3.0"]
#[inline]
pub fn cap3(self) -> &'a mut W {
self.variant(P0_23W::CAP3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_24`"]
pub enum P0_24W {
#[doc = "GPIO P0.24."]
GPIO_P0,
#[doc = "AD0.1"]
AD0,
#[doc = "I2SRX_WS"]
I2SRX_WS,
#[doc = "CAP3.1"]
CAP3,
}
impl P0_24W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_24W::GPIO_P0 => 0,
P0_24W::AD0 => 1,
P0_24W::I2SRX_WS => 2,
P0_24W::CAP3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_24W<'a> {
w: &'a mut W,
}
impl<'a> _P0_24W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_24W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.24."]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_24W::GPIO_P0)
}
#[doc = "AD0.1"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P0_24W::AD0)
}
#[doc = "I2SRX_WS"]
#[inline]
pub fn i2srx_ws(self) -> &'a mut W {
self.variant(P0_24W::I2SRX_WS)
}
#[doc = "CAP3.1"]
#[inline]
pub fn cap3(self) -> &'a mut W {
self.variant(P0_24W::CAP3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_25`"]
pub enum P0_25W {
#[doc = "GPIO P0.25"]
GPIO_P0,
#[doc = "AD0.2"]
AD0,
#[doc = "I2SRX_SDA"]
I2SRX_SDA,
#[doc = "TXD3"]
TXD3,
}
impl P0_25W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_25W::GPIO_P0 => 0,
P0_25W::AD0 => 1,
P0_25W::I2SRX_SDA => 2,
P0_25W::TXD3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_25W<'a> {
w: &'a mut W,
}
impl<'a> _P0_25W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_25W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.25"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_25W::GPIO_P0)
}
#[doc = "AD0.2"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P0_25W::AD0)
}
#[doc = "I2SRX_SDA"]
#[inline]
pub fn i2srx_sda(self) -> &'a mut W {
self.variant(P0_25W::I2SRX_SDA)
}
#[doc = "TXD3"]
#[inline]
pub fn txd3(self) -> &'a mut W {
self.variant(P0_25W::TXD3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_26`"]
pub enum P0_26W {
#[doc = "GPIO P0.26"]
GPIO_P0,
#[doc = "AD0.3"]
AD0,
#[doc = "AOUT"]
AOUT,
#[doc = "RXD3"]
RXD3,
}
impl P0_26W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_26W::GPIO_P0 => 0,
P0_26W::AD0 => 1,
P0_26W::AOUT => 2,
P0_26W::RXD3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_26W<'a> {
w: &'a mut W,
}
impl<'a> _P0_26W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_26W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P0.26"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_26W::GPIO_P0)
}
#[doc = "AD0.3"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P0_26W::AD0)
}
#[doc = "AOUT"]
#[inline]
pub fn aout(self) -> &'a mut W {
self.variant(P0_26W::AOUT)
}
#[doc = "RXD3"]
#[inline]
pub fn rxd3(self) -> &'a mut W {
self.variant(P0_26W::RXD3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_27`"]
pub enum P0_27W {
#[doc = "GPIO P0.27"]
GPIO_P0,
#[doc = "SDA0"]
SDA0,
#[doc = "USB_SDA"]
USB_SDA,
}
impl P0_27W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_27W::GPIO_P0 => 0,
P0_27W::SDA0 => 1,
P0_27W::USB_SDA => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_27W<'a> {
w: &'a mut W,
}
impl<'a> _P0_27W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_27W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.27"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_27W::GPIO_P0)
}
#[doc = "SDA0"]
#[inline]
pub fn sda0(self) -> &'a mut W {
self.variant(P0_27W::SDA0)
}
#[doc = "USB_SDA"]
#[inline]
pub fn usb_sda(self) -> &'a mut W {
self.variant(P0_27W::USB_SDA)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_28`"]
pub enum P0_28W {
#[doc = "GPIO P0.28"]
GPIO_P0,
#[doc = "SCL0"]
SCL0,
#[doc = "USB_SCL"]
USB_SCL,
}
impl P0_28W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_28W::GPIO_P0 => 0,
P0_28W::SCL0 => 1,
P0_28W::USB_SCL => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_28W<'a> {
w: &'a mut W,
}
impl<'a> _P0_28W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_28W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.28"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_28W::GPIO_P0)
}
#[doc = "SCL0"]
#[inline]
pub fn scl0(self) -> &'a mut W {
self.variant(P0_28W::SCL0)
}
#[doc = "USB_SCL"]
#[inline]
pub fn usb_scl(self) -> &'a mut W {
self.variant(P0_28W::USB_SCL)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_29`"]
pub enum P0_29W {
#[doc = "GPIO P0.29"]
GPIO_P0,
#[doc = "USB_D+"]
USB_DP,
}
impl P0_29W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_29W::GPIO_P0 => 0,
P0_29W::USB_DP => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_29W<'a> {
w: &'a mut W,
}
impl<'a> _P0_29W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_29W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.29"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_29W::GPIO_P0)
}
#[doc = "USB_D+"]
#[inline]
pub fn usb_dp(self) -> &'a mut W {
self.variant(P0_29W::USB_DP)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_30`"]
pub enum P0_30W {
#[doc = "GPIO P0.30"]
GPIO_P0,
#[doc = "USB_D-"]
USB_DM,
}
impl P0_30W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_30W::GPIO_P0 => 0,
P0_30W::USB_DM => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_30W<'a> {
w: &'a mut W,
}
impl<'a> _P0_30W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_30W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P0.30"]
#[inline]
pub fn gpio_p0(self) -> &'a mut W {
self.variant(P0_30W::GPIO_P0)
}
#[doc = "USB_D-"]
#[inline]
pub fn usb_dm(self) -> &'a mut W {
self.variant(P0_30W::USB_DM)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Pin function select P0.16."]
#[inline]
pub fn p0_16(&self) -> P0_16R {
P0_16R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Pin function select P0.17."]
#[inline]
pub fn p0_17(&self) -> P0_17R {
P0_17R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Pin function select P0.18."]
#[inline]
pub fn p0_18(&self) -> P0_18R {
P0_18R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Pin function select P019."]
#[inline]
pub fn p0_19(&self) -> P0_19R {
P0_19R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Pin function select P0.20."]
#[inline]
pub fn p0_20(&self) -> P0_20R {
P0_20R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Pin function select P0.21."]
#[inline]
pub fn p0_21(&self) -> P0_21R {
P0_21R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Pin function select P022"]
#[inline]
pub fn p0_22(&self) -> P0_22R {
P0_22R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Pin function select P023."]
#[inline]
pub fn p0_23(&self) -> P0_23R {
P0_23R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Pin function select P0.24."]
#[inline]
pub fn p0_24(&self) -> P0_24R {
P0_24R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Pin function select P0.25."]
#[inline]
pub fn p0_25(&self) -> P0_25R {
P0_25R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Pin function select P0.26."]
#[inline]
pub fn p0_26(&self) -> P0_26R {
P0_26R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Pin function select P0.27."]
#[inline]
pub fn p0_27(&self) -> P0_27R {
P0_27R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:25 - Pin function select P0.28."]
#[inline]
pub fn p0_28(&self) -> P0_28R {
P0_28R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Pin function select P0.29"]
#[inline]
pub fn p0_29(&self) -> P0_29R {
P0_29R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 28:29 - Pin function select P0.30."]
#[inline]
pub fn p0_30(&self) -> P0_30R {
P0_30R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Pin function select P0.16."]
#[inline]
pub fn p0_16(&mut self) -> _P0_16W {
_P0_16W { w: self }
}
#[doc = "Bits 2:3 - Pin function select P0.17."]
#[inline]
pub fn p0_17(&mut self) -> _P0_17W {
_P0_17W { w: self }
}
#[doc = "Bits 4:5 - Pin function select P0.18."]
#[inline]
pub fn p0_18(&mut self) -> _P0_18W {
_P0_18W { w: self }
}
#[doc = "Bits 6:7 - Pin function select P019."]
#[inline]
pub fn p0_19(&mut self) -> _P0_19W {
_P0_19W { w: self }
}
#[doc = "Bits 8:9 - Pin function select P0.20."]
#[inline]
pub fn p0_20(&mut self) -> _P0_20W {
_P0_20W { w: self }
}
#[doc = "Bits 10:11 - Pin function select P0.21."]
#[inline]
pub fn p0_21(&mut self) -> _P0_21W {
_P0_21W { w: self }
}
#[doc = "Bits 12:13 - Pin function select P022"]
#[inline]
pub fn p0_22(&mut self) -> _P0_22W {
_P0_22W { w: self }
}
#[doc = "Bits 14:15 - Pin function select P023."]
#[inline]
pub fn p0_23(&mut self) -> _P0_23W {
_P0_23W { w: self }
}
#[doc = "Bits 16:17 - Pin function select P0.24."]
#[inline]
pub fn p0_24(&mut self) -> _P0_24W {
_P0_24W { w: self }
}
#[doc = "Bits 18:19 - Pin function select P0.25."]
#[inline]
pub fn p0_25(&mut self) -> _P0_25W {
_P0_25W { w: self }
}
#[doc = "Bits 20:21 - Pin function select P0.26."]
#[inline]
pub fn p0_26(&mut self) -> _P0_26W {
_P0_26W { w: self }
}
#[doc = "Bits 22:23 - Pin function select P0.27."]
#[inline]
pub fn p0_27(&mut self) -> _P0_27W {
_P0_27W { w: self }
}
#[doc = "Bits 24:25 - Pin function select P0.28."]
#[inline]
pub fn p0_28(&mut self) -> _P0_28W {
_P0_28W { w: self }
}
#[doc = "Bits 26:27 - Pin function select P0.29"]
#[inline]
pub fn p0_29(&mut self) -> _P0_29W {
_P0_29W { w: self }
}
#[doc = "Bits 28:29 - Pin function select P0.30."]
#[inline]
pub fn p0_30(&mut self) -> _P0_30W {
_P0_30W { w: self }
}
}
}
#[doc = "Pin function select register 2."]
pub struct PINSEL2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 2."]
pub mod pinsel2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P1_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_0R {
#[doc = "GPIO P1.0"]
GPIO_P1,
#[doc = "ENET_TXD0"]
ENET_TXD0,
}
impl P1_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_0R::GPIO_P1 => 0,
P1_0R::ENET_TXD0 => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_0R {
match value {
0 => P1_0R::GPIO_P1,
1 => P1_0R::ENET_TXD0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_0R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_TXD0`"]
#[inline]
pub fn is_enet_txd0(&self) -> bool {
*self == P1_0R::ENET_TXD0
}
}
#[doc = "Possible values of the field `P1_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_1R {
#[doc = "GPIO P1.1"]
GPIO_P1,
#[doc = "ENET_TXD1"]
ENET_TXD1,
}
impl P1_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_1R::GPIO_P1 => 0,
P1_1R::ENET_TXD1 => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_1R {
match value {
0 => P1_1R::GPIO_P1,
1 => P1_1R::ENET_TXD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_1R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_TXD1`"]
#[inline]
pub fn is_enet_txd1(&self) -> bool {
*self == P1_1R::ENET_TXD1
}
}
#[doc = "Possible values of the field `P1_4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_4R {
#[doc = "GPIO P1.4."]
GPIO_P1,
#[doc = "ENET_TX_EN"]
ENET_TX_EN,
}
impl P1_4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_4R::GPIO_P1 => 0,
P1_4R::ENET_TX_EN => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_4R {
match value {
0 => P1_4R::GPIO_P1,
1 => P1_4R::ENET_TX_EN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_4R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_TX_EN`"]
#[inline]
pub fn is_enet_tx_en(&self) -> bool {
*self == P1_4R::ENET_TX_EN
}
}
#[doc = "Possible values of the field `P1_8`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_8R {
#[doc = "GPIO P1.8."]
GPIO_P1,
#[doc = "ENET_CRS"]
ENET_CRS,
}
impl P1_8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_8R::GPIO_P1 => 0,
P1_8R::ENET_CRS => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_8R {
match value {
0 => P1_8R::GPIO_P1,
1 => P1_8R::ENET_CRS,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_8R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_CRS`"]
#[inline]
pub fn is_enet_crs(&self) -> bool {
*self == P1_8R::ENET_CRS
}
}
#[doc = "Possible values of the field `P1_9`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_9R {
#[doc = "GPIO Port 1.9"]
GPIO_PORT_1,
#[doc = "ENET_RXD0"]
ENET_RXD0,
}
impl P1_9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_9R::GPIO_PORT_1 => 0,
P1_9R::ENET_RXD0 => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_9R {
match value {
0 => P1_9R::GPIO_PORT_1,
1 => P1_9R::ENET_RXD0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_PORT_1`"]
#[inline]
pub fn is_gpio_port_1(&self) -> bool {
*self == P1_9R::GPIO_PORT_1
}
#[doc = "Checks if the value of the field is `ENET_RXD0`"]
#[inline]
pub fn is_enet_rxd0(&self) -> bool {
*self == P1_9R::ENET_RXD0
}
}
#[doc = "Possible values of the field `P1_10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_10R {
#[doc = "GPIO P1.10"]
GPIO_P1,
#[doc = "ENET_RXD1"]
ENET_RXD1,
}
impl P1_10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_10R::GPIO_P1 => 0,
P1_10R::ENET_RXD1 => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_10R {
match value {
0 => P1_10R::GPIO_P1,
1 => P1_10R::ENET_RXD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_10R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_RXD1`"]
#[inline]
pub fn is_enet_rxd1(&self) -> bool {
*self == P1_10R::ENET_RXD1
}
}
#[doc = "Possible values of the field `P1_14`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_14R {
#[doc = "GPIO P1.14"]
GPIO_P1,
#[doc = "ENET_RX_ER"]
ENET_RX_ER,
}
impl P1_14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_14R::GPIO_P1 => 0,
P1_14R::ENET_RX_ER => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_14R {
match value {
0 => P1_14R::GPIO_P1,
1 => P1_14R::ENET_RX_ER,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_14R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_RX_ER`"]
#[inline]
pub fn is_enet_rx_er(&self) -> bool {
*self == P1_14R::ENET_RX_ER
}
}
#[doc = "Possible values of the field `P1_15`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_15R {
#[doc = "GPIO P1.15"]
GPIO_P1,
#[doc = "ENET_REF_CLK"]
ENET_REF_CLK,
}
impl P1_15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_15R::GPIO_P1 => 0,
P1_15R::ENET_REF_CLK => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_15R {
match value {
0 => P1_15R::GPIO_P1,
1 => P1_15R::ENET_REF_CLK,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_15R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_REF_CLK`"]
#[inline]
pub fn is_enet_ref_clk(&self) -> bool {
*self == P1_15R::ENET_REF_CLK
}
}
#[doc = "Values that can be written to the field `P1_0`"]
pub enum P1_0W {
#[doc = "GPIO P1.0"]
GPIO_P1,
#[doc = "ENET_TXD0"]
ENET_TXD0,
}
impl P1_0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_0W::GPIO_P1 => 0,
P1_0W::ENET_TXD0 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_0W<'a> {
w: &'a mut W,
}
impl<'a> _P1_0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_0W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.0"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_0W::GPIO_P1)
}
#[doc = "ENET_TXD0"]
#[inline]
pub fn enet_txd0(self) -> &'a mut W {
self.variant(P1_0W::ENET_TXD0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_1`"]
pub enum P1_1W {
#[doc = "GPIO P1.1"]
GPIO_P1,
#[doc = "ENET_TXD1"]
ENET_TXD1,
}
impl P1_1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_1W::GPIO_P1 => 0,
P1_1W::ENET_TXD1 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_1W<'a> {
w: &'a mut W,
}
impl<'a> _P1_1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_1W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.1"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_1W::GPIO_P1)
}
#[doc = "ENET_TXD1"]
#[inline]
pub fn enet_txd1(self) -> &'a mut W {
self.variant(P1_1W::ENET_TXD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_4`"]
pub enum P1_4W {
#[doc = "GPIO P1.4."]
GPIO_P1,
#[doc = "ENET_TX_EN"]
ENET_TX_EN,
}
impl P1_4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_4W::GPIO_P1 => 0,
P1_4W::ENET_TX_EN => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_4W<'a> {
w: &'a mut W,
}
impl<'a> _P1_4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_4W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.4."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_4W::GPIO_P1)
}
#[doc = "ENET_TX_EN"]
#[inline]
pub fn enet_tx_en(self) -> &'a mut W {
self.variant(P1_4W::ENET_TX_EN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_8`"]
pub enum P1_8W {
#[doc = "GPIO P1.8."]
GPIO_P1,
#[doc = "ENET_CRS"]
ENET_CRS,
}
impl P1_8W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_8W::GPIO_P1 => 0,
P1_8W::ENET_CRS => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_8W<'a> {
w: &'a mut W,
}
impl<'a> _P1_8W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_8W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.8."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_8W::GPIO_P1)
}
#[doc = "ENET_CRS"]
#[inline]
pub fn enet_crs(self) -> &'a mut W {
self.variant(P1_8W::ENET_CRS)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_9`"]
pub enum P1_9W {
#[doc = "GPIO Port 1.9"]
GPIO_PORT_1,
#[doc = "ENET_RXD0"]
ENET_RXD0,
}
impl P1_9W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_9W::GPIO_PORT_1 => 0,
P1_9W::ENET_RXD0 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_9W<'a> {
w: &'a mut W,
}
impl<'a> _P1_9W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_9W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO Port 1.9"]
#[inline]
pub fn gpio_port_1(self) -> &'a mut W {
self.variant(P1_9W::GPIO_PORT_1)
}
#[doc = "ENET_RXD0"]
#[inline]
pub fn enet_rxd0(self) -> &'a mut W {
self.variant(P1_9W::ENET_RXD0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_10`"]
pub enum P1_10W {
#[doc = "GPIO P1.10"]
GPIO_P1,
#[doc = "ENET_RXD1"]
ENET_RXD1,
}
impl P1_10W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_10W::GPIO_P1 => 0,
P1_10W::ENET_RXD1 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_10W<'a> {
w: &'a mut W,
}
impl<'a> _P1_10W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_10W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.10"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_10W::GPIO_P1)
}
#[doc = "ENET_RXD1"]
#[inline]
pub fn enet_rxd1(self) -> &'a mut W {
self.variant(P1_10W::ENET_RXD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_14`"]
pub enum P1_14W {
#[doc = "GPIO P1.14"]
GPIO_P1,
#[doc = "ENET_RX_ER"]
ENET_RX_ER,
}
impl P1_14W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_14W::GPIO_P1 => 0,
P1_14W::ENET_RX_ER => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_14W<'a> {
w: &'a mut W,
}
impl<'a> _P1_14W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_14W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.14"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_14W::GPIO_P1)
}
#[doc = "ENET_RX_ER"]
#[inline]
pub fn enet_rx_er(self) -> &'a mut W {
self.variant(P1_14W::ENET_RX_ER)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_15`"]
pub enum P1_15W {
#[doc = "GPIO P1.15"]
GPIO_P1,
#[doc = "ENET_REF_CLK"]
ENET_REF_CLK,
}
impl P1_15W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_15W::GPIO_P1 => 0,
P1_15W::ENET_REF_CLK => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_15W<'a> {
w: &'a mut W,
}
impl<'a> _P1_15W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_15W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.15"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_15W::GPIO_P1)
}
#[doc = "ENET_REF_CLK"]
#[inline]
pub fn enet_ref_clk(self) -> &'a mut W {
self.variant(P1_15W::ENET_REF_CLK)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Pin function select P1.0."]
#[inline]
pub fn p1_0(&self) -> P1_0R {
P1_0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Pin function select P1.1."]
#[inline]
pub fn p1_1(&self) -> P1_1R {
P1_1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Pin function select P1.4."]
#[inline]
pub fn p1_4(&self) -> P1_4R {
P1_4R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Pin function select P1.8."]
#[inline]
pub fn p1_8(&self) -> P1_8R {
P1_8R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Pin function select P1.9."]
#[inline]
pub fn p1_9(&self) -> P1_9R {
P1_9R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Pin function select P1.10."]
#[inline]
pub fn p1_10(&self) -> P1_10R {
P1_10R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Pin function select P1.14."]
#[inline]
pub fn p1_14(&self) -> P1_14R {
P1_14R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Pin function select P1.15."]
#[inline]
pub fn p1_15(&self) -> P1_15R {
P1_15R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Pin function select P1.0."]
#[inline]
pub fn p1_0(&mut self) -> _P1_0W {
_P1_0W { w: self }
}
#[doc = "Bits 2:3 - Pin function select P1.1."]
#[inline]
pub fn p1_1(&mut self) -> _P1_1W {
_P1_1W { w: self }
}
#[doc = "Bits 8:9 - Pin function select P1.4."]
#[inline]
pub fn p1_4(&mut self) -> _P1_4W {
_P1_4W { w: self }
}
#[doc = "Bits 16:17 - Pin function select P1.8."]
#[inline]
pub fn p1_8(&mut self) -> _P1_8W {
_P1_8W { w: self }
}
#[doc = "Bits 18:19 - Pin function select P1.9."]
#[inline]
pub fn p1_9(&mut self) -> _P1_9W {
_P1_9W { w: self }
}
#[doc = "Bits 20:21 - Pin function select P1.10."]
#[inline]
pub fn p1_10(&mut self) -> _P1_10W {
_P1_10W { w: self }
}
#[doc = "Bits 22:23 - Pin function select P1.14."]
#[inline]
pub fn p1_14(&mut self) -> _P1_14W {
_P1_14W { w: self }
}
#[doc = "Bits 30:31 - Pin function select P1.15."]
#[inline]
pub fn p1_15(&mut self) -> _P1_15W {
_P1_15W { w: self }
}
}
}
#[doc = "Pin function select register 3."]
pub struct PINSEL3 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 3."]
pub mod pinsel3 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P1_16`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_16R {
#[doc = "GPIO P1.16"]
GPIO_P1,
#[doc = "ENET_MDC"]
ENET_MDC,
}
impl P1_16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_16R::GPIO_P1 => 0,
P1_16R::ENET_MDC => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_16R {
match value {
0 => P1_16R::GPIO_P1,
1 => P1_16R::ENET_MDC,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_16R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_MDC`"]
#[inline]
pub fn is_enet_mdc(&self) -> bool {
*self == P1_16R::ENET_MDC
}
}
#[doc = "Possible values of the field `P1_17`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_17R {
#[doc = "GPIO P1.17"]
GPIO_P1,
#[doc = "ENET_MDIO"]
ENET_MDIO,
}
impl P1_17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_17R::GPIO_P1 => 0,
P1_17R::ENET_MDIO => 0x01,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_17R {
match value {
0 => P1_17R::GPIO_P1,
1 => P1_17R::ENET_MDIO,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_17R::GPIO_P1
}
#[doc = "Checks if the value of the field is `ENET_MDIO`"]
#[inline]
pub fn is_enet_mdio(&self) -> bool {
*self == P1_17R::ENET_MDIO
}
}
#[doc = "Possible values of the field `P1_18`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_18R {
#[doc = "GPIO P1.18"]
GPIO_P1,
#[doc = "USB_UP_LED"]
USB_UP_LED,
#[doc = "PWM1.1"]
PWM1,
#[doc = "CAP1.0"]
CAP1,
}
impl P1_18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_18R::GPIO_P1 => 0,
P1_18R::USB_UP_LED => 0x01,
P1_18R::PWM1 => 0x02,
P1_18R::CAP1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_18R {
match value {
0 => P1_18R::GPIO_P1,
1 => P1_18R::USB_UP_LED,
2 => P1_18R::PWM1,
3 => P1_18R::CAP1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_18R::GPIO_P1
}
#[doc = "Checks if the value of the field is `USB_UP_LED`"]
#[inline]
pub fn is_usb_up_led(&self) -> bool {
*self == P1_18R::USB_UP_LED
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P1_18R::PWM1
}
#[doc = "Checks if the value of the field is `CAP1`"]
#[inline]
pub fn is_cap1(&self) -> bool {
*self == P1_18R::CAP1
}
}
#[doc = "Possible values of the field `P1_19`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_19R {
#[doc = "GPIO P1.19."]
GPIO_P1,
#[doc = "MCOA0"]
MCOA0,
#[doc = "USB_PPWR"]
USB_PPWR,
#[doc = "CAP1.1"]
CAP1,
}
impl P1_19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_19R::GPIO_P1 => 0,
P1_19R::MCOA0 => 0x01,
P1_19R::USB_PPWR => 0x02,
P1_19R::CAP1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_19R {
match value {
0 => P1_19R::GPIO_P1,
1 => P1_19R::MCOA0,
2 => P1_19R::USB_PPWR,
3 => P1_19R::CAP1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_19R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCOA0`"]
#[inline]
pub fn is_mcoa0(&self) -> bool {
*self == P1_19R::MCOA0
}
#[doc = "Checks if the value of the field is `USB_PPWR`"]
#[inline]
pub fn is_usb_ppwr(&self) -> bool {
*self == P1_19R::USB_PPWR
}
#[doc = "Checks if the value of the field is `CAP1`"]
#[inline]
pub fn is_cap1(&self) -> bool {
*self == P1_19R::CAP1
}
}
#[doc = "Possible values of the field `P1_20`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_20R {
#[doc = "GPIO P1.20."]
GPIO_P1,
#[doc = "MCI0"]
MCI0,
#[doc = "PWM1.2"]
PWM1,
#[doc = "SCK0"]
SCK0,
}
impl P1_20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_20R::GPIO_P1 => 0,
P1_20R::MCI0 => 0x01,
P1_20R::PWM1 => 0x02,
P1_20R::SCK0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_20R {
match value {
0 => P1_20R::GPIO_P1,
1 => P1_20R::MCI0,
2 => P1_20R::PWM1,
3 => P1_20R::SCK0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_20R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCI0`"]
#[inline]
pub fn is_mci0(&self) -> bool {
*self == P1_20R::MCI0
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P1_20R::PWM1
}
#[doc = "Checks if the value of the field is `SCK0`"]
#[inline]
pub fn is_sck0(&self) -> bool {
*self == P1_20R::SCK0
}
}
#[doc = "Possible values of the field `P1_21`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_21R {
#[doc = "GPIO P1.21."]
GPIO_P1,
#[doc = "MCABORT"]
MCABORT,
#[doc = "PWM1.3"]
PWM1,
#[doc = "SSEL0"]
SSEL0,
}
impl P1_21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_21R::GPIO_P1 => 0,
P1_21R::MCABORT => 0x01,
P1_21R::PWM1 => 0x02,
P1_21R::SSEL0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_21R {
match value {
0 => P1_21R::GPIO_P1,
1 => P1_21R::MCABORT,
2 => P1_21R::PWM1,
3 => P1_21R::SSEL0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_21R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCABORT`"]
#[inline]
pub fn is_mcabort(&self) -> bool {
*self == P1_21R::MCABORT
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P1_21R::PWM1
}
#[doc = "Checks if the value of the field is `SSEL0`"]
#[inline]
pub fn is_ssel0(&self) -> bool {
*self == P1_21R::SSEL0
}
}
#[doc = "Possible values of the field `P1_22`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_22R {
#[doc = "GPIO P1.22."]
GPIO_P1,
#[doc = "MCOB0"]
MCOB0,
#[doc = "USB_PWRD"]
USB_PWRD,
#[doc = "MAT1.0"]
MAT1,
}
impl P1_22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_22R::GPIO_P1 => 0,
P1_22R::MCOB0 => 0x01,
P1_22R::USB_PWRD => 0x02,
P1_22R::MAT1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_22R {
match value {
0 => P1_22R::GPIO_P1,
1 => P1_22R::MCOB0,
2 => P1_22R::USB_PWRD,
3 => P1_22R::MAT1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_22R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCOB0`"]
#[inline]
pub fn is_mcob0(&self) -> bool {
*self == P1_22R::MCOB0
}
#[doc = "Checks if the value of the field is `USB_PWRD`"]
#[inline]
pub fn is_usb_pwrd(&self) -> bool {
*self == P1_22R::USB_PWRD
}
#[doc = "Checks if the value of the field is `MAT1`"]
#[inline]
pub fn is_mat1(&self) -> bool {
*self == P1_22R::MAT1
}
}
#[doc = "Possible values of the field `P1_23`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_23R {
#[doc = "GPIO P1.23."]
GPIO_P1,
#[doc = "MCI1"]
MCI1,
#[doc = "PWM1.4"]
PWM1,
#[doc = "MISO0"]
MISO0,
}
impl P1_23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_23R::GPIO_P1 => 0,
P1_23R::MCI1 => 0x01,
P1_23R::PWM1 => 0x02,
P1_23R::MISO0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_23R {
match value {
0 => P1_23R::GPIO_P1,
1 => P1_23R::MCI1,
2 => P1_23R::PWM1,
3 => P1_23R::MISO0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_23R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCI1`"]
#[inline]
pub fn is_mci1(&self) -> bool {
*self == P1_23R::MCI1
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P1_23R::PWM1
}
#[doc = "Checks if the value of the field is `MISO0`"]
#[inline]
pub fn is_miso0(&self) -> bool {
*self == P1_23R::MISO0
}
}
#[doc = "Possible values of the field `P1_24`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_24R {
#[doc = "GPIO P1.24."]
GPIO_P1,
#[doc = "MCI2"]
MCI2,
#[doc = "PWM1.5"]
PWM1,
#[doc = "MOSI0"]
MOSI0,
}
impl P1_24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_24R::GPIO_P1 => 0,
P1_24R::MCI2 => 0x01,
P1_24R::PWM1 => 0x02,
P1_24R::MOSI0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_24R {
match value {
0 => P1_24R::GPIO_P1,
1 => P1_24R::MCI2,
2 => P1_24R::PWM1,
3 => P1_24R::MOSI0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_24R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCI2`"]
#[inline]
pub fn is_mci2(&self) -> bool {
*self == P1_24R::MCI2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P1_24R::PWM1
}
#[doc = "Checks if the value of the field is `MOSI0`"]
#[inline]
pub fn is_mosi0(&self) -> bool {
*self == P1_24R::MOSI0
}
}
#[doc = "Possible values of the field `P1_25`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_25R {
#[doc = "GPIO P1.25"]
GPIO_P1,
#[doc = "MCOA1"]
MCOA1,
#[doc = "MAT1.1"]
MAT1,
}
impl P1_25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_25R::GPIO_P1 => 0,
P1_25R::MCOA1 => 0x01,
P1_25R::MAT1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_25R {
match value {
0 => P1_25R::GPIO_P1,
1 => P1_25R::MCOA1,
3 => P1_25R::MAT1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_25R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCOA1`"]
#[inline]
pub fn is_mcoa1(&self) -> bool {
*self == P1_25R::MCOA1
}
#[doc = "Checks if the value of the field is `MAT1`"]
#[inline]
pub fn is_mat1(&self) -> bool {
*self == P1_25R::MAT1
}
}
#[doc = "Possible values of the field `P1_26`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_26R {
#[doc = "GPIO P1.26"]
GPIO_P1,
#[doc = "MCOB1"]
MCOB1,
#[doc = "PWM1.6"]
PWM1,
#[doc = "CAP0.0"]
CAP0,
}
impl P1_26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_26R::GPIO_P1 => 0,
P1_26R::MCOB1 => 0x01,
P1_26R::PWM1 => 0x02,
P1_26R::CAP0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_26R {
match value {
0 => P1_26R::GPIO_P1,
1 => P1_26R::MCOB1,
2 => P1_26R::PWM1,
3 => P1_26R::CAP0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_26R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCOB1`"]
#[inline]
pub fn is_mcob1(&self) -> bool {
*self == P1_26R::MCOB1
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P1_26R::PWM1
}
#[doc = "Checks if the value of the field is `CAP0`"]
#[inline]
pub fn is_cap0(&self) -> bool {
*self == P1_26R::CAP0
}
}
#[doc = "Possible values of the field `P1_27`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_27R {
#[doc = "GPIO P1.27"]
GPIO_P1,
#[doc = "CLKOUT"]
CLKOUT,
#[doc = "USB_OVRCR"]
USB_OVRCR,
#[doc = "CAP0.1"]
CAP0,
}
impl P1_27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_27R::GPIO_P1 => 0,
P1_27R::CLKOUT => 0x01,
P1_27R::USB_OVRCR => 0x02,
P1_27R::CAP0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_27R {
match value {
0 => P1_27R::GPIO_P1,
1 => P1_27R::CLKOUT,
2 => P1_27R::USB_OVRCR,
3 => P1_27R::CAP0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_27R::GPIO_P1
}
#[doc = "Checks if the value of the field is `CLKOUT`"]
#[inline]
pub fn is_clkout(&self) -> bool {
*self == P1_27R::CLKOUT
}
#[doc = "Checks if the value of the field is `USB_OVRCR`"]
#[inline]
pub fn is_usb_ovrcr(&self) -> bool {
*self == P1_27R::USB_OVRCR
}
#[doc = "Checks if the value of the field is `CAP0`"]
#[inline]
pub fn is_cap0(&self) -> bool {
*self == P1_27R::CAP0
}
}
#[doc = "Possible values of the field `P1_28`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_28R {
#[doc = "GPIO P1.28"]
GPIO_P1,
#[doc = "MCOA2"]
MCOA2,
#[doc = "PCAP1.0"]
PCAP1,
#[doc = "MAT0.0"]
MAT0,
}
impl P1_28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_28R::GPIO_P1 => 0,
P1_28R::MCOA2 => 0x01,
P1_28R::PCAP1 => 0x02,
P1_28R::MAT0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_28R {
match value {
0 => P1_28R::GPIO_P1,
1 => P1_28R::MCOA2,
2 => P1_28R::PCAP1,
3 => P1_28R::MAT0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_28R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCOA2`"]
#[inline]
pub fn is_mcoa2(&self) -> bool {
*self == P1_28R::MCOA2
}
#[doc = "Checks if the value of the field is `PCAP1`"]
#[inline]
pub fn is_pcap1(&self) -> bool {
*self == P1_28R::PCAP1
}
#[doc = "Checks if the value of the field is `MAT0`"]
#[inline]
pub fn is_mat0(&self) -> bool {
*self == P1_28R::MAT0
}
}
#[doc = "Possible values of the field `P1_29`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_29R {
#[doc = "GPIO P1.29"]
GPIO_P1,
#[doc = "MCOB2"]
MCOB2,
#[doc = "PCAP1.1"]
PCAP1,
#[doc = "MAT0.1"]
MAT0,
}
impl P1_29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_29R::GPIO_P1 => 0,
P1_29R::MCOB2 => 0x01,
P1_29R::PCAP1 => 0x02,
P1_29R::MAT0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_29R {
match value {
0 => P1_29R::GPIO_P1,
1 => P1_29R::MCOB2,
2 => P1_29R::PCAP1,
3 => P1_29R::MAT0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_29R::GPIO_P1
}
#[doc = "Checks if the value of the field is `MCOB2`"]
#[inline]
pub fn is_mcob2(&self) -> bool {
*self == P1_29R::MCOB2
}
#[doc = "Checks if the value of the field is `PCAP1`"]
#[inline]
pub fn is_pcap1(&self) -> bool {
*self == P1_29R::PCAP1
}
#[doc = "Checks if the value of the field is `MAT0`"]
#[inline]
pub fn is_mat0(&self) -> bool {
*self == P1_29R::MAT0
}
}
#[doc = "Possible values of the field `P1_30`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_30R {
#[doc = "GPIO P1.30"]
GPIO_P1,
#[doc = "VBUS"]
VBUS,
#[doc = "AD0.4"]
AD0,
}
impl P1_30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_30R::GPIO_P1 => 0,
P1_30R::VBUS => 0x02,
P1_30R::AD0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_30R {
match value {
0 => P1_30R::GPIO_P1,
2 => P1_30R::VBUS,
3 => P1_30R::AD0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P1`"]
#[inline]
pub fn is_gpio_p1(&self) -> bool {
*self == P1_30R::GPIO_P1
}
#[doc = "Checks if the value of the field is `VBUS`"]
#[inline]
pub fn is_vbus(&self) -> bool {
*self == P1_30R::VBUS
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P1_30R::AD0
}
}
#[doc = "Possible values of the field `P1_31`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_31R {
#[doc = "GPIO Port 1.31"]
GPIO_PORT_1,
#[doc = "SCK1"]
SCK1,
#[doc = "AD0.5"]
AD0,
}
impl P1_31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_31R::GPIO_PORT_1 => 0,
P1_31R::SCK1 => 0x02,
P1_31R::AD0 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_31R {
match value {
0 => P1_31R::GPIO_PORT_1,
2 => P1_31R::SCK1,
3 => P1_31R::AD0,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_PORT_1`"]
#[inline]
pub fn is_gpio_port_1(&self) -> bool {
*self == P1_31R::GPIO_PORT_1
}
#[doc = "Checks if the value of the field is `SCK1`"]
#[inline]
pub fn is_sck1(&self) -> bool {
*self == P1_31R::SCK1
}
#[doc = "Checks if the value of the field is `AD0`"]
#[inline]
pub fn is_ad0(&self) -> bool {
*self == P1_31R::AD0
}
}
#[doc = "Values that can be written to the field `P1_16`"]
pub enum P1_16W {
#[doc = "GPIO P1.16"]
GPIO_P1,
#[doc = "ENET_MDC"]
ENET_MDC,
}
impl P1_16W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_16W::GPIO_P1 => 0,
P1_16W::ENET_MDC => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_16W<'a> {
w: &'a mut W,
}
impl<'a> _P1_16W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_16W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.16"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_16W::GPIO_P1)
}
#[doc = "ENET_MDC"]
#[inline]
pub fn enet_mdc(self) -> &'a mut W {
self.variant(P1_16W::ENET_MDC)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_17`"]
pub enum P1_17W {
#[doc = "GPIO P1.17"]
GPIO_P1,
#[doc = "ENET_MDIO"]
ENET_MDIO,
}
impl P1_17W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_17W::GPIO_P1 => 0,
P1_17W::ENET_MDIO => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_17W<'a> {
w: &'a mut W,
}
impl<'a> _P1_17W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_17W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.17"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_17W::GPIO_P1)
}
#[doc = "ENET_MDIO"]
#[inline]
pub fn enet_mdio(self) -> &'a mut W {
self.variant(P1_17W::ENET_MDIO)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_18`"]
pub enum P1_18W {
#[doc = "GPIO P1.18"]
GPIO_P1,
#[doc = "USB_UP_LED"]
USB_UP_LED,
#[doc = "PWM1.1"]
PWM1,
#[doc = "CAP1.0"]
CAP1,
}
impl P1_18W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_18W::GPIO_P1 => 0,
P1_18W::USB_UP_LED => 1,
P1_18W::PWM1 => 2,
P1_18W::CAP1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_18W<'a> {
w: &'a mut W,
}
impl<'a> _P1_18W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_18W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.18"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_18W::GPIO_P1)
}
#[doc = "USB_UP_LED"]
#[inline]
pub fn usb_up_led(self) -> &'a mut W {
self.variant(P1_18W::USB_UP_LED)
}
#[doc = "PWM1.1"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P1_18W::PWM1)
}
#[doc = "CAP1.0"]
#[inline]
pub fn cap1(self) -> &'a mut W {
self.variant(P1_18W::CAP1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_19`"]
pub enum P1_19W {
#[doc = "GPIO P1.19."]
GPIO_P1,
#[doc = "MCOA0"]
MCOA0,
#[doc = "USB_PPWR"]
USB_PPWR,
#[doc = "CAP1.1"]
CAP1,
}
impl P1_19W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_19W::GPIO_P1 => 0,
P1_19W::MCOA0 => 1,
P1_19W::USB_PPWR => 2,
P1_19W::CAP1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_19W<'a> {
w: &'a mut W,
}
impl<'a> _P1_19W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_19W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.19."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_19W::GPIO_P1)
}
#[doc = "MCOA0"]
#[inline]
pub fn mcoa0(self) -> &'a mut W {
self.variant(P1_19W::MCOA0)
}
#[doc = "USB_PPWR"]
#[inline]
pub fn usb_ppwr(self) -> &'a mut W {
self.variant(P1_19W::USB_PPWR)
}
#[doc = "CAP1.1"]
#[inline]
pub fn cap1(self) -> &'a mut W {
self.variant(P1_19W::CAP1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_20`"]
pub enum P1_20W {
#[doc = "GPIO P1.20."]
GPIO_P1,
#[doc = "MCI0"]
MCI0,
#[doc = "PWM1.2"]
PWM1,
#[doc = "SCK0"]
SCK0,
}
impl P1_20W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_20W::GPIO_P1 => 0,
P1_20W::MCI0 => 1,
P1_20W::PWM1 => 2,
P1_20W::SCK0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_20W<'a> {
w: &'a mut W,
}
impl<'a> _P1_20W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_20W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.20."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_20W::GPIO_P1)
}
#[doc = "MCI0"]
#[inline]
pub fn mci0(self) -> &'a mut W {
self.variant(P1_20W::MCI0)
}
#[doc = "PWM1.2"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P1_20W::PWM1)
}
#[doc = "SCK0"]
#[inline]
pub fn sck0(self) -> &'a mut W {
self.variant(P1_20W::SCK0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_21`"]
pub enum P1_21W {
#[doc = "GPIO P1.21."]
GPIO_P1,
#[doc = "MCABORT"]
MCABORT,
#[doc = "PWM1.3"]
PWM1,
#[doc = "SSEL0"]
SSEL0,
}
impl P1_21W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_21W::GPIO_P1 => 0,
P1_21W::MCABORT => 1,
P1_21W::PWM1 => 2,
P1_21W::SSEL0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_21W<'a> {
w: &'a mut W,
}
impl<'a> _P1_21W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_21W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.21."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_21W::GPIO_P1)
}
#[doc = "MCABORT"]
#[inline]
pub fn mcabort(self) -> &'a mut W {
self.variant(P1_21W::MCABORT)
}
#[doc = "PWM1.3"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P1_21W::PWM1)
}
#[doc = "SSEL0"]
#[inline]
pub fn ssel0(self) -> &'a mut W {
self.variant(P1_21W::SSEL0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_22`"]
pub enum P1_22W {
#[doc = "GPIO P1.22."]
GPIO_P1,
#[doc = "MCOB0"]
MCOB0,
#[doc = "USB_PWRD"]
USB_PWRD,
#[doc = "MAT1.0"]
MAT1,
}
impl P1_22W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_22W::GPIO_P1 => 0,
P1_22W::MCOB0 => 1,
P1_22W::USB_PWRD => 2,
P1_22W::MAT1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_22W<'a> {
w: &'a mut W,
}
impl<'a> _P1_22W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_22W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.22."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_22W::GPIO_P1)
}
#[doc = "MCOB0"]
#[inline]
pub fn mcob0(self) -> &'a mut W {
self.variant(P1_22W::MCOB0)
}
#[doc = "USB_PWRD"]
#[inline]
pub fn usb_pwrd(self) -> &'a mut W {
self.variant(P1_22W::USB_PWRD)
}
#[doc = "MAT1.0"]
#[inline]
pub fn mat1(self) -> &'a mut W {
self.variant(P1_22W::MAT1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_23`"]
pub enum P1_23W {
#[doc = "GPIO P1.23."]
GPIO_P1,
#[doc = "MCI1"]
MCI1,
#[doc = "PWM1.4"]
PWM1,
#[doc = "MISO0"]
MISO0,
}
impl P1_23W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_23W::GPIO_P1 => 0,
P1_23W::MCI1 => 1,
P1_23W::PWM1 => 2,
P1_23W::MISO0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_23W<'a> {
w: &'a mut W,
}
impl<'a> _P1_23W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_23W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.23."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_23W::GPIO_P1)
}
#[doc = "MCI1"]
#[inline]
pub fn mci1(self) -> &'a mut W {
self.variant(P1_23W::MCI1)
}
#[doc = "PWM1.4"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P1_23W::PWM1)
}
#[doc = "MISO0"]
#[inline]
pub fn miso0(self) -> &'a mut W {
self.variant(P1_23W::MISO0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_24`"]
pub enum P1_24W {
#[doc = "GPIO P1.24."]
GPIO_P1,
#[doc = "MCI2"]
MCI2,
#[doc = "PWM1.5"]
PWM1,
#[doc = "MOSI0"]
MOSI0,
}
impl P1_24W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_24W::GPIO_P1 => 0,
P1_24W::MCI2 => 1,
P1_24W::PWM1 => 2,
P1_24W::MOSI0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_24W<'a> {
w: &'a mut W,
}
impl<'a> _P1_24W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_24W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.24."]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_24W::GPIO_P1)
}
#[doc = "MCI2"]
#[inline]
pub fn mci2(self) -> &'a mut W {
self.variant(P1_24W::MCI2)
}
#[doc = "PWM1.5"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P1_24W::PWM1)
}
#[doc = "MOSI0"]
#[inline]
pub fn mosi0(self) -> &'a mut W {
self.variant(P1_24W::MOSI0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_25`"]
pub enum P1_25W {
#[doc = "GPIO P1.25"]
GPIO_P1,
#[doc = "MCOA1"]
MCOA1,
#[doc = "MAT1.1"]
MAT1,
}
impl P1_25W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_25W::GPIO_P1 => 0,
P1_25W::MCOA1 => 1,
P1_25W::MAT1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_25W<'a> {
w: &'a mut W,
}
impl<'a> _P1_25W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_25W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.25"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_25W::GPIO_P1)
}
#[doc = "MCOA1"]
#[inline]
pub fn mcoa1(self) -> &'a mut W {
self.variant(P1_25W::MCOA1)
}
#[doc = "MAT1.1"]
#[inline]
pub fn mat1(self) -> &'a mut W {
self.variant(P1_25W::MAT1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_26`"]
pub enum P1_26W {
#[doc = "GPIO P1.26"]
GPIO_P1,
#[doc = "MCOB1"]
MCOB1,
#[doc = "PWM1.6"]
PWM1,
#[doc = "CAP0.0"]
CAP0,
}
impl P1_26W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_26W::GPIO_P1 => 0,
P1_26W::MCOB1 => 1,
P1_26W::PWM1 => 2,
P1_26W::CAP0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_26W<'a> {
w: &'a mut W,
}
impl<'a> _P1_26W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_26W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.26"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_26W::GPIO_P1)
}
#[doc = "MCOB1"]
#[inline]
pub fn mcob1(self) -> &'a mut W {
self.variant(P1_26W::MCOB1)
}
#[doc = "PWM1.6"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P1_26W::PWM1)
}
#[doc = "CAP0.0"]
#[inline]
pub fn cap0(self) -> &'a mut W {
self.variant(P1_26W::CAP0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_27`"]
pub enum P1_27W {
#[doc = "GPIO P1.27"]
GPIO_P1,
#[doc = "CLKOUT"]
CLKOUT,
#[doc = "USB_OVRCR"]
USB_OVRCR,
#[doc = "CAP0.1"]
CAP0,
}
impl P1_27W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_27W::GPIO_P1 => 0,
P1_27W::CLKOUT => 1,
P1_27W::USB_OVRCR => 2,
P1_27W::CAP0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_27W<'a> {
w: &'a mut W,
}
impl<'a> _P1_27W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_27W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.27"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_27W::GPIO_P1)
}
#[doc = "CLKOUT"]
#[inline]
pub fn clkout(self) -> &'a mut W {
self.variant(P1_27W::CLKOUT)
}
#[doc = "USB_OVRCR"]
#[inline]
pub fn usb_ovrcr(self) -> &'a mut W {
self.variant(P1_27W::USB_OVRCR)
}
#[doc = "CAP0.1"]
#[inline]
pub fn cap0(self) -> &'a mut W {
self.variant(P1_27W::CAP0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_28`"]
pub enum P1_28W {
#[doc = "GPIO P1.28"]
GPIO_P1,
#[doc = "MCOA2"]
MCOA2,
#[doc = "PCAP1.0"]
PCAP1,
#[doc = "MAT0.0"]
MAT0,
}
impl P1_28W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_28W::GPIO_P1 => 0,
P1_28W::MCOA2 => 1,
P1_28W::PCAP1 => 2,
P1_28W::MAT0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_28W<'a> {
w: &'a mut W,
}
impl<'a> _P1_28W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_28W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.28"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_28W::GPIO_P1)
}
#[doc = "MCOA2"]
#[inline]
pub fn mcoa2(self) -> &'a mut W {
self.variant(P1_28W::MCOA2)
}
#[doc = "PCAP1.0"]
#[inline]
pub fn pcap1(self) -> &'a mut W {
self.variant(P1_28W::PCAP1)
}
#[doc = "MAT0.0"]
#[inline]
pub fn mat0(self) -> &'a mut W {
self.variant(P1_28W::MAT0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_29`"]
pub enum P1_29W {
#[doc = "GPIO P1.29"]
GPIO_P1,
#[doc = "MCOB2"]
MCOB2,
#[doc = "PCAP1.1"]
PCAP1,
#[doc = "MAT0.1"]
MAT0,
}
impl P1_29W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_29W::GPIO_P1 => 0,
P1_29W::MCOB2 => 1,
P1_29W::PCAP1 => 2,
P1_29W::MAT0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_29W<'a> {
w: &'a mut W,
}
impl<'a> _P1_29W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_29W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P1.29"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_29W::GPIO_P1)
}
#[doc = "MCOB2"]
#[inline]
pub fn mcob2(self) -> &'a mut W {
self.variant(P1_29W::MCOB2)
}
#[doc = "PCAP1.1"]
#[inline]
pub fn pcap1(self) -> &'a mut W {
self.variant(P1_29W::PCAP1)
}
#[doc = "MAT0.1"]
#[inline]
pub fn mat0(self) -> &'a mut W {
self.variant(P1_29W::MAT0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_30`"]
pub enum P1_30W {
#[doc = "GPIO P1.30"]
GPIO_P1,
#[doc = "VBUS"]
VBUS,
#[doc = "AD0.4"]
AD0,
}
impl P1_30W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_30W::GPIO_P1 => 0,
P1_30W::VBUS => 2,
P1_30W::AD0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_30W<'a> {
w: &'a mut W,
}
impl<'a> _P1_30W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_30W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P1.30"]
#[inline]
pub fn gpio_p1(self) -> &'a mut W {
self.variant(P1_30W::GPIO_P1)
}
#[doc = "VBUS"]
#[inline]
pub fn vbus(self) -> &'a mut W {
self.variant(P1_30W::VBUS)
}
#[doc = "AD0.4"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P1_30W::AD0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_31`"]
pub enum P1_31W {
#[doc = "GPIO Port 1.31"]
GPIO_PORT_1,
#[doc = "SCK1"]
SCK1,
#[doc = "AD0.5"]
AD0,
}
impl P1_31W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_31W::GPIO_PORT_1 => 0,
P1_31W::SCK1 => 2,
P1_31W::AD0 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_31W<'a> {
w: &'a mut W,
}
impl<'a> _P1_31W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_31W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO Port 1.31"]
#[inline]
pub fn gpio_port_1(self) -> &'a mut W {
self.variant(P1_31W::GPIO_PORT_1)
}
#[doc = "SCK1"]
#[inline]
pub fn sck1(self) -> &'a mut W {
self.variant(P1_31W::SCK1)
}
#[doc = "AD0.5"]
#[inline]
pub fn ad0(self) -> &'a mut W {
self.variant(P1_31W::AD0)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Pin function select P1.16."]
#[inline]
pub fn p1_16(&self) -> P1_16R {
P1_16R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Pin function select P1.17."]
#[inline]
pub fn p1_17(&self) -> P1_17R {
P1_17R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Pin function select P1.18."]
#[inline]
pub fn p1_18(&self) -> P1_18R {
P1_18R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Pin function select P1.19."]
#[inline]
pub fn p1_19(&self) -> P1_19R {
P1_19R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Pin function select P1.20."]
#[inline]
pub fn p1_20(&self) -> P1_20R {
P1_20R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Pin function select P1.21."]
#[inline]
pub fn p1_21(&self) -> P1_21R {
P1_21R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Pin function select P1.22"]
#[inline]
pub fn p1_22(&self) -> P1_22R {
P1_22R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Pin function select P1.23."]
#[inline]
pub fn p1_23(&self) -> P1_23R {
P1_23R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Pin function select P1.24."]
#[inline]
pub fn p1_24(&self) -> P1_24R {
P1_24R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Pin function select P1.25."]
#[inline]
pub fn p1_25(&self) -> P1_25R {
P1_25R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Pin function select P1.26."]
#[inline]
pub fn p1_26(&self) -> P1_26R {
P1_26R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Pin function select P1.27."]
#[inline]
pub fn p1_27(&self) -> P1_27R {
P1_27R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:25 - Pin function select P1.28."]
#[inline]
pub fn p1_28(&self) -> P1_28R {
P1_28R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Pin function select P1.29"]
#[inline]
pub fn p1_29(&self) -> P1_29R {
P1_29R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 28:29 - Pin function select P1.30."]
#[inline]
pub fn p1_30(&self) -> P1_30R {
P1_30R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Pin function select P1.31."]
#[inline]
pub fn p1_31(&self) -> P1_31R {
P1_31R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Pin function select P1.16."]
#[inline]
pub fn p1_16(&mut self) -> _P1_16W {
_P1_16W { w: self }
}
#[doc = "Bits 2:3 - Pin function select P1.17."]
#[inline]
pub fn p1_17(&mut self) -> _P1_17W {
_P1_17W { w: self }
}
#[doc = "Bits 4:5 - Pin function select P1.18."]
#[inline]
pub fn p1_18(&mut self) -> _P1_18W {
_P1_18W { w: self }
}
#[doc = "Bits 6:7 - Pin function select P1.19."]
#[inline]
pub fn p1_19(&mut self) -> _P1_19W {
_P1_19W { w: self }
}
#[doc = "Bits 8:9 - Pin function select P1.20."]
#[inline]
pub fn p1_20(&mut self) -> _P1_20W {
_P1_20W { w: self }
}
#[doc = "Bits 10:11 - Pin function select P1.21."]
#[inline]
pub fn p1_21(&mut self) -> _P1_21W {
_P1_21W { w: self }
}
#[doc = "Bits 12:13 - Pin function select P1.22"]
#[inline]
pub fn p1_22(&mut self) -> _P1_22W {
_P1_22W { w: self }
}
#[doc = "Bits 14:15 - Pin function select P1.23."]
#[inline]
pub fn p1_23(&mut self) -> _P1_23W {
_P1_23W { w: self }
}
#[doc = "Bits 16:17 - Pin function select P1.24."]
#[inline]
pub fn p1_24(&mut self) -> _P1_24W {
_P1_24W { w: self }
}
#[doc = "Bits 18:19 - Pin function select P1.25."]
#[inline]
pub fn p1_25(&mut self) -> _P1_25W {
_P1_25W { w: self }
}
#[doc = "Bits 20:21 - Pin function select P1.26."]
#[inline]
pub fn p1_26(&mut self) -> _P1_26W {
_P1_26W { w: self }
}
#[doc = "Bits 22:23 - Pin function select P1.27."]
#[inline]
pub fn p1_27(&mut self) -> _P1_27W {
_P1_27W { w: self }
}
#[doc = "Bits 24:25 - Pin function select P1.28."]
#[inline]
pub fn p1_28(&mut self) -> _P1_28W {
_P1_28W { w: self }
}
#[doc = "Bits 26:27 - Pin function select P1.29"]
#[inline]
pub fn p1_29(&mut self) -> _P1_29W {
_P1_29W { w: self }
}
#[doc = "Bits 28:29 - Pin function select P1.30."]
#[inline]
pub fn p1_30(&mut self) -> _P1_30W {
_P1_30W { w: self }
}
#[doc = "Bits 30:31 - Pin function select P1.31."]
#[inline]
pub fn p1_31(&mut self) -> _P1_31W {
_P1_31W { w: self }
}
}
}
#[doc = "Pin function select register 4"]
pub struct PINSEL4 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 4"]
pub mod pinsel4 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL4 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P2_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_0R {
#[doc = "GPIO P2.0"]
GPIO_P2,
#[doc = "PWM1.1"]
PWM1,
#[doc = "TXD1"]
TXD1,
}
impl P2_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_0R::GPIO_P2 => 0,
P2_0R::PWM1 => 0x01,
P2_0R::TXD1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_0R {
match value {
0 => P2_0R::GPIO_P2,
1 => P2_0R::PWM1,
2 => P2_0R::TXD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_0R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P2_0R::PWM1
}
#[doc = "Checks if the value of the field is `TXD1`"]
#[inline]
pub fn is_txd1(&self) -> bool {
*self == P2_0R::TXD1
}
}
#[doc = "Possible values of the field `P2_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_1R {
#[doc = "GPIO P2.1"]
GPIO_P2,
#[doc = "PWM1.2"]
PWM1,
#[doc = "RXD1"]
RXD1,
}
impl P2_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_1R::GPIO_P2 => 0,
P2_1R::PWM1 => 0x01,
P2_1R::RXD1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_1R {
match value {
0 => P2_1R::GPIO_P2,
1 => P2_1R::PWM1,
2 => P2_1R::RXD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_1R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P2_1R::PWM1
}
#[doc = "Checks if the value of the field is `RXD1`"]
#[inline]
pub fn is_rxd1(&self) -> bool {
*self == P2_1R::RXD1
}
}
#[doc = "Possible values of the field `P2_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_2R {
#[doc = "GPIO P2.2"]
GPIO_P2,
#[doc = "PWM1.3"]
PWM1,
#[doc = "CTS1"]
CTS1,
}
impl P2_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_2R::GPIO_P2 => 0,
P2_2R::PWM1 => 0x01,
P2_2R::CTS1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_2R {
match value {
0 => P2_2R::GPIO_P2,
1 => P2_2R::PWM1,
2 => P2_2R::CTS1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_2R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P2_2R::PWM1
}
#[doc = "Checks if the value of the field is `CTS1`"]
#[inline]
pub fn is_cts1(&self) -> bool {
*self == P2_2R::CTS1
}
}
#[doc = "Possible values of the field `P2_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_3R {
#[doc = "GPIO P2.3."]
GPIO_P2,
#[doc = "PWM1.4"]
PWM1,
#[doc = "DCD1"]
DCD1,
}
impl P2_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_3R::GPIO_P2 => 0,
P2_3R::PWM1 => 0x01,
P2_3R::DCD1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_3R {
match value {
0 => P2_3R::GPIO_P2,
1 => P2_3R::PWM1,
2 => P2_3R::DCD1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_3R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P2_3R::PWM1
}
#[doc = "Checks if the value of the field is `DCD1`"]
#[inline]
pub fn is_dcd1(&self) -> bool {
*self == P2_3R::DCD1
}
}
#[doc = "Possible values of the field `P2_4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_4R {
#[doc = "GPIO P2.4."]
GPIO_P2,
#[doc = "PWM1.5"]
PWM1,
#[doc = "DSR1"]
DSR1,
}
impl P2_4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_4R::GPIO_P2 => 0,
P2_4R::PWM1 => 0x01,
P2_4R::DSR1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_4R {
match value {
0 => P2_4R::GPIO_P2,
1 => P2_4R::PWM1,
2 => P2_4R::DSR1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_4R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P2_4R::PWM1
}
#[doc = "Checks if the value of the field is `DSR1`"]
#[inline]
pub fn is_dsr1(&self) -> bool {
*self == P2_4R::DSR1
}
}
#[doc = "Possible values of the field `P2_5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_5R {
#[doc = "GPIO P2.5."]
GPIO_P2,
#[doc = "PWM1.6"]
PWM1,
#[doc = "DTR1"]
DTR1,
}
impl P2_5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_5R::GPIO_P2 => 0,
P2_5R::PWM1 => 0x01,
P2_5R::DTR1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_5R {
match value {
0 => P2_5R::GPIO_P2,
1 => P2_5R::PWM1,
2 => P2_5R::DTR1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_5R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P2_5R::PWM1
}
#[doc = "Checks if the value of the field is `DTR1`"]
#[inline]
pub fn is_dtr1(&self) -> bool {
*self == P2_5R::DTR1
}
}
#[doc = "Possible values of the field `P2_6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_6R {
#[doc = "GPIO P2.6."]
GPIO_P2,
#[doc = "PCAP1.0"]
PCAP1,
#[doc = "RI1"]
RI1,
}
impl P2_6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_6R::GPIO_P2 => 0,
P2_6R::PCAP1 => 0x01,
P2_6R::RI1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_6R {
match value {
0 => P2_6R::GPIO_P2,
1 => P2_6R::PCAP1,
2 => P2_6R::RI1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_6R::GPIO_P2
}
#[doc = "Checks if the value of the field is `PCAP1`"]
#[inline]
pub fn is_pcap1(&self) -> bool {
*self == P2_6R::PCAP1
}
#[doc = "Checks if the value of the field is `RI1`"]
#[inline]
pub fn is_ri1(&self) -> bool {
*self == P2_6R::RI1
}
}
#[doc = "Possible values of the field `P2_7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_7R {
#[doc = "GPIO P2.7."]
GPIO_P2,
#[doc = "RD2"]
RD2,
#[doc = "RTS1"]
RTS1,
}
impl P2_7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_7R::GPIO_P2 => 0,
P2_7R::RD2 => 0x01,
P2_7R::RTS1 => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_7R {
match value {
0 => P2_7R::GPIO_P2,
1 => P2_7R::RD2,
2 => P2_7R::RTS1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_7R::GPIO_P2
}
#[doc = "Checks if the value of the field is `RD2`"]
#[inline]
pub fn is_rd2(&self) -> bool {
*self == P2_7R::RD2
}
#[doc = "Checks if the value of the field is `RTS1`"]
#[inline]
pub fn is_rts1(&self) -> bool {
*self == P2_7R::RTS1
}
}
#[doc = "Possible values of the field `P2_8`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_8R {
#[doc = "GPIO P2.8."]
GPIO_P2,
#[doc = "TD2"]
TD2,
#[doc = "TXD2"]
TXD2,
#[doc = "ENET_MDC"]
ENET_MDC,
}
impl P2_8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_8R::GPIO_P2 => 0,
P2_8R::TD2 => 0x01,
P2_8R::TXD2 => 0x02,
P2_8R::ENET_MDC => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_8R {
match value {
0 => P2_8R::GPIO_P2,
1 => P2_8R::TD2,
2 => P2_8R::TXD2,
3 => P2_8R::ENET_MDC,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_8R::GPIO_P2
}
#[doc = "Checks if the value of the field is `TD2`"]
#[inline]
pub fn is_td2(&self) -> bool {
*self == P2_8R::TD2
}
#[doc = "Checks if the value of the field is `TXD2`"]
#[inline]
pub fn is_txd2(&self) -> bool {
*self == P2_8R::TXD2
}
#[doc = "Checks if the value of the field is `ENET_MDC`"]
#[inline]
pub fn is_enet_mdc(&self) -> bool {
*self == P2_8R::ENET_MDC
}
}
#[doc = "Possible values of the field `P2_9`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_9R {
#[doc = "GPIO P2.9"]
GPIO_P2,
#[doc = "USB_CONNECT"]
USB_CONNECT,
#[doc = "RXD2"]
RXD2,
#[doc = "ENET_MDIO"]
ENET_MDIO,
}
impl P2_9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_9R::GPIO_P2 => 0,
P2_9R::USB_CONNECT => 0x01,
P2_9R::RXD2 => 0x02,
P2_9R::ENET_MDIO => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_9R {
match value {
0 => P2_9R::GPIO_P2,
1 => P2_9R::USB_CONNECT,
2 => P2_9R::RXD2,
3 => P2_9R::ENET_MDIO,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_9R::GPIO_P2
}
#[doc = "Checks if the value of the field is `USB_CONNECT`"]
#[inline]
pub fn is_usb_connect(&self) -> bool {
*self == P2_9R::USB_CONNECT
}
#[doc = "Checks if the value of the field is `RXD2`"]
#[inline]
pub fn is_rxd2(&self) -> bool {
*self == P2_9R::RXD2
}
#[doc = "Checks if the value of the field is `ENET_MDIO`"]
#[inline]
pub fn is_enet_mdio(&self) -> bool {
*self == P2_9R::ENET_MDIO
}
}
#[doc = "Possible values of the field `P2_10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_10R {
#[doc = "GPIO P2.10"]
GPIO_P2,
#[doc = "EINT0"]
EINT0,
#[doc = "NMI"]
NMI,
}
impl P2_10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_10R::GPIO_P2 => 0,
P2_10R::EINT0 => 0x01,
P2_10R::NMI => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_10R {
match value {
0 => P2_10R::GPIO_P2,
1 => P2_10R::EINT0,
2 => P2_10R::NMI,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_10R::GPIO_P2
}
#[doc = "Checks if the value of the field is `EINT0`"]
#[inline]
pub fn is_eint0(&self) -> bool {
*self == P2_10R::EINT0
}
#[doc = "Checks if the value of the field is `NMI`"]
#[inline]
pub fn is_nmi(&self) -> bool {
*self == P2_10R::NMI
}
}
#[doc = "Possible values of the field `P2_11`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_11R {
#[doc = "GPIO P2.11"]
GPIO_P2,
#[doc = "EINT1"]
EINT1,
#[doc = "I2STX_CLK"]
I2STX_CLK,
}
impl P2_11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_11R::GPIO_P2 => 0,
P2_11R::EINT1 => 0x01,
P2_11R::I2STX_CLK => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_11R {
match value {
0 => P2_11R::GPIO_P2,
1 => P2_11R::EINT1,
3 => P2_11R::I2STX_CLK,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_11R::GPIO_P2
}
#[doc = "Checks if the value of the field is `EINT1`"]
#[inline]
pub fn is_eint1(&self) -> bool {
*self == P2_11R::EINT1
}
#[doc = "Checks if the value of the field is `I2STX_CLK`"]
#[inline]
pub fn is_i2stx_clk(&self) -> bool {
*self == P2_11R::I2STX_CLK
}
}
#[doc = "Possible values of the field `P2_12`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_12R {
#[doc = "GPIO P2.12"]
GPIO_P2,
#[doc = "EINT2"]
EINT2,
#[doc = "I2STX_WS"]
I2STX_WS,
}
impl P2_12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_12R::GPIO_P2 => 0,
P2_12R::EINT2 => 0x01,
P2_12R::I2STX_WS => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_12R {
match value {
0 => P2_12R::GPIO_P2,
1 => P2_12R::EINT2,
3 => P2_12R::I2STX_WS,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_12R::GPIO_P2
}
#[doc = "Checks if the value of the field is `EINT2`"]
#[inline]
pub fn is_eint2(&self) -> bool {
*self == P2_12R::EINT2
}
#[doc = "Checks if the value of the field is `I2STX_WS`"]
#[inline]
pub fn is_i2stx_ws(&self) -> bool {
*self == P2_12R::I2STX_WS
}
}
#[doc = "Possible values of the field `P2_13`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_13R {
#[doc = "GPIO P2.13"]
GPIO_P2,
#[doc = "EINT3"]
EINT3,
#[doc = "I2STX_SDA"]
I2STX_SDA,
}
impl P2_13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_13R::GPIO_P2 => 0,
P2_13R::EINT3 => 0x01,
P2_13R::I2STX_SDA => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_13R {
match value {
0 => P2_13R::GPIO_P2,
1 => P2_13R::EINT3,
3 => P2_13R::I2STX_SDA,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P2`"]
#[inline]
pub fn is_gpio_p2(&self) -> bool {
*self == P2_13R::GPIO_P2
}
#[doc = "Checks if the value of the field is `EINT3`"]
#[inline]
pub fn is_eint3(&self) -> bool {
*self == P2_13R::EINT3
}
#[doc = "Checks if the value of the field is `I2STX_SDA`"]
#[inline]
pub fn is_i2stx_sda(&self) -> bool {
*self == P2_13R::I2STX_SDA
}
}
#[doc = "Values that can be written to the field `P2_0`"]
pub enum P2_0W {
#[doc = "GPIO P2.0"]
GPIO_P2,
#[doc = "PWM1.1"]
PWM1,
#[doc = "TXD1"]
TXD1,
}
impl P2_0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_0W::GPIO_P2 => 0,
P2_0W::PWM1 => 1,
P2_0W::TXD1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_0W<'a> {
w: &'a mut W,
}
impl<'a> _P2_0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_0W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.0"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_0W::GPIO_P2)
}
#[doc = "PWM1.1"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P2_0W::PWM1)
}
#[doc = "TXD1"]
#[inline]
pub fn txd1(self) -> &'a mut W {
self.variant(P2_0W::TXD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_1`"]
pub enum P2_1W {
#[doc = "GPIO P2.1"]
GPIO_P2,
#[doc = "PWM1.2"]
PWM1,
#[doc = "RXD1"]
RXD1,
}
impl P2_1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_1W::GPIO_P2 => 0,
P2_1W::PWM1 => 1,
P2_1W::RXD1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_1W<'a> {
w: &'a mut W,
}
impl<'a> _P2_1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_1W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.1"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_1W::GPIO_P2)
}
#[doc = "PWM1.2"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P2_1W::PWM1)
}
#[doc = "RXD1"]
#[inline]
pub fn rxd1(self) -> &'a mut W {
self.variant(P2_1W::RXD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_2`"]
pub enum P2_2W {
#[doc = "GPIO P2.2"]
GPIO_P2,
#[doc = "PWM1.3"]
PWM1,
#[doc = "CTS1"]
CTS1,
}
impl P2_2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_2W::GPIO_P2 => 0,
P2_2W::PWM1 => 1,
P2_2W::CTS1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_2W<'a> {
w: &'a mut W,
}
impl<'a> _P2_2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_2W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.2"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_2W::GPIO_P2)
}
#[doc = "PWM1.3"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P2_2W::PWM1)
}
#[doc = "CTS1"]
#[inline]
pub fn cts1(self) -> &'a mut W {
self.variant(P2_2W::CTS1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_3`"]
pub enum P2_3W {
#[doc = "GPIO P2.3."]
GPIO_P2,
#[doc = "PWM1.4"]
PWM1,
#[doc = "DCD1"]
DCD1,
}
impl P2_3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_3W::GPIO_P2 => 0,
P2_3W::PWM1 => 1,
P2_3W::DCD1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_3W<'a> {
w: &'a mut W,
}
impl<'a> _P2_3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_3W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.3."]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_3W::GPIO_P2)
}
#[doc = "PWM1.4"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P2_3W::PWM1)
}
#[doc = "DCD1"]
#[inline]
pub fn dcd1(self) -> &'a mut W {
self.variant(P2_3W::DCD1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_4`"]
pub enum P2_4W {
#[doc = "GPIO P2.4."]
GPIO_P2,
#[doc = "PWM1.5"]
PWM1,
#[doc = "DSR1"]
DSR1,
}
impl P2_4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_4W::GPIO_P2 => 0,
P2_4W::PWM1 => 1,
P2_4W::DSR1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_4W<'a> {
w: &'a mut W,
}
impl<'a> _P2_4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_4W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.4."]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_4W::GPIO_P2)
}
#[doc = "PWM1.5"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P2_4W::PWM1)
}
#[doc = "DSR1"]
#[inline]
pub fn dsr1(self) -> &'a mut W {
self.variant(P2_4W::DSR1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_5`"]
pub enum P2_5W {
#[doc = "GPIO P2.5."]
GPIO_P2,
#[doc = "PWM1.6"]
PWM1,
#[doc = "DTR1"]
DTR1,
}
impl P2_5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_5W::GPIO_P2 => 0,
P2_5W::PWM1 => 1,
P2_5W::DTR1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_5W<'a> {
w: &'a mut W,
}
impl<'a> _P2_5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_5W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.5."]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_5W::GPIO_P2)
}
#[doc = "PWM1.6"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P2_5W::PWM1)
}
#[doc = "DTR1"]
#[inline]
pub fn dtr1(self) -> &'a mut W {
self.variant(P2_5W::DTR1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_6`"]
pub enum P2_6W {
#[doc = "GPIO P2.6."]
GPIO_P2,
#[doc = "PCAP1.0"]
PCAP1,
#[doc = "RI1"]
RI1,
}
impl P2_6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_6W::GPIO_P2 => 0,
P2_6W::PCAP1 => 1,
P2_6W::RI1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_6W<'a> {
w: &'a mut W,
}
impl<'a> _P2_6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_6W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.6."]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_6W::GPIO_P2)
}
#[doc = "PCAP1.0"]
#[inline]
pub fn pcap1(self) -> &'a mut W {
self.variant(P2_6W::PCAP1)
}
#[doc = "RI1"]
#[inline]
pub fn ri1(self) -> &'a mut W {
self.variant(P2_6W::RI1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_7`"]
pub enum P2_7W {
#[doc = "GPIO P2.7."]
GPIO_P2,
#[doc = "RD2"]
RD2,
#[doc = "RTS1"]
RTS1,
}
impl P2_7W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_7W::GPIO_P2 => 0,
P2_7W::RD2 => 1,
P2_7W::RTS1 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_7W<'a> {
w: &'a mut W,
}
impl<'a> _P2_7W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_7W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.7."]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_7W::GPIO_P2)
}
#[doc = "RD2"]
#[inline]
pub fn rd2(self) -> &'a mut W {
self.variant(P2_7W::RD2)
}
#[doc = "RTS1"]
#[inline]
pub fn rts1(self) -> &'a mut W {
self.variant(P2_7W::RTS1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_8`"]
pub enum P2_8W {
#[doc = "GPIO P2.8."]
GPIO_P2,
#[doc = "TD2"]
TD2,
#[doc = "TXD2"]
TXD2,
#[doc = "ENET_MDC"]
ENET_MDC,
}
impl P2_8W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_8W::GPIO_P2 => 0,
P2_8W::TD2 => 1,
P2_8W::TXD2 => 2,
P2_8W::ENET_MDC => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_8W<'a> {
w: &'a mut W,
}
impl<'a> _P2_8W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_8W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P2.8."]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_8W::GPIO_P2)
}
#[doc = "TD2"]
#[inline]
pub fn td2(self) -> &'a mut W {
self.variant(P2_8W::TD2)
}
#[doc = "TXD2"]
#[inline]
pub fn txd2(self) -> &'a mut W {
self.variant(P2_8W::TXD2)
}
#[doc = "ENET_MDC"]
#[inline]
pub fn enet_mdc(self) -> &'a mut W {
self.variant(P2_8W::ENET_MDC)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_9`"]
pub enum P2_9W {
#[doc = "GPIO P2.9"]
GPIO_P2,
#[doc = "USB_CONNECT"]
USB_CONNECT,
#[doc = "RXD2"]
RXD2,
#[doc = "ENET_MDIO"]
ENET_MDIO,
}
impl P2_9W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_9W::GPIO_P2 => 0,
P2_9W::USB_CONNECT => 1,
P2_9W::RXD2 => 2,
P2_9W::ENET_MDIO => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_9W<'a> {
w: &'a mut W,
}
impl<'a> _P2_9W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_9W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P2.9"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_9W::GPIO_P2)
}
#[doc = "USB_CONNECT"]
#[inline]
pub fn usb_connect(self) -> &'a mut W {
self.variant(P2_9W::USB_CONNECT)
}
#[doc = "RXD2"]
#[inline]
pub fn rxd2(self) -> &'a mut W {
self.variant(P2_9W::RXD2)
}
#[doc = "ENET_MDIO"]
#[inline]
pub fn enet_mdio(self) -> &'a mut W {
self.variant(P2_9W::ENET_MDIO)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_10`"]
pub enum P2_10W {
#[doc = "GPIO P2.10"]
GPIO_P2,
#[doc = "EINT0"]
EINT0,
#[doc = "NMI"]
NMI,
}
impl P2_10W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_10W::GPIO_P2 => 0,
P2_10W::EINT0 => 1,
P2_10W::NMI => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_10W<'a> {
w: &'a mut W,
}
impl<'a> _P2_10W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_10W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.10"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_10W::GPIO_P2)
}
#[doc = "EINT0"]
#[inline]
pub fn eint0(self) -> &'a mut W {
self.variant(P2_10W::EINT0)
}
#[doc = "NMI"]
#[inline]
pub fn nmi(self) -> &'a mut W {
self.variant(P2_10W::NMI)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_11`"]
pub enum P2_11W {
#[doc = "GPIO P2.11"]
GPIO_P2,
#[doc = "EINT1"]
EINT1,
#[doc = "I2STX_CLK"]
I2STX_CLK,
}
impl P2_11W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_11W::GPIO_P2 => 0,
P2_11W::EINT1 => 1,
P2_11W::I2STX_CLK => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_11W<'a> {
w: &'a mut W,
}
impl<'a> _P2_11W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_11W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.11"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_11W::GPIO_P2)
}
#[doc = "EINT1"]
#[inline]
pub fn eint1(self) -> &'a mut W {
self.variant(P2_11W::EINT1)
}
#[doc = "I2STX_CLK"]
#[inline]
pub fn i2stx_clk(self) -> &'a mut W {
self.variant(P2_11W::I2STX_CLK)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_12`"]
pub enum P2_12W {
#[doc = "GPIO P2.12"]
GPIO_P2,
#[doc = "EINT2"]
EINT2,
#[doc = "I2STX_WS"]
I2STX_WS,
}
impl P2_12W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_12W::GPIO_P2 => 0,
P2_12W::EINT2 => 1,
P2_12W::I2STX_WS => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_12W<'a> {
w: &'a mut W,
}
impl<'a> _P2_12W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_12W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.12"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_12W::GPIO_P2)
}
#[doc = "EINT2"]
#[inline]
pub fn eint2(self) -> &'a mut W {
self.variant(P2_12W::EINT2)
}
#[doc = "I2STX_WS"]
#[inline]
pub fn i2stx_ws(self) -> &'a mut W {
self.variant(P2_12W::I2STX_WS)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_13`"]
pub enum P2_13W {
#[doc = "GPIO P2.13"]
GPIO_P2,
#[doc = "EINT3"]
EINT3,
#[doc = "I2STX_SDA"]
I2STX_SDA,
}
impl P2_13W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_13W::GPIO_P2 => 0,
P2_13W::EINT3 => 1,
P2_13W::I2STX_SDA => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_13W<'a> {
w: &'a mut W,
}
impl<'a> _P2_13W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_13W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P2.13"]
#[inline]
pub fn gpio_p2(self) -> &'a mut W {
self.variant(P2_13W::GPIO_P2)
}
#[doc = "EINT3"]
#[inline]
pub fn eint3(self) -> &'a mut W {
self.variant(P2_13W::EINT3)
}
#[doc = "I2STX_SDA"]
#[inline]
pub fn i2stx_sda(self) -> &'a mut W {
self.variant(P2_13W::I2STX_SDA)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Pin function select P2.0."]
#[inline]
pub fn p2_0(&self) -> P2_0R {
P2_0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Pin function select P2.1."]
#[inline]
pub fn p2_1(&self) -> P2_1R {
P2_1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Pin function select P2.2."]
#[inline]
pub fn p2_2(&self) -> P2_2R {
P2_2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Pin function select P2.3."]
#[inline]
pub fn p2_3(&self) -> P2_3R {
P2_3R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Pin function select P2.4."]
#[inline]
pub fn p2_4(&self) -> P2_4R {
P2_4R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Pin function select P2.5."]
#[inline]
pub fn p2_5(&self) -> P2_5R {
P2_5R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Pin function select P2.6."]
#[inline]
pub fn p2_6(&self) -> P2_6R {
P2_6R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Pin function select P2.7."]
#[inline]
pub fn p2_7(&self) -> P2_7R {
P2_7R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Pin function select P2.8."]
#[inline]
pub fn p2_8(&self) -> P2_8R {
P2_8R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Pin function select P2.9."]
#[inline]
pub fn p2_9(&self) -> P2_9R {
P2_9R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Pin function select P2.10."]
#[inline]
pub fn p2_10(&self) -> P2_10R {
P2_10R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Pin function select P2.11."]
#[inline]
pub fn p2_11(&self) -> P2_11R {
P2_11R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:25 - Pin function select P2.12."]
#[inline]
pub fn p2_12(&self) -> P2_12R {
P2_12R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Pin function select P2.13."]
#[inline]
pub fn p2_13(&self) -> P2_13R {
P2_13R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Pin function select P2.0."]
#[inline]
pub fn p2_0(&mut self) -> _P2_0W {
_P2_0W { w: self }
}
#[doc = "Bits 2:3 - Pin function select P2.1."]
#[inline]
pub fn p2_1(&mut self) -> _P2_1W {
_P2_1W { w: self }
}
#[doc = "Bits 4:5 - Pin function select P2.2."]
#[inline]
pub fn p2_2(&mut self) -> _P2_2W {
_P2_2W { w: self }
}
#[doc = "Bits 6:7 - Pin function select P2.3."]
#[inline]
pub fn p2_3(&mut self) -> _P2_3W {
_P2_3W { w: self }
}
#[doc = "Bits 8:9 - Pin function select P2.4."]
#[inline]
pub fn p2_4(&mut self) -> _P2_4W {
_P2_4W { w: self }
}
#[doc = "Bits 10:11 - Pin function select P2.5."]
#[inline]
pub fn p2_5(&mut self) -> _P2_5W {
_P2_5W { w: self }
}
#[doc = "Bits 12:13 - Pin function select P2.6."]
#[inline]
pub fn p2_6(&mut self) -> _P2_6W {
_P2_6W { w: self }
}
#[doc = "Bits 14:15 - Pin function select P2.7."]
#[inline]
pub fn p2_7(&mut self) -> _P2_7W {
_P2_7W { w: self }
}
#[doc = "Bits 16:17 - Pin function select P2.8."]
#[inline]
pub fn p2_8(&mut self) -> _P2_8W {
_P2_8W { w: self }
}
#[doc = "Bits 18:19 - Pin function select P2.9."]
#[inline]
pub fn p2_9(&mut self) -> _P2_9W {
_P2_9W { w: self }
}
#[doc = "Bits 20:21 - Pin function select P2.10."]
#[inline]
pub fn p2_10(&mut self) -> _P2_10W {
_P2_10W { w: self }
}
#[doc = "Bits 22:23 - Pin function select P2.11."]
#[inline]
pub fn p2_11(&mut self) -> _P2_11W {
_P2_11W { w: self }
}
#[doc = "Bits 24:25 - Pin function select P2.12."]
#[inline]
pub fn p2_12(&mut self) -> _P2_12W {
_P2_12W { w: self }
}
#[doc = "Bits 26:27 - Pin function select P2.13."]
#[inline]
pub fn p2_13(&mut self) -> _P2_13W {
_P2_13W { w: self }
}
}
}
#[doc = "Pin function select register 7"]
pub struct PINSEL7 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 7"]
pub mod pinsel7 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL7 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P3_25`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P3_25R {
#[doc = "GPIO P3.25"]
GPIO_P3,
#[doc = "MAT0.0"]
MAT0,
#[doc = "PWM1.2"]
PWM1,
}
impl P3_25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P3_25R::GPIO_P3 => 0,
P3_25R::MAT0 => 0x02,
P3_25R::PWM1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P3_25R {
match value {
0 => P3_25R::GPIO_P3,
2 => P3_25R::MAT0,
3 => P3_25R::PWM1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P3`"]
#[inline]
pub fn is_gpio_p3(&self) -> bool {
*self == P3_25R::GPIO_P3
}
#[doc = "Checks if the value of the field is `MAT0`"]
#[inline]
pub fn is_mat0(&self) -> bool {
*self == P3_25R::MAT0
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P3_25R::PWM1
}
}
#[doc = "Possible values of the field `P3_26`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P3_26R {
#[doc = "GPIO P3.26"]
GPIO_P3,
#[doc = "STCLK"]
STCLK,
#[doc = "MAT0.1"]
MAT0,
#[doc = "PWM1.3"]
PWM1,
}
impl P3_26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P3_26R::GPIO_P3 => 0,
P3_26R::STCLK => 0x01,
P3_26R::MAT0 => 0x02,
P3_26R::PWM1 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P3_26R {
match value {
0 => P3_26R::GPIO_P3,
1 => P3_26R::STCLK,
2 => P3_26R::MAT0,
3 => P3_26R::PWM1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P3`"]
#[inline]
pub fn is_gpio_p3(&self) -> bool {
*self == P3_26R::GPIO_P3
}
#[doc = "Checks if the value of the field is `STCLK`"]
#[inline]
pub fn is_stclk(&self) -> bool {
*self == P3_26R::STCLK
}
#[doc = "Checks if the value of the field is `MAT0`"]
#[inline]
pub fn is_mat0(&self) -> bool {
*self == P3_26R::MAT0
}
#[doc = "Checks if the value of the field is `PWM1`"]
#[inline]
pub fn is_pwm1(&self) -> bool {
*self == P3_26R::PWM1
}
}
#[doc = "Values that can be written to the field `P3_25`"]
pub enum P3_25W {
#[doc = "GPIO P3.25"]
GPIO_P3,
#[doc = "MAT0.0"]
MAT0,
#[doc = "PWM1.2"]
PWM1,
}
impl P3_25W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P3_25W::GPIO_P3 => 0,
P3_25W::MAT0 => 2,
P3_25W::PWM1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P3_25W<'a> {
w: &'a mut W,
}
impl<'a> _P3_25W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P3_25W) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "GPIO P3.25"]
#[inline]
pub fn gpio_p3(self) -> &'a mut W {
self.variant(P3_25W::GPIO_P3)
}
#[doc = "MAT0.0"]
#[inline]
pub fn mat0(self) -> &'a mut W {
self.variant(P3_25W::MAT0)
}
#[doc = "PWM1.2"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P3_25W::PWM1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P3_26`"]
pub enum P3_26W {
#[doc = "GPIO P3.26"]
GPIO_P3,
#[doc = "STCLK"]
STCLK,
#[doc = "MAT0.1"]
MAT0,
#[doc = "PWM1.3"]
PWM1,
}
impl P3_26W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P3_26W::GPIO_P3 => 0,
P3_26W::STCLK => 1,
P3_26W::MAT0 => 2,
P3_26W::PWM1 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P3_26W<'a> {
w: &'a mut W,
}
impl<'a> _P3_26W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P3_26W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P3.26"]
#[inline]
pub fn gpio_p3(self) -> &'a mut W {
self.variant(P3_26W::GPIO_P3)
}
#[doc = "STCLK"]
#[inline]
pub fn stclk(self) -> &'a mut W {
self.variant(P3_26W::STCLK)
}
#[doc = "MAT0.1"]
#[inline]
pub fn mat0(self) -> &'a mut W {
self.variant(P3_26W::MAT0)
}
#[doc = "PWM1.3"]
#[inline]
pub fn pwm1(self) -> &'a mut W {
self.variant(P3_26W::PWM1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 18:19 - Pin function select P3.25."]
#[inline]
pub fn p3_25(&self) -> P3_25R {
P3_25R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Pin function select P3.26."]
#[inline]
pub fn p3_26(&self) -> P3_26R {
P3_26R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 18:19 - Pin function select P3.25."]
#[inline]
pub fn p3_25(&mut self) -> _P3_25W {
_P3_25W { w: self }
}
#[doc = "Bits 20:21 - Pin function select P3.26."]
#[inline]
pub fn p3_26(&mut self) -> _P3_26W {
_P3_26W { w: self }
}
}
}
#[doc = "Pin function select register 9"]
pub struct PINSEL9 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 9"]
pub mod pinsel9 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL9 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P4_28`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P4_28R {
#[doc = "GPIO P4.28"]
GPIO_P4,
#[doc = "RX_MCLK"]
RX_MCLK,
#[doc = "MAT2.0"]
MAT2,
#[doc = "TXD3"]
TXD3,
}
impl P4_28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P4_28R::GPIO_P4 => 0,
P4_28R::RX_MCLK => 0x01,
P4_28R::MAT2 => 0x02,
P4_28R::TXD3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P4_28R {
match value {
0 => P4_28R::GPIO_P4,
1 => P4_28R::RX_MCLK,
2 => P4_28R::MAT2,
3 => P4_28R::TXD3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P4`"]
#[inline]
pub fn is_gpio_p4(&self) -> bool {
*self == P4_28R::GPIO_P4
}
#[doc = "Checks if the value of the field is `RX_MCLK`"]
#[inline]
pub fn is_rx_mclk(&self) -> bool {
*self == P4_28R::RX_MCLK
}
#[doc = "Checks if the value of the field is `MAT2`"]
#[inline]
pub fn is_mat2(&self) -> bool {
*self == P4_28R::MAT2
}
#[doc = "Checks if the value of the field is `TXD3`"]
#[inline]
pub fn is_txd3(&self) -> bool {
*self == P4_28R::TXD3
}
}
#[doc = "Possible values of the field `P4_29`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P4_29R {
#[doc = "GPIO P4.29"]
GPIO_P4,
#[doc = "TX_MCLK"]
TX_MCLK,
#[doc = "MAT2.1"]
MAT2,
#[doc = "RXD3"]
RXD3,
}
impl P4_29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P4_29R::GPIO_P4 => 0,
P4_29R::TX_MCLK => 0x01,
P4_29R::MAT2 => 0x02,
P4_29R::RXD3 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P4_29R {
match value {
0 => P4_29R::GPIO_P4,
1 => P4_29R::TX_MCLK,
2 => P4_29R::MAT2,
3 => P4_29R::RXD3,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `GPIO_P4`"]
#[inline]
pub fn is_gpio_p4(&self) -> bool {
*self == P4_29R::GPIO_P4
}
#[doc = "Checks if the value of the field is `TX_MCLK`"]
#[inline]
pub fn is_tx_mclk(&self) -> bool {
*self == P4_29R::TX_MCLK
}
#[doc = "Checks if the value of the field is `MAT2`"]
#[inline]
pub fn is_mat2(&self) -> bool {
*self == P4_29R::MAT2
}
#[doc = "Checks if the value of the field is `RXD3`"]
#[inline]
pub fn is_rxd3(&self) -> bool {
*self == P4_29R::RXD3
}
}
#[doc = "Values that can be written to the field `P4_28`"]
pub enum P4_28W {
#[doc = "GPIO P4.28"]
GPIO_P4,
#[doc = "RX_MCLK"]
RX_MCLK,
#[doc = "MAT2.0"]
MAT2,
#[doc = "TXD3"]
TXD3,
}
impl P4_28W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P4_28W::GPIO_P4 => 0,
P4_28W::RX_MCLK => 1,
P4_28W::MAT2 => 2,
P4_28W::TXD3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P4_28W<'a> {
w: &'a mut W,
}
impl<'a> _P4_28W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P4_28W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P4.28"]
#[inline]
pub fn gpio_p4(self) -> &'a mut W {
self.variant(P4_28W::GPIO_P4)
}
#[doc = "RX_MCLK"]
#[inline]
pub fn rx_mclk(self) -> &'a mut W {
self.variant(P4_28W::RX_MCLK)
}
#[doc = "MAT2.0"]
#[inline]
pub fn mat2(self) -> &'a mut W {
self.variant(P4_28W::MAT2)
}
#[doc = "TXD3"]
#[inline]
pub fn txd3(self) -> &'a mut W {
self.variant(P4_28W::TXD3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P4_29`"]
pub enum P4_29W {
#[doc = "GPIO P4.29"]
GPIO_P4,
#[doc = "TX_MCLK"]
TX_MCLK,
#[doc = "MAT2.1"]
MAT2,
#[doc = "RXD3"]
RXD3,
}
impl P4_29W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P4_29W::GPIO_P4 => 0,
P4_29W::TX_MCLK => 1,
P4_29W::MAT2 => 2,
P4_29W::RXD3 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P4_29W<'a> {
w: &'a mut W,
}
impl<'a> _P4_29W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P4_29W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "GPIO P4.29"]
#[inline]
pub fn gpio_p4(self) -> &'a mut W {
self.variant(P4_29W::GPIO_P4)
}
#[doc = "TX_MCLK"]
#[inline]
pub fn tx_mclk(self) -> &'a mut W {
self.variant(P4_29W::TX_MCLK)
}
#[doc = "MAT2.1"]
#[inline]
pub fn mat2(self) -> &'a mut W {
self.variant(P4_29W::MAT2)
}
#[doc = "RXD3"]
#[inline]
pub fn rxd3(self) -> &'a mut W {
self.variant(P4_29W::RXD3)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 24:25 - Pin function select P4.28."]
#[inline]
pub fn p4_28(&self) -> P4_28R {
P4_28R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Pin function select P4.29."]
#[inline]
pub fn p4_29(&self) -> P4_29R {
P4_29R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 24:25 - Pin function select P4.28."]
#[inline]
pub fn p4_28(&mut self) -> _P4_28W {
_P4_28W { w: self }
}
#[doc = "Bits 26:27 - Pin function select P4.29."]
#[inline]
pub fn p4_29(&mut self) -> _P4_29W {
_P4_29W { w: self }
}
}
}
#[doc = "Pin function select register 10"]
pub struct PINSEL10 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin function select register 10"]
pub mod pinsel10 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINSEL10 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TPIUCTRL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TPIUCTRLR {
#[doc = "Disabled. TPIU interface is disabled."]
DISABLED,
#[doc = "Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content."]
ENABLED,
}
impl TPIUCTRLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TPIUCTRLR::DISABLED => false,
TPIUCTRLR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TPIUCTRLR {
match value {
false => TPIUCTRLR::DISABLED,
true => TPIUCTRLR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == TPIUCTRLR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == TPIUCTRLR::ENABLED
}
}
#[doc = "Values that can be written to the field `TPIUCTRL`"]
pub enum TPIUCTRLW {
#[doc = "Disabled. TPIU interface is disabled."]
DISABLED,
#[doc = "Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content."]
ENABLED,
}
impl TPIUCTRLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TPIUCTRLW::DISABLED => false,
TPIUCTRLW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TPIUCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _TPIUCTRLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TPIUCTRLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. TPIU interface is disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(TPIUCTRLW::DISABLED)
}
#[doc = "Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(TPIUCTRLW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 3 - TPIU interface pins control."]
#[inline]
pub fn tpiuctrl(&self) -> TPIUCTRLR {
TPIUCTRLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 3 - TPIU interface pins control."]
#[inline]
pub fn tpiuctrl(&mut self) -> _TPIUCTRLW {
_TPIUCTRLW { w: self }
}
}
}
#[doc = "Pin mode select register 0"]
pub struct PINMODE0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 0"]
pub mod pinmode0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P0_00MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_00MODER {
#[doc = "Pull-up. P0.0 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.0 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.0 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.0 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_00MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_00MODER::PULL_UP => 0,
P0_00MODER::REPEATER => 0x01,
P0_00MODER::DISABLED => 0x02,
P0_00MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_00MODER {
match value {
0 => P0_00MODER::PULL_UP,
1 => P0_00MODER::REPEATER,
2 => P0_00MODER::DISABLED,
3 => P0_00MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_00MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_00MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_00MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_00MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_01MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_01MODER {
#[doc = "Pull-up. P0.1 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.1 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.1 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.1 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_01MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_01MODER::PULL_UP => 0,
P0_01MODER::REPEATER => 0x01,
P0_01MODER::DISABLED => 0x02,
P0_01MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_01MODER {
match value {
0 => P0_01MODER::PULL_UP,
1 => P0_01MODER::REPEATER,
2 => P0_01MODER::DISABLED,
3 => P0_01MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_01MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_01MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_01MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_01MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_02MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_02MODER {
#[doc = "Pull-up. P0.2 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.2 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.2 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.2 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_02MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_02MODER::PULL_UP => 0,
P0_02MODER::REPEATER => 0x01,
P0_02MODER::DISABLED => 0x02,
P0_02MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_02MODER {
match value {
0 => P0_02MODER::PULL_UP,
1 => P0_02MODER::REPEATER,
2 => P0_02MODER::DISABLED,
3 => P0_02MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_02MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_02MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_02MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_02MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_03MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_03MODER {
#[doc = "Pull-up. P0.3 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.3 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.3 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.3 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_03MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_03MODER::PULL_UP => 0,
P0_03MODER::REPEATER => 0x01,
P0_03MODER::DISABLED => 0x02,
P0_03MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_03MODER {
match value {
0 => P0_03MODER::PULL_UP,
1 => P0_03MODER::REPEATER,
2 => P0_03MODER::DISABLED,
3 => P0_03MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_03MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_03MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_03MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_03MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_04MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_04MODER {
#[doc = "Pull-up. P0.4 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.4 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.4 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.4 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_04MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_04MODER::PULL_UP => 0,
P0_04MODER::REPEATER => 0x01,
P0_04MODER::DISABLED => 0x02,
P0_04MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_04MODER {
match value {
0 => P0_04MODER::PULL_UP,
1 => P0_04MODER::REPEATER,
2 => P0_04MODER::DISABLED,
3 => P0_04MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_04MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_04MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_04MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_04MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_05MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_05MODER {
#[doc = "Pull-up. P0.5 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.5 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.5 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.5 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_05MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_05MODER::PULL_UP => 0,
P0_05MODER::REPEATER => 0x01,
P0_05MODER::DISABLED => 0x02,
P0_05MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_05MODER {
match value {
0 => P0_05MODER::PULL_UP,
1 => P0_05MODER::REPEATER,
2 => P0_05MODER::DISABLED,
3 => P0_05MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_05MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_05MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_05MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_05MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_06MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_06MODER {
#[doc = "Pull-up. P0.6 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Disabled. Repeater. P0.6 pin has repeater mode enabled."]
DISABLED_REP,
#[doc = "Disabled. P0.6 pin has neither pull-up nor pull-down."]
DISABLED_NEITHER,
#[doc = "Pull-down. P0.6 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_06MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_06MODER::PULL_UP => 0,
P0_06MODER::DISABLED_REP => 0x01,
P0_06MODER::DISABLED_NEITHER => 0x02,
P0_06MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_06MODER {
match value {
0 => P0_06MODER::PULL_UP,
1 => P0_06MODER::DISABLED_REP,
2 => P0_06MODER::DISABLED_NEITHER,
3 => P0_06MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_06MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled_rep(&self) -> bool {
*self == P0_06MODER::DISABLED_REP
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled_neither(&self) -> bool {
*self == P0_06MODER::DISABLED_NEITHER
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_06MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_07MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_07MODER {
#[doc = "Pull-up. P0.7 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.7 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.7 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.7 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_07MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_07MODER::PULL_UP => 0,
P0_07MODER::REPEATER => 0x01,
P0_07MODER::DISABLED => 0x02,
P0_07MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_07MODER {
match value {
0 => P0_07MODER::PULL_UP,
1 => P0_07MODER::REPEATER,
2 => P0_07MODER::DISABLED,
3 => P0_07MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_07MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_07MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_07MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_07MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_08MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_08MODER {
#[doc = "Pull-up. P0.8 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.8 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.8 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.8 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_08MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_08MODER::PULL_UP => 0,
P0_08MODER::REPEATER => 0x01,
P0_08MODER::DISABLED => 0x02,
P0_08MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_08MODER {
match value {
0 => P0_08MODER::PULL_UP,
1 => P0_08MODER::REPEATER,
2 => P0_08MODER::DISABLED,
3 => P0_08MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_08MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_08MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_08MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_08MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_09MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_09MODER {
#[doc = "Pull-up. P0.9 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.9 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.9 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.9 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_09MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_09MODER::PULL_UP => 0,
P0_09MODER::REPEATER => 0x01,
P0_09MODER::DISABLED => 0x02,
P0_09MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_09MODER {
match value {
0 => P0_09MODER::PULL_UP,
1 => P0_09MODER::REPEATER,
2 => P0_09MODER::DISABLED,
3 => P0_09MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_09MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_09MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_09MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_09MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_10MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_10MODER {
#[doc = "Pull-up. P0.10 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.10 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.10 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.10 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_10MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_10MODER::PULL_UP => 0,
P0_10MODER::REPEATER => 0x01,
P0_10MODER::DISABLED => 0x02,
P0_10MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_10MODER {
match value {
0 => P0_10MODER::PULL_UP,
1 => P0_10MODER::REPEATER,
2 => P0_10MODER::DISABLED,
3 => P0_10MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_10MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_10MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_10MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_10MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_11MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_11MODER {
#[doc = "Pull-up. P0.11 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.11 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.11 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.11 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_11MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_11MODER::PULL_UP => 0,
P0_11MODER::REPEATER => 0x01,
P0_11MODER::DISABLED => 0x02,
P0_11MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_11MODER {
match value {
0 => P0_11MODER::PULL_UP,
1 => P0_11MODER::REPEATER,
2 => P0_11MODER::DISABLED,
3 => P0_11MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_11MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_11MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_11MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_11MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_15MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_15MODER {
#[doc = "Pull-up. P0.15 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.15 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.15 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.15 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_15MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_15MODER::PULL_UP => 0,
P0_15MODER::REPEATER => 0x01,
P0_15MODER::DISABLED => 0x02,
P0_15MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_15MODER {
match value {
0 => P0_15MODER::PULL_UP,
1 => P0_15MODER::REPEATER,
2 => P0_15MODER::DISABLED,
3 => P0_15MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_15MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_15MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_15MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_15MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P0_00MODE`"]
pub enum P0_00MODEW {
#[doc = "Pull-up. P0.0 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.0 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.0 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.0 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_00MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_00MODEW::PULL_UP => 0,
P0_00MODEW::REPEATER => 1,
P0_00MODEW::DISABLED => 2,
P0_00MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_00MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_00MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_00MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.0 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_00MODEW::PULL_UP)
}
#[doc = "Repeater. P0.0 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_00MODEW::REPEATER)
}
#[doc = "Disabled. P0.0 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_00MODEW::DISABLED)
}
#[doc = "Pull-down. P0.0 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_00MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_01MODE`"]
pub enum P0_01MODEW {
#[doc = "Pull-up. P0.1 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.1 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.1 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.1 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_01MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_01MODEW::PULL_UP => 0,
P0_01MODEW::REPEATER => 1,
P0_01MODEW::DISABLED => 2,
P0_01MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_01MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_01MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_01MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.1 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_01MODEW::PULL_UP)
}
#[doc = "Repeater. P0.1 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_01MODEW::REPEATER)
}
#[doc = "Disabled. P0.1 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_01MODEW::DISABLED)
}
#[doc = "Pull-down. P0.1 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_01MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_02MODE`"]
pub enum P0_02MODEW {
#[doc = "Pull-up. P0.2 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.2 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.2 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.2 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_02MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_02MODEW::PULL_UP => 0,
P0_02MODEW::REPEATER => 1,
P0_02MODEW::DISABLED => 2,
P0_02MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_02MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_02MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_02MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.2 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_02MODEW::PULL_UP)
}
#[doc = "Repeater. P0.2 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_02MODEW::REPEATER)
}
#[doc = "Disabled. P0.2 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_02MODEW::DISABLED)
}
#[doc = "Pull-down. P0.2 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_02MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_03MODE`"]
pub enum P0_03MODEW {
#[doc = "Pull-up. P0.3 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.3 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.3 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.3 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_03MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_03MODEW::PULL_UP => 0,
P0_03MODEW::REPEATER => 1,
P0_03MODEW::DISABLED => 2,
P0_03MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_03MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_03MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_03MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.3 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_03MODEW::PULL_UP)
}
#[doc = "Repeater. P0.3 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_03MODEW::REPEATER)
}
#[doc = "Disabled. P0.3 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_03MODEW::DISABLED)
}
#[doc = "Pull-down. P0.3 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_03MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_04MODE`"]
pub enum P0_04MODEW {
#[doc = "Pull-up. P0.4 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.4 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.4 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.4 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_04MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_04MODEW::PULL_UP => 0,
P0_04MODEW::REPEATER => 1,
P0_04MODEW::DISABLED => 2,
P0_04MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_04MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_04MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_04MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.4 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_04MODEW::PULL_UP)
}
#[doc = "Repeater. P0.4 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_04MODEW::REPEATER)
}
#[doc = "Disabled. P0.4 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_04MODEW::DISABLED)
}
#[doc = "Pull-down. P0.4 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_04MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_05MODE`"]
pub enum P0_05MODEW {
#[doc = "Pull-up. P0.5 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.5 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.5 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.5 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_05MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_05MODEW::PULL_UP => 0,
P0_05MODEW::REPEATER => 1,
P0_05MODEW::DISABLED => 2,
P0_05MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_05MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_05MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_05MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.5 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_05MODEW::PULL_UP)
}
#[doc = "Repeater. P0.5 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_05MODEW::REPEATER)
}
#[doc = "Disabled. P0.5 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_05MODEW::DISABLED)
}
#[doc = "Pull-down. P0.5 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_05MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_06MODE`"]
pub enum P0_06MODEW {
#[doc = "Pull-up. P0.6 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Disabled. Repeater. P0.6 pin has repeater mode enabled."]
DISABLED_REP,
#[doc = "Disabled. P0.6 pin has neither pull-up nor pull-down."]
DISABLED_NEITHER,
#[doc = "Pull-down. P0.6 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_06MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_06MODEW::PULL_UP => 0,
P0_06MODEW::DISABLED_REP => 1,
P0_06MODEW::DISABLED_NEITHER => 2,
P0_06MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_06MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_06MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_06MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.6 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_06MODEW::PULL_UP)
}
#[doc = "Disabled. Repeater. P0.6 pin has repeater mode enabled."]
#[inline]
pub fn disabled_rep(self) -> &'a mut W {
self.variant(P0_06MODEW::DISABLED_REP)
}
#[doc = "Disabled. P0.6 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled_neither(self) -> &'a mut W {
self.variant(P0_06MODEW::DISABLED_NEITHER)
}
#[doc = "Pull-down. P0.6 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_06MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_07MODE`"]
pub enum P0_07MODEW {
#[doc = "Pull-up. P0.7 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.7 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.7 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.7 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_07MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_07MODEW::PULL_UP => 0,
P0_07MODEW::REPEATER => 1,
P0_07MODEW::DISABLED => 2,
P0_07MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_07MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_07MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_07MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.7 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_07MODEW::PULL_UP)
}
#[doc = "Repeater. P0.7 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_07MODEW::REPEATER)
}
#[doc = "Disabled. P0.7 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_07MODEW::DISABLED)
}
#[doc = "Pull-down. P0.7 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_07MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_08MODE`"]
pub enum P0_08MODEW {
#[doc = "Pull-up. P0.8 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.8 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.8 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.8 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_08MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_08MODEW::PULL_UP => 0,
P0_08MODEW::REPEATER => 1,
P0_08MODEW::DISABLED => 2,
P0_08MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_08MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_08MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_08MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.8 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_08MODEW::PULL_UP)
}
#[doc = "Repeater. P0.8 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_08MODEW::REPEATER)
}
#[doc = "Disabled. P0.8 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_08MODEW::DISABLED)
}
#[doc = "Pull-down. P0.8 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_08MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_09MODE`"]
pub enum P0_09MODEW {
#[doc = "Pull-up. P0.9 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.9 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.9 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.9 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_09MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_09MODEW::PULL_UP => 0,
P0_09MODEW::REPEATER => 1,
P0_09MODEW::DISABLED => 2,
P0_09MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_09MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_09MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_09MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.9 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_09MODEW::PULL_UP)
}
#[doc = "Repeater. P0.9 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_09MODEW::REPEATER)
}
#[doc = "Disabled. P0.9 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_09MODEW::DISABLED)
}
#[doc = "Pull-down. P0.9 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_09MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_10MODE`"]
pub enum P0_10MODEW {
#[doc = "Pull-up. P0.10 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.10 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.10 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.10 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_10MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_10MODEW::PULL_UP => 0,
P0_10MODEW::REPEATER => 1,
P0_10MODEW::DISABLED => 2,
P0_10MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_10MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_10MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_10MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.10 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_10MODEW::PULL_UP)
}
#[doc = "Repeater. P0.10 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_10MODEW::REPEATER)
}
#[doc = "Disabled. P0.10 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_10MODEW::DISABLED)
}
#[doc = "Pull-down. P0.10 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_10MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_11MODE`"]
pub enum P0_11MODEW {
#[doc = "Pull-up. P0.11 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.11 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.11 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.11 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_11MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_11MODEW::PULL_UP => 0,
P0_11MODEW::REPEATER => 1,
P0_11MODEW::DISABLED => 2,
P0_11MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_11MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_11MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_11MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.11 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_11MODEW::PULL_UP)
}
#[doc = "Repeater. P0.11 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_11MODEW::REPEATER)
}
#[doc = "Disabled. P0.11 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_11MODEW::DISABLED)
}
#[doc = "Pull-down. P0.11 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_11MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_15MODE`"]
pub enum P0_15MODEW {
#[doc = "Pull-up. P0.15 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.15 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.15 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.15 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_15MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_15MODEW::PULL_UP => 0,
P0_15MODEW::REPEATER => 1,
P0_15MODEW::DISABLED => 2,
P0_15MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_15MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_15MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_15MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.15 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_15MODEW::PULL_UP)
}
#[doc = "Repeater. P0.15 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_15MODEW::REPEATER)
}
#[doc = "Disabled. P0.15 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_15MODEW::DISABLED)
}
#[doc = "Pull-down. P0.15 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_15MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Port 0 pin 0 on-chip pull-up/down resistor control."]
#[inline]
pub fn p0_00mode(&self) -> P0_00MODER {
P0_00MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Port 0 pin 1 control."]
#[inline]
pub fn p0_01mode(&self) -> P0_01MODER {
P0_01MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Port 0 pin 2 control."]
#[inline]
pub fn p0_02mode(&self) -> P0_02MODER {
P0_02MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Port 0 pin 3 control."]
#[inline]
pub fn p0_03mode(&self) -> P0_03MODER {
P0_03MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Port 0 pin 4 control."]
#[inline]
pub fn p0_04mode(&self) -> P0_04MODER {
P0_04MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Port 0 pin 5 control."]
#[inline]
pub fn p0_05mode(&self) -> P0_05MODER {
P0_05MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Port 0 pin 6 control."]
#[inline]
pub fn p0_06mode(&self) -> P0_06MODER {
P0_06MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Port 0 pin 7 control."]
#[inline]
pub fn p0_07mode(&self) -> P0_07MODER {
P0_07MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Port 0 pin 8 control."]
#[inline]
pub fn p0_08mode(&self) -> P0_08MODER {
P0_08MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Port 0 pin 9 control."]
#[inline]
pub fn p0_09mode(&self) -> P0_09MODER {
P0_09MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Port 0 pin 10 control."]
#[inline]
pub fn p0_10mode(&self) -> P0_10MODER {
P0_10MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Port 0 pin 11 control."]
#[inline]
pub fn p0_11mode(&self) -> P0_11MODER {
P0_11MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Port 0 pin 15 control."]
#[inline]
pub fn p0_15mode(&self) -> P0_15MODER {
P0_15MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Port 0 pin 0 on-chip pull-up/down resistor control."]
#[inline]
pub fn p0_00mode(&mut self) -> _P0_00MODEW {
_P0_00MODEW { w: self }
}
#[doc = "Bits 2:3 - Port 0 pin 1 control."]
#[inline]
pub fn p0_01mode(&mut self) -> _P0_01MODEW {
_P0_01MODEW { w: self }
}
#[doc = "Bits 4:5 - Port 0 pin 2 control."]
#[inline]
pub fn p0_02mode(&mut self) -> _P0_02MODEW {
_P0_02MODEW { w: self }
}
#[doc = "Bits 6:7 - Port 0 pin 3 control."]
#[inline]
pub fn p0_03mode(&mut self) -> _P0_03MODEW {
_P0_03MODEW { w: self }
}
#[doc = "Bits 8:9 - Port 0 pin 4 control."]
#[inline]
pub fn p0_04mode(&mut self) -> _P0_04MODEW {
_P0_04MODEW { w: self }
}
#[doc = "Bits 10:11 - Port 0 pin 5 control."]
#[inline]
pub fn p0_05mode(&mut self) -> _P0_05MODEW {
_P0_05MODEW { w: self }
}
#[doc = "Bits 12:13 - Port 0 pin 6 control."]
#[inline]
pub fn p0_06mode(&mut self) -> _P0_06MODEW {
_P0_06MODEW { w: self }
}
#[doc = "Bits 14:15 - Port 0 pin 7 control."]
#[inline]
pub fn p0_07mode(&mut self) -> _P0_07MODEW {
_P0_07MODEW { w: self }
}
#[doc = "Bits 16:17 - Port 0 pin 8 control."]
#[inline]
pub fn p0_08mode(&mut self) -> _P0_08MODEW {
_P0_08MODEW { w: self }
}
#[doc = "Bits 18:19 - Port 0 pin 9 control."]
#[inline]
pub fn p0_09mode(&mut self) -> _P0_09MODEW {
_P0_09MODEW { w: self }
}
#[doc = "Bits 20:21 - Port 0 pin 10 control."]
#[inline]
pub fn p0_10mode(&mut self) -> _P0_10MODEW {
_P0_10MODEW { w: self }
}
#[doc = "Bits 22:23 - Port 0 pin 11 control."]
#[inline]
pub fn p0_11mode(&mut self) -> _P0_11MODEW {
_P0_11MODEW { w: self }
}
#[doc = "Bits 30:31 - Port 0 pin 15 control."]
#[inline]
pub fn p0_15mode(&mut self) -> _P0_15MODEW {
_P0_15MODEW { w: self }
}
}
}
#[doc = "Pin mode select register 1"]
pub struct PINMODE1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 1"]
pub mod pinmode1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P0_16MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_16MODER {
#[doc = "Pull-up. P0.16 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.16 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.16 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.16 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_16MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_16MODER::PULL_UP => 0,
P0_16MODER::REPEATER => 0x01,
P0_16MODER::DISABLED => 0x02,
P0_16MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_16MODER {
match value {
0 => P0_16MODER::PULL_UP,
1 => P0_16MODER::REPEATER,
2 => P0_16MODER::DISABLED,
3 => P0_16MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_16MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_16MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_16MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_16MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_17MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_17MODER {
#[doc = "Pull-up. P0.17 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.17 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.17 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.17 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_17MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_17MODER::PULL_UP => 0,
P0_17MODER::REPEATER => 0x01,
P0_17MODER::DISABLED => 0x02,
P0_17MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_17MODER {
match value {
0 => P0_17MODER::PULL_UP,
1 => P0_17MODER::REPEATER,
2 => P0_17MODER::DISABLED,
3 => P0_17MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_17MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_17MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_17MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_17MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_18MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_18MODER {
#[doc = "Pull-up. P0.18 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.18 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.18 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.18 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_18MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_18MODER::PULL_UP => 0,
P0_18MODER::REPEATER => 0x01,
P0_18MODER::DISABLED => 0x02,
P0_18MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_18MODER {
match value {
0 => P0_18MODER::PULL_UP,
1 => P0_18MODER::REPEATER,
2 => P0_18MODER::DISABLED,
3 => P0_18MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_18MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_18MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_18MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_18MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_19MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_19MODER {
#[doc = "Pull-up. P0.19 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.19 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.19 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.19 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_19MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_19MODER::PULL_UP => 0,
P0_19MODER::REPEATER => 0x01,
P0_19MODER::DISABLED => 0x02,
P0_19MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_19MODER {
match value {
0 => P0_19MODER::PULL_UP,
1 => P0_19MODER::REPEATER,
2 => P0_19MODER::DISABLED,
3 => P0_19MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_19MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_19MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_19MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_19MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_20MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_20MODER {
#[doc = "Pull-up. P0.20 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.20 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.20 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.20 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_20MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_20MODER::PULL_UP => 0,
P0_20MODER::REPEATER => 0x01,
P0_20MODER::DISABLED => 0x02,
P0_20MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_20MODER {
match value {
0 => P0_20MODER::PULL_UP,
1 => P0_20MODER::REPEATER,
2 => P0_20MODER::DISABLED,
3 => P0_20MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_20MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_20MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_20MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_20MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_21MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_21MODER {
#[doc = "Pull-up. P0.21 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.21 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.21 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.21 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_21MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_21MODER::PULL_UP => 0,
P0_21MODER::REPEATER => 0x01,
P0_21MODER::DISABLED => 0x02,
P0_21MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_21MODER {
match value {
0 => P0_21MODER::PULL_UP,
1 => P0_21MODER::REPEATER,
2 => P0_21MODER::DISABLED,
3 => P0_21MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_21MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_21MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_21MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_21MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_22MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_22MODER {
#[doc = "Pull-up. P0.22 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.22 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.22 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.22 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_22MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_22MODER::PULL_UP => 0,
P0_22MODER::REPEATER => 0x01,
P0_22MODER::DISABLED => 0x02,
P0_22MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_22MODER {
match value {
0 => P0_22MODER::PULL_UP,
1 => P0_22MODER::REPEATER,
2 => P0_22MODER::DISABLED,
3 => P0_22MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_22MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_22MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_22MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_22MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_23MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_23MODER {
#[doc = "Pull-up. P0.23 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.23 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.23 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.23 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_23MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_23MODER::PULL_UP => 0,
P0_23MODER::REPEATER => 0x01,
P0_23MODER::DISABLED => 0x02,
P0_23MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_23MODER {
match value {
0 => P0_23MODER::PULL_UP,
1 => P0_23MODER::REPEATER,
2 => P0_23MODER::DISABLED,
3 => P0_23MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_23MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_23MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_23MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_23MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_24MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_24MODER {
#[doc = "Pull-up. P0.24 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.24 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.24 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.24 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_24MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_24MODER::PULL_UP => 0,
P0_24MODER::REPEATER => 0x01,
P0_24MODER::DISABLED => 0x02,
P0_24MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_24MODER {
match value {
0 => P0_24MODER::PULL_UP,
1 => P0_24MODER::REPEATER,
2 => P0_24MODER::DISABLED,
3 => P0_24MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_24MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_24MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_24MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_24MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_25MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_25MODER {
#[doc = "Pull-up. P0.25 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.25 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.25 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.25 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_25MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_25MODER::PULL_UP => 0,
P0_25MODER::REPEATER => 0x01,
P0_25MODER::DISABLED => 0x02,
P0_25MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_25MODER {
match value {
0 => P0_25MODER::PULL_UP,
1 => P0_25MODER::REPEATER,
2 => P0_25MODER::DISABLED,
3 => P0_25MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_25MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_25MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_25MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_25MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P0_26MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_26MODER {
#[doc = "Pull-up. P0.26 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.26 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.26 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.26 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_26MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P0_26MODER::PULL_UP => 0,
P0_26MODER::REPEATER => 0x01,
P0_26MODER::DISABLED => 0x02,
P0_26MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P0_26MODER {
match value {
0 => P0_26MODER::PULL_UP,
1 => P0_26MODER::REPEATER,
2 => P0_26MODER::DISABLED,
3 => P0_26MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P0_26MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P0_26MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P0_26MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P0_26MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P0_16MODE`"]
pub enum P0_16MODEW {
#[doc = "Pull-up. P0.16 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.16 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.16 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.16 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_16MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_16MODEW::PULL_UP => 0,
P0_16MODEW::REPEATER => 1,
P0_16MODEW::DISABLED => 2,
P0_16MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_16MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_16MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_16MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.16 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_16MODEW::PULL_UP)
}
#[doc = "Repeater. P0.16 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_16MODEW::REPEATER)
}
#[doc = "Disabled. P0.16 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_16MODEW::DISABLED)
}
#[doc = "Pull-down. P0.16 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_16MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_17MODE`"]
pub enum P0_17MODEW {
#[doc = "Pull-up. P0.17 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.17 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.17 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.17 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_17MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_17MODEW::PULL_UP => 0,
P0_17MODEW::REPEATER => 1,
P0_17MODEW::DISABLED => 2,
P0_17MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_17MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_17MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_17MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.17 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_17MODEW::PULL_UP)
}
#[doc = "Repeater. P0.17 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_17MODEW::REPEATER)
}
#[doc = "Disabled. P0.17 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_17MODEW::DISABLED)
}
#[doc = "Pull-down. P0.17 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_17MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_18MODE`"]
pub enum P0_18MODEW {
#[doc = "Pull-up. P0.18 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.18 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.18 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.18 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_18MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_18MODEW::PULL_UP => 0,
P0_18MODEW::REPEATER => 1,
P0_18MODEW::DISABLED => 2,
P0_18MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_18MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_18MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_18MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.18 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_18MODEW::PULL_UP)
}
#[doc = "Repeater. P0.18 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_18MODEW::REPEATER)
}
#[doc = "Disabled. P0.18 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_18MODEW::DISABLED)
}
#[doc = "Pull-down. P0.18 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_18MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_19MODE`"]
pub enum P0_19MODEW {
#[doc = "Pull-up. P0.19 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.19 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.19 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.19 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_19MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_19MODEW::PULL_UP => 0,
P0_19MODEW::REPEATER => 1,
P0_19MODEW::DISABLED => 2,
P0_19MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_19MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_19MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_19MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.19 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_19MODEW::PULL_UP)
}
#[doc = "Repeater. P0.19 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_19MODEW::REPEATER)
}
#[doc = "Disabled. P0.19 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_19MODEW::DISABLED)
}
#[doc = "Pull-down. P0.19 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_19MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_20MODE`"]
pub enum P0_20MODEW {
#[doc = "Pull-up. P0.20 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.20 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.20 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.20 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_20MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_20MODEW::PULL_UP => 0,
P0_20MODEW::REPEATER => 1,
P0_20MODEW::DISABLED => 2,
P0_20MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_20MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_20MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_20MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.20 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_20MODEW::PULL_UP)
}
#[doc = "Repeater. P0.20 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_20MODEW::REPEATER)
}
#[doc = "Disabled. P0.20 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_20MODEW::DISABLED)
}
#[doc = "Pull-down. P0.20 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_20MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_21MODE`"]
pub enum P0_21MODEW {
#[doc = "Pull-up. P0.21 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.21 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.21 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.21 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_21MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_21MODEW::PULL_UP => 0,
P0_21MODEW::REPEATER => 1,
P0_21MODEW::DISABLED => 2,
P0_21MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_21MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_21MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_21MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.21 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_21MODEW::PULL_UP)
}
#[doc = "Repeater. P0.21 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_21MODEW::REPEATER)
}
#[doc = "Disabled. P0.21 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_21MODEW::DISABLED)
}
#[doc = "Pull-down. P0.21 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_21MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_22MODE`"]
pub enum P0_22MODEW {
#[doc = "Pull-up. P0.22 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.22 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.22 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.22 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_22MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_22MODEW::PULL_UP => 0,
P0_22MODEW::REPEATER => 1,
P0_22MODEW::DISABLED => 2,
P0_22MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_22MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_22MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_22MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.22 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_22MODEW::PULL_UP)
}
#[doc = "Repeater. P0.22 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_22MODEW::REPEATER)
}
#[doc = "Disabled. P0.22 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_22MODEW::DISABLED)
}
#[doc = "Pull-down. P0.22 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_22MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_23MODE`"]
pub enum P0_23MODEW {
#[doc = "Pull-up. P0.23 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.23 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.23 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.23 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_23MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_23MODEW::PULL_UP => 0,
P0_23MODEW::REPEATER => 1,
P0_23MODEW::DISABLED => 2,
P0_23MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_23MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_23MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_23MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.23 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_23MODEW::PULL_UP)
}
#[doc = "Repeater. P0.23 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_23MODEW::REPEATER)
}
#[doc = "Disabled. P0.23 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_23MODEW::DISABLED)
}
#[doc = "Pull-down. P0.23 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_23MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_24MODE`"]
pub enum P0_24MODEW {
#[doc = "Pull-up. P0.24 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.24 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.24 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.24 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_24MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_24MODEW::PULL_UP => 0,
P0_24MODEW::REPEATER => 1,
P0_24MODEW::DISABLED => 2,
P0_24MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_24MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_24MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_24MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.24 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_24MODEW::PULL_UP)
}
#[doc = "Repeater. P0.24 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_24MODEW::REPEATER)
}
#[doc = "Disabled. P0.24 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_24MODEW::DISABLED)
}
#[doc = "Pull-down. P0.24 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_24MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_25MODE`"]
pub enum P0_25MODEW {
#[doc = "Pull-up. P0.25 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.25 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.25 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.25 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_25MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_25MODEW::PULL_UP => 0,
P0_25MODEW::REPEATER => 1,
P0_25MODEW::DISABLED => 2,
P0_25MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_25MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_25MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_25MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.25 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_25MODEW::PULL_UP)
}
#[doc = "Repeater. P0.25 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_25MODEW::REPEATER)
}
#[doc = "Disabled. P0.25 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_25MODEW::DISABLED)
}
#[doc = "Pull-down. P0.25 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_25MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_26MODE`"]
pub enum P0_26MODEW {
#[doc = "Pull-up. P0.26 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P0.26 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P0.26 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P0.26 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P0_26MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P0_26MODEW::PULL_UP => 0,
P0_26MODEW::REPEATER => 1,
P0_26MODEW::DISABLED => 2,
P0_26MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_26MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P0_26MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_26MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P0.26 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P0_26MODEW::PULL_UP)
}
#[doc = "Repeater. P0.26 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P0_26MODEW::REPEATER)
}
#[doc = "Disabled. P0.26 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P0_26MODEW::DISABLED)
}
#[doc = "Pull-down. P0.26 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P0_26MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Port 1 pin 16 control."]
#[inline]
pub fn p0_16mode(&self) -> P0_16MODER {
P0_16MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Port 1 pin 17 control."]
#[inline]
pub fn p0_17mode(&self) -> P0_17MODER {
P0_17MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Port 1 pin 18 control."]
#[inline]
pub fn p0_18mode(&self) -> P0_18MODER {
P0_18MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Port 1 pin 19 control."]
#[inline]
pub fn p0_19mode(&self) -> P0_19MODER {
P0_19MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Port 1 pin 20 control."]
#[inline]
pub fn p0_20mode(&self) -> P0_20MODER {
P0_20MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Port 1 pin 21 control."]
#[inline]
pub fn p0_21mode(&self) -> P0_21MODER {
P0_21MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Port 1 pin 22 control."]
#[inline]
pub fn p0_22mode(&self) -> P0_22MODER {
P0_22MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Port 1 pin 23 control."]
#[inline]
pub fn p0_23mode(&self) -> P0_23MODER {
P0_23MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Port 1 pin 24 control."]
#[inline]
pub fn p0_24mode(&self) -> P0_24MODER {
P0_24MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Port 1 pin 25 control."]
#[inline]
pub fn p0_25mode(&self) -> P0_25MODER {
P0_25MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Port 1 pin 26 control."]
#[inline]
pub fn p0_26mode(&self) -> P0_26MODER {
P0_26MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Port 1 pin 16 control."]
#[inline]
pub fn p0_16mode(&mut self) -> _P0_16MODEW {
_P0_16MODEW { w: self }
}
#[doc = "Bits 2:3 - Port 1 pin 17 control."]
#[inline]
pub fn p0_17mode(&mut self) -> _P0_17MODEW {
_P0_17MODEW { w: self }
}
#[doc = "Bits 4:5 - Port 1 pin 18 control."]
#[inline]
pub fn p0_18mode(&mut self) -> _P0_18MODEW {
_P0_18MODEW { w: self }
}
#[doc = "Bits 6:7 - Port 1 pin 19 control."]
#[inline]
pub fn p0_19mode(&mut self) -> _P0_19MODEW {
_P0_19MODEW { w: self }
}
#[doc = "Bits 8:9 - Port 1 pin 20 control."]
#[inline]
pub fn p0_20mode(&mut self) -> _P0_20MODEW {
_P0_20MODEW { w: self }
}
#[doc = "Bits 10:11 - Port 1 pin 21 control."]
#[inline]
pub fn p0_21mode(&mut self) -> _P0_21MODEW {
_P0_21MODEW { w: self }
}
#[doc = "Bits 12:13 - Port 1 pin 22 control."]
#[inline]
pub fn p0_22mode(&mut self) -> _P0_22MODEW {
_P0_22MODEW { w: self }
}
#[doc = "Bits 14:15 - Port 1 pin 23 control."]
#[inline]
pub fn p0_23mode(&mut self) -> _P0_23MODEW {
_P0_23MODEW { w: self }
}
#[doc = "Bits 16:17 - Port 1 pin 24 control."]
#[inline]
pub fn p0_24mode(&mut self) -> _P0_24MODEW {
_P0_24MODEW { w: self }
}
#[doc = "Bits 18:19 - Port 1 pin 25 control."]
#[inline]
pub fn p0_25mode(&mut self) -> _P0_25MODEW {
_P0_25MODEW { w: self }
}
#[doc = "Bits 20:21 - Port 1 pin 26 control."]
#[inline]
pub fn p0_26mode(&mut self) -> _P0_26MODEW {
_P0_26MODEW { w: self }
}
}
}
#[doc = "Pin mode select register 2"]
pub struct PINMODE2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 2"]
pub mod pinmode2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P1_00MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_00MODER {
#[doc = "Pull-up. P1.0 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.0 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.0 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.0 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_00MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_00MODER::PULL_UP => 0,
P1_00MODER::REPEATER => 0x01,
P1_00MODER::DISABLED => 0x02,
P1_00MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_00MODER {
match value {
0 => P1_00MODER::PULL_UP,
1 => P1_00MODER::REPEATER,
2 => P1_00MODER::DISABLED,
3 => P1_00MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_00MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_00MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_00MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_00MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_01MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_01MODER {
#[doc = "Pull-up. P1.1 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.1 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.1 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.1 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_01MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_01MODER::PULL_UP => 0,
P1_01MODER::REPEATER => 0x01,
P1_01MODER::DISABLED => 0x02,
P1_01MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_01MODER {
match value {
0 => P1_01MODER::PULL_UP,
1 => P1_01MODER::REPEATER,
2 => P1_01MODER::DISABLED,
3 => P1_01MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_01MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_01MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_01MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_01MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_04MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_04MODER {
#[doc = "Pull-up. P1.4 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.4 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.4 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.4 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_04MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_04MODER::PULL_UP => 0,
P1_04MODER::REPEATER => 0x01,
P1_04MODER::DISABLED => 0x02,
P1_04MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_04MODER {
match value {
0 => P1_04MODER::PULL_UP,
1 => P1_04MODER::REPEATER,
2 => P1_04MODER::DISABLED,
3 => P1_04MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_04MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_04MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_04MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_04MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_08MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_08MODER {
#[doc = "Pull-up. P1.8 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.8 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.8 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.8 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_08MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_08MODER::PULL_UP => 0,
P1_08MODER::REPEATER => 0x01,
P1_08MODER::DISABLED => 0x02,
P1_08MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_08MODER {
match value {
0 => P1_08MODER::PULL_UP,
1 => P1_08MODER::REPEATER,
2 => P1_08MODER::DISABLED,
3 => P1_08MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_08MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_08MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_08MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_08MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_09MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_09MODER {
#[doc = "Pull-up. P1.9 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.9 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.9 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.9 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_09MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_09MODER::PULL_UP => 0,
P1_09MODER::REPEATER => 0x01,
P1_09MODER::DISABLED => 0x02,
P1_09MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_09MODER {
match value {
0 => P1_09MODER::PULL_UP,
1 => P1_09MODER::REPEATER,
2 => P1_09MODER::DISABLED,
3 => P1_09MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_09MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_09MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_09MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_09MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_10MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_10MODER {
#[doc = "Pull-up. P1.10 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.10 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.10 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.10 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_10MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_10MODER::PULL_UP => 0,
P1_10MODER::REPEATER => 0x01,
P1_10MODER::DISABLED => 0x02,
P1_10MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_10MODER {
match value {
0 => P1_10MODER::PULL_UP,
1 => P1_10MODER::REPEATER,
2 => P1_10MODER::DISABLED,
3 => P1_10MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_10MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_10MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_10MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_10MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_14MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_14MODER {
#[doc = "Pull-up. P1.14 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.14 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.14 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.14 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_14MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_14MODER::PULL_UP => 0,
P1_14MODER::REPEATER => 0x01,
P1_14MODER::DISABLED => 0x02,
P1_14MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_14MODER {
match value {
0 => P1_14MODER::PULL_UP,
1 => P1_14MODER::REPEATER,
2 => P1_14MODER::DISABLED,
3 => P1_14MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_14MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_14MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_14MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_14MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_15MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_15MODER {
#[doc = "Pull-up. P1.15 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.15 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.15 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.15 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_15MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_15MODER::PULL_UP => 0,
P1_15MODER::REPEATER => 0x01,
P1_15MODER::DISABLED => 0x02,
P1_15MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_15MODER {
match value {
0 => P1_15MODER::PULL_UP,
1 => P1_15MODER::REPEATER,
2 => P1_15MODER::DISABLED,
3 => P1_15MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_15MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_15MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_15MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_15MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P1_00MODE`"]
pub enum P1_00MODEW {
#[doc = "Pull-up. P1.0 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.0 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.0 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.0 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_00MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_00MODEW::PULL_UP => 0,
P1_00MODEW::REPEATER => 1,
P1_00MODEW::DISABLED => 2,
P1_00MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_00MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_00MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_00MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.0 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_00MODEW::PULL_UP)
}
#[doc = "Repeater. P1.0 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_00MODEW::REPEATER)
}
#[doc = "Disabled. P1.0 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_00MODEW::DISABLED)
}
#[doc = "Pull-down. P1.0 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_00MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_01MODE`"]
pub enum P1_01MODEW {
#[doc = "Pull-up. P1.1 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.1 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.1 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.1 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_01MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_01MODEW::PULL_UP => 0,
P1_01MODEW::REPEATER => 1,
P1_01MODEW::DISABLED => 2,
P1_01MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_01MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_01MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_01MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.1 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_01MODEW::PULL_UP)
}
#[doc = "Repeater. P1.1 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_01MODEW::REPEATER)
}
#[doc = "Disabled. P1.1 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_01MODEW::DISABLED)
}
#[doc = "Pull-down. P1.1 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_01MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_04MODE`"]
pub enum P1_04MODEW {
#[doc = "Pull-up. P1.4 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.4 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.4 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.4 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_04MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_04MODEW::PULL_UP => 0,
P1_04MODEW::REPEATER => 1,
P1_04MODEW::DISABLED => 2,
P1_04MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_04MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_04MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_04MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.4 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_04MODEW::PULL_UP)
}
#[doc = "Repeater. P1.4 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_04MODEW::REPEATER)
}
#[doc = "Disabled. P1.4 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_04MODEW::DISABLED)
}
#[doc = "Pull-down. P1.4 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_04MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_08MODE`"]
pub enum P1_08MODEW {
#[doc = "Pull-up. P1.8 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.8 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.8 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.8 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_08MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_08MODEW::PULL_UP => 0,
P1_08MODEW::REPEATER => 1,
P1_08MODEW::DISABLED => 2,
P1_08MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_08MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_08MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_08MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.8 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_08MODEW::PULL_UP)
}
#[doc = "Repeater. P1.8 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_08MODEW::REPEATER)
}
#[doc = "Disabled. P1.8 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_08MODEW::DISABLED)
}
#[doc = "Pull-down. P1.8 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_08MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_09MODE`"]
pub enum P1_09MODEW {
#[doc = "Pull-up. P1.9 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.9 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.9 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.9 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_09MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_09MODEW::PULL_UP => 0,
P1_09MODEW::REPEATER => 1,
P1_09MODEW::DISABLED => 2,
P1_09MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_09MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_09MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_09MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.9 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_09MODEW::PULL_UP)
}
#[doc = "Repeater. P1.9 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_09MODEW::REPEATER)
}
#[doc = "Disabled. P1.9 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_09MODEW::DISABLED)
}
#[doc = "Pull-down. P1.9 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_09MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_10MODE`"]
pub enum P1_10MODEW {
#[doc = "Pull-up. P1.10 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.10 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.10 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.10 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_10MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_10MODEW::PULL_UP => 0,
P1_10MODEW::REPEATER => 1,
P1_10MODEW::DISABLED => 2,
P1_10MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_10MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_10MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_10MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.10 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_10MODEW::PULL_UP)
}
#[doc = "Repeater. P1.10 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_10MODEW::REPEATER)
}
#[doc = "Disabled. P1.10 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_10MODEW::DISABLED)
}
#[doc = "Pull-down. P1.10 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_10MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_14MODE`"]
pub enum P1_14MODEW {
#[doc = "Pull-up. P1.14 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.14 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.14 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.14 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_14MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_14MODEW::PULL_UP => 0,
P1_14MODEW::REPEATER => 1,
P1_14MODEW::DISABLED => 2,
P1_14MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_14MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_14MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_14MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.14 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_14MODEW::PULL_UP)
}
#[doc = "Repeater. P1.14 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_14MODEW::REPEATER)
}
#[doc = "Disabled. P1.14 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_14MODEW::DISABLED)
}
#[doc = "Pull-down. P1.14 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_14MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_15MODE`"]
pub enum P1_15MODEW {
#[doc = "Pull-up. P1.15 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.15 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.15 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.15 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_15MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_15MODEW::PULL_UP => 0,
P1_15MODEW::REPEATER => 1,
P1_15MODEW::DISABLED => 2,
P1_15MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_15MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_15MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_15MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.15 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_15MODEW::PULL_UP)
}
#[doc = "Repeater. P1.15 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_15MODEW::REPEATER)
}
#[doc = "Disabled. P1.15 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_15MODEW::DISABLED)
}
#[doc = "Pull-down. P1.15 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_15MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Port 1 pin 0 control."]
#[inline]
pub fn p1_00mode(&self) -> P1_00MODER {
P1_00MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Port 1 pin 1 control."]
#[inline]
pub fn p1_01mode(&self) -> P1_01MODER {
P1_01MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Port 1 pin 4 control."]
#[inline]
pub fn p1_04mode(&self) -> P1_04MODER {
P1_04MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Port 1 pin 8 control."]
#[inline]
pub fn p1_08mode(&self) -> P1_08MODER {
P1_08MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Port 1 pin 9 control."]
#[inline]
pub fn p1_09mode(&self) -> P1_09MODER {
P1_09MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Port 1 pin 10 control."]
#[inline]
pub fn p1_10mode(&self) -> P1_10MODER {
P1_10MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 28:29 - Port 1 pin 14 control."]
#[inline]
pub fn p1_14mode(&self) -> P1_14MODER {
P1_14MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Port 1 pin 15 control."]
#[inline]
pub fn p1_15mode(&self) -> P1_15MODER {
P1_15MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Port 1 pin 0 control."]
#[inline]
pub fn p1_00mode(&mut self) -> _P1_00MODEW {
_P1_00MODEW { w: self }
}
#[doc = "Bits 2:3 - Port 1 pin 1 control."]
#[inline]
pub fn p1_01mode(&mut self) -> _P1_01MODEW {
_P1_01MODEW { w: self }
}
#[doc = "Bits 8:9 - Port 1 pin 4 control."]
#[inline]
pub fn p1_04mode(&mut self) -> _P1_04MODEW {
_P1_04MODEW { w: self }
}
#[doc = "Bits 16:17 - Port 1 pin 8 control."]
#[inline]
pub fn p1_08mode(&mut self) -> _P1_08MODEW {
_P1_08MODEW { w: self }
}
#[doc = "Bits 18:19 - Port 1 pin 9 control."]
#[inline]
pub fn p1_09mode(&mut self) -> _P1_09MODEW {
_P1_09MODEW { w: self }
}
#[doc = "Bits 20:21 - Port 1 pin 10 control."]
#[inline]
pub fn p1_10mode(&mut self) -> _P1_10MODEW {
_P1_10MODEW { w: self }
}
#[doc = "Bits 28:29 - Port 1 pin 14 control."]
#[inline]
pub fn p1_14mode(&mut self) -> _P1_14MODEW {
_P1_14MODEW { w: self }
}
#[doc = "Bits 30:31 - Port 1 pin 15 control."]
#[inline]
pub fn p1_15mode(&mut self) -> _P1_15MODEW {
_P1_15MODEW { w: self }
}
}
}
#[doc = "Pin mode select register 3."]
pub struct PINMODE3 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 3."]
pub mod pinmode3 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P1_16MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_16MODER {
#[doc = "Pull-up. P1.16 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.16 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.16 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.16 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_16MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_16MODER::PULL_UP => 0,
P1_16MODER::REPEATER => 0x01,
P1_16MODER::DISABLED => 0x02,
P1_16MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_16MODER {
match value {
0 => P1_16MODER::PULL_UP,
1 => P1_16MODER::REPEATER,
2 => P1_16MODER::DISABLED,
3 => P1_16MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_16MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_16MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_16MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_16MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_17MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_17MODER {
#[doc = "Pull-up. P1.17 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.17 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.17 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.17 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_17MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_17MODER::PULL_UP => 0,
P1_17MODER::REPEATER => 0x01,
P1_17MODER::DISABLED => 0x02,
P1_17MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_17MODER {
match value {
0 => P1_17MODER::PULL_UP,
1 => P1_17MODER::REPEATER,
2 => P1_17MODER::DISABLED,
3 => P1_17MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_17MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_17MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_17MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_17MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_18MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_18MODER {
#[doc = "Pull-up. P1.18 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.18 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.18 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.18 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_18MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_18MODER::PULL_UP => 0,
P1_18MODER::REPEATER => 0x01,
P1_18MODER::DISABLED => 0x02,
P1_18MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_18MODER {
match value {
0 => P1_18MODER::PULL_UP,
1 => P1_18MODER::REPEATER,
2 => P1_18MODER::DISABLED,
3 => P1_18MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_18MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_18MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_18MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_18MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_19MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_19MODER {
#[doc = "Pull-up. P1.19 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.19 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.19 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.19 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_19MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_19MODER::PULL_UP => 0,
P1_19MODER::REPEATER => 0x01,
P1_19MODER::DISABLED => 0x02,
P1_19MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_19MODER {
match value {
0 => P1_19MODER::PULL_UP,
1 => P1_19MODER::REPEATER,
2 => P1_19MODER::DISABLED,
3 => P1_19MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_19MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_19MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_19MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_19MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_20MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_20MODER {
#[doc = "Pull-up. P1.20 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.20 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.20 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.20 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_20MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_20MODER::PULL_UP => 0,
P1_20MODER::REPEATER => 0x01,
P1_20MODER::DISABLED => 0x02,
P1_20MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_20MODER {
match value {
0 => P1_20MODER::PULL_UP,
1 => P1_20MODER::REPEATER,
2 => P1_20MODER::DISABLED,
3 => P1_20MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_20MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_20MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_20MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_20MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_21MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_21MODER {
#[doc = "Pull-up. P1.21 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.21 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.21 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.21 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_21MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_21MODER::PULL_UP => 0,
P1_21MODER::REPEATER => 0x01,
P1_21MODER::DISABLED => 0x02,
P1_21MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_21MODER {
match value {
0 => P1_21MODER::PULL_UP,
1 => P1_21MODER::REPEATER,
2 => P1_21MODER::DISABLED,
3 => P1_21MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_21MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_21MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_21MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_21MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_22MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_22MODER {
#[doc = "Pull-up. P1.22 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.22 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.22 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.22 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_22MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_22MODER::PULL_UP => 0,
P1_22MODER::REPEATER => 0x01,
P1_22MODER::DISABLED => 0x02,
P1_22MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_22MODER {
match value {
0 => P1_22MODER::PULL_UP,
1 => P1_22MODER::REPEATER,
2 => P1_22MODER::DISABLED,
3 => P1_22MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_22MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_22MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_22MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_22MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_23MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_23MODER {
#[doc = "Pull-up. P1.23 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.23 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.23 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.23 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_23MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_23MODER::PULL_UP => 0,
P1_23MODER::REPEATER => 0x01,
P1_23MODER::DISABLED => 0x02,
P1_23MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_23MODER {
match value {
0 => P1_23MODER::PULL_UP,
1 => P1_23MODER::REPEATER,
2 => P1_23MODER::DISABLED,
3 => P1_23MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_23MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_23MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_23MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_23MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_24MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_24MODER {
#[doc = "Pull-up. P1.24 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.24 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.24 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.24 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_24MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_24MODER::PULL_UP => 0,
P1_24MODER::REPEATER => 0x01,
P1_24MODER::DISABLED => 0x02,
P1_24MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_24MODER {
match value {
0 => P1_24MODER::PULL_UP,
1 => P1_24MODER::REPEATER,
2 => P1_24MODER::DISABLED,
3 => P1_24MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_24MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_24MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_24MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_24MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_25MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_25MODER {
#[doc = "Pull-up. P1.25 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.25 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.25 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.25 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_25MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_25MODER::PULL_UP => 0,
P1_25MODER::REPEATER => 0x01,
P1_25MODER::DISABLED => 0x02,
P1_25MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_25MODER {
match value {
0 => P1_25MODER::PULL_UP,
1 => P1_25MODER::REPEATER,
2 => P1_25MODER::DISABLED,
3 => P1_25MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_25MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_25MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_25MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_25MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_26MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_26MODER {
#[doc = "Pull-up. P1.26 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.26 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.26 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.26 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_26MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_26MODER::PULL_UP => 0,
P1_26MODER::REPEATER => 0x01,
P1_26MODER::DISABLED => 0x02,
P1_26MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_26MODER {
match value {
0 => P1_26MODER::PULL_UP,
1 => P1_26MODER::REPEATER,
2 => P1_26MODER::DISABLED,
3 => P1_26MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_26MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_26MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_26MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_26MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_27MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_27MODER {
#[doc = "Pull-up. P1.27 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.27 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.27 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.27 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_27MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_27MODER::PULL_UP => 0,
P1_27MODER::REPEATER => 0x01,
P1_27MODER::DISABLED => 0x02,
P1_27MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_27MODER {
match value {
0 => P1_27MODER::PULL_UP,
1 => P1_27MODER::REPEATER,
2 => P1_27MODER::DISABLED,
3 => P1_27MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_27MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_27MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_27MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_27MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_28MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_28MODER {
#[doc = "Pull-up. P1.28 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.28 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.28 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.28 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_28MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_28MODER::PULL_UP => 0,
P1_28MODER::REPEATER => 0x01,
P1_28MODER::DISABLED => 0x02,
P1_28MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_28MODER {
match value {
0 => P1_28MODER::PULL_UP,
1 => P1_28MODER::REPEATER,
2 => P1_28MODER::DISABLED,
3 => P1_28MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_28MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_28MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_28MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_28MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_29MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_29MODER {
#[doc = "Pull-up. P1.29 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.29 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.29 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.29 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_29MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_29MODER::PULL_UP => 0,
P1_29MODER::REPEATER => 0x01,
P1_29MODER::DISABLED => 0x02,
P1_29MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_29MODER {
match value {
0 => P1_29MODER::PULL_UP,
1 => P1_29MODER::REPEATER,
2 => P1_29MODER::DISABLED,
3 => P1_29MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_29MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_29MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_29MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_29MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_30MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_30MODER {
#[doc = "Pull-up. P1.30 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.30 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.30 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.30 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_30MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_30MODER::PULL_UP => 0,
P1_30MODER::REPEATER => 0x01,
P1_30MODER::DISABLED => 0x02,
P1_30MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_30MODER {
match value {
0 => P1_30MODER::PULL_UP,
1 => P1_30MODER::REPEATER,
2 => P1_30MODER::DISABLED,
3 => P1_30MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_30MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_30MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_30MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_30MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P1_31MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_31MODER {
#[doc = "Pull-up. P1.31 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.31 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.31 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.31 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_31MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P1_31MODER::PULL_UP => 0,
P1_31MODER::REPEATER => 0x01,
P1_31MODER::DISABLED => 0x02,
P1_31MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P1_31MODER {
match value {
0 => P1_31MODER::PULL_UP,
1 => P1_31MODER::REPEATER,
2 => P1_31MODER::DISABLED,
3 => P1_31MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P1_31MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P1_31MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P1_31MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P1_31MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P1_16MODE`"]
pub enum P1_16MODEW {
#[doc = "Pull-up. P1.16 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.16 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.16 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.16 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_16MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_16MODEW::PULL_UP => 0,
P1_16MODEW::REPEATER => 1,
P1_16MODEW::DISABLED => 2,
P1_16MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_16MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_16MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_16MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.16 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_16MODEW::PULL_UP)
}
#[doc = "Repeater. P1.16 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_16MODEW::REPEATER)
}
#[doc = "Disabled. P1.16 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_16MODEW::DISABLED)
}
#[doc = "Pull-down. P1.16 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_16MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_17MODE`"]
pub enum P1_17MODEW {
#[doc = "Pull-up. P1.17 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.17 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.17 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.17 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_17MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_17MODEW::PULL_UP => 0,
P1_17MODEW::REPEATER => 1,
P1_17MODEW::DISABLED => 2,
P1_17MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_17MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_17MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_17MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.17 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_17MODEW::PULL_UP)
}
#[doc = "Repeater. P1.17 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_17MODEW::REPEATER)
}
#[doc = "Disabled. P1.17 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_17MODEW::DISABLED)
}
#[doc = "Pull-down. P1.17 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_17MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_18MODE`"]
pub enum P1_18MODEW {
#[doc = "Pull-up. P1.18 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.18 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.18 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.18 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_18MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_18MODEW::PULL_UP => 0,
P1_18MODEW::REPEATER => 1,
P1_18MODEW::DISABLED => 2,
P1_18MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_18MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_18MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_18MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.18 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_18MODEW::PULL_UP)
}
#[doc = "Repeater. P1.18 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_18MODEW::REPEATER)
}
#[doc = "Disabled. P1.18 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_18MODEW::DISABLED)
}
#[doc = "Pull-down. P1.18 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_18MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_19MODE`"]
pub enum P1_19MODEW {
#[doc = "Pull-up. P1.19 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.19 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.19 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.19 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_19MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_19MODEW::PULL_UP => 0,
P1_19MODEW::REPEATER => 1,
P1_19MODEW::DISABLED => 2,
P1_19MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_19MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_19MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_19MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.19 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_19MODEW::PULL_UP)
}
#[doc = "Repeater. P1.19 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_19MODEW::REPEATER)
}
#[doc = "Disabled. P1.19 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_19MODEW::DISABLED)
}
#[doc = "Pull-down. P1.19 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_19MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_20MODE`"]
pub enum P1_20MODEW {
#[doc = "Pull-up. P1.20 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.20 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.20 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.20 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_20MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_20MODEW::PULL_UP => 0,
P1_20MODEW::REPEATER => 1,
P1_20MODEW::DISABLED => 2,
P1_20MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_20MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_20MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_20MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.20 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_20MODEW::PULL_UP)
}
#[doc = "Repeater. P1.20 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_20MODEW::REPEATER)
}
#[doc = "Disabled. P1.20 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_20MODEW::DISABLED)
}
#[doc = "Pull-down. P1.20 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_20MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_21MODE`"]
pub enum P1_21MODEW {
#[doc = "Pull-up. P1.21 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.21 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.21 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.21 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_21MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_21MODEW::PULL_UP => 0,
P1_21MODEW::REPEATER => 1,
P1_21MODEW::DISABLED => 2,
P1_21MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_21MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_21MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_21MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.21 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_21MODEW::PULL_UP)
}
#[doc = "Repeater. P1.21 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_21MODEW::REPEATER)
}
#[doc = "Disabled. P1.21 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_21MODEW::DISABLED)
}
#[doc = "Pull-down. P1.21 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_21MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_22MODE`"]
pub enum P1_22MODEW {
#[doc = "Pull-up. P1.22 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.22 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.22 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.22 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_22MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_22MODEW::PULL_UP => 0,
P1_22MODEW::REPEATER => 1,
P1_22MODEW::DISABLED => 2,
P1_22MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_22MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_22MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_22MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.22 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_22MODEW::PULL_UP)
}
#[doc = "Repeater. P1.22 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_22MODEW::REPEATER)
}
#[doc = "Disabled. P1.22 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_22MODEW::DISABLED)
}
#[doc = "Pull-down. P1.22 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_22MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_23MODE`"]
pub enum P1_23MODEW {
#[doc = "Pull-up. P1.23 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.23 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.23 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.23 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_23MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_23MODEW::PULL_UP => 0,
P1_23MODEW::REPEATER => 1,
P1_23MODEW::DISABLED => 2,
P1_23MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_23MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_23MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_23MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.23 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_23MODEW::PULL_UP)
}
#[doc = "Repeater. P1.23 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_23MODEW::REPEATER)
}
#[doc = "Disabled. P1.23 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_23MODEW::DISABLED)
}
#[doc = "Pull-down. P1.23 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_23MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_24MODE`"]
pub enum P1_24MODEW {
#[doc = "Pull-up. P1.24 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.24 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.24 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.24 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_24MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_24MODEW::PULL_UP => 0,
P1_24MODEW::REPEATER => 1,
P1_24MODEW::DISABLED => 2,
P1_24MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_24MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_24MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_24MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.24 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_24MODEW::PULL_UP)
}
#[doc = "Repeater. P1.24 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_24MODEW::REPEATER)
}
#[doc = "Disabled. P1.24 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_24MODEW::DISABLED)
}
#[doc = "Pull-down. P1.24 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_24MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_25MODE`"]
pub enum P1_25MODEW {
#[doc = "Pull-up. P1.25 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.25 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.25 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.25 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_25MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_25MODEW::PULL_UP => 0,
P1_25MODEW::REPEATER => 1,
P1_25MODEW::DISABLED => 2,
P1_25MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_25MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_25MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_25MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.25 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_25MODEW::PULL_UP)
}
#[doc = "Repeater. P1.25 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_25MODEW::REPEATER)
}
#[doc = "Disabled. P1.25 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_25MODEW::DISABLED)
}
#[doc = "Pull-down. P1.25 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_25MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_26MODE`"]
pub enum P1_26MODEW {
#[doc = "Pull-up. P1.26 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.26 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.26 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.26 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_26MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_26MODEW::PULL_UP => 0,
P1_26MODEW::REPEATER => 1,
P1_26MODEW::DISABLED => 2,
P1_26MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_26MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_26MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_26MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.26 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_26MODEW::PULL_UP)
}
#[doc = "Repeater. P1.26 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_26MODEW::REPEATER)
}
#[doc = "Disabled. P1.26 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_26MODEW::DISABLED)
}
#[doc = "Pull-down. P1.26 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_26MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_27MODE`"]
pub enum P1_27MODEW {
#[doc = "Pull-up. P1.27 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.27 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.27 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.27 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_27MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_27MODEW::PULL_UP => 0,
P1_27MODEW::REPEATER => 1,
P1_27MODEW::DISABLED => 2,
P1_27MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_27MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_27MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_27MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.27 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_27MODEW::PULL_UP)
}
#[doc = "Repeater. P1.27 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_27MODEW::REPEATER)
}
#[doc = "Disabled. P1.27 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_27MODEW::DISABLED)
}
#[doc = "Pull-down. P1.27 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_27MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_28MODE`"]
pub enum P1_28MODEW {
#[doc = "Pull-up. P1.28 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.28 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.28 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.28 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_28MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_28MODEW::PULL_UP => 0,
P1_28MODEW::REPEATER => 1,
P1_28MODEW::DISABLED => 2,
P1_28MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_28MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_28MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_28MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.28 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_28MODEW::PULL_UP)
}
#[doc = "Repeater. P1.28 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_28MODEW::REPEATER)
}
#[doc = "Disabled. P1.28 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_28MODEW::DISABLED)
}
#[doc = "Pull-down. P1.28 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_28MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_29MODE`"]
pub enum P1_29MODEW {
#[doc = "Pull-up. P1.29 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.29 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.29 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.29 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_29MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_29MODEW::PULL_UP => 0,
P1_29MODEW::REPEATER => 1,
P1_29MODEW::DISABLED => 2,
P1_29MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_29MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_29MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_29MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.29 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_29MODEW::PULL_UP)
}
#[doc = "Repeater. P1.29 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_29MODEW::REPEATER)
}
#[doc = "Disabled. P1.29 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_29MODEW::DISABLED)
}
#[doc = "Pull-down. P1.29 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_29MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_30MODE`"]
pub enum P1_30MODEW {
#[doc = "Pull-up. P1.30 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.30 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.30 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.30 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_30MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_30MODEW::PULL_UP => 0,
P1_30MODEW::REPEATER => 1,
P1_30MODEW::DISABLED => 2,
P1_30MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_30MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_30MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_30MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.30 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_30MODEW::PULL_UP)
}
#[doc = "Repeater. P1.30 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_30MODEW::REPEATER)
}
#[doc = "Disabled. P1.30 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_30MODEW::DISABLED)
}
#[doc = "Pull-down. P1.30 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_30MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_31MODE`"]
pub enum P1_31MODEW {
#[doc = "Pull-up. P1.31 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P1.31 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P1.31 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P1.31 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P1_31MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P1_31MODEW::PULL_UP => 0,
P1_31MODEW::REPEATER => 1,
P1_31MODEW::DISABLED => 2,
P1_31MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_31MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P1_31MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_31MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P1.31 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P1_31MODEW::PULL_UP)
}
#[doc = "Repeater. P1.31 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P1_31MODEW::REPEATER)
}
#[doc = "Disabled. P1.31 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P1_31MODEW::DISABLED)
}
#[doc = "Pull-down. P1.31 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P1_31MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Port 1 pin 16 control."]
#[inline]
pub fn p1_16mode(&self) -> P1_16MODER {
P1_16MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Port 1 pin 17 control."]
#[inline]
pub fn p1_17mode(&self) -> P1_17MODER {
P1_17MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Port 1 pin 18 control."]
#[inline]
pub fn p1_18mode(&self) -> P1_18MODER {
P1_18MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Port 1 pin 19 control."]
#[inline]
pub fn p1_19mode(&self) -> P1_19MODER {
P1_19MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Port 1 pin 20 control."]
#[inline]
pub fn p1_20mode(&self) -> P1_20MODER {
P1_20MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Port 1 pin 21 control."]
#[inline]
pub fn p1_21mode(&self) -> P1_21MODER {
P1_21MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Port 1 pin 22 control."]
#[inline]
pub fn p1_22mode(&self) -> P1_22MODER {
P1_22MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Port 1 pin 23 control."]
#[inline]
pub fn p1_23mode(&self) -> P1_23MODER {
P1_23MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Port 1 pin 24 control."]
#[inline]
pub fn p1_24mode(&self) -> P1_24MODER {
P1_24MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Port 1 pin 25 control."]
#[inline]
pub fn p1_25mode(&self) -> P1_25MODER {
P1_25MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Port 1 pin 26 control."]
#[inline]
pub fn p1_26mode(&self) -> P1_26MODER {
P1_26MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Port 1 pin 27 control."]
#[inline]
pub fn p1_27mode(&self) -> P1_27MODER {
P1_27MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:25 - Port 1 pin 28 control."]
#[inline]
pub fn p1_28mode(&self) -> P1_28MODER {
P1_28MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Port 1 pin 29 control."]
#[inline]
pub fn p1_29mode(&self) -> P1_29MODER {
P1_29MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 28:29 - Port 1 pin 30 control."]
#[inline]
pub fn p1_30mode(&self) -> P1_30MODER {
P1_30MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Port 1 pin 31 control."]
#[inline]
pub fn p1_31mode(&self) -> P1_31MODER {
P1_31MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Port 1 pin 16 control."]
#[inline]
pub fn p1_16mode(&mut self) -> _P1_16MODEW {
_P1_16MODEW { w: self }
}
#[doc = "Bits 2:3 - Port 1 pin 17 control."]
#[inline]
pub fn p1_17mode(&mut self) -> _P1_17MODEW {
_P1_17MODEW { w: self }
}
#[doc = "Bits 4:5 - Port 1 pin 18 control."]
#[inline]
pub fn p1_18mode(&mut self) -> _P1_18MODEW {
_P1_18MODEW { w: self }
}
#[doc = "Bits 6:7 - Port 1 pin 19 control."]
#[inline]
pub fn p1_19mode(&mut self) -> _P1_19MODEW {
_P1_19MODEW { w: self }
}
#[doc = "Bits 8:9 - Port 1 pin 20 control."]
#[inline]
pub fn p1_20mode(&mut self) -> _P1_20MODEW {
_P1_20MODEW { w: self }
}
#[doc = "Bits 10:11 - Port 1 pin 21 control."]
#[inline]
pub fn p1_21mode(&mut self) -> _P1_21MODEW {
_P1_21MODEW { w: self }
}
#[doc = "Bits 12:13 - Port 1 pin 22 control."]
#[inline]
pub fn p1_22mode(&mut self) -> _P1_22MODEW {
_P1_22MODEW { w: self }
}
#[doc = "Bits 14:15 - Port 1 pin 23 control."]
#[inline]
pub fn p1_23mode(&mut self) -> _P1_23MODEW {
_P1_23MODEW { w: self }
}
#[doc = "Bits 16:17 - Port 1 pin 24 control."]
#[inline]
pub fn p1_24mode(&mut self) -> _P1_24MODEW {
_P1_24MODEW { w: self }
}
#[doc = "Bits 18:19 - Port 1 pin 25 control."]
#[inline]
pub fn p1_25mode(&mut self) -> _P1_25MODEW {
_P1_25MODEW { w: self }
}
#[doc = "Bits 20:21 - Port 1 pin 26 control."]
#[inline]
pub fn p1_26mode(&mut self) -> _P1_26MODEW {
_P1_26MODEW { w: self }
}
#[doc = "Bits 22:23 - Port 1 pin 27 control."]
#[inline]
pub fn p1_27mode(&mut self) -> _P1_27MODEW {
_P1_27MODEW { w: self }
}
#[doc = "Bits 24:25 - Port 1 pin 28 control."]
#[inline]
pub fn p1_28mode(&mut self) -> _P1_28MODEW {
_P1_28MODEW { w: self }
}
#[doc = "Bits 26:27 - Port 1 pin 29 control."]
#[inline]
pub fn p1_29mode(&mut self) -> _P1_29MODEW {
_P1_29MODEW { w: self }
}
#[doc = "Bits 28:29 - Port 1 pin 30 control."]
#[inline]
pub fn p1_30mode(&mut self) -> _P1_30MODEW {
_P1_30MODEW { w: self }
}
#[doc = "Bits 30:31 - Port 1 pin 31 control."]
#[inline]
pub fn p1_31mode(&mut self) -> _P1_31MODEW {
_P1_31MODEW { w: self }
}
}
}
#[doc = "Pin mode select register 4"]
pub struct PINMODE4 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 4"]
pub mod pinmode4 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE4 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P2_00MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_00MODER {
#[doc = "Pull-up. P2.0 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.0 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.0 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.0 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_00MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_00MODER::PULL_UP => 0,
P2_00MODER::REPEATER => 0x01,
P2_00MODER::DISABLED => 0x02,
P2_00MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_00MODER {
match value {
0 => P2_00MODER::PULL_UP,
1 => P2_00MODER::REPEATER,
2 => P2_00MODER::DISABLED,
3 => P2_00MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_00MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_00MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_00MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_00MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_01MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_01MODER {
#[doc = "Pull-up. P2.1 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.1 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.1 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.1 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_01MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_01MODER::PULL_UP => 0,
P2_01MODER::REPEATER => 0x01,
P2_01MODER::DISABLED => 0x02,
P2_01MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_01MODER {
match value {
0 => P2_01MODER::PULL_UP,
1 => P2_01MODER::REPEATER,
2 => P2_01MODER::DISABLED,
3 => P2_01MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_01MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_01MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_01MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_01MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_02MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_02MODER {
#[doc = "Pull-up. P2.2 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.2 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.2 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.2 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_02MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_02MODER::PULL_UP => 0,
P2_02MODER::REPEATER => 0x01,
P2_02MODER::DISABLED => 0x02,
P2_02MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_02MODER {
match value {
0 => P2_02MODER::PULL_UP,
1 => P2_02MODER::REPEATER,
2 => P2_02MODER::DISABLED,
3 => P2_02MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_02MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_02MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_02MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_02MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_03MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_03MODER {
#[doc = "Pull-up. P2.3 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.3 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.3 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.3 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_03MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_03MODER::PULL_UP => 0,
P2_03MODER::REPEATER => 0x01,
P2_03MODER::DISABLED => 0x02,
P2_03MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_03MODER {
match value {
0 => P2_03MODER::PULL_UP,
1 => P2_03MODER::REPEATER,
2 => P2_03MODER::DISABLED,
3 => P2_03MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_03MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_03MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_03MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_03MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_04MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_04MODER {
#[doc = "Pull-up. P2.4 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.4 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.4 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.4 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_04MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_04MODER::PULL_UP => 0,
P2_04MODER::REPEATER => 0x01,
P2_04MODER::DISABLED => 0x02,
P2_04MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_04MODER {
match value {
0 => P2_04MODER::PULL_UP,
1 => P2_04MODER::REPEATER,
2 => P2_04MODER::DISABLED,
3 => P2_04MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_04MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_04MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_04MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_04MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_05MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_05MODER {
#[doc = "Pull-up. P2.5 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.5 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.5 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.5 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_05MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_05MODER::PULL_UP => 0,
P2_05MODER::REPEATER => 0x01,
P2_05MODER::DISABLED => 0x02,
P2_05MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_05MODER {
match value {
0 => P2_05MODER::PULL_UP,
1 => P2_05MODER::REPEATER,
2 => P2_05MODER::DISABLED,
3 => P2_05MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_05MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_05MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_05MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_05MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_06MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_06MODER {
#[doc = "Pull-up. P2.6 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.6 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.6 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.6 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_06MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_06MODER::PULL_UP => 0,
P2_06MODER::REPEATER => 0x01,
P2_06MODER::DISABLED => 0x02,
P2_06MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_06MODER {
match value {
0 => P2_06MODER::PULL_UP,
1 => P2_06MODER::REPEATER,
2 => P2_06MODER::DISABLED,
3 => P2_06MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_06MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_06MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_06MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_06MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_07MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_07MODER {
#[doc = "Pull-up. P2.7 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.7 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.7 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.7 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_07MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_07MODER::PULL_UP => 0,
P2_07MODER::REPEATER => 0x01,
P2_07MODER::DISABLED => 0x02,
P2_07MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_07MODER {
match value {
0 => P2_07MODER::PULL_UP,
1 => P2_07MODER::REPEATER,
2 => P2_07MODER::DISABLED,
3 => P2_07MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_07MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_07MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_07MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_07MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_08MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_08MODER {
#[doc = "Pull-up. P2.8 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.8 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.8 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.8 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_08MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_08MODER::PULL_UP => 0,
P2_08MODER::REPEATER => 0x01,
P2_08MODER::DISABLED => 0x02,
P2_08MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_08MODER {
match value {
0 => P2_08MODER::PULL_UP,
1 => P2_08MODER::REPEATER,
2 => P2_08MODER::DISABLED,
3 => P2_08MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_08MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_08MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_08MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_08MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_09MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_09MODER {
#[doc = "Pull-up. P2.9 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.9 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.9 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.9 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_09MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_09MODER::PULL_UP => 0,
P2_09MODER::REPEATER => 0x01,
P2_09MODER::DISABLED => 0x02,
P2_09MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_09MODER {
match value {
0 => P2_09MODER::PULL_UP,
1 => P2_09MODER::REPEATER,
2 => P2_09MODER::DISABLED,
3 => P2_09MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_09MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_09MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_09MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_09MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_10MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_10MODER {
#[doc = "Pull-up. P2.10 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.10 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.10 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.10 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_10MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_10MODER::PULL_UP => 0,
P2_10MODER::REPEATER => 0x01,
P2_10MODER::DISABLED => 0x02,
P2_10MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_10MODER {
match value {
0 => P2_10MODER::PULL_UP,
1 => P2_10MODER::REPEATER,
2 => P2_10MODER::DISABLED,
3 => P2_10MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_10MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_10MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_10MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_10MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_11MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_11MODER {
#[doc = "Pull-up. P2.11 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.11 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.11 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.11 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_11MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_11MODER::PULL_UP => 0,
P2_11MODER::REPEATER => 0x01,
P2_11MODER::DISABLED => 0x02,
P2_11MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_11MODER {
match value {
0 => P2_11MODER::PULL_UP,
1 => P2_11MODER::REPEATER,
2 => P2_11MODER::DISABLED,
3 => P2_11MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_11MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_11MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_11MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_11MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_12MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_12MODER {
#[doc = "Pull-up. P2.12 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.12 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.12 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.12 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_12MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_12MODER::PULL_UP => 0,
P2_12MODER::REPEATER => 0x01,
P2_12MODER::DISABLED => 0x02,
P2_12MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_12MODER {
match value {
0 => P2_12MODER::PULL_UP,
1 => P2_12MODER::REPEATER,
2 => P2_12MODER::DISABLED,
3 => P2_12MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_12MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_12MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_12MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_12MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P2_13MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_13MODER {
#[doc = "Pull-up. P2.13 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.13 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.13 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.13 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_13MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P2_13MODER::PULL_UP => 0,
P2_13MODER::REPEATER => 0x01,
P2_13MODER::DISABLED => 0x02,
P2_13MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P2_13MODER {
match value {
0 => P2_13MODER::PULL_UP,
1 => P2_13MODER::REPEATER,
2 => P2_13MODER::DISABLED,
3 => P2_13MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P2_13MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P2_13MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P2_13MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P2_13MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P2_00MODE`"]
pub enum P2_00MODEW {
#[doc = "Pull-up. P2.0 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.0 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.0 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.0 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_00MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_00MODEW::PULL_UP => 0,
P2_00MODEW::REPEATER => 1,
P2_00MODEW::DISABLED => 2,
P2_00MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_00MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_00MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_00MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.0 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_00MODEW::PULL_UP)
}
#[doc = "Repeater. P2.0 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_00MODEW::REPEATER)
}
#[doc = "Disabled. P2.0 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_00MODEW::DISABLED)
}
#[doc = "Pull-down. P2.0 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_00MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_01MODE`"]
pub enum P2_01MODEW {
#[doc = "Pull-up. P2.1 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.1 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.1 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.1 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_01MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_01MODEW::PULL_UP => 0,
P2_01MODEW::REPEATER => 1,
P2_01MODEW::DISABLED => 2,
P2_01MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_01MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_01MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_01MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.1 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_01MODEW::PULL_UP)
}
#[doc = "Repeater. P2.1 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_01MODEW::REPEATER)
}
#[doc = "Disabled. P2.1 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_01MODEW::DISABLED)
}
#[doc = "Pull-down. P2.1 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_01MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_02MODE`"]
pub enum P2_02MODEW {
#[doc = "Pull-up. P2.2 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.2 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.2 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.2 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_02MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_02MODEW::PULL_UP => 0,
P2_02MODEW::REPEATER => 1,
P2_02MODEW::DISABLED => 2,
P2_02MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_02MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_02MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_02MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.2 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_02MODEW::PULL_UP)
}
#[doc = "Repeater. P2.2 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_02MODEW::REPEATER)
}
#[doc = "Disabled. P2.2 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_02MODEW::DISABLED)
}
#[doc = "Pull-down. P2.2 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_02MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_03MODE`"]
pub enum P2_03MODEW {
#[doc = "Pull-up. P2.3 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.3 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.3 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.3 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_03MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_03MODEW::PULL_UP => 0,
P2_03MODEW::REPEATER => 1,
P2_03MODEW::DISABLED => 2,
P2_03MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_03MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_03MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_03MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.3 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_03MODEW::PULL_UP)
}
#[doc = "Repeater. P2.3 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_03MODEW::REPEATER)
}
#[doc = "Disabled. P2.3 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_03MODEW::DISABLED)
}
#[doc = "Pull-down. P2.3 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_03MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_04MODE`"]
pub enum P2_04MODEW {
#[doc = "Pull-up. P2.4 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.4 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.4 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.4 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_04MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_04MODEW::PULL_UP => 0,
P2_04MODEW::REPEATER => 1,
P2_04MODEW::DISABLED => 2,
P2_04MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_04MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_04MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_04MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.4 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_04MODEW::PULL_UP)
}
#[doc = "Repeater. P2.4 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_04MODEW::REPEATER)
}
#[doc = "Disabled. P2.4 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_04MODEW::DISABLED)
}
#[doc = "Pull-down. P2.4 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_04MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_05MODE`"]
pub enum P2_05MODEW {
#[doc = "Pull-up. P2.5 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.5 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.5 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.5 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_05MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_05MODEW::PULL_UP => 0,
P2_05MODEW::REPEATER => 1,
P2_05MODEW::DISABLED => 2,
P2_05MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_05MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_05MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_05MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.5 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_05MODEW::PULL_UP)
}
#[doc = "Repeater. P2.5 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_05MODEW::REPEATER)
}
#[doc = "Disabled. P2.5 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_05MODEW::DISABLED)
}
#[doc = "Pull-down. P2.5 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_05MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_06MODE`"]
pub enum P2_06MODEW {
#[doc = "Pull-up. P2.6 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.6 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.6 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.6 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_06MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_06MODEW::PULL_UP => 0,
P2_06MODEW::REPEATER => 1,
P2_06MODEW::DISABLED => 2,
P2_06MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_06MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_06MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_06MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.6 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_06MODEW::PULL_UP)
}
#[doc = "Repeater. P2.6 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_06MODEW::REPEATER)
}
#[doc = "Disabled. P2.6 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_06MODEW::DISABLED)
}
#[doc = "Pull-down. P2.6 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_06MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_07MODE`"]
pub enum P2_07MODEW {
#[doc = "Pull-up. P2.7 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.7 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.7 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.7 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_07MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_07MODEW::PULL_UP => 0,
P2_07MODEW::REPEATER => 1,
P2_07MODEW::DISABLED => 2,
P2_07MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_07MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_07MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_07MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.7 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_07MODEW::PULL_UP)
}
#[doc = "Repeater. P2.7 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_07MODEW::REPEATER)
}
#[doc = "Disabled. P2.7 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_07MODEW::DISABLED)
}
#[doc = "Pull-down. P2.7 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_07MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_08MODE`"]
pub enum P2_08MODEW {
#[doc = "Pull-up. P2.8 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.8 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.8 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.8 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_08MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_08MODEW::PULL_UP => 0,
P2_08MODEW::REPEATER => 1,
P2_08MODEW::DISABLED => 2,
P2_08MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_08MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_08MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_08MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.8 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_08MODEW::PULL_UP)
}
#[doc = "Repeater. P2.8 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_08MODEW::REPEATER)
}
#[doc = "Disabled. P2.8 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_08MODEW::DISABLED)
}
#[doc = "Pull-down. P2.8 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_08MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_09MODE`"]
pub enum P2_09MODEW {
#[doc = "Pull-up. P2.9 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.9 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.9 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.9 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_09MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_09MODEW::PULL_UP => 0,
P2_09MODEW::REPEATER => 1,
P2_09MODEW::DISABLED => 2,
P2_09MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_09MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_09MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_09MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.9 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_09MODEW::PULL_UP)
}
#[doc = "Repeater. P2.9 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_09MODEW::REPEATER)
}
#[doc = "Disabled. P2.9 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_09MODEW::DISABLED)
}
#[doc = "Pull-down. P2.9 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_09MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_10MODE`"]
pub enum P2_10MODEW {
#[doc = "Pull-up. P2.10 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.10 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.10 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.10 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_10MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_10MODEW::PULL_UP => 0,
P2_10MODEW::REPEATER => 1,
P2_10MODEW::DISABLED => 2,
P2_10MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_10MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_10MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_10MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.10 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_10MODEW::PULL_UP)
}
#[doc = "Repeater. P2.10 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_10MODEW::REPEATER)
}
#[doc = "Disabled. P2.10 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_10MODEW::DISABLED)
}
#[doc = "Pull-down. P2.10 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_10MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_11MODE`"]
pub enum P2_11MODEW {
#[doc = "Pull-up. P2.11 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.11 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.11 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.11 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_11MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_11MODEW::PULL_UP => 0,
P2_11MODEW::REPEATER => 1,
P2_11MODEW::DISABLED => 2,
P2_11MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_11MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_11MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_11MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.11 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_11MODEW::PULL_UP)
}
#[doc = "Repeater. P2.11 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_11MODEW::REPEATER)
}
#[doc = "Disabled. P2.11 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_11MODEW::DISABLED)
}
#[doc = "Pull-down. P2.11 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_11MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_12MODE`"]
pub enum P2_12MODEW {
#[doc = "Pull-up. P2.12 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.12 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.12 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.12 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_12MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_12MODEW::PULL_UP => 0,
P2_12MODEW::REPEATER => 1,
P2_12MODEW::DISABLED => 2,
P2_12MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_12MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_12MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_12MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.12 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_12MODEW::PULL_UP)
}
#[doc = "Repeater. P2.12 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_12MODEW::REPEATER)
}
#[doc = "Disabled. P2.12 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_12MODEW::DISABLED)
}
#[doc = "Pull-down. P2.12 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_12MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_13MODE`"]
pub enum P2_13MODEW {
#[doc = "Pull-up. P2.13 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P2.13 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P2.13 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P2.13 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P2_13MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P2_13MODEW::PULL_UP => 0,
P2_13MODEW::REPEATER => 1,
P2_13MODEW::DISABLED => 2,
P2_13MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_13MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P2_13MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_13MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P2.13 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P2_13MODEW::PULL_UP)
}
#[doc = "Repeater. P2.13 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P2_13MODEW::REPEATER)
}
#[doc = "Disabled. P2.13 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P2_13MODEW::DISABLED)
}
#[doc = "Pull-down. P2.13 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P2_13MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Port 2 pin 0 control."]
#[inline]
pub fn p2_00mode(&self) -> P2_00MODER {
P2_00MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Port 2 pin 1 control."]
#[inline]
pub fn p2_01mode(&self) -> P2_01MODER {
P2_01MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Port 2 pin 2 control."]
#[inline]
pub fn p2_02mode(&self) -> P2_02MODER {
P2_02MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Port 2 pin 3 control."]
#[inline]
pub fn p2_03mode(&self) -> P2_03MODER {
P2_03MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Port 2 pin 4 control."]
#[inline]
pub fn p2_04mode(&self) -> P2_04MODER {
P2_04MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Port 2 pin 5 control."]
#[inline]
pub fn p2_05mode(&self) -> P2_05MODER {
P2_05MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Port 2 pin 6 control."]
#[inline]
pub fn p2_06mode(&self) -> P2_06MODER {
P2_06MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Port 2 pin 7 control."]
#[inline]
pub fn p2_07mode(&self) -> P2_07MODER {
P2_07MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Port 2 pin 8 control."]
#[inline]
pub fn p2_08mode(&self) -> P2_08MODER {
P2_08MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Port 2 pin 9 control."]
#[inline]
pub fn p2_09mode(&self) -> P2_09MODER {
P2_09MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Port 2 pin 10 control."]
#[inline]
pub fn p2_10mode(&self) -> P2_10MODER {
P2_10MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Port 2 pin 11 control."]
#[inline]
pub fn p2_11mode(&self) -> P2_11MODER {
P2_11MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:25 - Port 2 pin 12 control."]
#[inline]
pub fn p2_12mode(&self) -> P2_12MODER {
P2_12MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Port 2 pin 13 control."]
#[inline]
pub fn p2_13mode(&self) -> P2_13MODER {
P2_13MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Port 2 pin 0 control."]
#[inline]
pub fn p2_00mode(&mut self) -> _P2_00MODEW {
_P2_00MODEW { w: self }
}
#[doc = "Bits 2:3 - Port 2 pin 1 control."]
#[inline]
pub fn p2_01mode(&mut self) -> _P2_01MODEW {
_P2_01MODEW { w: self }
}
#[doc = "Bits 4:5 - Port 2 pin 2 control."]
#[inline]
pub fn p2_02mode(&mut self) -> _P2_02MODEW {
_P2_02MODEW { w: self }
}
#[doc = "Bits 6:7 - Port 2 pin 3 control."]
#[inline]
pub fn p2_03mode(&mut self) -> _P2_03MODEW {
_P2_03MODEW { w: self }
}
#[doc = "Bits 8:9 - Port 2 pin 4 control."]
#[inline]
pub fn p2_04mode(&mut self) -> _P2_04MODEW {
_P2_04MODEW { w: self }
}
#[doc = "Bits 10:11 - Port 2 pin 5 control."]
#[inline]
pub fn p2_05mode(&mut self) -> _P2_05MODEW {
_P2_05MODEW { w: self }
}
#[doc = "Bits 12:13 - Port 2 pin 6 control."]
#[inline]
pub fn p2_06mode(&mut self) -> _P2_06MODEW {
_P2_06MODEW { w: self }
}
#[doc = "Bits 14:15 - Port 2 pin 7 control."]
#[inline]
pub fn p2_07mode(&mut self) -> _P2_07MODEW {
_P2_07MODEW { w: self }
}
#[doc = "Bits 16:17 - Port 2 pin 8 control."]
#[inline]
pub fn p2_08mode(&mut self) -> _P2_08MODEW {
_P2_08MODEW { w: self }
}
#[doc = "Bits 18:19 - Port 2 pin 9 control."]
#[inline]
pub fn p2_09mode(&mut self) -> _P2_09MODEW {
_P2_09MODEW { w: self }
}
#[doc = "Bits 20:21 - Port 2 pin 10 control."]
#[inline]
pub fn p2_10mode(&mut self) -> _P2_10MODEW {
_P2_10MODEW { w: self }
}
#[doc = "Bits 22:23 - Port 2 pin 11 control."]
#[inline]
pub fn p2_11mode(&mut self) -> _P2_11MODEW {
_P2_11MODEW { w: self }
}
#[doc = "Bits 24:25 - Port 2 pin 12 control."]
#[inline]
pub fn p2_12mode(&mut self) -> _P2_12MODEW {
_P2_12MODEW { w: self }
}
#[doc = "Bits 26:27 - Port 2 pin 13 control."]
#[inline]
pub fn p2_13mode(&mut self) -> _P2_13MODEW {
_P2_13MODEW { w: self }
}
}
}
#[doc = "Pin mode select register 7"]
pub struct PINMODE7 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 7"]
pub mod pinmode7 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE7 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P3_25MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P3_25MODER {
#[doc = "Pull-up. P3.25 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P3.25 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P3.25 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P3.25 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P3_25MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P3_25MODER::PULL_UP => 0,
P3_25MODER::REPEATER => 0x01,
P3_25MODER::DISABLED => 0x02,
P3_25MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P3_25MODER {
match value {
0 => P3_25MODER::PULL_UP,
1 => P3_25MODER::REPEATER,
2 => P3_25MODER::DISABLED,
3 => P3_25MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P3_25MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P3_25MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P3_25MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P3_25MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P3_26MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P3_26MODER {
#[doc = "Pull-up. P3.26 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P3.26 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P3.26 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P3.26 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P3_26MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P3_26MODER::PULL_UP => 0,
P3_26MODER::REPEATER => 0x01,
P3_26MODER::DISABLED => 0x02,
P3_26MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P3_26MODER {
match value {
0 => P3_26MODER::PULL_UP,
1 => P3_26MODER::REPEATER,
2 => P3_26MODER::DISABLED,
3 => P3_26MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P3_26MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P3_26MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P3_26MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P3_26MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P3_25MODE`"]
pub enum P3_25MODEW {
#[doc = "Pull-up. P3.25 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P3.25 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P3.25 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P3.25 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P3_25MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P3_25MODEW::PULL_UP => 0,
P3_25MODEW::REPEATER => 1,
P3_25MODEW::DISABLED => 2,
P3_25MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P3_25MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P3_25MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P3_25MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P3.25 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P3_25MODEW::PULL_UP)
}
#[doc = "Repeater. P3.25 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P3_25MODEW::REPEATER)
}
#[doc = "Disabled. P3.25 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P3_25MODEW::DISABLED)
}
#[doc = "Pull-down. P3.25 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P3_25MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P3_26MODE`"]
pub enum P3_26MODEW {
#[doc = "Pull-up. P3.26 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P3.26 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P3.26 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P3.26 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P3_26MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P3_26MODEW::PULL_UP => 0,
P3_26MODEW::REPEATER => 1,
P3_26MODEW::DISABLED => 2,
P3_26MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P3_26MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P3_26MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P3_26MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P3.26 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P3_26MODEW::PULL_UP)
}
#[doc = "Repeater. P3.26 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P3_26MODEW::REPEATER)
}
#[doc = "Disabled. P3.26 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P3_26MODEW::DISABLED)
}
#[doc = "Pull-down. P3.26 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P3_26MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 18:19 - Port 3 pin 25 control."]
#[inline]
pub fn p3_25mode(&self) -> P3_25MODER {
P3_25MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Port 3 pin 26 control."]
#[inline]
pub fn p3_26mode(&self) -> P3_26MODER {
P3_26MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 18:19 - Port 3 pin 25 control."]
#[inline]
pub fn p3_25mode(&mut self) -> _P3_25MODEW {
_P3_25MODEW { w: self }
}
#[doc = "Bits 20:21 - Port 3 pin 26 control."]
#[inline]
pub fn p3_26mode(&mut self) -> _P3_26MODEW {
_P3_26MODEW { w: self }
}
}
}
#[doc = "Pin mode select register 9"]
pub struct PINMODE9 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Pin mode select register 9"]
pub mod pinmode9 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE9 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P4_28MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P4_28MODER {
#[doc = "Pull-up. P4.28 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P4.28 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P4.28 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P4.28 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P4_28MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P4_28MODER::PULL_UP => 0,
P4_28MODER::REPEATER => 0x01,
P4_28MODER::DISABLED => 0x02,
P4_28MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P4_28MODER {
match value {
0 => P4_28MODER::PULL_UP,
1 => P4_28MODER::REPEATER,
2 => P4_28MODER::DISABLED,
3 => P4_28MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P4_28MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P4_28MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P4_28MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P4_28MODER::PULL_DOWN
}
}
#[doc = "Possible values of the field `P4_29MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P4_29MODER {
#[doc = "Pull-up. P4.29 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P4.29 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P4.29 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P4.29 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P4_29MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
P4_29MODER::PULL_UP => 0,
P4_29MODER::REPEATER => 0x01,
P4_29MODER::DISABLED => 0x02,
P4_29MODER::PULL_DOWN => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> P4_29MODER {
match value {
0 => P4_29MODER::PULL_UP,
1 => P4_29MODER::REPEATER,
2 => P4_29MODER::DISABLED,
3 => P4_29MODER::PULL_DOWN,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PULL_UP`"]
#[inline]
pub fn is_pull_up(&self) -> bool {
*self == P4_29MODER::PULL_UP
}
#[doc = "Checks if the value of the field is `REPEATER`"]
#[inline]
pub fn is_repeater(&self) -> bool {
*self == P4_29MODER::REPEATER
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == P4_29MODER::DISABLED
}
#[doc = "Checks if the value of the field is `PULL_DOWN`"]
#[inline]
pub fn is_pull_down(&self) -> bool {
*self == P4_29MODER::PULL_DOWN
}
}
#[doc = "Values that can be written to the field `P4_28MODE`"]
pub enum P4_28MODEW {
#[doc = "Pull-up. P4.28 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P4.28 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P4.28 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P4.28 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P4_28MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P4_28MODEW::PULL_UP => 0,
P4_28MODEW::REPEATER => 1,
P4_28MODEW::DISABLED => 2,
P4_28MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P4_28MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P4_28MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P4_28MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P4.28 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P4_28MODEW::PULL_UP)
}
#[doc = "Repeater. P4.28 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P4_28MODEW::REPEATER)
}
#[doc = "Disabled. P4.28 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P4_28MODEW::DISABLED)
}
#[doc = "Pull-down. P4.28 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P4_28MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P4_29MODE`"]
pub enum P4_29MODEW {
#[doc = "Pull-up. P4.29 pin has a pull-up resistor enabled."]
PULL_UP,
#[doc = "Repeater. P4.29 pin has repeater mode enabled."]
REPEATER,
#[doc = "Disabled. P4.29 pin has neither pull-up nor pull-down."]
DISABLED,
#[doc = "Pull-down. P4.29 has a pull-down resistor enabled."]
PULL_DOWN,
}
impl P4_29MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
P4_29MODEW::PULL_UP => 0,
P4_29MODEW::REPEATER => 1,
P4_29MODEW::DISABLED => 2,
P4_29MODEW::PULL_DOWN => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _P4_29MODEW<'a> {
w: &'a mut W,
}
impl<'a> _P4_29MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P4_29MODEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Pull-up. P4.29 pin has a pull-up resistor enabled."]
#[inline]
pub fn pull_up(self) -> &'a mut W {
self.variant(P4_29MODEW::PULL_UP)
}
#[doc = "Repeater. P4.29 pin has repeater mode enabled."]
#[inline]
pub fn repeater(self) -> &'a mut W {
self.variant(P4_29MODEW::REPEATER)
}
#[doc = "Disabled. P4.29 pin has neither pull-up nor pull-down."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(P4_29MODEW::DISABLED)
}
#[doc = "Pull-down. P4.29 has a pull-down resistor enabled."]
#[inline]
pub fn pull_down(self) -> &'a mut W {
self.variant(P4_29MODEW::PULL_DOWN)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 24:25 - Port 4 pin 28 control."]
#[inline]
pub fn p4_28mode(&self) -> P4_28MODER {
P4_28MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Port 4 pin 29 control."]
#[inline]
pub fn p4_29mode(&self) -> P4_29MODER {
P4_29MODER::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 24:25 - Port 4 pin 28 control."]
#[inline]
pub fn p4_28mode(&mut self) -> _P4_28MODEW {
_P4_28MODEW { w: self }
}
#[doc = "Bits 26:27 - Port 4 pin 29 control."]
#[inline]
pub fn p4_29mode(&mut self) -> _P4_29MODEW {
_P4_29MODEW { w: self }
}
}
}
#[doc = "Open drain mode control register 0"]
pub struct PINMODE_OD0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Open drain mode control register 0"]
pub mod pinmode_od0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE_OD0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P0_00OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_00ODR {
#[doc = "Normal. P0.0 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.0 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_00ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_00ODR::NORMAL => false,
P0_00ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_00ODR {
match value {
false => P0_00ODR::NORMAL,
true => P0_00ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_00ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_00ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_01OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_01ODR {
#[doc = "Normal. P0.1 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.1 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_01ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_01ODR::NORMAL => false,
P0_01ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_01ODR {
match value {
false => P0_01ODR::NORMAL,
true => P0_01ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_01ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_01ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_02OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_02ODR {
#[doc = "Normal. P0.2 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.2 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_02ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_02ODR::NORMAL => false,
P0_02ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_02ODR {
match value {
false => P0_02ODR::NORMAL,
true => P0_02ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_02ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_02ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_03OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_03ODR {
#[doc = "Normal. P0.3 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.3 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_03ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_03ODR::NORMAL => false,
P0_03ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_03ODR {
match value {
false => P0_03ODR::NORMAL,
true => P0_03ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_03ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_03ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_04OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_04ODR {
#[doc = "Normal. P0.4 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.4 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_04ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_04ODR::NORMAL => false,
P0_04ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_04ODR {
match value {
false => P0_04ODR::NORMAL,
true => P0_04ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_04ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_04ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_05OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_05ODR {
#[doc = "Normal. P0.5 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.5 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_05ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_05ODR::NORMAL => false,
P0_05ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_05ODR {
match value {
false => P0_05ODR::NORMAL,
true => P0_05ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_05ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_05ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_06OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_06ODR {
#[doc = "Normal. P0.6 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.6 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_06ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_06ODR::NORMAL => false,
P0_06ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_06ODR {
match value {
false => P0_06ODR::NORMAL,
true => P0_06ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_06ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_06ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_07OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_07ODR {
#[doc = "Normal. P0.7 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.7 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_07ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_07ODR::NORMAL => false,
P0_07ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_07ODR {
match value {
false => P0_07ODR::NORMAL,
true => P0_07ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_07ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_07ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_08OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_08ODR {
#[doc = "Normal. P0.8 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.8 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_08ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_08ODR::NORMAL => false,
P0_08ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_08ODR {
match value {
false => P0_08ODR::NORMAL,
true => P0_08ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_08ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_08ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_09OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_09ODR {
#[doc = "Normal. P0.9 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.9 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_09ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_09ODR::NORMAL => false,
P0_09ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_09ODR {
match value {
false => P0_09ODR::NORMAL,
true => P0_09ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_09ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_09ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_10OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_10ODR {
#[doc = "Normal. P0.10 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.10 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_10ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_10ODR::NORMAL => false,
P0_10ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_10ODR {
match value {
false => P0_10ODR::NORMAL,
true => P0_10ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_10ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_10ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_11OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_11ODR {
#[doc = "Normal. P0.11 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.11 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_11ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_11ODR::NORMAL => false,
P0_11ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_11ODR {
match value {
false => P0_11ODR::NORMAL,
true => P0_11ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_11ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_11ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_15OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_15ODR {
#[doc = "Normal. P0.15 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.15 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_15ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_15ODR::NORMAL => false,
P0_15ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_15ODR {
match value {
false => P0_15ODR::NORMAL,
true => P0_15ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_15ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_15ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_16OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_16ODR {
#[doc = "Normal. P0.16 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.16 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_16ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_16ODR::NORMAL => false,
P0_16ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_16ODR {
match value {
false => P0_16ODR::NORMAL,
true => P0_16ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_16ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_16ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_17OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_17ODR {
#[doc = "Normal. P0.17 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.17 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_17ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_17ODR::NORMAL => false,
P0_17ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_17ODR {
match value {
false => P0_17ODR::NORMAL,
true => P0_17ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_17ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_17ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_18OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_18ODR {
#[doc = "Normal. P0.18 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.18 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_18ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_18ODR::NORMAL => false,
P0_18ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_18ODR {
match value {
false => P0_18ODR::NORMAL,
true => P0_18ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_18ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_18ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_19OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_19ODR {
#[doc = "Normal. P0.19 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.19 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_19ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_19ODR::NORMAL => false,
P0_19ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_19ODR {
match value {
false => P0_19ODR::NORMAL,
true => P0_19ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_19ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_19ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_20OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_20ODR {
#[doc = "Normal. P0.20 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.20 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_20ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_20ODR::NORMAL => false,
P0_20ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_20ODR {
match value {
false => P0_20ODR::NORMAL,
true => P0_20ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_20ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_20ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_21OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_21ODR {
#[doc = "Normal. P0.21 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.21 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_21ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_21ODR::NORMAL => false,
P0_21ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_21ODR {
match value {
false => P0_21ODR::NORMAL,
true => P0_21ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_21ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_21ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_22OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_22ODR {
#[doc = "Normal. P0.22 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.22 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_22ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_22ODR::NORMAL => false,
P0_22ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_22ODR {
match value {
false => P0_22ODR::NORMAL,
true => P0_22ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_22ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_22ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_23OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_23ODR {
#[doc = "Normal. P0.23 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.23 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_23ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_23ODR::NORMAL => false,
P0_23ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_23ODR {
match value {
false => P0_23ODR::NORMAL,
true => P0_23ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_23ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_23ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_24OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_24ODR {
#[doc = "Normal. P0.23 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.23 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_24ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_24ODR::NORMAL => false,
P0_24ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_24ODR {
match value {
false => P0_24ODR::NORMAL,
true => P0_24ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_24ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_24ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_25OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_25ODR {
#[doc = "Normal. P0.25 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.25 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_25ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_25ODR::NORMAL => false,
P0_25ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_25ODR {
match value {
false => P0_25ODR::NORMAL,
true => P0_25ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_25ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_25ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_26OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_26ODR {
#[doc = "Normal. P0.26 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.26 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_26ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_26ODR::NORMAL => false,
P0_26ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_26ODR {
match value {
false => P0_26ODR::NORMAL,
true => P0_26ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_26ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_26ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_29OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_29ODR {
#[doc = "Normal. P0.29 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.29 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_29ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_29ODR::NORMAL => false,
P0_29ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_29ODR {
match value {
false => P0_29ODR::NORMAL,
true => P0_29ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_29ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_29ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P0_30OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P0_30ODR {
#[doc = "Normal. P0.30 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.30 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_30ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P0_30ODR::NORMAL => false,
P0_30ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P0_30ODR {
match value {
false => P0_30ODR::NORMAL,
true => P0_30ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P0_30ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P0_30ODR::OPEN_DRAIN
}
}
#[doc = "Values that can be written to the field `P0_00OD`"]
pub enum P0_00ODW {
#[doc = "Normal. P0.0 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.0 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_00ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_00ODW::NORMAL => false,
P0_00ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_00ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_00ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_00ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.0 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_00ODW::NORMAL)
}
#[doc = "Open-drain. P0.0 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_00ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_01OD`"]
pub enum P0_01ODW {
#[doc = "Normal. P0.1 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.1 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_01ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_01ODW::NORMAL => false,
P0_01ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_01ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_01ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_01ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.1 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_01ODW::NORMAL)
}
#[doc = "Open-drain. P0.1 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_01ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_02OD`"]
pub enum P0_02ODW {
#[doc = "Normal. P0.2 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.2 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_02ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_02ODW::NORMAL => false,
P0_02ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_02ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_02ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_02ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.2 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_02ODW::NORMAL)
}
#[doc = "Open-drain. P0.2 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_02ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_03OD`"]
pub enum P0_03ODW {
#[doc = "Normal. P0.3 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.3 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_03ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_03ODW::NORMAL => false,
P0_03ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_03ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_03ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_03ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.3 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_03ODW::NORMAL)
}
#[doc = "Open-drain. P0.3 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_03ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_04OD`"]
pub enum P0_04ODW {
#[doc = "Normal. P0.4 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.4 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_04ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_04ODW::NORMAL => false,
P0_04ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_04ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_04ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_04ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.4 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_04ODW::NORMAL)
}
#[doc = "Open-drain. P0.4 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_04ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_05OD`"]
pub enum P0_05ODW {
#[doc = "Normal. P0.5 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.5 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_05ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_05ODW::NORMAL => false,
P0_05ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_05ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_05ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_05ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.5 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_05ODW::NORMAL)
}
#[doc = "Open-drain. P0.5 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_05ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_06OD`"]
pub enum P0_06ODW {
#[doc = "Normal. P0.6 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.6 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_06ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_06ODW::NORMAL => false,
P0_06ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_06ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_06ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_06ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.6 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_06ODW::NORMAL)
}
#[doc = "Open-drain. P0.6 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_06ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_07OD`"]
pub enum P0_07ODW {
#[doc = "Normal. P0.7 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.7 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_07ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_07ODW::NORMAL => false,
P0_07ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_07ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_07ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_07ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.7 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_07ODW::NORMAL)
}
#[doc = "Open-drain. P0.7 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_07ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_08OD`"]
pub enum P0_08ODW {
#[doc = "Normal. P0.8 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.8 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_08ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_08ODW::NORMAL => false,
P0_08ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_08ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_08ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_08ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.8 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_08ODW::NORMAL)
}
#[doc = "Open-drain. P0.8 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_08ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_09OD`"]
pub enum P0_09ODW {
#[doc = "Normal. P0.9 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.9 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_09ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_09ODW::NORMAL => false,
P0_09ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_09ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_09ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_09ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.9 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_09ODW::NORMAL)
}
#[doc = "Open-drain. P0.9 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_09ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_10OD`"]
pub enum P0_10ODW {
#[doc = "Normal. P0.10 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.10 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_10ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_10ODW::NORMAL => false,
P0_10ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_10ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_10ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_10ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.10 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_10ODW::NORMAL)
}
#[doc = "Open-drain. P0.10 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_10ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_11OD`"]
pub enum P0_11ODW {
#[doc = "Normal. P0.11 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.11 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_11ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_11ODW::NORMAL => false,
P0_11ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_11ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_11ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_11ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.11 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_11ODW::NORMAL)
}
#[doc = "Open-drain. P0.11 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_11ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_15OD`"]
pub enum P0_15ODW {
#[doc = "Normal. P0.15 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.15 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_15ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_15ODW::NORMAL => false,
P0_15ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_15ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_15ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_15ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.15 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_15ODW::NORMAL)
}
#[doc = "Open-drain. P0.15 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_15ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_16OD`"]
pub enum P0_16ODW {
#[doc = "Normal. P0.16 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.16 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_16ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_16ODW::NORMAL => false,
P0_16ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_16ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_16ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_16ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.16 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_16ODW::NORMAL)
}
#[doc = "Open-drain. P0.16 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_16ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_17OD`"]
pub enum P0_17ODW {
#[doc = "Normal. P0.17 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.17 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_17ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_17ODW::NORMAL => false,
P0_17ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_17ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_17ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_17ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.17 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_17ODW::NORMAL)
}
#[doc = "Open-drain. P0.17 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_17ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_18OD`"]
pub enum P0_18ODW {
#[doc = "Normal. P0.18 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.18 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_18ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_18ODW::NORMAL => false,
P0_18ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_18ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_18ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_18ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.18 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_18ODW::NORMAL)
}
#[doc = "Open-drain. P0.18 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_18ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_19OD`"]
pub enum P0_19ODW {
#[doc = "Normal. P0.19 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.19 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_19ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_19ODW::NORMAL => false,
P0_19ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_19ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_19ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_19ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.19 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_19ODW::NORMAL)
}
#[doc = "Open-drain. P0.19 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_19ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_20OD`"]
pub enum P0_20ODW {
#[doc = "Normal. P0.20 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.20 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_20ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_20ODW::NORMAL => false,
P0_20ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_20ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_20ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_20ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.20 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_20ODW::NORMAL)
}
#[doc = "Open-drain. P0.20 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_20ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_21OD`"]
pub enum P0_21ODW {
#[doc = "Normal. P0.21 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.21 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_21ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_21ODW::NORMAL => false,
P0_21ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_21ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_21ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_21ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.21 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_21ODW::NORMAL)
}
#[doc = "Open-drain. P0.21 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_21ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_22OD`"]
pub enum P0_22ODW {
#[doc = "Normal. P0.22 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.22 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_22ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_22ODW::NORMAL => false,
P0_22ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_22ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_22ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_22ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.22 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_22ODW::NORMAL)
}
#[doc = "Open-drain. P0.22 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_22ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_23OD`"]
pub enum P0_23ODW {
#[doc = "Normal. P0.23 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.23 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_23ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_23ODW::NORMAL => false,
P0_23ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_23ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_23ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_23ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.23 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_23ODW::NORMAL)
}
#[doc = "Open-drain. P0.23 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_23ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_24OD`"]
pub enum P0_24ODW {
#[doc = "Normal. P0.23 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.23 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_24ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_24ODW::NORMAL => false,
P0_24ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_24ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_24ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_24ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.23 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_24ODW::NORMAL)
}
#[doc = "Open-drain. P0.23 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_24ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_25OD`"]
pub enum P0_25ODW {
#[doc = "Normal. P0.25 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.25 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_25ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_25ODW::NORMAL => false,
P0_25ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_25ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_25ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_25ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.25 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_25ODW::NORMAL)
}
#[doc = "Open-drain. P0.25 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_25ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_26OD`"]
pub enum P0_26ODW {
#[doc = "Normal. P0.26 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.26 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_26ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_26ODW::NORMAL => false,
P0_26ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_26ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_26ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_26ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.26 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_26ODW::NORMAL)
}
#[doc = "Open-drain. P0.26 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_26ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_29OD`"]
pub enum P0_29ODW {
#[doc = "Normal. P0.29 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.29 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_29ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_29ODW::NORMAL => false,
P0_29ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_29ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_29ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_29ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.29 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_29ODW::NORMAL)
}
#[doc = "Open-drain. P0.29 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_29ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P0_30OD`"]
pub enum P0_30ODW {
#[doc = "Normal. P0.30 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P0.30 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P0_30ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P0_30ODW::NORMAL => false,
P0_30ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P0_30ODW<'a> {
w: &'a mut W,
}
impl<'a> _P0_30ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P0_30ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P0.30 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P0_30ODW::NORMAL)
}
#[doc = "Open-drain. P0.30 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P0_30ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_00od(&self) -> P0_00ODR {
P0_00ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_01od(&self) -> P0_01ODR {
P0_01ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Port 0 pin 2 open drain mode control"]
#[inline]
pub fn p0_02od(&self) -> P0_02ODR {
P0_02ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Port 0 pin 3 open drain mode control"]
#[inline]
pub fn p0_03od(&self) -> P0_03ODR {
P0_03ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Port 0 pin 4 open drain mode control"]
#[inline]
pub fn p0_04od(&self) -> P0_04ODR {
P0_04ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Port 0 pin 5 open drain mode control"]
#[inline]
pub fn p0_05od(&self) -> P0_05ODR {
P0_05ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Port 0 pin 6 open drain mode control"]
#[inline]
pub fn p0_06od(&self) -> P0_06ODR {
P0_06ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Port 0 pin 7 open drain mode control"]
#[inline]
pub fn p0_07od(&self) -> P0_07ODR {
P0_07ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Port 0 pin 8 open drain mode control"]
#[inline]
pub fn p0_08od(&self) -> P0_08ODR {
P0_08ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Port 0 pin 9 open drain mode control"]
#[inline]
pub fn p0_09od(&self) -> P0_09ODR {
P0_09ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_10od(&self) -> P0_10ODR {
P0_10ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_11od(&self) -> P0_11ODR {
P0_11ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Port 0 pin 15 open drain mode control"]
#[inline]
pub fn p0_15od(&self) -> P0_15ODR {
P0_15ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Port 0 pin 16 open drain mode control"]
#[inline]
pub fn p0_16od(&self) -> P0_16ODR {
P0_16ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Port 0 pin 17 open drain mode control"]
#[inline]
pub fn p0_17od(&self) -> P0_17ODR {
P0_17ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Port 0 pin 18 open drain mode control"]
#[inline]
pub fn p0_18od(&self) -> P0_18ODR {
P0_18ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 19 - Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_19od(&self) -> P0_19ODR {
P0_19ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 20 - Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_20od(&self) -> P0_20ODR {
P0_20ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Port 0 pin 21 open drain mode control"]
#[inline]
pub fn p0_21od(&self) -> P0_21ODR {
P0_21ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Port 0 pin 22 open drain mode control"]
#[inline]
pub fn p0_22od(&self) -> P0_22ODR {
P0_22ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Port 0 pin 23 open drain mode control"]
#[inline]
pub fn p0_23od(&self) -> P0_23ODR {
P0_23ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - Port 0 pin 24open drain mode control"]
#[inline]
pub fn p0_24od(&self) -> P0_24ODR {
P0_24ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Port 0 pin 25 open drain mode control"]
#[inline]
pub fn p0_25od(&self) -> P0_25ODR {
P0_25ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Port 0 pin 26 open drain mode control"]
#[inline]
pub fn p0_26od(&self) -> P0_26ODR {
P0_26ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Port 0 pin 29 open drain mode control"]
#[inline]
pub fn p0_29od(&self) -> P0_29ODR {
P0_29ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Port 0 pin 30 open drain mode control"]
#[inline]
pub fn p0_30od(&self) -> P0_30ODR {
P0_30ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_00od(&mut self) -> _P0_00ODW {
_P0_00ODW { w: self }
}
#[doc = "Bit 1 - Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_01od(&mut self) -> _P0_01ODW {
_P0_01ODW { w: self }
}
#[doc = "Bit 2 - Port 0 pin 2 open drain mode control"]
#[inline]
pub fn p0_02od(&mut self) -> _P0_02ODW {
_P0_02ODW { w: self }
}
#[doc = "Bit 3 - Port 0 pin 3 open drain mode control"]
#[inline]
pub fn p0_03od(&mut self) -> _P0_03ODW {
_P0_03ODW { w: self }
}
#[doc = "Bit 4 - Port 0 pin 4 open drain mode control"]
#[inline]
pub fn p0_04od(&mut self) -> _P0_04ODW {
_P0_04ODW { w: self }
}
#[doc = "Bit 5 - Port 0 pin 5 open drain mode control"]
#[inline]
pub fn p0_05od(&mut self) -> _P0_05ODW {
_P0_05ODW { w: self }
}
#[doc = "Bit 6 - Port 0 pin 6 open drain mode control"]
#[inline]
pub fn p0_06od(&mut self) -> _P0_06ODW {
_P0_06ODW { w: self }
}
#[doc = "Bit 7 - Port 0 pin 7 open drain mode control"]
#[inline]
pub fn p0_07od(&mut self) -> _P0_07ODW {
_P0_07ODW { w: self }
}
#[doc = "Bit 8 - Port 0 pin 8 open drain mode control"]
#[inline]
pub fn p0_08od(&mut self) -> _P0_08ODW {
_P0_08ODW { w: self }
}
#[doc = "Bit 9 - Port 0 pin 9 open drain mode control"]
#[inline]
pub fn p0_09od(&mut self) -> _P0_09ODW {
_P0_09ODW { w: self }
}
#[doc = "Bit 10 - Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_10od(&mut self) -> _P0_10ODW {
_P0_10ODW { w: self }
}
#[doc = "Bit 11 - Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_11od(&mut self) -> _P0_11ODW {
_P0_11ODW { w: self }
}
#[doc = "Bit 15 - Port 0 pin 15 open drain mode control"]
#[inline]
pub fn p0_15od(&mut self) -> _P0_15ODW {
_P0_15ODW { w: self }
}
#[doc = "Bit 16 - Port 0 pin 16 open drain mode control"]
#[inline]
pub fn p0_16od(&mut self) -> _P0_16ODW {
_P0_16ODW { w: self }
}
#[doc = "Bit 17 - Port 0 pin 17 open drain mode control"]
#[inline]
pub fn p0_17od(&mut self) -> _P0_17ODW {
_P0_17ODW { w: self }
}
#[doc = "Bit 18 - Port 0 pin 18 open drain mode control"]
#[inline]
pub fn p0_18od(&mut self) -> _P0_18ODW {
_P0_18ODW { w: self }
}
#[doc = "Bit 19 - Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_19od(&mut self) -> _P0_19ODW {
_P0_19ODW { w: self }
}
#[doc = "Bit 20 - Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0."]
#[inline]
pub fn p0_20od(&mut self) -> _P0_20ODW {
_P0_20ODW { w: self }
}
#[doc = "Bit 21 - Port 0 pin 21 open drain mode control"]
#[inline]
pub fn p0_21od(&mut self) -> _P0_21ODW {
_P0_21ODW { w: self }
}
#[doc = "Bit 22 - Port 0 pin 22 open drain mode control"]
#[inline]
pub fn p0_22od(&mut self) -> _P0_22ODW {
_P0_22ODW { w: self }
}
#[doc = "Bit 23 - Port 0 pin 23 open drain mode control"]
#[inline]
pub fn p0_23od(&mut self) -> _P0_23ODW {
_P0_23ODW { w: self }
}
#[doc = "Bit 24 - Port 0 pin 24open drain mode control"]
#[inline]
pub fn p0_24od(&mut self) -> _P0_24ODW {
_P0_24ODW { w: self }
}
#[doc = "Bit 25 - Port 0 pin 25 open drain mode control"]
#[inline]
pub fn p0_25od(&mut self) -> _P0_25ODW {
_P0_25ODW { w: self }
}
#[doc = "Bit 26 - Port 0 pin 26 open drain mode control"]
#[inline]
pub fn p0_26od(&mut self) -> _P0_26ODW {
_P0_26ODW { w: self }
}
#[doc = "Bit 29 - Port 0 pin 29 open drain mode control"]
#[inline]
pub fn p0_29od(&mut self) -> _P0_29ODW {
_P0_29ODW { w: self }
}
#[doc = "Bit 30 - Port 0 pin 30 open drain mode control"]
#[inline]
pub fn p0_30od(&mut self) -> _P0_30ODW {
_P0_30ODW { w: self }
}
}
}
#[doc = "Open drain mode control register 1"]
pub struct PINMODE_OD1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Open drain mode control register 1"]
pub mod pinmode_od1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE_OD1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P1_00OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_00ODR {
#[doc = "Normal. P1.0 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.0 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_00ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_00ODR::NORMAL => false,
P1_00ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_00ODR {
match value {
false => P1_00ODR::NORMAL,
true => P1_00ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_00ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_00ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_01OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_01ODR {
#[doc = "Normal. P1.1 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.1 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_01ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_01ODR::NORMAL => false,
P1_01ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_01ODR {
match value {
false => P1_01ODR::NORMAL,
true => P1_01ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_01ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_01ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_04OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_04ODR {
#[doc = "Normal. P1.4 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.4 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_04ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_04ODR::NORMAL => false,
P1_04ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_04ODR {
match value {
false => P1_04ODR::NORMAL,
true => P1_04ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_04ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_04ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_08OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_08ODR {
#[doc = "Normal. P1.8 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.8 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_08ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_08ODR::NORMAL => false,
P1_08ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_08ODR {
match value {
false => P1_08ODR::NORMAL,
true => P1_08ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_08ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_08ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_09OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_09ODR {
#[doc = "Normal. P1.9 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.9 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_09ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_09ODR::NORMAL => false,
P1_09ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_09ODR {
match value {
false => P1_09ODR::NORMAL,
true => P1_09ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_09ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_09ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_10OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_10ODR {
#[doc = "Normal. P1.10 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.10 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_10ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_10ODR::NORMAL => false,
P1_10ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_10ODR {
match value {
false => P1_10ODR::NORMAL,
true => P1_10ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_10ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_10ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_14OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_14ODR {
#[doc = "Normal. P1.14 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.14 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_14ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_14ODR::NORMAL => false,
P1_14ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_14ODR {
match value {
false => P1_14ODR::NORMAL,
true => P1_14ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_14ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_14ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_15OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_15ODR {
#[doc = "Normal. P1.15 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.15 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_15ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_15ODR::NORMAL => false,
P1_15ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_15ODR {
match value {
false => P1_15ODR::NORMAL,
true => P1_15ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_15ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_15ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_16OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_16ODR {
#[doc = "Normal. P1.16 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.16 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_16ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_16ODR::NORMAL => false,
P1_16ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_16ODR {
match value {
false => P1_16ODR::NORMAL,
true => P1_16ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_16ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_16ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_17OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_17ODR {
#[doc = "Normal. P1.17 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.17 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_17ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_17ODR::NORMAL => false,
P1_17ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_17ODR {
match value {
false => P1_17ODR::NORMAL,
true => P1_17ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_17ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_17ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_18OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_18ODR {
#[doc = "Normal. P1.18 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.18 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_18ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_18ODR::NORMAL => false,
P1_18ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_18ODR {
match value {
false => P1_18ODR::NORMAL,
true => P1_18ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_18ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_18ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_19OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_19ODR {
#[doc = "Normal. P1.19 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.19 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_19ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_19ODR::NORMAL => false,
P1_19ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_19ODR {
match value {
false => P1_19ODR::NORMAL,
true => P1_19ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_19ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_19ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_20OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_20ODR {
#[doc = "Normal. P1.20 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.20 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_20ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_20ODR::NORMAL => false,
P1_20ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_20ODR {
match value {
false => P1_20ODR::NORMAL,
true => P1_20ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_20ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_20ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_21OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_21ODR {
#[doc = "Normal. P1.21 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.21 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_21ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_21ODR::NORMAL => false,
P1_21ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_21ODR {
match value {
false => P1_21ODR::NORMAL,
true => P1_21ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_21ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_21ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_22OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_22ODR {
#[doc = "Normal. P1.22 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.22 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_22ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_22ODR::NORMAL => false,
P1_22ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_22ODR {
match value {
false => P1_22ODR::NORMAL,
true => P1_22ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_22ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_22ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_23OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_23ODR {
#[doc = "Normal. P1.23 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.23 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_23ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_23ODR::NORMAL => false,
P1_23ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_23ODR {
match value {
false => P1_23ODR::NORMAL,
true => P1_23ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_23ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_23ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_24OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_24ODR {
#[doc = "Normal. P1.24 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.24 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_24ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_24ODR::NORMAL => false,
P1_24ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_24ODR {
match value {
false => P1_24ODR::NORMAL,
true => P1_24ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_24ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_24ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_25OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_25ODR {
#[doc = "Normal. P1.25 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.25 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_25ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_25ODR::NORMAL => false,
P1_25ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_25ODR {
match value {
false => P1_25ODR::NORMAL,
true => P1_25ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_25ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_25ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_26OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_26ODR {
#[doc = "Normal. P1.26 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.26 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_26ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_26ODR::NORMAL => false,
P1_26ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_26ODR {
match value {
false => P1_26ODR::NORMAL,
true => P1_26ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_26ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_26ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_27OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_27ODR {
#[doc = "Normal. P1.27 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.27 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_27ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_27ODR::NORMAL => false,
P1_27ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_27ODR {
match value {
false => P1_27ODR::NORMAL,
true => P1_27ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_27ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_27ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_28OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_28ODR {
#[doc = "Normal. P1.28 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.28 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_28ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_28ODR::NORMAL => false,
P1_28ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_28ODR {
match value {
false => P1_28ODR::NORMAL,
true => P1_28ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_28ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_28ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_29OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_29ODR {
#[doc = "Normal. P1.29 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.29 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_29ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_29ODR::NORMAL => false,
P1_29ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_29ODR {
match value {
false => P1_29ODR::NORMAL,
true => P1_29ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_29ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_29ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_30OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_30ODR {
#[doc = "Normal. P1.30 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.30 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_30ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_30ODR::NORMAL => false,
P1_30ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_30ODR {
match value {
false => P1_30ODR::NORMAL,
true => P1_30ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_30ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_30ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P1_31OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P1_31ODR {
#[doc = "Normal. P1.31 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.31 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_31ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P1_31ODR::NORMAL => false,
P1_31ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P1_31ODR {
match value {
false => P1_31ODR::NORMAL,
true => P1_31ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P1_31ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P1_31ODR::OPEN_DRAIN
}
}
#[doc = "Values that can be written to the field `P1_00OD`"]
pub enum P1_00ODW {
#[doc = "Normal. P1.0 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.0 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_00ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_00ODW::NORMAL => false,
P1_00ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_00ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_00ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_00ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.0 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_00ODW::NORMAL)
}
#[doc = "Open-drain. P1.0 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_00ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_01OD`"]
pub enum P1_01ODW {
#[doc = "Normal. P1.1 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.1 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_01ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_01ODW::NORMAL => false,
P1_01ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_01ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_01ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_01ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.1 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_01ODW::NORMAL)
}
#[doc = "Open-drain. P1.1 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_01ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_04OD`"]
pub enum P1_04ODW {
#[doc = "Normal. P1.4 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.4 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_04ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_04ODW::NORMAL => false,
P1_04ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_04ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_04ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_04ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.4 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_04ODW::NORMAL)
}
#[doc = "Open-drain. P1.4 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_04ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_08OD`"]
pub enum P1_08ODW {
#[doc = "Normal. P1.8 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.8 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_08ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_08ODW::NORMAL => false,
P1_08ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_08ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_08ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_08ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.8 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_08ODW::NORMAL)
}
#[doc = "Open-drain. P1.8 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_08ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_09OD`"]
pub enum P1_09ODW {
#[doc = "Normal. P1.9 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.9 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_09ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_09ODW::NORMAL => false,
P1_09ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_09ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_09ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_09ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.9 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_09ODW::NORMAL)
}
#[doc = "Open-drain. P1.9 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_09ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_10OD`"]
pub enum P1_10ODW {
#[doc = "Normal. P1.10 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.10 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_10ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_10ODW::NORMAL => false,
P1_10ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_10ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_10ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_10ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.10 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_10ODW::NORMAL)
}
#[doc = "Open-drain. P1.10 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_10ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_14OD`"]
pub enum P1_14ODW {
#[doc = "Normal. P1.14 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.14 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_14ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_14ODW::NORMAL => false,
P1_14ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_14ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_14ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_14ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.14 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_14ODW::NORMAL)
}
#[doc = "Open-drain. P1.14 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_14ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_15OD`"]
pub enum P1_15ODW {
#[doc = "Normal. P1.15 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.15 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_15ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_15ODW::NORMAL => false,
P1_15ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_15ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_15ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_15ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.15 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_15ODW::NORMAL)
}
#[doc = "Open-drain. P1.15 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_15ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_16OD`"]
pub enum P1_16ODW {
#[doc = "Normal. P1.16 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.16 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_16ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_16ODW::NORMAL => false,
P1_16ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_16ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_16ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_16ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.16 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_16ODW::NORMAL)
}
#[doc = "Open-drain. P1.16 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_16ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_17OD`"]
pub enum P1_17ODW {
#[doc = "Normal. P1.17 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.17 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_17ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_17ODW::NORMAL => false,
P1_17ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_17ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_17ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_17ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.17 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_17ODW::NORMAL)
}
#[doc = "Open-drain. P1.17 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_17ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_18OD`"]
pub enum P1_18ODW {
#[doc = "Normal. P1.18 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.18 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_18ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_18ODW::NORMAL => false,
P1_18ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_18ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_18ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_18ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.18 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_18ODW::NORMAL)
}
#[doc = "Open-drain. P1.18 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_18ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_19OD`"]
pub enum P1_19ODW {
#[doc = "Normal. P1.19 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.19 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_19ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_19ODW::NORMAL => false,
P1_19ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_19ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_19ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_19ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.19 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_19ODW::NORMAL)
}
#[doc = "Open-drain. P1.19 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_19ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_20OD`"]
pub enum P1_20ODW {
#[doc = "Normal. P1.20 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.20 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_20ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_20ODW::NORMAL => false,
P1_20ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_20ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_20ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_20ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.20 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_20ODW::NORMAL)
}
#[doc = "Open-drain. P1.20 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_20ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_21OD`"]
pub enum P1_21ODW {
#[doc = "Normal. P1.21 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.21 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_21ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_21ODW::NORMAL => false,
P1_21ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_21ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_21ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_21ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.21 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_21ODW::NORMAL)
}
#[doc = "Open-drain. P1.21 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_21ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_22OD`"]
pub enum P1_22ODW {
#[doc = "Normal. P1.22 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.22 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_22ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_22ODW::NORMAL => false,
P1_22ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_22ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_22ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_22ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.22 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_22ODW::NORMAL)
}
#[doc = "Open-drain. P1.22 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_22ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_23OD`"]
pub enum P1_23ODW {
#[doc = "Normal. P1.23 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.23 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_23ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_23ODW::NORMAL => false,
P1_23ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_23ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_23ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_23ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.23 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_23ODW::NORMAL)
}
#[doc = "Open-drain. P1.23 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_23ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_24OD`"]
pub enum P1_24ODW {
#[doc = "Normal. P1.24 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.24 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_24ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_24ODW::NORMAL => false,
P1_24ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_24ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_24ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_24ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.24 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_24ODW::NORMAL)
}
#[doc = "Open-drain. P1.24 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_24ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_25OD`"]
pub enum P1_25ODW {
#[doc = "Normal. P1.25 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.25 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_25ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_25ODW::NORMAL => false,
P1_25ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_25ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_25ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_25ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.25 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_25ODW::NORMAL)
}
#[doc = "Open-drain. P1.25 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_25ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_26OD`"]
pub enum P1_26ODW {
#[doc = "Normal. P1.26 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.26 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_26ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_26ODW::NORMAL => false,
P1_26ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_26ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_26ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_26ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.26 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_26ODW::NORMAL)
}
#[doc = "Open-drain. P1.26 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_26ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_27OD`"]
pub enum P1_27ODW {
#[doc = "Normal. P1.27 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.27 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_27ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_27ODW::NORMAL => false,
P1_27ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_27ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_27ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_27ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.27 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_27ODW::NORMAL)
}
#[doc = "Open-drain. P1.27 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_27ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_28OD`"]
pub enum P1_28ODW {
#[doc = "Normal. P1.28 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.28 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_28ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_28ODW::NORMAL => false,
P1_28ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_28ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_28ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_28ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.28 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_28ODW::NORMAL)
}
#[doc = "Open-drain. P1.28 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_28ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_29OD`"]
pub enum P1_29ODW {
#[doc = "Normal. P1.29 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.29 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_29ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_29ODW::NORMAL => false,
P1_29ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_29ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_29ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_29ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.29 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_29ODW::NORMAL)
}
#[doc = "Open-drain. P1.29 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_29ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_30OD`"]
pub enum P1_30ODW {
#[doc = "Normal. P1.30 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.30 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_30ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_30ODW::NORMAL => false,
P1_30ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_30ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_30ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_30ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.30 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_30ODW::NORMAL)
}
#[doc = "Open-drain. P1.30 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_30ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P1_31OD`"]
pub enum P1_31ODW {
#[doc = "Normal. P1.31 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P1.31 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P1_31ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P1_31ODW::NORMAL => false,
P1_31ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P1_31ODW<'a> {
w: &'a mut W,
}
impl<'a> _P1_31ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P1_31ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P1.31 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P1_31ODW::NORMAL)
}
#[doc = "Open-drain. P1.31 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P1_31ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Port 1 pin 0 open drain mode control."]
#[inline]
pub fn p1_00od(&self) -> P1_00ODR {
P1_00ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Port 1 pin 1 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_01od(&self) -> P1_01ODR {
P1_01ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Port 1 pin 4 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_04od(&self) -> P1_04ODR {
P1_04ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Port 1 pin 8 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_08od(&self) -> P1_08ODR {
P1_08ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Port 1 pin 9 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_09od(&self) -> P1_09ODR {
P1_09ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Port 1 pin 10 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_10od(&self) -> P1_10ODR {
P1_10ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Port 1 pin 14 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_14od(&self) -> P1_14ODR {
P1_14ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Port 1 pin 15 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_15od(&self) -> P1_15ODR {
P1_15ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Port 1 pin 16 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_16od(&self) -> P1_16ODR {
P1_16ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Port 1 pin 17 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_17od(&self) -> P1_17ODR {
P1_17ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Port 1 pin 18 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_18od(&self) -> P1_18ODR {
P1_18ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 19 - Port 1 pin 19 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_19od(&self) -> P1_19ODR {
P1_19ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 20 - Port 1 pin 20open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_20od(&self) -> P1_20ODR {
P1_20ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Port 1 pin 21 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_21od(&self) -> P1_21ODR {
P1_21ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Port 1 pin 22 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_22od(&self) -> P1_22ODR {
P1_22ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Port 1 pin 23 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_23od(&self) -> P1_23ODR {
P1_23ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - Port 1 pin 24open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_24od(&self) -> P1_24ODR {
P1_24ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Port 1 pin 25 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_25od(&self) -> P1_25ODR {
P1_25ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Port 1 pin 26 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_26od(&self) -> P1_26ODR {
P1_26ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 27 - Port 1 pin 27 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_27od(&self) -> P1_27ODR {
P1_27ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 28 - Port 1 pin 28 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_28od(&self) -> P1_28ODR {
P1_28ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Port 1 pin 29 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_29od(&self) -> P1_29ODR {
P1_29ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Port 1 pin 30 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_30od(&self) -> P1_30ODR {
P1_30ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 31 - Port 1 pin 31 open drain mode control."]
#[inline]
pub fn p1_31od(&self) -> P1_31ODR {
P1_31ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Port 1 pin 0 open drain mode control."]
#[inline]
pub fn p1_00od(&mut self) -> _P1_00ODW {
_P1_00ODW { w: self }
}
#[doc = "Bit 1 - Port 1 pin 1 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_01od(&mut self) -> _P1_01ODW {
_P1_01ODW { w: self }
}
#[doc = "Bit 4 - Port 1 pin 4 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_04od(&mut self) -> _P1_04ODW {
_P1_04ODW { w: self }
}
#[doc = "Bit 8 - Port 1 pin 8 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_08od(&mut self) -> _P1_08ODW {
_P1_08ODW { w: self }
}
#[doc = "Bit 9 - Port 1 pin 9 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_09od(&mut self) -> _P1_09ODW {
_P1_09ODW { w: self }
}
#[doc = "Bit 10 - Port 1 pin 10 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_10od(&mut self) -> _P1_10ODW {
_P1_10ODW { w: self }
}
#[doc = "Bit 14 - Port 1 pin 14 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_14od(&mut self) -> _P1_14ODW {
_P1_14ODW { w: self }
}
#[doc = "Bit 15 - Port 1 pin 15 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_15od(&mut self) -> _P1_15ODW {
_P1_15ODW { w: self }
}
#[doc = "Bit 16 - Port 1 pin 16 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_16od(&mut self) -> _P1_16ODW {
_P1_16ODW { w: self }
}
#[doc = "Bit 17 - Port 1 pin 17 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_17od(&mut self) -> _P1_17ODW {
_P1_17ODW { w: self }
}
#[doc = "Bit 18 - Port 1 pin 18 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_18od(&mut self) -> _P1_18ODW {
_P1_18ODW { w: self }
}
#[doc = "Bit 19 - Port 1 pin 19 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_19od(&mut self) -> _P1_19ODW {
_P1_19ODW { w: self }
}
#[doc = "Bit 20 - Port 1 pin 20open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_20od(&mut self) -> _P1_20ODW {
_P1_20ODW { w: self }
}
#[doc = "Bit 21 - Port 1 pin 21 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_21od(&mut self) -> _P1_21ODW {
_P1_21ODW { w: self }
}
#[doc = "Bit 22 - Port 1 pin 22 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_22od(&mut self) -> _P1_22ODW {
_P1_22ODW { w: self }
}
#[doc = "Bit 23 - Port 1 pin 23 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_23od(&mut self) -> _P1_23ODW {
_P1_23ODW { w: self }
}
#[doc = "Bit 24 - Port 1 pin 24open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_24od(&mut self) -> _P1_24ODW {
_P1_24ODW { w: self }
}
#[doc = "Bit 25 - Port 1 pin 25 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_25od(&mut self) -> _P1_25ODW {
_P1_25ODW { w: self }
}
#[doc = "Bit 26 - Port 1 pin 26 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_26od(&mut self) -> _P1_26ODW {
_P1_26ODW { w: self }
}
#[doc = "Bit 27 - Port 1 pin 27 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_27od(&mut self) -> _P1_27ODW {
_P1_27ODW { w: self }
}
#[doc = "Bit 28 - Port 1 pin 28 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_28od(&mut self) -> _P1_28ODW {
_P1_28ODW { w: self }
}
#[doc = "Bit 29 - Port 1 pin 29 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_29od(&mut self) -> _P1_29ODW {
_P1_29ODW { w: self }
}
#[doc = "Bit 30 - Port 1 pin 30 open drain mode control, see P1.00OD"]
#[inline]
pub fn p1_30od(&mut self) -> _P1_30ODW {
_P1_30ODW { w: self }
}
#[doc = "Bit 31 - Port 1 pin 31 open drain mode control."]
#[inline]
pub fn p1_31od(&mut self) -> _P1_31ODW {
_P1_31ODW { w: self }
}
}
}
#[doc = "Open drain mode control register 2"]
pub struct PINMODE_OD2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Open drain mode control register 2"]
pub mod pinmode_od2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE_OD2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P2_00OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_00ODR {
#[doc = "Normal. P2.0 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.0 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_00ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_00ODR::NORMAL => false,
P2_00ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_00ODR {
match value {
false => P2_00ODR::NORMAL,
true => P2_00ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_00ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_00ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_01OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_01ODR {
#[doc = "Normal. P2.1 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.1p in is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_01ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_01ODR::NORMAL => false,
P2_01ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_01ODR {
match value {
false => P2_01ODR::NORMAL,
true => P2_01ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_01ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_01ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_02OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_02ODR {
#[doc = "Normal. P2.2 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.2 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_02ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_02ODR::NORMAL => false,
P2_02ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_02ODR {
match value {
false => P2_02ODR::NORMAL,
true => P2_02ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_02ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_02ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_03OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_03ODR {
#[doc = "Normal. P2.3 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.3 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_03ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_03ODR::NORMAL => false,
P2_03ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_03ODR {
match value {
false => P2_03ODR::NORMAL,
true => P2_03ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_03ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_03ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_04OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_04ODR {
#[doc = "Normal. P2.4 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.4 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_04ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_04ODR::NORMAL => false,
P2_04ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_04ODR {
match value {
false => P2_04ODR::NORMAL,
true => P2_04ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_04ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_04ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_05OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_05ODR {
#[doc = "Normal. P2.5 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.5 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_05ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_05ODR::NORMAL => false,
P2_05ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_05ODR {
match value {
false => P2_05ODR::NORMAL,
true => P2_05ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_05ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_05ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_06OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_06ODR {
#[doc = "Normal. P2.6 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.6 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_06ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_06ODR::NORMAL => false,
P2_06ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_06ODR {
match value {
false => P2_06ODR::NORMAL,
true => P2_06ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_06ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_06ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_07OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_07ODR {
#[doc = "Normal. P2.7 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.7 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_07ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_07ODR::NORMAL => false,
P2_07ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_07ODR {
match value {
false => P2_07ODR::NORMAL,
true => P2_07ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_07ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_07ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_08OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_08ODR {
#[doc = "Normal. P2.8 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.8 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_08ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_08ODR::NORMAL => false,
P2_08ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_08ODR {
match value {
false => P2_08ODR::NORMAL,
true => P2_08ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_08ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_08ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_09OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_09ODR {
#[doc = "Normal. P2.9 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.9 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_09ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_09ODR::NORMAL => false,
P2_09ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_09ODR {
match value {
false => P2_09ODR::NORMAL,
true => P2_09ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_09ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_09ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_10OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_10ODR {
#[doc = "Normal. P2.10 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.10 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_10ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_10ODR::NORMAL => false,
P2_10ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_10ODR {
match value {
false => P2_10ODR::NORMAL,
true => P2_10ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_10ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_10ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_11OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_11ODR {
#[doc = "Normal. P2.11 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.11 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_11ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_11ODR::NORMAL => false,
P2_11ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_11ODR {
match value {
false => P2_11ODR::NORMAL,
true => P2_11ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_11ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_11ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_12OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_12ODR {
#[doc = "Normal. P2.12 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.12 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_12ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_12ODR::NORMAL => false,
P2_12ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_12ODR {
match value {
false => P2_12ODR::NORMAL,
true => P2_12ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_12ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_12ODR::OPEN_DRAIN
}
}
#[doc = "Possible values of the field `P2_13OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P2_13ODR {
#[doc = "Normal. P2.13 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.13 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_13ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P2_13ODR::NORMAL => false,
P2_13ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P2_13ODR {
match value {
false => P2_13ODR::NORMAL,
true => P2_13ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P2_13ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P2_13ODR::OPEN_DRAIN
}
}
#[doc = "Values that can be written to the field `P2_00OD`"]
pub enum P2_00ODW {
#[doc = "Normal. P2.0 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.0 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_00ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_00ODW::NORMAL => false,
P2_00ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_00ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_00ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_00ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.0 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_00ODW::NORMAL)
}
#[doc = "Open-drain. P2.0 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_00ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_01OD`"]
pub enum P2_01ODW {
#[doc = "Normal. P2.1 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.1p in is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_01ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_01ODW::NORMAL => false,
P2_01ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_01ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_01ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_01ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.1 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_01ODW::NORMAL)
}
#[doc = "Open-drain. P2.1p in is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_01ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_02OD`"]
pub enum P2_02ODW {
#[doc = "Normal. P2.2 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.2 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_02ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_02ODW::NORMAL => false,
P2_02ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_02ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_02ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_02ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.2 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_02ODW::NORMAL)
}
#[doc = "Open-drain. P2.2 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_02ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_03OD`"]
pub enum P2_03ODW {
#[doc = "Normal. P2.3 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.3 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_03ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_03ODW::NORMAL => false,
P2_03ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_03ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_03ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_03ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.3 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_03ODW::NORMAL)
}
#[doc = "Open-drain. P2.3 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_03ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_04OD`"]
pub enum P2_04ODW {
#[doc = "Normal. P2.4 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.4 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_04ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_04ODW::NORMAL => false,
P2_04ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_04ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_04ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_04ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.4 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_04ODW::NORMAL)
}
#[doc = "Open-drain. P2.4 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_04ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_05OD`"]
pub enum P2_05ODW {
#[doc = "Normal. P2.5 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.5 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_05ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_05ODW::NORMAL => false,
P2_05ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_05ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_05ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_05ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.5 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_05ODW::NORMAL)
}
#[doc = "Open-drain. P2.5 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_05ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_06OD`"]
pub enum P2_06ODW {
#[doc = "Normal. P2.6 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.6 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_06ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_06ODW::NORMAL => false,
P2_06ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_06ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_06ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_06ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.6 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_06ODW::NORMAL)
}
#[doc = "Open-drain. P2.6 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_06ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_07OD`"]
pub enum P2_07ODW {
#[doc = "Normal. P2.7 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.7 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_07ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_07ODW::NORMAL => false,
P2_07ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_07ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_07ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_07ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.7 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_07ODW::NORMAL)
}
#[doc = "Open-drain. P2.7 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_07ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_08OD`"]
pub enum P2_08ODW {
#[doc = "Normal. P2.8 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.8 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_08ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_08ODW::NORMAL => false,
P2_08ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_08ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_08ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_08ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.8 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_08ODW::NORMAL)
}
#[doc = "Open-drain. P2.8 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_08ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_09OD`"]
pub enum P2_09ODW {
#[doc = "Normal. P2.9 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.9 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_09ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_09ODW::NORMAL => false,
P2_09ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_09ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_09ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_09ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.9 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_09ODW::NORMAL)
}
#[doc = "Open-drain. P2.9 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_09ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_10OD`"]
pub enum P2_10ODW {
#[doc = "Normal. P2.10 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.10 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_10ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_10ODW::NORMAL => false,
P2_10ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_10ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_10ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_10ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.10 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_10ODW::NORMAL)
}
#[doc = "Open-drain. P2.10 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_10ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_11OD`"]
pub enum P2_11ODW {
#[doc = "Normal. P2.11 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.11 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_11ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_11ODW::NORMAL => false,
P2_11ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_11ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_11ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_11ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.11 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_11ODW::NORMAL)
}
#[doc = "Open-drain. P2.11 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_11ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_12OD`"]
pub enum P2_12ODW {
#[doc = "Normal. P2.12 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.12 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_12ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_12ODW::NORMAL => false,
P2_12ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_12ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_12ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_12ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.12 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_12ODW::NORMAL)
}
#[doc = "Open-drain. P2.12 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_12ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `P2_13OD`"]
pub enum P2_13ODW {
#[doc = "Normal. P2.13 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P2.13 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P2_13ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P2_13ODW::NORMAL => false,
P2_13ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P2_13ODW<'a> {
w: &'a mut W,
}
impl<'a> _P2_13ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P2_13ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P2.13 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P2_13ODW::NORMAL)
}
#[doc = "Open-drain. P2.13 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P2_13ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Port 2 pin 0 open drain mode control."]
#[inline]
pub fn p2_00od(&self) -> P2_00ODR {
P2_00ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Port 2 pin 1 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_01od(&self) -> P2_01ODR {
P2_01ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Port 2 pin 2 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_02od(&self) -> P2_02ODR {
P2_02ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Port 2 pin 3 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_03od(&self) -> P2_03ODR {
P2_03ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Port 2 pin 4 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_04od(&self) -> P2_04ODR {
P2_04ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Port 2 pin 5 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_05od(&self) -> P2_05ODR {
P2_05ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Port 2 pin 6 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_06od(&self) -> P2_06ODR {
P2_06ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Port 2 pin 7 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_07od(&self) -> P2_07ODR {
P2_07ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Port 2 pin 8 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_08od(&self) -> P2_08ODR {
P2_08ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Port 2 pin 9 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_09od(&self) -> P2_09ODR {
P2_09ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Port 2 pin 10 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_10od(&self) -> P2_10ODR {
P2_10ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Port 2 pin 11 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_11od(&self) -> P2_11ODR {
P2_11ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Port 2 pin 12 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_12od(&self) -> P2_12ODR {
P2_12ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - Port 2 pin 13 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_13od(&self) -> P2_13ODR {
P2_13ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Port 2 pin 0 open drain mode control."]
#[inline]
pub fn p2_00od(&mut self) -> _P2_00ODW {
_P2_00ODW { w: self }
}
#[doc = "Bit 1 - Port 2 pin 1 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_01od(&mut self) -> _P2_01ODW {
_P2_01ODW { w: self }
}
#[doc = "Bit 2 - Port 2 pin 2 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_02od(&mut self) -> _P2_02ODW {
_P2_02ODW { w: self }
}
#[doc = "Bit 3 - Port 2 pin 3 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_03od(&mut self) -> _P2_03ODW {
_P2_03ODW { w: self }
}
#[doc = "Bit 4 - Port 2 pin 4 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_04od(&mut self) -> _P2_04ODW {
_P2_04ODW { w: self }
}
#[doc = "Bit 5 - Port 2 pin 5 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_05od(&mut self) -> _P2_05ODW {
_P2_05ODW { w: self }
}
#[doc = "Bit 6 - Port 2 pin 6 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_06od(&mut self) -> _P2_06ODW {
_P2_06ODW { w: self }
}
#[doc = "Bit 7 - Port 2 pin 7 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_07od(&mut self) -> _P2_07ODW {
_P2_07ODW { w: self }
}
#[doc = "Bit 8 - Port 2 pin 8 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_08od(&mut self) -> _P2_08ODW {
_P2_08ODW { w: self }
}
#[doc = "Bit 9 - Port 2 pin 9 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_09od(&mut self) -> _P2_09ODW {
_P2_09ODW { w: self }
}
#[doc = "Bit 10 - Port 2 pin 10 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_10od(&mut self) -> _P2_10ODW {
_P2_10ODW { w: self }
}
#[doc = "Bit 11 - Port 2 pin 11 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_11od(&mut self) -> _P2_11ODW {
_P2_11ODW { w: self }
}
#[doc = "Bit 12 - Port 2 pin 12 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_12od(&mut self) -> _P2_12ODW {
_P2_12ODW { w: self }
}
#[doc = "Bit 13 - Port 2 pin 13 open drain mode control, see P2.00OD"]
#[inline]
pub fn p2_13od(&mut self) -> _P2_13ODW {
_P2_13ODW { w: self }
}
}
}
#[doc = "Open drain mode control register 3"]
pub struct PINMODE_OD3 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Open drain mode control register 3"]
pub mod pinmode_od3 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE_OD3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P3_25OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P3_25ODR {
#[doc = "Normal. P3.25 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P3.25 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P3_25ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P3_25ODR::NORMAL => false,
P3_25ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P3_25ODR {
match value {
false => P3_25ODR::NORMAL,
true => P3_25ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P3_25ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P3_25ODR::OPEN_DRAIN
}
}
#[doc = r" Value of the field"]
pub struct P3_26ODR {
bits: bool,
}
impl P3_26ODR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `P3_25OD`"]
pub enum P3_25ODW {
#[doc = "Normal. P3.25 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P3.25 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P3_25ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P3_25ODW::NORMAL => false,
P3_25ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P3_25ODW<'a> {
w: &'a mut W,
}
impl<'a> _P3_25ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P3_25ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P3.25 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P3_25ODW::NORMAL)
}
#[doc = "Open-drain. P3.25 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P3_25ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P3_26ODW<'a> {
w: &'a mut W,
}
impl<'a> _P3_26ODW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 25 - Port 3 pin 25 open drain mode control."]
#[inline]
pub fn p3_25od(&self) -> P3_25ODR {
P3_25ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Port 3 pin 26 open drain mode control, see P3.25OD"]
#[inline]
pub fn p3_26od(&self) -> P3_26ODR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P3_26ODR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 25 - Port 3 pin 25 open drain mode control."]
#[inline]
pub fn p3_25od(&mut self) -> _P3_25ODW {
_P3_25ODW { w: self }
}
#[doc = "Bit 26 - Port 3 pin 26 open drain mode control, see P3.25OD"]
#[inline]
pub fn p3_26od(&mut self) -> _P3_26ODW {
_P3_26ODW { w: self }
}
}
}
#[doc = "Open drain mode control register 4"]
pub struct PINMODE_OD4 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Open drain mode control register 4"]
pub mod pinmode_od4 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PINMODE_OD4 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `P4_28OD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum P4_28ODR {
#[doc = "Normal. P4.28 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P4.28 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P4_28ODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
P4_28ODR::NORMAL => false,
P4_28ODR::OPEN_DRAIN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> P4_28ODR {
match value {
false => P4_28ODR::NORMAL,
true => P4_28ODR::OPEN_DRAIN,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == P4_28ODR::NORMAL
}
#[doc = "Checks if the value of the field is `OPEN_DRAIN`"]
#[inline]
pub fn is_open_drain(&self) -> bool {
*self == P4_28ODR::OPEN_DRAIN
}
}
#[doc = r" Value of the field"]
pub struct P4_29ODR {
bits: bool,
}
impl P4_29ODR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `P4_28OD`"]
pub enum P4_28ODW {
#[doc = "Normal. P4.28 pin is in the normal (not open drain) mode."]
NORMAL,
#[doc = "Open-drain. P4.28 pin is in the open drain mode."]
OPEN_DRAIN,
}
impl P4_28ODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
P4_28ODW::NORMAL => false,
P4_28ODW::OPEN_DRAIN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _P4_28ODW<'a> {
w: &'a mut W,
}
impl<'a> _P4_28ODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: P4_28ODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. P4.28 pin is in the normal (not open drain) mode."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(P4_28ODW::NORMAL)
}
#[doc = "Open-drain. P4.28 pin is in the open drain mode."]
#[inline]
pub fn open_drain(self) -> &'a mut W {
self.variant(P4_28ODW::OPEN_DRAIN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _P4_29ODW<'a> {
w: &'a mut W,
}
impl<'a> _P4_29ODW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 28 - Port 4 pin 28 open drain mode control."]
#[inline]
pub fn p4_28od(&self) -> P4_28ODR {
P4_28ODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Port 4 pin 29 open drain mode control, see P4.28OD"]
#[inline]
pub fn p4_29od(&self) -> P4_29ODR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
P4_29ODR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 28 - Port 4 pin 28 open drain mode control."]
#[inline]
pub fn p4_28od(&mut self) -> _P4_28ODW {
_P4_28ODW { w: self }
}
#[doc = "Bit 29 - Port 4 pin 29 open drain mode control, see P4.28OD"]
#[inline]
pub fn p4_29od(&mut self) -> _P4_29ODW {
_P4_29ODW { w: self }
}
}
}
#[doc = "I2C Pin Configuration register"]
pub struct I2CPADCFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Pin Configuration register"]
pub mod i2cpadcfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::I2CPADCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SDADRV0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SDADRV0R {
#[doc = "Standard. The SDA0 pin is in the standard drive mode."]
STANDARD,
#[doc = "Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode."]
FAST_MODE_PLUS,
}
impl SDADRV0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SDADRV0R::STANDARD => false,
SDADRV0R::FAST_MODE_PLUS => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SDADRV0R {
match value {
false => SDADRV0R::STANDARD,
true => SDADRV0R::FAST_MODE_PLUS,
}
}
#[doc = "Checks if the value of the field is `STANDARD`"]
#[inline]
pub fn is_standard(&self) -> bool {
*self == SDADRV0R::STANDARD
}
#[doc = "Checks if the value of the field is `FAST_MODE_PLUS`"]
#[inline]
pub fn is_fast_mode_plus(&self) -> bool {
*self == SDADRV0R::FAST_MODE_PLUS
}
}
#[doc = "Possible values of the field `SDAI2C0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SDAI2C0R {
#[doc = "Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled."]
ENABLED,
#[doc = "Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled."]
DISABLED,
}
impl SDAI2C0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SDAI2C0R::ENABLED => false,
SDAI2C0R::DISABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SDAI2C0R {
match value {
false => SDAI2C0R::ENABLED,
true => SDAI2C0R::DISABLED,
}
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == SDAI2C0R::ENABLED
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == SDAI2C0R::DISABLED
}
}
#[doc = "Possible values of the field `SCLDRV0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCLDRV0R {
#[doc = "Standard. The SCL0 pin is in the standard drive mode."]
STANDARD,
#[doc = "Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode."]
FAST_MODE_PLUS,
}
impl SCLDRV0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SCLDRV0R::STANDARD => false,
SCLDRV0R::FAST_MODE_PLUS => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SCLDRV0R {
match value {
false => SCLDRV0R::STANDARD,
true => SCLDRV0R::FAST_MODE_PLUS,
}
}
#[doc = "Checks if the value of the field is `STANDARD`"]
#[inline]
pub fn is_standard(&self) -> bool {
*self == SCLDRV0R::STANDARD
}
#[doc = "Checks if the value of the field is `FAST_MODE_PLUS`"]
#[inline]
pub fn is_fast_mode_plus(&self) -> bool {
*self == SCLDRV0R::FAST_MODE_PLUS
}
}
#[doc = "Possible values of the field `SCLI2C0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCLI2C0R {
#[doc = "Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled."]
ENABLED,
#[doc = "Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled."]
DISABLED,
}
impl SCLI2C0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SCLI2C0R::ENABLED => false,
SCLI2C0R::DISABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SCLI2C0R {
match value {
false => SCLI2C0R::ENABLED,
true => SCLI2C0R::DISABLED,
}
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == SCLI2C0R::ENABLED
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == SCLI2C0R::DISABLED
}
}
#[doc = "Values that can be written to the field `SDADRV0`"]
pub enum SDADRV0W {
#[doc = "Standard. The SDA0 pin is in the standard drive mode."]
STANDARD,
#[doc = "Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode."]
FAST_MODE_PLUS,
}
impl SDADRV0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SDADRV0W::STANDARD => false,
SDADRV0W::FAST_MODE_PLUS => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SDADRV0W<'a> {
w: &'a mut W,
}
impl<'a> _SDADRV0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SDADRV0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Standard. The SDA0 pin is in the standard drive mode."]
#[inline]
pub fn standard(self) -> &'a mut W {
self.variant(SDADRV0W::STANDARD)
}
#[doc = "Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode."]
#[inline]
pub fn fast_mode_plus(self) -> &'a mut W {
self.variant(SDADRV0W::FAST_MODE_PLUS)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SDAI2C0`"]
pub enum SDAI2C0W {
#[doc = "Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled."]
ENABLED,
#[doc = "Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled."]
DISABLED,
}
impl SDAI2C0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SDAI2C0W::ENABLED => false,
SDAI2C0W::DISABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SDAI2C0W<'a> {
w: &'a mut W,
}
impl<'a> _SDAI2C0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SDAI2C0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(SDAI2C0W::ENABLED)
}
#[doc = "Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(SDAI2C0W::DISABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SCLDRV0`"]
pub enum SCLDRV0W {
#[doc = "Standard. The SCL0 pin is in the standard drive mode."]
STANDARD,
#[doc = "Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode."]
FAST_MODE_PLUS,
}
impl SCLDRV0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SCLDRV0W::STANDARD => false,
SCLDRV0W::FAST_MODE_PLUS => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SCLDRV0W<'a> {
w: &'a mut W,
}
impl<'a> _SCLDRV0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SCLDRV0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Standard. The SCL0 pin is in the standard drive mode."]
#[inline]
pub fn standard(self) -> &'a mut W {
self.variant(SCLDRV0W::STANDARD)
}
#[doc = "Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode."]
#[inline]
pub fn fast_mode_plus(self) -> &'a mut W {
self.variant(SCLDRV0W::FAST_MODE_PLUS)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SCLI2C0`"]
pub enum SCLI2C0W {
#[doc = "Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled."]
ENABLED,
#[doc = "Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled."]
DISABLED,
}
impl SCLI2C0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SCLI2C0W::ENABLED => false,
SCLI2C0W::DISABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SCLI2C0W<'a> {
w: &'a mut W,
}
impl<'a> _SCLI2C0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SCLI2C0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(SCLI2C0W::ENABLED)
}
#[doc = "Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(SCLI2C0W::DISABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Drive mode control for the SDA0 pin, P0.27."]
#[inline]
pub fn sdadrv0(&self) -> SDADRV0R {
SDADRV0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - I 2C filter mode control for the SDA0 pin, P0.27."]
#[inline]
pub fn sdai2c0(&self) -> SDAI2C0R {
SDAI2C0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Drive mode control for the SCL0 pin, P0.28."]
#[inline]
pub fn scldrv0(&self) -> SCLDRV0R {
SCLDRV0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - I 2C filter mode control for the SCL0 pin, P0.28."]
#[inline]
pub fn scli2c0(&self) -> SCLI2C0R {
SCLI2C0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Drive mode control for the SDA0 pin, P0.27."]
#[inline]
pub fn sdadrv0(&mut self) -> _SDADRV0W {
_SDADRV0W { w: self }
}
#[doc = "Bit 1 - I 2C filter mode control for the SDA0 pin, P0.27."]
#[inline]
pub fn sdai2c0(&mut self) -> _SDAI2C0W {
_SDAI2C0W { w: self }
}
#[doc = "Bit 2 - Drive mode control for the SCL0 pin, P0.28."]
#[inline]
pub fn scldrv0(&mut self) -> _SCLDRV0W {
_SCLDRV0W { w: self }
}
#[doc = "Bit 3 - I 2C filter mode control for the SCL0 pin, P0.28."]
#[inline]
pub fn scli2c0(&mut self) -> _SCLI2C0W {
_SCLI2C0W { w: self }
}
}
}
}
#[doc = "SSP1 controller"]
pub struct SSP1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SSP1 {}
impl SSP1 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const ssp1::RegisterBlock {
0x4003_0000 as *const _
}
}
impl Deref for SSP1 {
type Target = ssp1::RegisterBlock;
fn deref(&self) -> &ssp1::RegisterBlock {
unsafe { &*SSP1::ptr() }
}
}
#[doc = "SSP1 controller"]
pub mod ssp1 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control Register 0. Selects the serial clock rate, bus type, and data size."]
pub cr0: CR0,
#[doc = "0x04 - Control Register 1. Selects master/slave and other modes."]
pub cr1: CR1,
#[doc = "0x08 - Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO."]
pub dr: DR,
#[doc = "0x0c - Status Register"]
pub sr: SR,
#[doc = "0x10 - Clock Prescale Register"]
pub cpsr: CPSR,
#[doc = "0x14 - Interrupt Mask Set and Clear Register"]
pub imsc: IMSC,
#[doc = "0x18 - Raw Interrupt Status Register"]
pub ris: RIS,
#[doc = "0x1c - Masked Interrupt Status Register"]
pub mis: MIS,
#[doc = "0x20 - SSPICR Interrupt Clear Register"]
pub icr: ICR,
#[doc = "0x24 - SSP0 DMA control register"]
pub dmacr: DMACR,
}
#[doc = "Control Register 0. Selects the serial clock rate, bus type, and data size."]
pub struct CR0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control Register 0. Selects the serial clock rate, bus type, and data size."]
pub mod cr0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `DSS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DSSR {
#[doc = "4-bit transfer"]
_4_BIT_TRANSFER,
#[doc = "5-bit transfer"]
_5_BIT_TRANSFER,
#[doc = "6-bit transfer"]
_6_BIT_TRANSFER,
#[doc = "7-bit transfer"]
_7_BIT_TRANSFER,
#[doc = "8-bit transfer"]
_8_BIT_TRANSFER,
#[doc = "9-bit transfer"]
_9_BIT_TRANSFER,
#[doc = "10-bit transfer"]
_10_BIT_TRANSFER,
#[doc = "11-bit transfer"]
_11_BIT_TRANSFER,
#[doc = "12-bit transfer"]
_12_BIT_TRANSFER,
#[doc = "13-bit transfer"]
_13_BIT_TRANSFER,
#[doc = "14-bit transfer"]
_14_BIT_TRANSFER,
#[doc = "15-bit transfer"]
_15_BIT_TRANSFER,
#[doc = "16-bit transfer"]
_16_BIT_TRANSFER,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl DSSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
DSSR::_4_BIT_TRANSFER => 0x03,
DSSR::_5_BIT_TRANSFER => 0x04,
DSSR::_6_BIT_TRANSFER => 0x05,
DSSR::_7_BIT_TRANSFER => 0x06,
DSSR::_8_BIT_TRANSFER => 0x07,
DSSR::_9_BIT_TRANSFER => 0x08,
DSSR::_10_BIT_TRANSFER => 0x09,
DSSR::_11_BIT_TRANSFER => 0x0a,
DSSR::_12_BIT_TRANSFER => 0x0b,
DSSR::_13_BIT_TRANSFER => 0x0c,
DSSR::_14_BIT_TRANSFER => 0x0d,
DSSR::_15_BIT_TRANSFER => 0x0e,
DSSR::_16_BIT_TRANSFER => 0x0f,
DSSR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> DSSR {
match value {
3 => DSSR::_4_BIT_TRANSFER,
4 => DSSR::_5_BIT_TRANSFER,
5 => DSSR::_6_BIT_TRANSFER,
6 => DSSR::_7_BIT_TRANSFER,
7 => DSSR::_8_BIT_TRANSFER,
8 => DSSR::_9_BIT_TRANSFER,
9 => DSSR::_10_BIT_TRANSFER,
10 => DSSR::_11_BIT_TRANSFER,
11 => DSSR::_12_BIT_TRANSFER,
12 => DSSR::_13_BIT_TRANSFER,
13 => DSSR::_14_BIT_TRANSFER,
14 => DSSR::_15_BIT_TRANSFER,
15 => DSSR::_16_BIT_TRANSFER,
i => DSSR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_4_BIT_TRANSFER`"]
#[inline]
pub fn is_4_bit_transfer(&self) -> bool {
*self == DSSR::_4_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_5_BIT_TRANSFER`"]
#[inline]
pub fn is_5_bit_transfer(&self) -> bool {
*self == DSSR::_5_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_6_BIT_TRANSFER`"]
#[inline]
pub fn is_6_bit_transfer(&self) -> bool {
*self == DSSR::_6_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_7_BIT_TRANSFER`"]
#[inline]
pub fn is_7_bit_transfer(&self) -> bool {
*self == DSSR::_7_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_8_BIT_TRANSFER`"]
#[inline]
pub fn is_8_bit_transfer(&self) -> bool {
*self == DSSR::_8_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_9_BIT_TRANSFER`"]
#[inline]
pub fn is_9_bit_transfer(&self) -> bool {
*self == DSSR::_9_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_10_BIT_TRANSFER`"]
#[inline]
pub fn is_10_bit_transfer(&self) -> bool {
*self == DSSR::_10_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_11_BIT_TRANSFER`"]
#[inline]
pub fn is_11_bit_transfer(&self) -> bool {
*self == DSSR::_11_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_12_BIT_TRANSFER`"]
#[inline]
pub fn is_12_bit_transfer(&self) -> bool {
*self == DSSR::_12_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_13_BIT_TRANSFER`"]
#[inline]
pub fn is_13_bit_transfer(&self) -> bool {
*self == DSSR::_13_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_14_BIT_TRANSFER`"]
#[inline]
pub fn is_14_bit_transfer(&self) -> bool {
*self == DSSR::_14_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_15_BIT_TRANSFER`"]
#[inline]
pub fn is_15_bit_transfer(&self) -> bool {
*self == DSSR::_15_BIT_TRANSFER
}
#[doc = "Checks if the value of the field is `_16_BIT_TRANSFER`"]
#[inline]
pub fn is_16_bit_transfer(&self) -> bool {
*self == DSSR::_16_BIT_TRANSFER
}
}
#[doc = "Possible values of the field `FRF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRFR {
#[doc = "SPI"]
SPI,
#[doc = "TI"]
TI,
#[doc = "Microwire"]
MICROWIRE,
#[doc = "This combination is not supported and should not be used."]
THIS_COMBINATION_IS_,
}
impl FRFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
FRFR::SPI => 0,
FRFR::TI => 0x01,
FRFR::MICROWIRE => 0x02,
FRFR::THIS_COMBINATION_IS_ => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> FRFR {
match value {
0 => FRFR::SPI,
1 => FRFR::TI,
2 => FRFR::MICROWIRE,
3 => FRFR::THIS_COMBINATION_IS_,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `SPI`"]
#[inline]
pub fn is_spi(&self) -> bool {
*self == FRFR::SPI
}
#[doc = "Checks if the value of the field is `TI`"]
#[inline]
pub fn is_ti(&self) -> bool {
*self == FRFR::TI
}
#[doc = "Checks if the value of the field is `MICROWIRE`"]
#[inline]
pub fn is_microwire(&self) -> bool {
*self == FRFR::MICROWIRE
}
#[doc = "Checks if the value of the field is `THIS_COMBINATION_IS_`"]
#[inline]
pub fn is_this_combination_is_(&self) -> bool {
*self == FRFR::THIS_COMBINATION_IS_
}
}
#[doc = "Possible values of the field `CPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPOLR {
#[doc = "SSP controller maintains the bus clock low between frames."]
BUS_LOW,
#[doc = "SSP controller maintains the bus clock high between frames."]
BUS_HIGH,
}
impl CPOLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CPOLR::BUS_LOW => false,
CPOLR::BUS_HIGH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CPOLR {
match value {
false => CPOLR::BUS_LOW,
true => CPOLR::BUS_HIGH,
}
}
#[doc = "Checks if the value of the field is `BUS_LOW`"]
#[inline]
pub fn is_bus_low(&self) -> bool {
*self == CPOLR::BUS_LOW
}
#[doc = "Checks if the value of the field is `BUS_HIGH`"]
#[inline]
pub fn is_bus_high(&self) -> bool {
*self == CPOLR::BUS_HIGH
}
}
#[doc = "Possible values of the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPHAR {
#[doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."]
FIRST_CLOCK,
#[doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."]
SECOND_CLOCK,
}
impl CPHAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CPHAR::FIRST_CLOCK => false,
CPHAR::SECOND_CLOCK => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CPHAR {
match value {
false => CPHAR::FIRST_CLOCK,
true => CPHAR::SECOND_CLOCK,
}
}
#[doc = "Checks if the value of the field is `FIRST_CLOCK`"]
#[inline]
pub fn is_first_clock(&self) -> bool {
*self == CPHAR::FIRST_CLOCK
}
#[doc = "Checks if the value of the field is `SECOND_CLOCK`"]
#[inline]
pub fn is_second_clock(&self) -> bool {
*self == CPHAR::SECOND_CLOCK
}
}
#[doc = r" Value of the field"]
pub struct SCRR {
bits: u8,
}
impl SCRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Values that can be written to the field `DSS`"]
pub enum DSSW {
#[doc = "4-bit transfer"]
_4_BIT_TRANSFER,
#[doc = "5-bit transfer"]
_5_BIT_TRANSFER,
#[doc = "6-bit transfer"]
_6_BIT_TRANSFER,
#[doc = "7-bit transfer"]
_7_BIT_TRANSFER,
#[doc = "8-bit transfer"]
_8_BIT_TRANSFER,
#[doc = "9-bit transfer"]
_9_BIT_TRANSFER,
#[doc = "10-bit transfer"]
_10_BIT_TRANSFER,
#[doc = "11-bit transfer"]
_11_BIT_TRANSFER,
#[doc = "12-bit transfer"]
_12_BIT_TRANSFER,
#[doc = "13-bit transfer"]
_13_BIT_TRANSFER,
#[doc = "14-bit transfer"]
_14_BIT_TRANSFER,
#[doc = "15-bit transfer"]
_15_BIT_TRANSFER,
#[doc = "16-bit transfer"]
_16_BIT_TRANSFER,
}
impl DSSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
DSSW::_4_BIT_TRANSFER => 3,
DSSW::_5_BIT_TRANSFER => 4,
DSSW::_6_BIT_TRANSFER => 5,
DSSW::_7_BIT_TRANSFER => 6,
DSSW::_8_BIT_TRANSFER => 7,
DSSW::_9_BIT_TRANSFER => 8,
DSSW::_10_BIT_TRANSFER => 9,
DSSW::_11_BIT_TRANSFER => 10,
DSSW::_12_BIT_TRANSFER => 11,
DSSW::_13_BIT_TRANSFER => 12,
DSSW::_14_BIT_TRANSFER => 13,
DSSW::_15_BIT_TRANSFER => 14,
DSSW::_16_BIT_TRANSFER => 15,
}
}
}
#[doc = r" Proxy"]
pub struct _DSSW<'a> {
w: &'a mut W,
}
impl<'a> _DSSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DSSW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "4-bit transfer"]
#[inline]
pub fn _4_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_4_BIT_TRANSFER)
}
#[doc = "5-bit transfer"]
#[inline]
pub fn _5_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_5_BIT_TRANSFER)
}
#[doc = "6-bit transfer"]
#[inline]
pub fn _6_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_6_BIT_TRANSFER)
}
#[doc = "7-bit transfer"]
#[inline]
pub fn _7_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_7_BIT_TRANSFER)
}
#[doc = "8-bit transfer"]
#[inline]
pub fn _8_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_8_BIT_TRANSFER)
}
#[doc = "9-bit transfer"]
#[inline]
pub fn _9_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_9_BIT_TRANSFER)
}
#[doc = "10-bit transfer"]
#[inline]
pub fn _10_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_10_BIT_TRANSFER)
}
#[doc = "11-bit transfer"]
#[inline]
pub fn _11_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_11_BIT_TRANSFER)
}
#[doc = "12-bit transfer"]
#[inline]
pub fn _12_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_12_BIT_TRANSFER)
}
#[doc = "13-bit transfer"]
#[inline]
pub fn _13_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_13_BIT_TRANSFER)
}
#[doc = "14-bit transfer"]
#[inline]
pub fn _14_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_14_BIT_TRANSFER)
}
#[doc = "15-bit transfer"]
#[inline]
pub fn _15_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_15_BIT_TRANSFER)
}
#[doc = "16-bit transfer"]
#[inline]
pub fn _16_bit_transfer(self) -> &'a mut W {
self.variant(DSSW::_16_BIT_TRANSFER)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FRF`"]
pub enum FRFW {
#[doc = "SPI"]
SPI,
#[doc = "TI"]
TI,
#[doc = "Microwire"]
MICROWIRE,
#[doc = "This combination is not supported and should not be used."]
THIS_COMBINATION_IS_,
}
impl FRFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
FRFW::SPI => 0,
FRFW::TI => 1,
FRFW::MICROWIRE => 2,
FRFW::THIS_COMBINATION_IS_ => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _FRFW<'a> {
w: &'a mut W,
}
impl<'a> _FRFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FRFW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "SPI"]
#[inline]
pub fn spi(self) -> &'a mut W {
self.variant(FRFW::SPI)
}
#[doc = "TI"]
#[inline]
pub fn ti(self) -> &'a mut W {
self.variant(FRFW::TI)
}
#[doc = "Microwire"]
#[inline]
pub fn microwire(self) -> &'a mut W {
self.variant(FRFW::MICROWIRE)
}
#[doc = "This combination is not supported and should not be used."]
#[inline]
pub fn this_combination_is_(self) -> &'a mut W {
self.variant(FRFW::THIS_COMBINATION_IS_)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CPOL`"]
pub enum CPOLW {
#[doc = "SSP controller maintains the bus clock low between frames."]
BUS_LOW,
#[doc = "SSP controller maintains the bus clock high between frames."]
BUS_HIGH,
}
impl CPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CPOLW::BUS_LOW => false,
CPOLW::BUS_HIGH => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CPOLW<'a> {
w: &'a mut W,
}
impl<'a> _CPOLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CPOLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SSP controller maintains the bus clock low between frames."]
#[inline]
pub fn bus_low(self) -> &'a mut W {
self.variant(CPOLW::BUS_LOW)
}
#[doc = "SSP controller maintains the bus clock high between frames."]
#[inline]
pub fn bus_high(self) -> &'a mut W {
self.variant(CPOLW::BUS_HIGH)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CPHA`"]
pub enum CPHAW {
#[doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."]
FIRST_CLOCK,
#[doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."]
SECOND_CLOCK,
}
impl CPHAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CPHAW::FIRST_CLOCK => false,
CPHAW::SECOND_CLOCK => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CPHAW<'a> {
w: &'a mut W,
}
impl<'a> _CPHAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CPHAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."]
#[inline]
pub fn first_clock(self) -> &'a mut W {
self.variant(CPHAW::FIRST_CLOCK)
}
#[doc = "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."]
#[inline]
pub fn second_clock(self) -> &'a mut W {
self.variant(CPHAW::SECOND_CLOCK)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SCRW<'a> {
w: &'a mut W,
}
impl<'a> _SCRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."]
#[inline]
pub fn dss(&self) -> DSSR {
DSSR::_from({
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Frame Format."]
#[inline]
pub fn frf(&self) -> FRFR {
FRFR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Clock Out Polarity. This bit is only used in SPI mode."]
#[inline]
pub fn cpol(&self) -> CPOLR {
CPOLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Clock Out Phase. This bit is only used in SPI mode."]
#[inline]
pub fn cpha(&self) -> CPHAR {
CPHAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X \\[SCR+1\\])."]
#[inline]
pub fn scr(&self) -> SCRR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SCRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."]
#[inline]
pub fn dss(&mut self) -> _DSSW {
_DSSW { w: self }
}
#[doc = "Bits 4:5 - Frame Format."]
#[inline]
pub fn frf(&mut self) -> _FRFW {
_FRFW { w: self }
}
#[doc = "Bit 6 - Clock Out Polarity. This bit is only used in SPI mode."]
#[inline]
pub fn cpol(&mut self) -> _CPOLW {
_CPOLW { w: self }
}
#[doc = "Bit 7 - Clock Out Phase. This bit is only used in SPI mode."]
#[inline]
pub fn cpha(&mut self) -> _CPHAW {
_CPHAW { w: self }
}
#[doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X \\[SCR+1\\])."]
#[inline]
pub fn scr(&mut self) -> _SCRW {
_SCRW { w: self }
}
}
}
#[doc = "Control Register 1. Selects master/slave and other modes."]
pub struct CR1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control Register 1. Selects master/slave and other modes."]
pub mod cr1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `LBM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LBMR {
#[doc = "During normal operation."]
NORMAL,
#[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."]
OUPTU,
}
impl LBMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LBMR::NORMAL => false,
LBMR::OUPTU => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LBMR {
match value {
false => LBMR::NORMAL,
true => LBMR::OUPTU,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline]
pub fn is_normal(&self) -> bool {
*self == LBMR::NORMAL
}
#[doc = "Checks if the value of the field is `OUPTU`"]
#[inline]
pub fn is_ouptu(&self) -> bool {
*self == LBMR::OUPTU
}
}
#[doc = "Possible values of the field `SSE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSER {
#[doc = "The SSP controller is disabled."]
DISABLED,
#[doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit."]
ENABLED,
}
impl SSER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SSER::DISABLED => false,
SSER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SSER {
match value {
false => SSER::DISABLED,
true => SSER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == SSER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == SSER::ENABLED
}
}
#[doc = "Possible values of the field `MS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MSR {
#[doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."]
MASTER,
#[doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."]
SLAVE,
}
impl MSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MSR::MASTER => false,
MSR::SLAVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MSR {
match value {
false => MSR::MASTER,
true => MSR::SLAVE,
}
}
#[doc = "Checks if the value of the field is `MASTER`"]
#[inline]
pub fn is_master(&self) -> bool {
*self == MSR::MASTER
}
#[doc = "Checks if the value of the field is `SLAVE`"]
#[inline]
pub fn is_slave(&self) -> bool {
*self == MSR::SLAVE
}
}
#[doc = r" Value of the field"]
pub struct SODR {
bits: bool,
}
impl SODR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `LBM`"]
pub enum LBMW {
#[doc = "During normal operation."]
NORMAL,
#[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."]
OUPTU,
}
impl LBMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LBMW::NORMAL => false,
LBMW::OUPTU => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LBMW<'a> {
w: &'a mut W,
}
impl<'a> _LBMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LBMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "During normal operation."]
#[inline]
pub fn normal(self) -> &'a mut W {
self.variant(LBMW::NORMAL)
}
#[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."]
#[inline]
pub fn ouptu(self) -> &'a mut W {
self.variant(LBMW::OUPTU)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SSE`"]
pub enum SSEW {
#[doc = "The SSP controller is disabled."]
DISABLED,
#[doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit."]
ENABLED,
}
impl SSEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SSEW::DISABLED => false,
SSEW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SSEW<'a> {
w: &'a mut W,
}
impl<'a> _SSEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SSEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The SSP controller is disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(SSEW::DISABLED)
}
#[doc = "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(SSEW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MS`"]
pub enum MSW {
#[doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."]
MASTER,
#[doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."]
SLAVE,
}
impl MSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MSW::MASTER => false,
MSW::SLAVE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MSW<'a> {
w: &'a mut W,
}
impl<'a> _MSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."]
#[inline]
pub fn master(self) -> &'a mut W {
self.variant(MSW::MASTER)
}
#[doc = "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."]
#[inline]
pub fn slave(self) -> &'a mut W {
self.variant(MSW::SLAVE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SODW<'a> {
w: &'a mut W,
}
impl<'a> _SODW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Loop Back Mode."]
#[inline]
pub fn lbm(&self) -> LBMR {
LBMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - SSP Enable."]
#[inline]
pub fn sse(&self) -> SSER {
SSER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Master/Slave Mode.This bit can only be written when the SSE bit is 0."]
#[inline]
pub fn ms(&self) -> MSR {
MSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)."]
#[inline]
pub fn sod(&self) -> SODR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SODR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Loop Back Mode."]
#[inline]
pub fn lbm(&mut self) -> _LBMW {
_LBMW { w: self }
}
#[doc = "Bit 1 - SSP Enable."]
#[inline]
pub fn sse(&mut self) -> _SSEW {
_SSEW { w: self }
}
#[doc = "Bit 2 - Master/Slave Mode.This bit can only be written when the SSE bit is 0."]
#[inline]
pub fn ms(&mut self) -> _MSW {
_MSW { w: self }
}
#[doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)."]
#[inline]
pub fn sod(&mut self) -> _SODW {
_SODW { w: self }
}
}
}
#[doc = "Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO."]
pub struct DR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO."]
pub mod dr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATAR {
bits: u16,
}
impl DATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATAW<'a> {
w: &'a mut W,
}
impl<'a> _DATAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s."]
#[inline]
pub fn data(&self) -> DATAR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DATAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s."]
#[inline]
pub fn data(&mut self) -> _DATAW {
_DATAW { w: self }
}
}
}
#[doc = "Status Register"]
pub struct SR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status Register"]
pub mod sr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::SR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct TFER {
bits: bool,
}
impl TFER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TNFR {
bits: bool,
}
impl TNFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RNER {
bits: bool,
}
impl RNER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RFFR {
bits: bool,
}
impl RFFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BSYR {
bits: bool,
}
impl BSYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not."]
#[inline]
pub fn tfe(&self) -> TFER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TFER { bits }
}
#[doc = "Bit 1 - Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not."]
#[inline]
pub fn tnf(&self) -> TNFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TNFR { bits }
}
#[doc = "Bit 2 - Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not."]
#[inline]
pub fn rne(&self) -> RNER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RNER { bits }
}
#[doc = "Bit 3 - Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not."]
#[inline]
pub fn rff(&self) -> RFFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RFFR { bits }
}
#[doc = "Bit 4 - Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty."]
#[inline]
pub fn bsy(&self) -> BSYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BSYR { bits }
}
}
}
#[doc = "Clock Prescale Register"]
pub struct CPSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clock Prescale Register"]
pub mod cpsr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CPSR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CPSDVSRR {
bits: u8,
}
impl CPSDVSRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CPSDVSRW<'a> {
w: &'a mut W,
}
impl<'a> _CPSDVSRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."]
#[inline]
pub fn cpsdvsr(&self) -> CPSDVSRR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CPSDVSRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."]
#[inline]
pub fn cpsdvsr(&mut self) -> _CPSDVSRW {
_CPSDVSRW { w: self }
}
}
}
#[doc = "Interrupt Mask Set and Clear Register"]
pub struct IMSC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Mask Set and Clear Register"]
pub mod imsc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IMSC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RORIMR {
bits: bool,
}
impl RORIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RTIMR {
bits: bool,
}
impl RTIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXIMR {
bits: bool,
}
impl RXIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXIMR {
bits: bool,
}
impl TXIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RORIMW<'a> {
w: &'a mut W,
}
impl<'a> _RORIMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTIMW<'a> {
w: &'a mut W,
}
impl<'a> _RTIMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXIMW<'a> {
w: &'a mut W,
}
impl<'a> _RXIMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXIMW<'a> {
w: &'a mut W,
}
impl<'a> _TXIMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
#[inline]
pub fn rorim(&self) -> RORIMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RORIMR { bits }
}
#[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X \\[SCR+1\\])."]
#[inline]
pub fn rtim(&self) -> RTIMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTIMR { bits }
}
#[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
#[inline]
pub fn rxim(&self) -> RXIMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXIMR { bits }
}
#[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
#[inline]
pub fn txim(&self) -> TXIMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXIMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
#[inline]
pub fn rorim(&mut self) -> _RORIMW {
_RORIMW { w: self }
}
#[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X \\[SCR+1\\])."]
#[inline]
pub fn rtim(&mut self) -> _RTIMW {
_RTIMW { w: self }
}
#[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
#[inline]
pub fn rxim(&mut self) -> _RXIMW {
_RXIMW { w: self }
}
#[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
#[inline]
pub fn txim(&mut self) -> _TXIMW {
_TXIMW { w: self }
}
}
}
#[doc = "Raw Interrupt Status Register"]
pub struct RIS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Raw Interrupt Status Register"]
pub mod ris {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RIS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RORRISR {
bits: bool,
}
impl RORRISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RTRISR {
bits: bool,
}
impl RTRISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXRISR {
bits: bool,
}
impl RXRISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXRISR {
bits: bool,
}
impl TXRISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
#[inline]
pub fn rorris(&self) -> RORRISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RORRISR { bits }
}
#[doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X \\[SCR+1\\])."]
#[inline]
pub fn rtris(&self) -> RTRISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTRISR { bits }
}
#[doc = "Bit 2 - This bit is 1 if the Rx FIFO is at least half full."]
#[inline]
pub fn rxris(&self) -> RXRISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXRISR { bits }
}
#[doc = "Bit 3 - This bit is 1 if the Tx FIFO is at least half empty."]
#[inline]
pub fn txris(&self) -> TXRISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXRISR { bits }
}
}
}
#[doc = "Masked Interrupt Status Register"]
pub struct MIS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Masked Interrupt Status Register"]
pub mod mis {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::MIS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RORMISR {
bits: bool,
}
impl RORMISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RTMISR {
bits: bool,
}
impl RTMISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXMISR {
bits: bool,
}
impl RXMISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXMISR {
bits: bool,
}
impl TXMISR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled."]
#[inline]
pub fn rormis(&self) -> RORMISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RORMISR { bits }
}
#[doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X \\[SCR+1\\])."]
#[inline]
pub fn rtmis(&self) -> RTMISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTMISR { bits }
}
#[doc = "Bit 2 - This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled."]
#[inline]
pub fn rxmis(&self) -> RXMISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXMISR { bits }
}
#[doc = "Bit 3 - This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled."]
#[inline]
pub fn txmis(&self) -> TXMISR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXMISR { bits }
}
}
}
#[doc = "SSPICR Interrupt Clear Register"]
pub struct ICR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SSPICR Interrupt Clear Register"]
pub mod icr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ICR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _RORICW<'a> {
w: &'a mut W,
}
impl<'a> _RORICW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTICW<'a> {
w: &'a mut W,
}
impl<'a> _RTICW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt."]
#[inline]
pub fn roric(&mut self) -> _RORICW {
_RORICW { w: self }
}
#[doc = "Bit 1 - Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / \\[SCR+1\\])."]
#[inline]
pub fn rtic(&mut self) -> _RTICW {
_RTICW { w: self }
}
}
}
#[doc = "SSP0 DMA control register"]
pub struct DMACR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "SSP0 DMA control register"]
pub mod dmacr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMACR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXDMAER {
bits: bool,
}
impl RXDMAER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXDMAER {
bits: bool,
}
impl TXDMAER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RXDMAEW<'a> {
w: &'a mut W,
}
impl<'a> _RXDMAEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXDMAEW<'a> {
w: &'a mut W,
}
impl<'a> _TXDMAEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled."]
#[inline]
pub fn rxdmae(&self) -> RXDMAER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXDMAER { bits }
}
#[doc = "Bit 1 - Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled"]
#[inline]
pub fn txdmae(&self) -> TXDMAER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXDMAER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled."]
#[inline]
pub fn rxdmae(&mut self) -> _RXDMAEW {
_RXDMAEW { w: self }
}
#[doc = "Bit 1 - Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled"]
#[inline]
pub fn txdmae(&mut self) -> _TXDMAEW {
_TXDMAEW { w: self }
}
}
}
}
#[doc = "Analog-to-Digital Converter (ADC)"]
pub struct ADC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC {}
impl ADC {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const adc::RegisterBlock {
0x4003_4000 as *const _
}
}
impl Deref for ADC {
type Target = adc::RegisterBlock;
fn deref(&self) -> &adc::RegisterBlock {
unsafe { &*ADC::ptr() }
}
}
#[doc = "Analog-to-Digital Converter (ADC)"]
pub mod adc {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
pub cr: CR,
#[doc = "0x04 - A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion."]
pub gdr: GDR,
_reserved2: [u8; 4usize],
#[doc = "0x0c - A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
pub inten: INTEN,
#[doc = "0x10 - A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0."]
pub dr: [DR; 8],
#[doc = "0x30 - A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag."]
pub stat: STAT,
#[doc = "0x34 - ADC trim register."]
pub trm: TRM,
}
#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
pub struct CR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SELR {
bits: u8,
}
impl SELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct CLKDIVR {
bits: u8,
}
impl CLKDIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `BURST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BURSTR {
#[doc = "The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start."]
BURST,
#[doc = "Conversions are software controlled and require 31 clocks."]
SW,
}
impl BURSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BURSTR::BURST => true,
BURSTR::SW => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BURSTR {
match value {
true => BURSTR::BURST,
false => BURSTR::SW,
}
}
#[doc = "Checks if the value of the field is `BURST`"]
#[inline]
pub fn is_burst(&self) -> bool {
*self == BURSTR::BURST
}
#[doc = "Checks if the value of the field is `SW`"]
#[inline]
pub fn is_sw(&self) -> bool {
*self == BURSTR::SW
}
}
#[doc = "Possible values of the field `PDN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PDNR {
#[doc = "The A/D converter is operational."]
POWERED,
#[doc = "The A/D converter is in power-down mode."]
POWERDOWN,
}
impl PDNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
PDNR::POWERED => true,
PDNR::POWERDOWN => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> PDNR {
match value {
true => PDNR::POWERED,
false => PDNR::POWERDOWN,
}
}
#[doc = "Checks if the value of the field is `POWERED`"]
#[inline]
pub fn is_powered(&self) -> bool {
*self == PDNR::POWERED
}
#[doc = "Checks if the value of the field is `POWERDOWN`"]
#[inline]
pub fn is_powerdown(&self) -> bool {
*self == PDNR::POWERDOWN
}
}
#[doc = "Possible values of the field `START`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum STARTR {
#[doc = "No start (this value should be used when clearing PDN to 0)."]
NO_START_THIS_VALUE,
#[doc = "Start conversion now."]
START_CONVERSION_NOW,
#[doc = "Start conversion when the edge selected by bit 27 occurs on the P2\\[10\\] pin."]
P2_10,
#[doc = "Start conversion when the edge selected by bit 27 occurs on the P1\\[27\\] pin."]
P1_27,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin."]
MAT0_1,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin."]
MAT0_3,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin."]
MAT1_0,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin."]
MAT1_1,
}
impl STARTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
STARTR::NO_START_THIS_VALUE => 0,
STARTR::START_CONVERSION_NOW => 0x01,
STARTR::P2_10 => 0x02,
STARTR::P1_27 => 0x03,
STARTR::MAT0_1 => 0x04,
STARTR::MAT0_3 => 0x05,
STARTR::MAT1_0 => 0x06,
STARTR::MAT1_1 => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> STARTR {
match value {
0 => STARTR::NO_START_THIS_VALUE,
1 => STARTR::START_CONVERSION_NOW,
2 => STARTR::P2_10,
3 => STARTR::P1_27,
4 => STARTR::MAT0_1,
5 => STARTR::MAT0_3,
6 => STARTR::MAT1_0,
7 => STARTR::MAT1_1,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `NO_START_THIS_VALUE`"]
#[inline]
pub fn is_no_start_this_value(&self) -> bool {
*self == STARTR::NO_START_THIS_VALUE
}
#[doc = "Checks if the value of the field is `START_CONVERSION_NOW`"]
#[inline]
pub fn is_start_conversion_now(&self) -> bool {
*self == STARTR::START_CONVERSION_NOW
}
#[doc = "Checks if the value of the field is `P2_10`"]
#[inline]
pub fn is_p2_10(&self) -> bool {
*self == STARTR::P2_10
}
#[doc = "Checks if the value of the field is `P1_27`"]
#[inline]
pub fn is_p1_27(&self) -> bool {
*self == STARTR::P1_27
}
#[doc = "Checks if the value of the field is `MAT0_1`"]
#[inline]
pub fn is_mat0_1(&self) -> bool {
*self == STARTR::MAT0_1
}
#[doc = "Checks if the value of the field is `MAT0_3`"]
#[inline]
pub fn is_mat0_3(&self) -> bool {
*self == STARTR::MAT0_3
}
#[doc = "Checks if the value of the field is `MAT1_0`"]
#[inline]
pub fn is_mat1_0(&self) -> bool {
*self == STARTR::MAT1_0
}
#[doc = "Checks if the value of the field is `MAT1_1`"]
#[inline]
pub fn is_mat1_1(&self) -> bool {
*self == STARTR::MAT1_1
}
}
#[doc = "Possible values of the field `EDGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EDGER {
#[doc = "Start conversion on a falling edge on the selected CAP/MAT signal."]
FALLLING,
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
RISING,
}
impl EDGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EDGER::FALLLING => true,
EDGER::RISING => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EDGER {
match value {
true => EDGER::FALLLING,
false => EDGER::RISING,
}
}
#[doc = "Checks if the value of the field is `FALLLING`"]
#[inline]
pub fn is_fallling(&self) -> bool {
*self == EDGER::FALLLING
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == EDGER::RISING
}
}
#[doc = r" Proxy"]
pub struct _SELW<'a> {
w: &'a mut W,
}
impl<'a> _SELW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLKDIVW<'a> {
w: &'a mut W,
}
impl<'a> _CLKDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BURST`"]
pub enum BURSTW {
#[doc = "The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start."]
BURST,
#[doc = "Conversions are software controlled and require 31 clocks."]
SW,
}
impl BURSTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BURSTW::BURST => true,
BURSTW::SW => false,
}
}
}
#[doc = r" Proxy"]
pub struct _BURSTW<'a> {
w: &'a mut W,
}
impl<'a> _BURSTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BURSTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start."]
#[inline]
pub fn burst(self) -> &'a mut W {
self.variant(BURSTW::BURST)
}
#[doc = "Conversions are software controlled and require 31 clocks."]
#[inline]
pub fn sw(self) -> &'a mut W {
self.variant(BURSTW::SW)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PDN`"]
pub enum PDNW {
#[doc = "The A/D converter is operational."]
POWERED,
#[doc = "The A/D converter is in power-down mode."]
POWERDOWN,
}
impl PDNW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
PDNW::POWERED => true,
PDNW::POWERDOWN => false,
}
}
}
#[doc = r" Proxy"]
pub struct _PDNW<'a> {
w: &'a mut W,
}
impl<'a> _PDNW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PDNW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The A/D converter is operational."]
#[inline]
pub fn powered(self) -> &'a mut W {
self.variant(PDNW::POWERED)
}
#[doc = "The A/D converter is in power-down mode."]
#[inline]
pub fn powerdown(self) -> &'a mut W {
self.variant(PDNW::POWERDOWN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `START`"]
pub enum STARTW {
#[doc = "No start (this value should be used when clearing PDN to 0)."]
NO_START_THIS_VALUE,
#[doc = "Start conversion now."]
START_CONVERSION_NOW,
#[doc = "Start conversion when the edge selected by bit 27 occurs on the P2\\[10\\] pin."]
P2_10,
#[doc = "Start conversion when the edge selected by bit 27 occurs on the P1\\[27\\] pin."]
P1_27,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin."]
MAT0_1,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin."]
MAT0_3,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin."]
MAT1_0,
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin."]
MAT1_1,
}
impl STARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
STARTW::NO_START_THIS_VALUE => 0,
STARTW::START_CONVERSION_NOW => 1,
STARTW::P2_10 => 2,
STARTW::P1_27 => 3,
STARTW::MAT0_1 => 4,
STARTW::MAT0_3 => 5,
STARTW::MAT1_0 => 6,
STARTW::MAT1_1 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _STARTW<'a> {
w: &'a mut W,
}
impl<'a> _STARTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STARTW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "No start (this value should be used when clearing PDN to 0)."]
#[inline]
pub fn no_start_this_value(self) -> &'a mut W {
self.variant(STARTW::NO_START_THIS_VALUE)
}
#[doc = "Start conversion now."]
#[inline]
pub fn start_conversion_now(self) -> &'a mut W {
self.variant(STARTW::START_CONVERSION_NOW)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on the P2\\[10\\] pin."]
#[inline]
pub fn p2_10(self) -> &'a mut W {
self.variant(STARTW::P2_10)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on the P1\\[27\\] pin."]
#[inline]
pub fn p1_27(self) -> &'a mut W {
self.variant(STARTW::P1_27)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin."]
#[inline]
pub fn mat0_1(self) -> &'a mut W {
self.variant(STARTW::MAT0_1)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin."]
#[inline]
pub fn mat0_3(self) -> &'a mut W {
self.variant(STARTW::MAT0_3)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin."]
#[inline]
pub fn mat1_0(self) -> &'a mut W {
self.variant(STARTW::MAT1_0)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin."]
#[inline]
pub fn mat1_1(self) -> &'a mut W {
self.variant(STARTW::MAT1_1)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EDGE`"]
pub enum EDGEW {
#[doc = "Start conversion on a falling edge on the selected CAP/MAT signal."]
FALLLING,
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
RISING,
}
impl EDGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EDGEW::FALLLING => true,
EDGEW::RISING => false,
}
}
}
#[doc = r" Proxy"]
pub struct _EDGEW<'a> {
w: &'a mut W,
}
impl<'a> _EDGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EDGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Start conversion on a falling edge on the selected CAP/MAT signal."]
#[inline]
pub fn fallling(self) -> &'a mut W {
self.variant(EDGEW::FALLLING)
}
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
#[inline]
pub fn rising(self) -> &'a mut W {
self.variant(EDGEW::RISING)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Selects which of the AD0\\[7:0\\] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0\\[0\\], and bit 7 selects pin AD0\\[7\\]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01."]
#[inline]
pub fn sel(&self) -> SELR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SELR { bits }
}
#[doc = "Bits 8:15 - The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
#[inline]
pub fn clkdiv(&self) -> CLKDIVR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLKDIVR { bits }
}
#[doc = "Bit 16 - Burst mode"]
#[inline]
pub fn burst(&self) -> BURSTR {
BURSTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Power down mode"]
#[inline]
pub fn pdn(&self) -> PDNR {
PDNR::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
#[inline]
pub fn start(&self) -> STARTR {
STARTR::_from({
const MASK: u8 = 0x07;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases:"]
#[inline]
pub fn edge(&self) -> EDGER {
EDGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Selects which of the AD0\\[7:0\\] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0\\[0\\], and bit 7 selects pin AD0\\[7\\]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01."]
#[inline]
pub fn sel(&mut self) -> _SELW {
_SELW { w: self }
}
#[doc = "Bits 8:15 - The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
#[inline]
pub fn clkdiv(&mut self) -> _CLKDIVW {
_CLKDIVW { w: self }
}
#[doc = "Bit 16 - Burst mode"]
#[inline]
pub fn burst(&mut self) -> _BURSTW {
_BURSTW { w: self }
}
#[doc = "Bit 21 - Power down mode"]
#[inline]
pub fn pdn(&mut self) -> _PDNW {
_PDNW { w: self }
}
#[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
#[inline]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
#[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases:"]
#[inline]
pub fn edge(&mut self) -> _EDGEW {
_EDGEW { w: self }
}
}
}
#[doc = "A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion."]
pub struct GDR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion."]
pub mod gdr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::GDR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RESULTR {
bits: u16,
}
impl RESULTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct CHNR {
bits: u8,
}
impl CHNR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct OVERRUNR {
bits: bool,
}
impl OVERRUNR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONER {
bits: bool,
}
impl DONER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RESULTW<'a> {
w: &'a mut W,
}
impl<'a> _RESULTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CHNW<'a> {
w: &'a mut W,
}
impl<'a> _CHNW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _OVERRUNW<'a> {
w: &'a mut W,
}
impl<'a> _OVERRUNW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DONEW<'a> {
w: &'a mut W,
}
impl<'a> _DONEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 4:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the AD0\\[n\\] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP."]
#[inline]
pub fn result(&self) -> RESULTR {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RESULTR { bits }
}
#[doc = "Bits 24:26 - These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)."]
#[inline]
pub fn chn(&self) -> CHNR {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CHNR { bits }
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register."]
#[inline]
pub fn overrun(&self) -> OVERRUNR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUNR { bits }
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
#[inline]
pub fn done(&self) -> DONER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 4:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the AD0\\[n\\] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP."]
#[inline]
pub fn result(&mut self) -> _RESULTW {
_RESULTW { w: self }
}
#[doc = "Bits 24:26 - These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)."]
#[inline]
pub fn chn(&mut self) -> _CHNW {
_CHNW { w: self }
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register."]
#[inline]
pub fn overrun(&mut self) -> _OVERRUNW {
_OVERRUNW { w: self }
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
#[inline]
pub fn done(&mut self) -> _DONEW {
_DONEW { w: self }
}
}
}
#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
pub struct INTEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
pub mod inten {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTEN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADINTEN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN0R {
#[doc = "Completion of a conversion on ADC channel 0 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 0 will generate an interrupt."]
ENABLE,
}
impl ADINTEN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN0R::DISABLE => false,
ADINTEN0R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN0R {
match value {
false => ADINTEN0R::DISABLE,
true => ADINTEN0R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN0R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN0R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN1R {
#[doc = "Completion of a conversion on ADC channel 1 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 1 will generate an interrupt."]
ENABLE,
}
impl ADINTEN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN1R::DISABLE => false,
ADINTEN1R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN1R {
match value {
false => ADINTEN1R::DISABLE,
true => ADINTEN1R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN1R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN1R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN2R {
#[doc = "Completion of a conversion on ADC channel 2 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 2 will generate an interrupt."]
ENABLE,
}
impl ADINTEN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN2R::DISABLE => false,
ADINTEN2R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN2R {
match value {
false => ADINTEN2R::DISABLE,
true => ADINTEN2R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN2R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN2R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN3R {
#[doc = "Completion of a conversion on ADC channel 3 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 3 will generate an interrupt."]
ENABLE,
}
impl ADINTEN3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN3R::DISABLE => false,
ADINTEN3R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN3R {
match value {
false => ADINTEN3R::DISABLE,
true => ADINTEN3R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN3R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN3R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN4`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN4R {
#[doc = "Completion of a conversion on ADC channel 4 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 4 will generate an interrupt."]
ENABLE,
}
impl ADINTEN4R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN4R::DISABLE => false,
ADINTEN4R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN4R {
match value {
false => ADINTEN4R::DISABLE,
true => ADINTEN4R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN4R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN4R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN5`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN5R {
#[doc = "Completion of a conversion on ADC channel 5 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 5 will generate an interrupt."]
ENABLE,
}
impl ADINTEN5R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN5R::DISABLE => false,
ADINTEN5R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN5R {
match value {
false => ADINTEN5R::DISABLE,
true => ADINTEN5R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN5R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN5R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN6`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN6R {
#[doc = "Completion of a conversion on ADC channel 6 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 6 will generate an interrupt."]
ENABLE,
}
impl ADINTEN6R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN6R::DISABLE => false,
ADINTEN6R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN6R {
match value {
false => ADINTEN6R::DISABLE,
true => ADINTEN6R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN6R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN6R::ENABLE
}
}
#[doc = "Possible values of the field `ADINTEN7`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADINTEN7R {
#[doc = "Completion of a conversion on ADC channel 7 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 7 will generate an interrupt."]
ENABLE,
}
impl ADINTEN7R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADINTEN7R::DISABLE => false,
ADINTEN7R::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADINTEN7R {
match value {
false => ADINTEN7R::DISABLE,
true => ADINTEN7R::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == ADINTEN7R::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == ADINTEN7R::ENABLE
}
}
#[doc = "Possible values of the field `ADGINTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADGINTENR {
#[doc = "Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts."]
CHANNELS,
#[doc = "The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts."]
GLOBAL,
}
impl ADGINTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADGINTENR::CHANNELS => false,
ADGINTENR::GLOBAL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADGINTENR {
match value {
false => ADGINTENR::CHANNELS,
true => ADGINTENR::GLOBAL,
}
}
#[doc = "Checks if the value of the field is `CHANNELS`"]
#[inline]
pub fn is_channels(&self) -> bool {
*self == ADGINTENR::CHANNELS
}
#[doc = "Checks if the value of the field is `GLOBAL`"]
#[inline]
pub fn is_global(&self) -> bool {
*self == ADGINTENR::GLOBAL
}
}
#[doc = "Values that can be written to the field `ADINTEN0`"]
pub enum ADINTEN0W {
#[doc = "Completion of a conversion on ADC channel 0 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 0 will generate an interrupt."]
ENABLE,
}
impl ADINTEN0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN0W::DISABLE => false,
ADINTEN0W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN0W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 0 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN0W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 0 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN0W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN1`"]
pub enum ADINTEN1W {
#[doc = "Completion of a conversion on ADC channel 1 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 1 will generate an interrupt."]
ENABLE,
}
impl ADINTEN1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN1W::DISABLE => false,
ADINTEN1W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN1W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 1 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN1W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 1 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN1W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN2`"]
pub enum ADINTEN2W {
#[doc = "Completion of a conversion on ADC channel 2 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 2 will generate an interrupt."]
ENABLE,
}
impl ADINTEN2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN2W::DISABLE => false,
ADINTEN2W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN2W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 2 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN2W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 2 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN2W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN3`"]
pub enum ADINTEN3W {
#[doc = "Completion of a conversion on ADC channel 3 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 3 will generate an interrupt."]
ENABLE,
}
impl ADINTEN3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN3W::DISABLE => false,
ADINTEN3W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN3W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 3 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN3W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 3 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN3W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN4`"]
pub enum ADINTEN4W {
#[doc = "Completion of a conversion on ADC channel 4 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 4 will generate an interrupt."]
ENABLE,
}
impl ADINTEN4W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN4W::DISABLE => false,
ADINTEN4W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN4W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN4W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN4W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 4 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN4W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 4 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN4W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN5`"]
pub enum ADINTEN5W {
#[doc = "Completion of a conversion on ADC channel 5 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 5 will generate an interrupt."]
ENABLE,
}
impl ADINTEN5W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN5W::DISABLE => false,
ADINTEN5W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN5W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN5W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN5W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 5 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN5W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 5 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN5W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN6`"]
pub enum ADINTEN6W {
#[doc = "Completion of a conversion on ADC channel 6 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 6 will generate an interrupt."]
ENABLE,
}
impl ADINTEN6W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN6W::DISABLE => false,
ADINTEN6W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN6W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN6W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN6W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 6 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN6W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 6 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN6W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADINTEN7`"]
pub enum ADINTEN7W {
#[doc = "Completion of a conversion on ADC channel 7 will not generate an interrupt."]
DISABLE,
#[doc = "Completion of a conversion on ADC channel 7 will generate an interrupt."]
ENABLE,
}
impl ADINTEN7W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADINTEN7W::DISABLE => false,
ADINTEN7W::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADINTEN7W<'a> {
w: &'a mut W,
}
impl<'a> _ADINTEN7W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADINTEN7W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Completion of a conversion on ADC channel 7 will not generate an interrupt."]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(ADINTEN7W::DISABLE)
}
#[doc = "Completion of a conversion on ADC channel 7 will generate an interrupt."]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(ADINTEN7W::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADGINTEN`"]
pub enum ADGINTENW {
#[doc = "Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts."]
CHANNELS,
#[doc = "The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts."]
GLOBAL,
}
impl ADGINTENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADGINTENW::CHANNELS => false,
ADGINTENW::GLOBAL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADGINTENW<'a> {
w: &'a mut W,
}
impl<'a> _ADGINTENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADGINTENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts."]
#[inline]
pub fn channels(self) -> &'a mut W {
self.variant(ADGINTENW::CHANNELS)
}
#[doc = "The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts."]
#[inline]
pub fn global(self) -> &'a mut W {
self.variant(ADGINTENW::GLOBAL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt enable"]
#[inline]
pub fn adinten0(&self) -> ADINTEN0R {
ADINTEN0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Interrupt enable"]
#[inline]
pub fn adinten1(&self) -> ADINTEN1R {
ADINTEN1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Interrupt enable"]
#[inline]
pub fn adinten2(&self) -> ADINTEN2R {
ADINTEN2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Interrupt enable"]
#[inline]
pub fn adinten3(&self) -> ADINTEN3R {
ADINTEN3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Interrupt enable"]
#[inline]
pub fn adinten4(&self) -> ADINTEN4R {
ADINTEN4R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Interrupt enable"]
#[inline]
pub fn adinten5(&self) -> ADINTEN5R {
ADINTEN5R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Interrupt enable"]
#[inline]
pub fn adinten6(&self) -> ADINTEN6R {
ADINTEN6R::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Interrupt enable"]
#[inline]
pub fn adinten7(&self) -> ADINTEN7R {
ADINTEN7R::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Interrupt enable"]
#[inline]
pub fn adginten(&self) -> ADGINTENR {
ADGINTENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x0100 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt enable"]
#[inline]
pub fn adinten0(&mut self) -> _ADINTEN0W {
_ADINTEN0W { w: self }
}
#[doc = "Bit 1 - Interrupt enable"]
#[inline]
pub fn adinten1(&mut self) -> _ADINTEN1W {
_ADINTEN1W { w: self }
}
#[doc = "Bit 2 - Interrupt enable"]
#[inline]
pub fn adinten2(&mut self) -> _ADINTEN2W {
_ADINTEN2W { w: self }
}
#[doc = "Bit 3 - Interrupt enable"]
#[inline]
pub fn adinten3(&mut self) -> _ADINTEN3W {
_ADINTEN3W { w: self }
}
#[doc = "Bit 4 - Interrupt enable"]
#[inline]
pub fn adinten4(&mut self) -> _ADINTEN4W {
_ADINTEN4W { w: self }
}
#[doc = "Bit 5 - Interrupt enable"]
#[inline]
pub fn adinten5(&mut self) -> _ADINTEN5W {
_ADINTEN5W { w: self }
}
#[doc = "Bit 6 - Interrupt enable"]
#[inline]
pub fn adinten6(&mut self) -> _ADINTEN6W {
_ADINTEN6W { w: self }
}
#[doc = "Bit 7 - Interrupt enable"]
#[inline]
pub fn adinten7(&mut self) -> _ADINTEN7W {
_ADINTEN7W { w: self }
}
#[doc = "Bit 8 - Interrupt enable"]
#[inline]
pub fn adginten(&mut self) -> _ADGINTENW {
_ADGINTENW { w: self }
}
}
}
#[doc = "A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0."]
pub struct DR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0."]
pub mod dr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RESULTR {
bits: u16,
}
impl RESULTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct OVERRUNR {
bits: bool,
}
impl OVERRUNR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONER {
bits: bool,
}
impl DONER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 4:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the AD0\\[n\\] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP."]
#[inline]
pub fn result(&self) -> RESULTR {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RESULTR { bits }
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register."]
#[inline]
pub fn overrun(&self) -> OVERRUNR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUNR { bits }
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
#[inline]
pub fn done(&self) -> DONER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONER { bits }
}
}
}
#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag."]
pub struct STAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag."]
pub mod stat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DONE0R {
bits: bool,
}
impl DONE0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE1R {
bits: bool,
}
impl DONE1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE2R {
bits: bool,
}
impl DONE2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE3R {
bits: bool,
}
impl DONE3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE4R {
bits: bool,
}
impl DONE4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE5R {
bits: bool,
}
impl DONE5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE6R {
bits: bool,
}
impl DONE6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONE7R {
bits: bool,
}
impl DONE7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN0R {
bits: bool,
}
impl OVERRUN0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN1R {
bits: bool,
}
impl OVERRUN1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN2R {
bits: bool,
}
impl OVERRUN2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN3R {
bits: bool,
}
impl OVERRUN3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN4R {
bits: bool,
}
impl OVERRUN4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN5R {
bits: bool,
}
impl OVERRUN5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN6R {
bits: bool,
}
impl OVERRUN6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct OVERRUN7R {
bits: bool,
}
impl OVERRUN7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ADINTR {
bits: bool,
}
impl ADINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - This bit mirrors the DONE status flag from the result register for A/D channel 0."]
#[inline]
pub fn done0(&self) -> DONE0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE0R { bits }
}
#[doc = "Bit 1 - This bit mirrors the DONE status flag from the result register for A/D channel 1."]
#[inline]
pub fn done1(&self) -> DONE1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE1R { bits }
}
#[doc = "Bit 2 - This bit mirrors the DONE status flag from the result register for A/D channel 2."]
#[inline]
pub fn done2(&self) -> DONE2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE2R { bits }
}
#[doc = "Bit 3 - This bit mirrors the DONE status flag from the result register for A/D channel 3."]
#[inline]
pub fn done3(&self) -> DONE3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE3R { bits }
}
#[doc = "Bit 4 - This bit mirrors the DONE status flag from the result register for A/D channel 4."]
#[inline]
pub fn done4(&self) -> DONE4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE4R { bits }
}
#[doc = "Bit 5 - This bit mirrors the DONE status flag from the result register for A/D channel 5."]
#[inline]
pub fn done5(&self) -> DONE5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE5R { bits }
}
#[doc = "Bit 6 - This bit mirrors the DONE status flag from the result register for A/D channel 6."]
#[inline]
pub fn done6(&self) -> DONE6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE6R { bits }
}
#[doc = "Bit 7 - This bit mirrors the DONE status flag from the result register for A/D channel 7."]
#[inline]
pub fn done7(&self) -> DONE7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONE7R { bits }
}
#[doc = "Bit 8 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0."]
#[inline]
pub fn overrun0(&self) -> OVERRUN0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN0R { bits }
}
#[doc = "Bit 9 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1."]
#[inline]
pub fn overrun1(&self) -> OVERRUN1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN1R { bits }
}
#[doc = "Bit 10 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2."]
#[inline]
pub fn overrun2(&self) -> OVERRUN2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN2R { bits }
}
#[doc = "Bit 11 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3."]
#[inline]
pub fn overrun3(&self) -> OVERRUN3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN3R { bits }
}
#[doc = "Bit 12 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4."]
#[inline]
pub fn overrun4(&self) -> OVERRUN4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN4R { bits }
}
#[doc = "Bit 13 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5."]
#[inline]
pub fn overrun5(&self) -> OVERRUN5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN5R { bits }
}
#[doc = "Bit 14 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6."]
#[inline]
pub fn overrun6(&self) -> OVERRUN6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN6R { bits }
}
#[doc = "Bit 15 - This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7."]
#[inline]
pub fn overrun7(&self) -> OVERRUN7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
OVERRUN7R { bits }
}
#[doc = "Bit 16 - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."]
#[inline]
pub fn adint(&self) -> ADINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ADINTR { bits }
}
}
}
#[doc = "ADC trim register."]
pub struct TRM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC trim register."]
pub mod trm {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TRM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADCOFFSR {
bits: u8,
}
impl ADCOFFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TRIMR {
bits: u8,
}
impl TRIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ADCOFFSW<'a> {
w: &'a mut W,
}
impl<'a> _ADCOFFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TRIMW<'a> {
w: &'a mut W,
}
impl<'a> _TRIMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 4:7 - Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user."]
#[inline]
pub fn adcoffs(&self) -> ADCOFFSR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ADCOFFSR { bits }
}
#[doc = "Bits 8:11 - written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write."]
#[inline]
pub fn trim(&self) -> TRIMR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TRIMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 4:7 - Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user."]
#[inline]
pub fn adcoffs(&mut self) -> _ADCOFFSW {
_ADCOFFSW { w: self }
}
#[doc = "Bits 8:11 - written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write."]
#[inline]
pub fn trim(&mut self) -> _TRIMW {
_TRIMW { w: self }
}
}
}
}
#[doc = "CAN acceptance filter RAM"]
pub struct CANAFRAM {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CANAFRAM {}
impl CANAFRAM {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const canafram::RegisterBlock {
0x4003_8000 as *const _
}
}
impl Deref for CANAFRAM {
type Target = canafram::RegisterBlock;
fn deref(&self) -> &canafram::RegisterBlock {
unsafe { &*CANAFRAM::ptr() }
}
}
#[doc = "CAN acceptance filter RAM"]
pub mod canafram {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - CAN AF ram access register"]
pub mask: [MASK; 512],
}
#[doc = "CAN AF ram access register"]
pub struct MASK {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "CAN AF ram access register"]
pub mod mask {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MASK {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MASKR {
bits: u32,
}
impl MASKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MASKW<'a> {
w: &'a mut W,
}
impl<'a> _MASKW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - CAN AF RAM mask"]
#[inline]
pub fn mask(&self) -> MASKR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MASKR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - CAN AF RAM mask"]
#[inline]
pub fn mask(&mut self) -> _MASKW {
_MASKW { w: self }
}
}
}
}
#[doc = "CAN controller acceptance filter"]
pub struct CANAF {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CANAF {}
impl CANAF {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const canaf::RegisterBlock {
0x4003_c000 as *const _
}
}
impl Deref for CANAF {
type Target = canaf::RegisterBlock;
fn deref(&self) -> &canaf::RegisterBlock {
unsafe { &*CANAF::ptr() }
}
}
#[doc = "CAN controller acceptance filter"]
pub mod canaf {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Acceptance Filter Register"]
pub afmr: AFMR,
#[doc = "0x04 - Standard Frame Individual Start Address Register"]
pub sff_sa: SFF_SA,
#[doc = "0x08 - Standard Frame Group Start Address Register"]
pub sff_grp_sa: SFF_GRP_SA,
#[doc = "0x0c - Extended Frame Start Address Register"]
pub eff_sa: EFF_SA,
#[doc = "0x10 - Extended Frame Group Start Address Register"]
pub eff_grp_sa: EFF_GRP_SA,
#[doc = "0x14 - End of AF Tables register"]
pub endoftable: ENDOFTABLE,
#[doc = "0x18 - LUT Error Address register"]
pub luterrad: LUTERRAD,
#[doc = "0x1c - LUT Error Register"]
pub luterr: LUTERR,
#[doc = "0x20 - FullCAN interrupt enable register"]
pub fcanie: FCANIE,
#[doc = "0x24 - FullCAN interrupt and capture register0"]
pub fcanic0: FCANIC0,
#[doc = "0x28 - FullCAN interrupt and capture register1"]
pub fcanic1: FCANIC1,
}
#[doc = "Acceptance Filter Register"]
pub struct AFMR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Acceptance Filter Register"]
pub mod afmr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AFMR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ACCOFFR {
bits: bool,
}
impl ACCOFFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ACCBPR {
bits: bool,
}
impl ACCBPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `EFCAN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EFCANR {
#[doc = "Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers."]
SOFTWARE_MUST_READ_A,
#[doc = "The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576."]
THE_ACCEPTANCE_FILTE,
}
impl EFCANR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EFCANR::SOFTWARE_MUST_READ_A => false,
EFCANR::THE_ACCEPTANCE_FILTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EFCANR {
match value {
false => EFCANR::SOFTWARE_MUST_READ_A,
true => EFCANR::THE_ACCEPTANCE_FILTE,
}
}
#[doc = "Checks if the value of the field is `SOFTWARE_MUST_READ_A`"]
#[inline]
pub fn is_software_must_read_a(&self) -> bool {
*self == EFCANR::SOFTWARE_MUST_READ_A
}
#[doc = "Checks if the value of the field is `THE_ACCEPTANCE_FILTE`"]
#[inline]
pub fn is_the_acceptance_filte(&self) -> bool {
*self == EFCANR::THE_ACCEPTANCE_FILTE
}
}
#[doc = r" Proxy"]
pub struct _ACCOFFW<'a> {
w: &'a mut W,
}
impl<'a> _ACCOFFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACCBPW<'a> {
w: &'a mut W,
}
impl<'a> _ACCBPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EFCAN`"]
pub enum EFCANW {
#[doc = "Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers."]
SOFTWARE_MUST_READ_A,
#[doc = "The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576."]
THE_ACCEPTANCE_FILTE,
}
impl EFCANW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EFCANW::SOFTWARE_MUST_READ_A => false,
EFCANW::THE_ACCEPTANCE_FILTE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EFCANW<'a> {
w: &'a mut W,
}
impl<'a> _EFCANW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EFCANW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers."]
#[inline]
pub fn software_must_read_a(self) -> &'a mut W {
self.variant(EFCANW::SOFTWARE_MUST_READ_A)
}
#[doc = "The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576."]
#[inline]
pub fn the_acceptance_filte(self) -> &'a mut W {
self.variant(EFCANW::THE_ACCEPTANCE_FILTE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored."]
#[inline]
pub fn accoff(&self) -> ACCOFFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACCOFFR { bits }
}
#[doc = "Bit 1 - All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers."]
#[inline]
pub fn accbp(&self) -> ACCBPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACCBPR { bits }
}
#[doc = "Bit 2 - FullCAN mode"]
#[inline]
pub fn efcan(&self) -> EFCANR {
EFCANR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored."]
#[inline]
pub fn accoff(&mut self) -> _ACCOFFW {
_ACCOFFW { w: self }
}
#[doc = "Bit 1 - All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers."]
#[inline]
pub fn accbp(&mut self) -> _ACCBPW {
_ACCBPW { w: self }
}
#[doc = "Bit 2 - FullCAN mode"]
#[inline]
pub fn efcan(&mut self) -> _EFCANW {
_EFCANW { w: self }
}
}
}
#[doc = "Standard Frame Individual Start Address Register"]
pub struct SFF_SA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Standard Frame Individual Start Address Register"]
pub mod sff_sa {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SFF_SA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SFF_SAR {
bits: u16,
}
impl SFF_SAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SFF_SAW<'a> {
w: &'a mut W,
}
impl<'a> _SFF_SAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:10 - The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM."]
#[inline]
pub fn sff_sa(&self) -> SFF_SAR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u16
};
SFF_SAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:10 - The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM."]
#[inline]
pub fn sff_sa(&mut self) -> _SFF_SAW {
_SFF_SAW { w: self }
}
}
}
#[doc = "Standard Frame Group Start Address Register"]
pub struct SFF_GRP_SA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Standard Frame Group Start Address Register"]
pub mod sff_grp_sa {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SFF_GRP_SA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SFF_GRP_SAR {
bits: u16,
}
impl SFF_GRP_SAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SFF_GRP_SAW<'a> {
w: &'a mut W,
}
impl<'a> _SFF_GRP_SAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:11 - The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register."]
#[inline]
pub fn sff_grp_sa(&self) -> SFF_GRP_SAR {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u16
};
SFF_GRP_SAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:11 - The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register."]
#[inline]
pub fn sff_grp_sa(&mut self) -> _SFF_GRP_SAW {
_SFF_GRP_SAW { w: self }
}
}
}
#[doc = "Extended Frame Start Address Register"]
pub struct EFF_SA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Extended Frame Start Address Register"]
pub mod eff_sa {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EFF_SA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EFF_SAR {
bits: u16,
}
impl EFF_SAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _EFF_SAW<'a> {
w: &'a mut W,
}
impl<'a> _EFF_SAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:10 - The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register."]
#[inline]
pub fn eff_sa(&self) -> EFF_SAR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u16
};
EFF_SAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:10 - The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register."]
#[inline]
pub fn eff_sa(&mut self) -> _EFF_SAW {
_EFF_SAW { w: self }
}
}
}
#[doc = "Extended Frame Group Start Address Register"]
pub struct EFF_GRP_SA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Extended Frame Group Start Address Register"]
pub mod eff_grp_sa {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EFF_GRP_SA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EFF_GRP_SAR {
bits: u16,
}
impl EFF_GRP_SAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _EFF_GRP_SAW<'a> {
w: &'a mut W,
}
impl<'a> _EFF_GRP_SAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:11 - The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register."]
#[inline]
pub fn eff_grp_sa(&self) -> EFF_GRP_SAR {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u16
};
EFF_GRP_SAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:11 - The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register."]
#[inline]
pub fn eff_grp_sa(&mut self) -> _EFF_GRP_SAW {
_EFF_GRP_SAW { w: self }
}
}
}
#[doc = "End of AF Tables register"]
pub struct ENDOFTABLE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "End of AF Tables register"]
pub mod endoftable {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::ENDOFTABLE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ENDOFTABLER {
bits: u16,
}
impl ENDOFTABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ENDOFTABLEW<'a> {
w: &'a mut W,
}
impl<'a> _ENDOFTABLEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:11 - The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table."]
#[inline]
pub fn endoftable(&self) -> ENDOFTABLER {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u16
};
ENDOFTABLER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:11 - The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table."]
#[inline]
pub fn endoftable(&mut self) -> _ENDOFTABLEW {
_ENDOFTABLEW { w: self }
}
}
}
#[doc = "LUT Error Address register"]
pub struct LUTERRAD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "LUT Error Address register"]
pub mod luterrad {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::LUTERRAD {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct LUTERRADR {
bits: u16,
}
impl LUTERRADR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:10 - It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables."]
#[inline]
pub fn luterrad(&self) -> LUTERRADR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u16
};
LUTERRADR { bits }
}
}
}
#[doc = "LUT Error Register"]
pub struct LUTERR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "LUT Error Register"]
pub mod luterr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::LUTERR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct LUTERRR {
bits: bool,
}
impl LUTERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC."]
#[inline]
pub fn luterr(&self) -> LUTERRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LUTERRR { bits }
}
}
}
#[doc = "FullCAN interrupt enable register"]
pub struct FCANIE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "FullCAN interrupt enable register"]
pub mod fcanie {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FCANIE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FCANIER {
bits: bool,
}
impl FCANIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _FCANIEW<'a> {
w: &'a mut W,
}
impl<'a> _FCANIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Global FullCAN Interrupt Enable. When 1, this interrupt is enabled."]
#[inline]
pub fn fcanie(&self) -> FCANIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FCANIER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Global FullCAN Interrupt Enable. When 1, this interrupt is enabled."]
#[inline]
pub fn fcanie(&mut self) -> _FCANIEW {
_FCANIEW { w: self }
}
}
}
#[doc = "FullCAN interrupt and capture register0"]
pub struct FCANIC0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "FullCAN interrupt and capture register0"]
pub mod fcanic0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FCANIC0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct INTPNDR {
bits: u32,
}
impl INTPNDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _INTPNDW<'a> {
w: &'a mut W,
}
impl<'a> _INTPNDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31."]
#[inline]
pub fn intpnd(&self) -> INTPNDR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
INTPNDR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31."]
#[inline]
pub fn intpnd(&mut self) -> _INTPNDW {
_INTPNDW { w: self }
}
}
}
#[doc = "FullCAN interrupt and capture register1"]
pub struct FCANIC1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "FullCAN interrupt and capture register1"]
pub mod fcanic1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FCANIC1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct INTPND32R {
bits: u32,
}
impl INTPND32R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _INTPND32W<'a> {
w: &'a mut W,
}
impl<'a> _INTPND32W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63."]
#[inline]
pub fn int_pnd32(&self) -> INTPND32R {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
INTPND32R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63."]
#[inline]
pub fn int_pnd32(&mut self) -> _INTPND32W {
_INTPND32W { w: self }
}
}
}
}
#[doc = "Central CAN controller"]
pub struct CCAN {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CCAN {}
impl CCAN {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const ccan::RegisterBlock {
0x4004_0000 as *const _
}
}
impl Deref for CCAN {
type Target = ccan::RegisterBlock;
fn deref(&self) -> &ccan::RegisterBlock {
unsafe { &*CCAN::ptr() }
}
}
#[doc = "Central CAN controller"]
pub mod ccan {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - CAN Central Transmit Status Register"]
pub txsr: TXSR,
#[doc = "0x04 - CAN Central Receive Status Register"]
pub rxsr: RXSR,
#[doc = "0x08 - CAN Central Miscellaneous Register"]
pub msr: MSR,
}
#[doc = "CAN Central Transmit Status Register"]
pub struct TXSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "CAN Central Transmit Status Register"]
pub mod txsr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::TXSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct TS1R {
bits: bool,
}
impl TS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TS2R {
bits: bool,
}
impl TS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TBS1R {
bits: bool,
}
impl TBS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TBS2R {
bits: bool,
}
impl TBS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TCS1R {
bits: bool,
}
impl TCS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TCS2R {
bits: bool,
}
impl TCS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)."]
#[inline]
pub fn ts1(&self) -> TS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TS1R { bits }
}
#[doc = "Bit 1 - When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)"]
#[inline]
pub fn ts2(&self) -> TS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TS2R { bits }
}
#[doc = "Bit 8 - When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)."]
#[inline]
pub fn tbs1(&self) -> TBS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TBS1R { bits }
}
#[doc = "Bit 9 - When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)."]
#[inline]
pub fn tbs2(&self) -> TBS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TBS2R { bits }
}
#[doc = "Bit 16 - When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)."]
#[inline]
pub fn tcs1(&self) -> TCS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TCS1R { bits }
}
#[doc = "Bit 17 - When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)."]
#[inline]
pub fn tcs2(&self) -> TCS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TCS2R { bits }
}
}
}
#[doc = "CAN Central Receive Status Register"]
pub struct RXSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "CAN Central Receive Status Register"]
pub mod rxsr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RXSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RS1R {
bits: bool,
}
impl RS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RS2R {
bits: bool,
}
impl RS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RB1R {
bits: bool,
}
impl RB1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RB2R {
bits: bool,
}
impl RB2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DOS1R {
bits: bool,
}
impl DOS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DOS2R {
bits: bool,
}
impl DOS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, CAN1 is receiving a message (same as RS in CAN1GSR)."]
#[inline]
pub fn rs1(&self) -> RS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RS1R { bits }
}
#[doc = "Bit 1 - When 1, CAN2 is receiving a message (same as RS in CAN2GSR)."]
#[inline]
pub fn rs2(&self) -> RS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RS2R { bits }
}
#[doc = "Bit 8 - When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)."]
#[inline]
pub fn rb1(&self) -> RB1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RB1R { bits }
}
#[doc = "Bit 9 - When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)."]
#[inline]
pub fn rb2(&self) -> RB2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RB2R { bits }
}
#[doc = "Bit 16 - When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)."]
#[inline]
pub fn dos1(&self) -> DOS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DOS1R { bits }
}
#[doc = "Bit 17 - When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)."]
#[inline]
pub fn dos2(&self) -> DOS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DOS2R { bits }
}
}
}
#[doc = "CAN Central Miscellaneous Register"]
pub struct MSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "CAN Central Miscellaneous Register"]
pub mod msr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::MSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct E1R {
bits: bool,
}
impl E1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct E2R {
bits: bool,
}
impl E2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BS1R {
bits: bool,
}
impl BS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BS2R {
bits: bool,
}
impl BS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)"]
#[inline]
pub fn e1(&self) -> E1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
E1R { bits }
}
#[doc = "Bit 1 - When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)"]
#[inline]
pub fn e2(&self) -> E2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
E2R { bits }
}
#[doc = "Bit 8 - When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)."]
#[inline]
pub fn bs1(&self) -> BS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BS1R { bits }
}
#[doc = "Bit 9 - When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)."]
#[inline]
pub fn bs2(&self) -> BS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BS2R { bits }
}
}
}
}
#[doc = "CAN1 controller"]
pub struct CAN1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CAN1 {}
impl CAN1 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const can1::RegisterBlock {
0x4004_4000 as *const _
}
}
impl Deref for CAN1 {
type Target = can1::RegisterBlock;
fn deref(&self) -> &can1::RegisterBlock {
unsafe { &*CAN1::ptr() }
}
}
#[doc = "CAN1 controller"]
pub mod can1 {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Controls the operating mode of the CAN Controller."]
pub mod_: MOD,
#[doc = "0x04 - Command bits that affect the state of the CAN Controller"]
pub cmr: CMR,
#[doc = "0x08 - Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1."]
pub gsr: GSR,
#[doc = "0x0c - Interrupt status, Arbitration Lost Capture, Error Code Capture"]
pub icr: ICR,
#[doc = "0x10 - Interrupt Enable"]
pub ier: IER,
#[doc = "0x14 - Bus Timing. Can only be written when RM in CANMOD is 1."]
pub btr: BTR,
#[doc = "0x18 - Error Warning Limit. Can only be written when RM in CANMOD is 1."]
pub ewl: EWL,
#[doc = "0x1c - Status Register"]
pub sr: SR,
#[doc = "0x20 - Receive frame status. Can only be written when RM in CANMOD is 1."]
pub rfs: RFS,
#[doc = "0x24 - Received Identifier. Can only be written when RM in CANMOD is 1."]
pub rid: RID,
#[doc = "0x28 - Received data bytes 1-4. Can only be written when RM in CANMOD is 1."]
pub rda: RDA,
#[doc = "0x2c - Received data bytes 5-8. Can only be written when RM in CANMOD is 1."]
pub rdb: RDB,
#[doc = "0x30 - Transmit frame info (Tx Buffer )"]
pub tfi1: TFI,
#[doc = "0x34 - Transmit Identifier (Tx Buffer)"]
pub tid1: TID,
#[doc = "0x38 - Transmit data bytes 1-4 (Tx Buffer)"]
pub tda1: TDA,
#[doc = "0x3c - Transmit data bytes 5-8 (Tx Buffer )"]
pub tdb1: TDB,
#[doc = "0x40 - Transmit frame info (Tx Buffer )"]
pub tfi2: TFI,
#[doc = "0x44 - Transmit Identifier (Tx Buffer)"]
pub tid2: TID,
#[doc = "0x48 - Transmit data bytes 1-4 (Tx Buffer)"]
pub tda2: TDA,
#[doc = "0x4c - Transmit data bytes 5-8 (Tx Buffer )"]
pub tdb2: TDB,
#[doc = "0x50 - Transmit frame info (Tx Buffer )"]
pub tfi3: TFI,
#[doc = "0x54 - Transmit Identifier (Tx Buffer)"]
pub tid3: TID,
#[doc = "0x58 - Transmit data bytes 1-4 (Tx Buffer)"]
pub tda3: TDA,
#[doc = "0x5c - Transmit data bytes 5-8 (Tx Buffer )"]
pub tdb3: TDB,
}
#[doc = "Controls the operating mode of the CAN Controller."]
pub struct MOD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Controls the operating mode of the CAN Controller."]
pub mod mod_ {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MOD {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RMR {
#[doc = "Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written."]
NORMAL_THE_CAN_CONTR,
#[doc = "Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted."]
RESET_CAN_OPERATION,
}
impl RMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RMR::NORMAL_THE_CAN_CONTR => false,
RMR::RESET_CAN_OPERATION => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RMR {
match value {
false => RMR::NORMAL_THE_CAN_CONTR,
true => RMR::RESET_CAN_OPERATION,
}
}
#[doc = "Checks if the value of the field is `NORMAL_THE_CAN_CONTR`"]
#[inline]
pub fn is_normal_the_can_contr(&self) -> bool {
*self == RMR::NORMAL_THE_CAN_CONTR
}
#[doc = "Checks if the value of the field is `RESET_CAN_OPERATION`"]
#[inline]
pub fn is_reset_can_operation(&self) -> bool {
*self == RMR::RESET_CAN_OPERATION
}
}
#[doc = "Possible values of the field `LOM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LOMR {
#[doc = "Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value."]
NORMAL_THE_CAN_CONT,
#[doc = "Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging."]
LISTEN_ONLY_THE_CON,
}
impl LOMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LOMR::NORMAL_THE_CAN_CONT => false,
LOMR::LISTEN_ONLY_THE_CON => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LOMR {
match value {
false => LOMR::NORMAL_THE_CAN_CONT,
true => LOMR::LISTEN_ONLY_THE_CON,
}
}
#[doc = "Checks if the value of the field is `NORMAL_THE_CAN_CONT`"]
#[inline]
pub fn is_normal_the_can_cont(&self) -> bool {
*self == LOMR::NORMAL_THE_CAN_CONT
}
#[doc = "Checks if the value of the field is `LISTEN_ONLY_THE_CON`"]
#[inline]
pub fn is_listen_only_the_con(&self) -> bool {
*self == LOMR::LISTEN_ONLY_THE_CON
}
}
#[doc = "Possible values of the field `STM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum STMR {
#[doc = "Normal. A transmitted message must be acknowledged to be considered successful."]
NORMAL_A_TRANSMITTE,
#[doc = "Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR."]
SELF_TEST_THE_CONTR,
}
impl STMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
STMR::NORMAL_A_TRANSMITTE => false,
STMR::SELF_TEST_THE_CONTR => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> STMR {
match value {
false => STMR::NORMAL_A_TRANSMITTE,
true => STMR::SELF_TEST_THE_CONTR,
}
}
#[doc = "Checks if the value of the field is `NORMAL_A_TRANSMITTE`"]
#[inline]
pub fn is_normal_a_transmitte(&self) -> bool {
*self == STMR::NORMAL_A_TRANSMITTE
}
#[doc = "Checks if the value of the field is `SELF_TEST_THE_CONTR`"]
#[inline]
pub fn is_self_test_the_contr(&self) -> bool {
*self == STMR::SELF_TEST_THE_CONTR
}
}
#[doc = "Possible values of the field `TPM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TPMR {
#[doc = "CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier."]
CAN_ID_THE_TRANSMIT,
#[doc = "Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer."]
LOCAL_PRIORITY_THE_,
}
impl TPMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TPMR::CAN_ID_THE_TRANSMIT => false,
TPMR::LOCAL_PRIORITY_THE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TPMR {
match value {
false => TPMR::CAN_ID_THE_TRANSMIT,
true => TPMR::LOCAL_PRIORITY_THE_,
}
}
#[doc = "Checks if the value of the field is `CAN_ID_THE_TRANSMIT`"]
#[inline]
pub fn is_can_id_the_transmit(&self) -> bool {
*self == TPMR::CAN_ID_THE_TRANSMIT
}
#[doc = "Checks if the value of the field is `LOCAL_PRIORITY_THE_`"]
#[inline]
pub fn is_local_priority_the_(&self) -> bool {
*self == TPMR::LOCAL_PRIORITY_THE_
}
}
#[doc = "Possible values of the field `SM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SMR {
#[doc = "Wake-up. Normal operation."]
WAKE_UP_NORMAL_OPER,
#[doc = "Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565."]
SLEEP_THE_CAN_CONTR,
}
impl SMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SMR::WAKE_UP_NORMAL_OPER => false,
SMR::SLEEP_THE_CAN_CONTR => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SMR {
match value {
false => SMR::WAKE_UP_NORMAL_OPER,
true => SMR::SLEEP_THE_CAN_CONTR,
}
}
#[doc = "Checks if the value of the field is `WAKE_UP_NORMAL_OPER`"]
#[inline]
pub fn is_wake_up_normal_oper(&self) -> bool {
*self == SMR::WAKE_UP_NORMAL_OPER
}
#[doc = "Checks if the value of the field is `SLEEP_THE_CAN_CONTR`"]
#[inline]
pub fn is_sleep_the_can_contr(&self) -> bool {
*self == SMR::SLEEP_THE_CAN_CONTR
}
}
#[doc = "Possible values of the field `RPM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RPMR {
#[doc = "Low active. RD input is active Low (dominant bit = 0)."]
LOW_ACTIVE_RD_INPUT,
#[doc = "High active. RD input is active High (dominant bit = 1) -- reverse polarity."]
HIGH_ACTIVE_RD_INPU,
}
impl RPMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RPMR::LOW_ACTIVE_RD_INPUT => false,
RPMR::HIGH_ACTIVE_RD_INPU => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RPMR {
match value {
false => RPMR::LOW_ACTIVE_RD_INPUT,
true => RPMR::HIGH_ACTIVE_RD_INPU,
}
}
#[doc = "Checks if the value of the field is `LOW_ACTIVE_RD_INPUT`"]
#[inline]
pub fn is_low_active_rd_input(&self) -> bool {
*self == RPMR::LOW_ACTIVE_RD_INPUT
}
#[doc = "Checks if the value of the field is `HIGH_ACTIVE_RD_INPU`"]
#[inline]
pub fn is_high_active_rd_inpu(&self) -> bool {
*self == RPMR::HIGH_ACTIVE_RD_INPU
}
}
#[doc = "Possible values of the field `TM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TMR {
#[doc = "Disabled. Normal operation."]
DISABLED_NORMAL_OPE,
#[doc = "Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock."]
ENABLED_THE_TD_PIN_,
}
impl TMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TMR::DISABLED_NORMAL_OPE => false,
TMR::ENABLED_THE_TD_PIN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TMR {
match value {
false => TMR::DISABLED_NORMAL_OPE,
true => TMR::ENABLED_THE_TD_PIN_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_NORMAL_OPE`"]
#[inline]
pub fn is_disabled_normal_ope(&self) -> bool {
*self == TMR::DISABLED_NORMAL_OPE
}
#[doc = "Checks if the value of the field is `ENABLED_THE_TD_PIN_`"]
#[inline]
pub fn is_enabled_the_td_pin_(&self) -> bool {
*self == TMR::ENABLED_THE_TD_PIN_
}
}
#[doc = "Values that can be written to the field `RM`"]
pub enum RMW {
#[doc = "Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written."]
NORMAL_THE_CAN_CONTR,
#[doc = "Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted."]
RESET_CAN_OPERATION,
}
impl RMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RMW::NORMAL_THE_CAN_CONTR => false,
RMW::RESET_CAN_OPERATION => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RMW<'a> {
w: &'a mut W,
}
impl<'a> _RMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written."]
#[inline]
pub fn normal_the_can_contr(self) -> &'a mut W {
self.variant(RMW::NORMAL_THE_CAN_CONTR)
}
#[doc = "Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted."]
#[inline]
pub fn reset_can_operation(self) -> &'a mut W {
self.variant(RMW::RESET_CAN_OPERATION)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LOM`"]
pub enum LOMW {
#[doc = "Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value."]
NORMAL_THE_CAN_CONT,
#[doc = "Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging."]
LISTEN_ONLY_THE_CON,
}
impl LOMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LOMW::NORMAL_THE_CAN_CONT => false,
LOMW::LISTEN_ONLY_THE_CON => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LOMW<'a> {
w: &'a mut W,
}
impl<'a> _LOMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LOMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value."]
#[inline]
pub fn normal_the_can_cont(self) -> &'a mut W {
self.variant(LOMW::NORMAL_THE_CAN_CONT)
}
#[doc = "Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging."]
#[inline]
pub fn listen_only_the_con(self) -> &'a mut W {
self.variant(LOMW::LISTEN_ONLY_THE_CON)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `STM`"]
pub enum STMW {
#[doc = "Normal. A transmitted message must be acknowledged to be considered successful."]
NORMAL_A_TRANSMITTE,
#[doc = "Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR."]
SELF_TEST_THE_CONTR,
}
impl STMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
STMW::NORMAL_A_TRANSMITTE => false,
STMW::SELF_TEST_THE_CONTR => true,
}
}
}
#[doc = r" Proxy"]
pub struct _STMW<'a> {
w: &'a mut W,
}
impl<'a> _STMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Normal. A transmitted message must be acknowledged to be considered successful."]
#[inline]
pub fn normal_a_transmitte(self) -> &'a mut W {
self.variant(STMW::NORMAL_A_TRANSMITTE)
}
#[doc = "Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR."]
#[inline]
pub fn self_test_the_contr(self) -> &'a mut W {
self.variant(STMW::SELF_TEST_THE_CONTR)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TPM`"]
pub enum TPMW {
#[doc = "CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier."]
CAN_ID_THE_TRANSMIT,
#[doc = "Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer."]
LOCAL_PRIORITY_THE_,
}
impl TPMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TPMW::CAN_ID_THE_TRANSMIT => false,
TPMW::LOCAL_PRIORITY_THE_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TPMW<'a> {
w: &'a mut W,
}
impl<'a> _TPMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TPMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier."]
#[inline]
pub fn can_id_the_transmit(self) -> &'a mut W {
self.variant(TPMW::CAN_ID_THE_TRANSMIT)
}
#[doc = "Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer."]
#[inline]
pub fn local_priority_the_(self) -> &'a mut W {
self.variant(TPMW::LOCAL_PRIORITY_THE_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SM`"]
pub enum SMW {
#[doc = "Wake-up. Normal operation."]
WAKE_UP_NORMAL_OPER,
#[doc = "Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565."]
SLEEP_THE_CAN_CONTR,
}
impl SMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SMW::WAKE_UP_NORMAL_OPER => false,
SMW::SLEEP_THE_CAN_CONTR => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SMW<'a> {
w: &'a mut W,
}
impl<'a> _SMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Wake-up. Normal operation."]
#[inline]
pub fn wake_up_normal_oper(self) -> &'a mut W {
self.variant(SMW::WAKE_UP_NORMAL_OPER)
}
#[doc = "Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565."]
#[inline]
pub fn sleep_the_can_contr(self) -> &'a mut W {
self.variant(SMW::SLEEP_THE_CAN_CONTR)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RPM`"]
pub enum RPMW {
#[doc = "Low active. RD input is active Low (dominant bit = 0)."]
LOW_ACTIVE_RD_INPUT,
#[doc = "High active. RD input is active High (dominant bit = 1) -- reverse polarity."]
HIGH_ACTIVE_RD_INPU,
}
impl RPMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RPMW::LOW_ACTIVE_RD_INPUT => false,
RPMW::HIGH_ACTIVE_RD_INPU => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RPMW<'a> {
w: &'a mut W,
}
impl<'a> _RPMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RPMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Low active. RD input is active Low (dominant bit = 0)."]
#[inline]
pub fn low_active_rd_input(self) -> &'a mut W {
self.variant(RPMW::LOW_ACTIVE_RD_INPUT)
}
#[doc = "High active. RD input is active High (dominant bit = 1) -- reverse polarity."]
#[inline]
pub fn high_active_rd_inpu(self) -> &'a mut W {
self.variant(RPMW::HIGH_ACTIVE_RD_INPU)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TM`"]
pub enum TMW {
#[doc = "Disabled. Normal operation."]
DISABLED_NORMAL_OPE,
#[doc = "Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock."]
ENABLED_THE_TD_PIN_,
}
impl TMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TMW::DISABLED_NORMAL_OPE => false,
TMW::ENABLED_THE_TD_PIN_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TMW<'a> {
w: &'a mut W,
}
impl<'a> _TMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. Normal operation."]
#[inline]
pub fn disabled_normal_ope(self) -> &'a mut W {
self.variant(TMW::DISABLED_NORMAL_OPE)
}
#[doc = "Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock."]
#[inline]
pub fn enabled_the_td_pin_(self) -> &'a mut W {
self.variant(TMW::ENABLED_THE_TD_PIN_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Reset Mode."]
#[inline]
pub fn rm(&self) -> RMR {
RMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Listen Only Mode."]
#[inline]
pub fn lom(&self) -> LOMR {
LOMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Self Test Mode."]
#[inline]
pub fn stm(&self) -> STMR {
STMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Transmit Priority Mode."]
#[inline]
pub fn tpm(&self) -> TPMR {
TPMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Sleep Mode."]
#[inline]
pub fn sm(&self) -> SMR {
SMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Receive Polarity Mode."]
#[inline]
pub fn rpm(&self) -> RPMR {
RPMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Test Mode."]
#[inline]
pub fn tm(&self) -> TMR {
TMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Reset Mode."]
#[inline]
pub fn rm(&mut self) -> _RMW {
_RMW { w: self }
}
#[doc = "Bit 1 - Listen Only Mode."]
#[inline]
pub fn lom(&mut self) -> _LOMW {
_LOMW { w: self }
}
#[doc = "Bit 2 - Self Test Mode."]
#[inline]
pub fn stm(&mut self) -> _STMW {
_STMW { w: self }
}
#[doc = "Bit 3 - Transmit Priority Mode."]
#[inline]
pub fn tpm(&mut self) -> _TPMW {
_TPMW { w: self }
}
#[doc = "Bit 4 - Sleep Mode."]
#[inline]
pub fn sm(&mut self) -> _SMW {
_SMW { w: self }
}
#[doc = "Bit 5 - Receive Polarity Mode."]
#[inline]
pub fn rpm(&mut self) -> _RPMW {
_RPMW { w: self }
}
#[doc = "Bit 7 - Test Mode."]
#[inline]
pub fn tm(&mut self) -> _TMW {
_TMW { w: self }
}
}
}
#[doc = "Command bits that affect the state of the CAN Controller"]
pub struct CMR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Command bits that affect the state of the CAN Controller"]
pub mod cmr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CMR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `TR`"]
pub enum TRW {
#[doc = "Absent.No transmission request."]
ABSENT_NO_TRANSMISSI,
#[doc = "Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))"]
PRESENT_THE_MESSAGE,
}
impl TRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TRW::ABSENT_NO_TRANSMISSI => false,
TRW::PRESENT_THE_MESSAGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TRW<'a> {
w: &'a mut W,
}
impl<'a> _TRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Absent.No transmission request."]
#[inline]
pub fn absent_no_transmissi(self) -> &'a mut W {
self.variant(TRW::ABSENT_NO_TRANSMISSI)
}
#[doc = "Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))"]
#[inline]
pub fn present_the_message(self) -> &'a mut W {
self.variant(TRW::PRESENT_THE_MESSAGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AT`"]
pub enum ATW {
#[doc = "No action. Do not abort the transmission."]
NO_ACTION_DO_NOT_AB,
#[doc = "Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled."]
PRESENT_IF_NOT_ALRE,
}
impl ATW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ATW::NO_ACTION_DO_NOT_AB => false,
ATW::PRESENT_IF_NOT_ALRE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ATW<'a> {
w: &'a mut W,
}
impl<'a> _ATW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ATW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No action. Do not abort the transmission."]
#[inline]
pub fn no_action_do_not_ab(self) -> &'a mut W {
self.variant(ATW::NO_ACTION_DO_NOT_AB)
}
#[doc = "Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled."]
#[inline]
pub fn present_if_not_alre(self) -> &'a mut W {
self.variant(ATW::PRESENT_IF_NOT_ALRE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RRB`"]
pub enum RRBW {
#[doc = "No action. Do not release the receive buffer."]
NO_ACTION_DO_NOT_RE,
#[doc = "Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)."]
RELEASED_THE_INFORM,
}
impl RRBW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RRBW::NO_ACTION_DO_NOT_RE => false,
RRBW::RELEASED_THE_INFORM => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RRBW<'a> {
w: &'a mut W,
}
impl<'a> _RRBW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RRBW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No action. Do not release the receive buffer."]
#[inline]
pub fn no_action_do_not_re(self) -> &'a mut W {
self.variant(RRBW::NO_ACTION_DO_NOT_RE)
}
#[doc = "Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)."]
#[inline]
pub fn released_the_inform(self) -> &'a mut W {
self.variant(RRBW::RELEASED_THE_INFORM)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CDO`"]
pub enum CDOW {
#[doc = "No action. Do not clear the data overrun bit."]
NO_ACTION_DO_NOT_CL,
#[doc = "Clear. The Data Overrun bit in Status Register(s) is cleared."]
CLEAR_THE_DATA_OVER,
}
impl CDOW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CDOW::NO_ACTION_DO_NOT_CL => false,
CDOW::CLEAR_THE_DATA_OVER => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CDOW<'a> {
w: &'a mut W,
}
impl<'a> _CDOW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CDOW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No action. Do not clear the data overrun bit."]
#[inline]
pub fn no_action_do_not_cl(self) -> &'a mut W {
self.variant(CDOW::NO_ACTION_DO_NOT_CL)
}
#[doc = "Clear. The Data Overrun bit in Status Register(s) is cleared."]
#[inline]
pub fn clear_the_data_over(self) -> &'a mut W {
self.variant(CDOW::CLEAR_THE_DATA_OVER)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SRR`"]
pub enum SRRW {
#[doc = "Absent. No self reception request."]
ABSENT_NO_SELF_RECE,
#[doc = "Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter."]
PRESENT_THE_MESSAGE,
}
impl SRRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SRRW::ABSENT_NO_SELF_RECE => false,
SRRW::PRESENT_THE_MESSAGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SRRW<'a> {
w: &'a mut W,
}
impl<'a> _SRRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SRRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Absent. No self reception request."]
#[inline]
pub fn absent_no_self_rece(self) -> &'a mut W {
self.variant(SRRW::ABSENT_NO_SELF_RECE)
}
#[doc = "Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter."]
#[inline]
pub fn present_the_message(self) -> &'a mut W {
self.variant(SRRW::PRESENT_THE_MESSAGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `STB1`"]
pub enum STB1W {
#[doc = "Not selected. Tx Buffer 1 is not selected for transmission."]
NOT_SELECTED_TX_BUF,
#[doc = "Selected. Tx Buffer 1 is selected for transmission."]
SELECTED_TX_BUFFER_,
}
impl STB1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
STB1W::NOT_SELECTED_TX_BUF => false,
STB1W::SELECTED_TX_BUFFER_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _STB1W<'a> {
w: &'a mut W,
}
impl<'a> _STB1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STB1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not selected. Tx Buffer 1 is not selected for transmission."]
#[inline]
pub fn not_selected_tx_buf(self) -> &'a mut W {
self.variant(STB1W::NOT_SELECTED_TX_BUF)
}
#[doc = "Selected. Tx Buffer 1 is selected for transmission."]
#[inline]
pub fn selected_tx_buffer_(self) -> &'a mut W {
self.variant(STB1W::SELECTED_TX_BUFFER_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `STB2`"]
pub enum STB2W {
#[doc = "Not selected. Tx Buffer 2 is not selected for transmission."]
NOT_SELECTED_TX_BUF,
#[doc = "Selected. Tx Buffer 2 is selected for transmission."]
SELECTED_TX_BUFFER_,
}
impl STB2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
STB2W::NOT_SELECTED_TX_BUF => false,
STB2W::SELECTED_TX_BUFFER_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _STB2W<'a> {
w: &'a mut W,
}
impl<'a> _STB2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STB2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not selected. Tx Buffer 2 is not selected for transmission."]
#[inline]
pub fn not_selected_tx_buf(self) -> &'a mut W {
self.variant(STB2W::NOT_SELECTED_TX_BUF)
}
#[doc = "Selected. Tx Buffer 2 is selected for transmission."]
#[inline]
pub fn selected_tx_buffer_(self) -> &'a mut W {
self.variant(STB2W::SELECTED_TX_BUFFER_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `STB3`"]
pub enum STB3W {
#[doc = "Not selected. Tx Buffer 3 is not selected for transmission."]
NOT_SELECTED_TX_BUF,
#[doc = "Selected. Tx Buffer 3 is selected for transmission."]
SELECTED_TX_BUFFER_,
}
impl STB3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
STB3W::NOT_SELECTED_TX_BUF => false,
STB3W::SELECTED_TX_BUFFER_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _STB3W<'a> {
w: &'a mut W,
}
impl<'a> _STB3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: STB3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not selected. Tx Buffer 3 is not selected for transmission."]
#[inline]
pub fn not_selected_tx_buf(self) -> &'a mut W {
self.variant(STB3W::NOT_SELECTED_TX_BUF)
}
#[doc = "Selected. Tx Buffer 3 is selected for transmission."]
#[inline]
pub fn selected_tx_buffer_(self) -> &'a mut W {
self.variant(STB3W::SELECTED_TX_BUFFER_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Transmission Request."]
#[inline]
pub fn tr(&mut self) -> _TRW {
_TRW { w: self }
}
#[doc = "Bit 1 - Abort Transmission."]
#[inline]
pub fn at(&mut self) -> _ATW {
_ATW { w: self }
}
#[doc = "Bit 2 - Release Receive Buffer."]
#[inline]
pub fn rrb(&mut self) -> _RRBW {
_RRBW { w: self }
}
#[doc = "Bit 3 - Clear Data Overrun."]
#[inline]
pub fn cdo(&mut self) -> _CDOW {
_CDOW { w: self }
}
#[doc = "Bit 4 - Self Reception Request."]
#[inline]
pub fn srr(&mut self) -> _SRRW {
_SRRW { w: self }
}
#[doc = "Bit 5 - Select Tx Buffer 1."]
#[inline]
pub fn stb1(&mut self) -> _STB1W {
_STB1W { w: self }
}
#[doc = "Bit 6 - Select Tx Buffer 2."]
#[inline]
pub fn stb2(&mut self) -> _STB2W {
_STB2W { w: self }
}
#[doc = "Bit 7 - Select Tx Buffer 3."]
#[inline]
pub fn stb3(&mut self) -> _STB3W {
_STB3W { w: self }
}
}
}
#[doc = "Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1."]
pub struct GSR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1."]
pub mod gsr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::GSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `RBS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RBSR {
#[doc = "Empty. No message is available."]
EMPTY_NO_MESSAGE_IS,
#[doc = "Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available."]
FULL_AT_LEAST_ONE_C,
}
impl RBSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RBSR::EMPTY_NO_MESSAGE_IS => false,
RBSR::FULL_AT_LEAST_ONE_C => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RBSR {
match value {
false => RBSR::EMPTY_NO_MESSAGE_IS,
true => RBSR::FULL_AT_LEAST_ONE_C,
}
}
#[doc = "Checks if the value of the field is `EMPTY_NO_MESSAGE_IS`"]
#[inline]
pub fn is_empty_no_message_is(&self) -> bool {
*self == RBSR::EMPTY_NO_MESSAGE_IS
}
#[doc = "Checks if the value of the field is `FULL_AT_LEAST_ONE_C`"]
#[inline]
pub fn is_full_at_least_one_c(&self) -> bool {
*self == RBSR::FULL_AT_LEAST_ONE_C
}
}
#[doc = "Possible values of the field `DOS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DOSR {
#[doc = "Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)."]
ABSENT_NO_DATA_OVER,
#[doc = "Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)."]
OVERRUN_A_MESSAGE_W,
}
impl DOSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DOSR::ABSENT_NO_DATA_OVER => false,
DOSR::OVERRUN_A_MESSAGE_W => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DOSR {
match value {
false => DOSR::ABSENT_NO_DATA_OVER,
true => DOSR::OVERRUN_A_MESSAGE_W,
}
}
#[doc = "Checks if the value of the field is `ABSENT_NO_DATA_OVER`"]
#[inline]
pub fn is_absent_no_data_over(&self) -> bool {
*self == DOSR::ABSENT_NO_DATA_OVER
}
#[doc = "Checks if the value of the field is `OVERRUN_A_MESSAGE_W`"]
#[inline]
pub fn is_overrun_a_message_w(&self) -> bool {
*self == DOSR::OVERRUN_A_MESSAGE_W
}
}
#[doc = "Possible values of the field `TBS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TBSR {
#[doc = "Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)."]
LOCKED_AT_LEAST_ONE,
#[doc = "Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers."]
RELEASED_ALL_THREE_,
}
impl TBSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TBSR::LOCKED_AT_LEAST_ONE => false,
TBSR::RELEASED_ALL_THREE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TBSR {
match value {
false => TBSR::LOCKED_AT_LEAST_ONE,
true => TBSR::RELEASED_ALL_THREE_,
}
}
#[doc = "Checks if the value of the field is `LOCKED_AT_LEAST_ONE`"]
#[inline]
pub fn is_locked_at_least_one(&self) -> bool {
*self == TBSR::LOCKED_AT_LEAST_ONE
}
#[doc = "Checks if the value of the field is `RELEASED_ALL_THREE_`"]
#[inline]
pub fn is_released_all_three_(&self) -> bool {
*self == TBSR::RELEASED_ALL_THREE_
}
}
#[doc = "Possible values of the field `TCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TCSR {
#[doc = "Incomplete. At least one requested transmission has not been successfully completed yet."]
INCOMPLETE_AT_LEAST,
#[doc = "Complete. All requested transmission(s) has (have) been successfully completed."]
COMPLETE_ALL_REQUES,
}
impl TCSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TCSR::INCOMPLETE_AT_LEAST => false,
TCSR::COMPLETE_ALL_REQUES => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TCSR {
match value {
false => TCSR::INCOMPLETE_AT_LEAST,
true => TCSR::COMPLETE_ALL_REQUES,
}
}
#[doc = "Checks if the value of the field is `INCOMPLETE_AT_LEAST`"]
#[inline]
pub fn is_incomplete_at_least(&self) -> bool {
*self == TCSR::INCOMPLETE_AT_LEAST
}
#[doc = "Checks if the value of the field is `COMPLETE_ALL_REQUES`"]
#[inline]
pub fn is_complete_all_reques(&self) -> bool {
*self == TCSR::COMPLETE_ALL_REQUES
}
}
#[doc = "Possible values of the field `RS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RSR {
#[doc = "Idle. The CAN controller is idle."]
IDLE_THE_CAN_CONTRO,
#[doc = "Receive. The CAN controller is receiving a message."]
RECEIVE_THE_CAN_CON,
}
impl RSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RSR::IDLE_THE_CAN_CONTRO => false,
RSR::RECEIVE_THE_CAN_CON => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RSR {
match value {
false => RSR::IDLE_THE_CAN_CONTRO,
true => RSR::RECEIVE_THE_CAN_CON,
}
}
#[doc = "Checks if the value of the field is `IDLE_THE_CAN_CONTRO`"]
#[inline]
pub fn is_idle_the_can_contro(&self) -> bool {
*self == RSR::IDLE_THE_CAN_CONTRO
}
#[doc = "Checks if the value of the field is `RECEIVE_THE_CAN_CON`"]
#[inline]
pub fn is_receive_the_can_con(&self) -> bool {
*self == RSR::RECEIVE_THE_CAN_CON
}
}
#[doc = "Possible values of the field `TS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TSR {
#[doc = "Idle. The CAN controller is idle."]
IDLE_THE_CAN_CONTRO,
#[doc = "Transmit. The CAN controller is sending a message."]
TRANSMIT_THE_CAN_CO,
}
impl TSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TSR::IDLE_THE_CAN_CONTRO => false,
TSR::TRANSMIT_THE_CAN_CO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TSR {
match value {
false => TSR::IDLE_THE_CAN_CONTRO,
true => TSR::TRANSMIT_THE_CAN_CO,
}
}
#[doc = "Checks if the value of the field is `IDLE_THE_CAN_CONTRO`"]
#[inline]
pub fn is_idle_the_can_contro(&self) -> bool {
*self == TSR::IDLE_THE_CAN_CONTRO
}
#[doc = "Checks if the value of the field is `TRANSMIT_THE_CAN_CO`"]
#[inline]
pub fn is_transmit_the_can_co(&self) -> bool {
*self == TSR::TRANSMIT_THE_CAN_CO
}
}
#[doc = "Possible values of the field `ES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ESR {
#[doc = "OK. Both error counters are below the Error Warning Limit."]
OK_BOTH_ERROR_COUNT,
#[doc = "Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register."]
ERROR_ONE_OR_BOTH_O,
}
impl ESR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ESR::OK_BOTH_ERROR_COUNT => false,
ESR::ERROR_ONE_OR_BOTH_O => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ESR {
match value {
false => ESR::OK_BOTH_ERROR_COUNT,
true => ESR::ERROR_ONE_OR_BOTH_O,
}
}
#[doc = "Checks if the value of the field is `OK_BOTH_ERROR_COUNT`"]
#[inline]
pub fn is_ok_both_error_count(&self) -> bool {
*self == ESR::OK_BOTH_ERROR_COUNT
}
#[doc = "Checks if the value of the field is `ERROR_ONE_OR_BOTH_O`"]
#[inline]
pub fn is_error_one_or_both_o(&self) -> bool {
*self == ESR::ERROR_ONE_OR_BOTH_O
}
}
#[doc = "Possible values of the field `BS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BSR {
#[doc = "Bus-on. The CAN Controller is involved in bus activities"]
BUS_ON_THE_CAN_CONT,
#[doc = "Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255."]
BUS_OFF_THE_CAN_CON,
}
impl BSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BSR::BUS_ON_THE_CAN_CONT => false,
BSR::BUS_OFF_THE_CAN_CON => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BSR {
match value {
false => BSR::BUS_ON_THE_CAN_CONT,
true => BSR::BUS_OFF_THE_CAN_CON,
}
}
#[doc = "Checks if the value of the field is `BUS_ON_THE_CAN_CONT`"]
#[inline]
pub fn is_bus_on_the_can_cont(&self) -> bool {
*self == BSR::BUS_ON_THE_CAN_CONT
}
#[doc = "Checks if the value of the field is `BUS_OFF_THE_CAN_CON`"]
#[inline]
pub fn is_bus_off_the_can_con(&self) -> bool {
*self == BSR::BUS_OFF_THE_CAN_CON
}
}
#[doc = r" Value of the field"]
pub struct RXERRR {
bits: u8,
}
impl RXERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TXERRR {
bits: u8,
}
impl TXERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared."]
#[inline]
pub fn rbs(&self) -> RBSR {
RBSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled."]
#[inline]
pub fn dos(&self) -> DOSR {
DOSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Transmit Buffer Status."]
#[inline]
pub fn tbs(&self) -> TBSR {
TBSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully."]
#[inline]
pub fn tcs(&self) -> TCSR {
TCSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."]
#[inline]
pub fn rs(&self) -> RSR {
RSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits."]
#[inline]
pub fn ts(&self) -> TSR {
TSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)."]
#[inline]
pub fn es(&self) -> ESR {
ESR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery."]
#[inline]
pub fn bs(&self) -> BSR {
BSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 16:23 - The current value of the Rx Error Counter (an 8-bit value)."]
#[inline]
pub fn rxerr(&self) -> RXERRR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RXERRR { bits }
}
#[doc = "Bits 24:31 - The current value of the Tx Error Counter (an 8-bit value)."]
#[inline]
pub fn txerr(&self) -> TXERRR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TXERRR { bits }
}
}
}
#[doc = "Interrupt status, Arbitration Lost Capture, Error Code Capture"]
pub struct ICR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt status, Arbitration Lost Capture, Error Code Capture"]
pub mod icr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::ICR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `RI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl RIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RIR::RESET => false,
RIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RIR {
match value {
false => RIR::RESET,
true => RIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == RIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == RIR::SET
}
}
#[doc = "Possible values of the field `TI1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TI1R {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl TI1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TI1R::RESET => false,
TI1R::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TI1R {
match value {
false => TI1R::RESET,
true => TI1R::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == TI1R::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == TI1R::SET
}
}
#[doc = "Possible values of the field `EI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl EIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EIR::RESET => false,
EIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EIR {
match value {
false => EIR::RESET,
true => EIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == EIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == EIR::SET
}
}
#[doc = "Possible values of the field `DOI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DOIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl DOIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DOIR::RESET => false,
DOIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DOIR {
match value {
false => DOIR::RESET,
true => DOIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == DOIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == DOIR::SET
}
}
#[doc = "Possible values of the field `WUI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WUIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl WUIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WUIR::RESET => false,
WUIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WUIR {
match value {
false => WUIR::RESET,
true => WUIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == WUIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == WUIR::SET
}
}
#[doc = "Possible values of the field `EPI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EPIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl EPIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EPIR::RESET => false,
EPIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EPIR {
match value {
false => EPIR::RESET,
true => EPIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == EPIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == EPIR::SET
}
}
#[doc = "Possible values of the field `ALI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ALIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl ALIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ALIR::RESET => false,
ALIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ALIR {
match value {
false => ALIR::RESET,
true => ALIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == ALIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == ALIR::SET
}
}
#[doc = "Possible values of the field `BEI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BEIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl BEIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BEIR::RESET => false,
BEIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BEIR {
match value {
false => BEIR::RESET,
true => BEIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == BEIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == BEIR::SET
}
}
#[doc = "Possible values of the field `IDI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IDIR {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl IDIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IDIR::RESET => false,
IDIR::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IDIR {
match value {
false => IDIR::RESET,
true => IDIR::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == IDIR::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == IDIR::SET
}
}
#[doc = "Possible values of the field `TI2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TI2R {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl TI2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TI2R::RESET => false,
TI2R::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TI2R {
match value {
false => TI2R::RESET,
true => TI2R::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == TI2R::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == TI2R::SET
}
}
#[doc = "Possible values of the field `TI3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TI3R {
#[doc = "Reset"]
RESET,
#[doc = "Set"]
SET,
}
impl TI3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TI3R::RESET => false,
TI3R::SET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TI3R {
match value {
false => TI3R::RESET,
true => TI3R::SET,
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == TI3R::RESET
}
#[doc = "Checks if the value of the field is `SET`"]
#[inline]
pub fn is_set(&self) -> bool {
*self == TI3R::SET
}
}
#[doc = r" Value of the field"]
pub struct ERRBIT4_0R {
bits: u8,
}
impl ERRBIT4_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `ERRDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRDIRR {
#[doc = "Error occurred during transmitting."]
ERROR_OCCURRED_DURING_TRANSMITTING,
#[doc = "Error occurred during receiving."]
ERROR_OCCURRED_DURING_RECEIVING,
}
impl ERRDIRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ERRDIRR::ERROR_OCCURRED_DURING_TRANSMITTING => false,
ERRDIRR::ERROR_OCCURRED_DURING_RECEIVING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ERRDIRR {
match value {
false => ERRDIRR::ERROR_OCCURRED_DURING_TRANSMITTING,
true => ERRDIRR::ERROR_OCCURRED_DURING_RECEIVING,
}
}
#[doc = "Checks if the value of the field is `ERROR_OCCURRED_DURING_TRANSMITTING`"]
#[inline]
pub fn is_error_occurred_during_transmitting(&self) -> bool {
*self == ERRDIRR::ERROR_OCCURRED_DURING_TRANSMITTING
}
#[doc = "Checks if the value of the field is `ERROR_OCCURRED_DURING_RECEIVING`"]
#[inline]
pub fn is_error_occurred_during_receiving(&self) -> bool {
*self == ERRDIRR::ERROR_OCCURRED_DURING_RECEIVING
}
}
#[doc = "Possible values of the field `ERRC1_0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRC1_0R {
#[doc = "Bit error"]
BIT_ERROR,
#[doc = "Form error"]
FORM_ERROR,
#[doc = "Stuff error"]
STUFF_ERROR,
#[doc = "Other error"]
OTHER_ERROR,
}
impl ERRC1_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ERRC1_0R::BIT_ERROR => 0,
ERRC1_0R::FORM_ERROR => 0x01,
ERRC1_0R::STUFF_ERROR => 0x02,
ERRC1_0R::OTHER_ERROR => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ERRC1_0R {
match value {
0 => ERRC1_0R::BIT_ERROR,
1 => ERRC1_0R::FORM_ERROR,
2 => ERRC1_0R::STUFF_ERROR,
3 => ERRC1_0R::OTHER_ERROR,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `BIT_ERROR`"]
#[inline]
pub fn is_bit_error(&self) -> bool {
*self == ERRC1_0R::BIT_ERROR
}
#[doc = "Checks if the value of the field is `FORM_ERROR`"]
#[inline]
pub fn is_form_error(&self) -> bool {
*self == ERRC1_0R::FORM_ERROR
}
#[doc = "Checks if the value of the field is `STUFF_ERROR`"]
#[inline]
pub fn is_stuff_error(&self) -> bool {
*self == ERRC1_0R::STUFF_ERROR
}
#[doc = "Checks if the value of the field is `OTHER_ERROR`"]
#[inline]
pub fn is_other_error(&self) -> bool {
*self == ERRC1_0R::OTHER_ERROR
}
}
#[doc = r" Value of the field"]
pub struct ALCBITR {
bits: u8,
}
impl ALCBITR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared."]
#[inline]
pub fn ri(&self) -> RIR {
RIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1."]
#[inline]
pub fn ti1(&self) -> TI1R {
TI1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change."]
#[inline]
pub fn ei(&self) -> EIR {
EIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1."]
#[inline]
pub fn doi(&self) -> DOIR {
DOIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted."]
#[inline]
pub fn wui(&self) -> WUIR {
WUIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again."]
#[inline]
pub fn epi(&self) -> EPIR {
EPIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver."]
#[inline]
pub fn ali(&self) -> ALIR {
ALIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus."]
#[inline]
pub fn bei(&self) -> BEIR {
BEIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register."]
#[inline]
pub fn idi(&self) -> IDIR {
IDIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1."]
#[inline]
pub fn ti2(&self) -> TI2R {
TI2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1."]
#[inline]
pub fn ti3(&self) -> TI3R {
TI3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 16:20 - Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt."]
#[inline]
pub fn errbit4_0(&self) -> ERRBIT4_0R {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ERRBIT4_0R { bits }
}
#[doc = "Bit 21 - When the CAN controller detects a bus error, the direction of the current bit is captured in this bit."]
#[inline]
pub fn errdir(&self) -> ERRDIRR {
ERRDIRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 22:23 - When the CAN controller detects a bus error, the type of error is captured in this field:"]
#[inline]
pub fn errc1_0(&self) -> ERRC1_0R {
ERRC1_0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:31 - Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again."]
#[inline]
pub fn alcbit(&self) -> ALCBITR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ALCBITR { bits }
}
}
}
#[doc = "Interrupt Enable"]
pub struct IER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable"]
pub mod ier {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RIER {
bits: bool,
}
impl RIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TIE1R {
bits: bool,
}
impl TIE1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EIER {
bits: bool,
}
impl EIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DOIER {
bits: bool,
}
impl DOIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WUIER {
bits: bool,
}
impl WUIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPIER {
bits: bool,
}
impl EPIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ALIER {
bits: bool,
}
impl ALIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BEIER {
bits: bool,
}
impl BEIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IDIER {
bits: bool,
}
impl IDIER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TIE2R {
bits: bool,
}
impl TIE2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TIE3R {
bits: bool,
}
impl TIE3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RIEW<'a> {
w: &'a mut W,
}
impl<'a> _RIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIE1W<'a> {
w: &'a mut W,
}
impl<'a> _TIE1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EIEW<'a> {
w: &'a mut W,
}
impl<'a> _EIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DOIEW<'a> {
w: &'a mut W,
}
impl<'a> _DOIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WUIEW<'a> {
w: &'a mut W,
}
impl<'a> _WUIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPIEW<'a> {
w: &'a mut W,
}
impl<'a> _EPIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ALIEW<'a> {
w: &'a mut W,
}
impl<'a> _ALIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BEIEW<'a> {
w: &'a mut W,
}
impl<'a> _BEIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IDIEW<'a> {
w: &'a mut W,
}
impl<'a> _IDIEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIE2W<'a> {
w: &'a mut W,
}
impl<'a> _TIE2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIE3W<'a> {
w: &'a mut W,
}
impl<'a> _TIE3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt."]
#[inline]
pub fn rie(&self) -> RIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RIER { bits }
}
#[doc = "Bit 1 - Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn tie1(&self) -> TIE1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TIE1R { bits }
}
#[doc = "Bit 2 - Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn eie(&self) -> EIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EIER { bits }
}
#[doc = "Bit 3 - Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn doie(&self) -> DOIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DOIER { bits }
}
#[doc = "Bit 4 - Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested."]
#[inline]
pub fn wuie(&self) -> WUIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WUIER { bits }
}
#[doc = "Bit 5 - Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested."]
#[inline]
pub fn epie(&self) -> EPIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPIER { bits }
}
#[doc = "Bit 6 - Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested."]
#[inline]
pub fn alie(&self) -> ALIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ALIER { bits }
}
#[doc = "Bit 7 - Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt."]
#[inline]
pub fn beie(&self) -> BEIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BEIER { bits }
}
#[doc = "Bit 8 - ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt."]
#[inline]
pub fn idie(&self) -> IDIER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IDIER { bits }
}
#[doc = "Bit 9 - Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn tie2(&self) -> TIE2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TIE2R { bits }
}
#[doc = "Bit 10 - Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn tie3(&self) -> TIE3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TIE3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt."]
#[inline]
pub fn rie(&mut self) -> _RIEW {
_RIEW { w: self }
}
#[doc = "Bit 1 - Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn tie1(&mut self) -> _TIE1W {
_TIE1W { w: self }
}
#[doc = "Bit 2 - Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn eie(&mut self) -> _EIEW {
_EIEW { w: self }
}
#[doc = "Bit 3 - Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn doie(&mut self) -> _DOIEW {
_DOIEW { w: self }
}
#[doc = "Bit 4 - Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested."]
#[inline]
pub fn wuie(&mut self) -> _WUIEW {
_WUIEW { w: self }
}
#[doc = "Bit 5 - Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested."]
#[inline]
pub fn epie(&mut self) -> _EPIEW {
_EPIEW { w: self }
}
#[doc = "Bit 6 - Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested."]
#[inline]
pub fn alie(&mut self) -> _ALIEW {
_ALIEW { w: self }
}
#[doc = "Bit 7 - Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt."]
#[inline]
pub fn beie(&mut self) -> _BEIEW {
_BEIEW { w: self }
}
#[doc = "Bit 8 - ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt."]
#[inline]
pub fn idie(&mut self) -> _IDIEW {
_IDIEW { w: self }
}
#[doc = "Bit 9 - Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn tie2(&mut self) -> _TIE2W {
_TIE2W { w: self }
}
#[doc = "Bit 10 - Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt."]
#[inline]
pub fn tie3(&mut self) -> _TIE3W {
_TIE3W { w: self }
}
}
}
#[doc = "Bus Timing. Can only be written when RM in CANMOD is 1."]
pub struct BTR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Bus Timing. Can only be written when RM in CANMOD is 1."]
pub mod btr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::BTR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct BRPR {
bits: u16,
}
impl BRPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SJWR {
bits: u8,
}
impl SJWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TESG1R {
bits: u8,
}
impl TESG1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TESG2R {
bits: u8,
}
impl TESG2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `SAM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAMR {
#[doc = "The bus is sampled once (recommended for high speed buses)"]
THE_BUS_IS_SAMPLED_O,
#[doc = "The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)"]
THE_BUS_IS_SAMPLED_3,
}
impl SAMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SAMR::THE_BUS_IS_SAMPLED_O => false,
SAMR::THE_BUS_IS_SAMPLED_3 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SAMR {
match value {
false => SAMR::THE_BUS_IS_SAMPLED_O,
true => SAMR::THE_BUS_IS_SAMPLED_3,
}
}
#[doc = "Checks if the value of the field is `THE_BUS_IS_SAMPLED_O`"]
#[inline]
pub fn is_the_bus_is_sampled_o(&self) -> bool {
*self == SAMR::THE_BUS_IS_SAMPLED_O
}
#[doc = "Checks if the value of the field is `THE_BUS_IS_SAMPLED_3`"]
#[inline]
pub fn is_the_bus_is_sampled_3(&self) -> bool {
*self == SAMR::THE_BUS_IS_SAMPLED_3
}
}
#[doc = r" Proxy"]
pub struct _BRPW<'a> {
w: &'a mut W,
}
impl<'a> _BRPW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SJWW<'a> {
w: &'a mut W,
}
impl<'a> _SJWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TESG1W<'a> {
w: &'a mut W,
}
impl<'a> _TESG1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TESG2W<'a> {
w: &'a mut W,
}
impl<'a> _TESG2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SAM`"]
pub enum SAMW {
#[doc = "The bus is sampled once (recommended for high speed buses)"]
THE_BUS_IS_SAMPLED_O,
#[doc = "The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)"]
THE_BUS_IS_SAMPLED_3,
}
impl SAMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SAMW::THE_BUS_IS_SAMPLED_O => false,
SAMW::THE_BUS_IS_SAMPLED_3 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SAMW<'a> {
w: &'a mut W,
}
impl<'a> _SAMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SAMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The bus is sampled once (recommended for high speed buses)"]
#[inline]
pub fn the_bus_is_sampled_o(self) -> &'a mut W {
self.variant(SAMW::THE_BUS_IS_SAMPLED_O)
}
#[doc = "The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)"]
#[inline]
pub fn the_bus_is_sampled_3(self) -> &'a mut W {
self.variant(SAMW::THE_BUS_IS_SAMPLED_3)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock."]
#[inline]
pub fn brp(&self) -> BRPR {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
BRPR { bits }
}
#[doc = "Bits 14:15 - The Synchronization Jump Width is (this value plus one) CAN clocks."]
#[inline]
pub fn sjw(&self) -> SJWR {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SJWR { bits }
}
#[doc = "Bits 16:19 - The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks."]
#[inline]
pub fn tesg1(&self) -> TESG1R {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TESG1R { bits }
}
#[doc = "Bits 20:22 - The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks."]
#[inline]
pub fn tesg2(&self) -> TESG2R {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TESG2R { bits }
}
#[doc = "Bit 23 - Sampling"]
#[inline]
pub fn sam(&self) -> SAMR {
SAMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x001c_0000 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock."]
#[inline]
pub fn brp(&mut self) -> _BRPW {
_BRPW { w: self }
}
#[doc = "Bits 14:15 - The Synchronization Jump Width is (this value plus one) CAN clocks."]
#[inline]
pub fn sjw(&mut self) -> _SJWW {
_SJWW { w: self }
}
#[doc = "Bits 16:19 - The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks."]
#[inline]
pub fn tesg1(&mut self) -> _TESG1W {
_TESG1W { w: self }
}
#[doc = "Bits 20:22 - The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks."]
#[inline]
pub fn tesg2(&mut self) -> _TESG2W {
_TESG2W { w: self }
}
#[doc = "Bit 23 - Sampling"]
#[inline]
pub fn sam(&mut self) -> _SAMW {
_SAMW { w: self }
}
}
}
#[doc = "Error Warning Limit. Can only be written when RM in CANMOD is 1."]
pub struct EWL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Error Warning Limit. Can only be written when RM in CANMOD is 1."]
pub mod ewl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EWL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EWLR {
bits: u8,
}
impl EWLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _EWLW<'a> {
w: &'a mut W,
}
impl<'a> _EWLW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set."]
#[inline]
pub fn ewl(&self) -> EWLR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EWLR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x60 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set."]
#[inline]
pub fn ewl(&mut self) -> _EWLW {
_EWLW { w: self }
}
}
}
#[doc = "Status Register"]
pub struct SR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status Register"]
pub mod sr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::SR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RBS_1R {
bits: bool,
}
impl RBS_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DOS_1R {
bits: bool,
}
impl DOS_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `TBS1_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TBS1_1R {
#[doc = "Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process."]
LOCKED_SOFTWARE_CAN,
#[doc = "Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers."]
RELEASED_SOFTWARE_M,
}
impl TBS1_1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TBS1_1R::LOCKED_SOFTWARE_CAN => false,
TBS1_1R::RELEASED_SOFTWARE_M => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TBS1_1R {
match value {
false => TBS1_1R::LOCKED_SOFTWARE_CAN,
true => TBS1_1R::RELEASED_SOFTWARE_M,
}
}
#[doc = "Checks if the value of the field is `LOCKED_SOFTWARE_CAN`"]
#[inline]
pub fn is_locked_software_can(&self) -> bool {
*self == TBS1_1R::LOCKED_SOFTWARE_CAN
}
#[doc = "Checks if the value of the field is `RELEASED_SOFTWARE_M`"]
#[inline]
pub fn is_released_software_m(&self) -> bool {
*self == TBS1_1R::RELEASED_SOFTWARE_M
}
}
#[doc = "Possible values of the field `TCS1_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TCS1_1R {
#[doc = "Incomplete. The previously requested transmission for Tx Buffer 1 is not complete."]
INCOMPLETE_THE_PREV,
#[doc = "Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed."]
COMPLETE_THE_PREVIO,
}
impl TCS1_1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TCS1_1R::INCOMPLETE_THE_PREV => false,
TCS1_1R::COMPLETE_THE_PREVIO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TCS1_1R {
match value {
false => TCS1_1R::INCOMPLETE_THE_PREV,
true => TCS1_1R::COMPLETE_THE_PREVIO,
}
}
#[doc = "Checks if the value of the field is `INCOMPLETE_THE_PREV`"]
#[inline]
pub fn is_incomplete_the_prev(&self) -> bool {
*self == TCS1_1R::INCOMPLETE_THE_PREV
}
#[doc = "Checks if the value of the field is `COMPLETE_THE_PREVIO`"]
#[inline]
pub fn is_complete_the_previo(&self) -> bool {
*self == TCS1_1R::COMPLETE_THE_PREVIO
}
}
#[doc = r" Value of the field"]
pub struct RS_1R {
bits: bool,
}
impl RS_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `TS1_1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TS1_1R {
#[doc = "Idle. There is no transmission from Tx Buffer 1."]
IDLE_THERE_IS_NO_TR,
#[doc = "Transmit. The CAN Controller is transmitting a message from Tx Buffer 1."]
TRANSMIT_THE_CAN_CO,
}
impl TS1_1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TS1_1R::IDLE_THERE_IS_NO_TR => false,
TS1_1R::TRANSMIT_THE_CAN_CO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TS1_1R {
match value {
false => TS1_1R::IDLE_THERE_IS_NO_TR,
true => TS1_1R::TRANSMIT_THE_CAN_CO,
}
}
#[doc = "Checks if the value of the field is `IDLE_THERE_IS_NO_TR`"]
#[inline]
pub fn is_idle_there_is_no_tr(&self) -> bool {
*self == TS1_1R::IDLE_THERE_IS_NO_TR
}
#[doc = "Checks if the value of the field is `TRANSMIT_THE_CAN_CO`"]
#[inline]
pub fn is_transmit_the_can_co(&self) -> bool {
*self == TS1_1R::TRANSMIT_THE_CAN_CO
}
}
#[doc = r" Value of the field"]
pub struct ES_1R {
bits: bool,
}
impl ES_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BS_1R {
bits: bool,
}
impl BS_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RBS_2R {
bits: bool,
}
impl RBS_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DOS_2R {
bits: bool,
}
impl DOS_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `TBS2_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TBS2_2R {
#[doc = "Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process."]
LOCKED_SOFTWARE_CAN,
#[doc = "Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers."]
RELEASED_SOFTWARE_M,
}
impl TBS2_2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TBS2_2R::LOCKED_SOFTWARE_CAN => false,
TBS2_2R::RELEASED_SOFTWARE_M => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TBS2_2R {
match value {
false => TBS2_2R::LOCKED_SOFTWARE_CAN,
true => TBS2_2R::RELEASED_SOFTWARE_M,
}
}
#[doc = "Checks if the value of the field is `LOCKED_SOFTWARE_CAN`"]
#[inline]
pub fn is_locked_software_can(&self) -> bool {
*self == TBS2_2R::LOCKED_SOFTWARE_CAN
}
#[doc = "Checks if the value of the field is `RELEASED_SOFTWARE_M`"]
#[inline]
pub fn is_released_software_m(&self) -> bool {
*self == TBS2_2R::RELEASED_SOFTWARE_M
}
}
#[doc = "Possible values of the field `TCS2_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TCS2_2R {
#[doc = "Incomplete. The previously requested transmission for Tx Buffer 2 is not complete."]
INCOMPLETE_THE_PREV,
#[doc = "Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed."]
COMPLETE_THE_PREVIO,
}
impl TCS2_2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TCS2_2R::INCOMPLETE_THE_PREV => false,
TCS2_2R::COMPLETE_THE_PREVIO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TCS2_2R {
match value {
false => TCS2_2R::INCOMPLETE_THE_PREV,
true => TCS2_2R::COMPLETE_THE_PREVIO,
}
}
#[doc = "Checks if the value of the field is `INCOMPLETE_THE_PREV`"]
#[inline]
pub fn is_incomplete_the_prev(&self) -> bool {
*self == TCS2_2R::INCOMPLETE_THE_PREV
}
#[doc = "Checks if the value of the field is `COMPLETE_THE_PREVIO`"]
#[inline]
pub fn is_complete_the_previo(&self) -> bool {
*self == TCS2_2R::COMPLETE_THE_PREVIO
}
}
#[doc = r" Value of the field"]
pub struct RS_2R {
bits: bool,
}
impl RS_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `TS2_2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TS2_2R {
#[doc = "Idle. There is no transmission from Tx Buffer 2."]
IDLE_THERE_IS_NO_TR,
#[doc = "Transmit. The CAN Controller is transmitting a message from Tx Buffer 2."]
TRANSMIT_THE_CAN_CO,
}
impl TS2_2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TS2_2R::IDLE_THERE_IS_NO_TR => false,
TS2_2R::TRANSMIT_THE_CAN_CO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TS2_2R {
match value {
false => TS2_2R::IDLE_THERE_IS_NO_TR,
true => TS2_2R::TRANSMIT_THE_CAN_CO,
}
}
#[doc = "Checks if the value of the field is `IDLE_THERE_IS_NO_TR`"]
#[inline]
pub fn is_idle_there_is_no_tr(&self) -> bool {
*self == TS2_2R::IDLE_THERE_IS_NO_TR
}
#[doc = "Checks if the value of the field is `TRANSMIT_THE_CAN_CO`"]
#[inline]
pub fn is_transmit_the_can_co(&self) -> bool {
*self == TS2_2R::TRANSMIT_THE_CAN_CO
}
}
#[doc = r" Value of the field"]
pub struct ES_2R {
bits: bool,
}
impl ES_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BS_2R {
bits: bool,
}
impl BS_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RBS_3R {
bits: bool,
}
impl RBS_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DOS_3R {
bits: bool,
}
impl DOS_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `TBS3_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TBS3_3R {
#[doc = "Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process."]
LOCKED_SOFTWARE_CAN,
#[doc = "Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers."]
RELEASED_SOFTWARE_M,
}
impl TBS3_3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TBS3_3R::LOCKED_SOFTWARE_CAN => false,
TBS3_3R::RELEASED_SOFTWARE_M => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TBS3_3R {
match value {
false => TBS3_3R::LOCKED_SOFTWARE_CAN,
true => TBS3_3R::RELEASED_SOFTWARE_M,
}
}
#[doc = "Checks if the value of the field is `LOCKED_SOFTWARE_CAN`"]
#[inline]
pub fn is_locked_software_can(&self) -> bool {
*self == TBS3_3R::LOCKED_SOFTWARE_CAN
}
#[doc = "Checks if the value of the field is `RELEASED_SOFTWARE_M`"]
#[inline]
pub fn is_released_software_m(&self) -> bool {
*self == TBS3_3R::RELEASED_SOFTWARE_M
}
}
#[doc = "Possible values of the field `TCS3_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TCS3_3R {
#[doc = "Incomplete. The previously requested transmission for Tx Buffer 3 is not complete."]
INCOMPLETE_THE_PREV,
#[doc = "Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed."]
COMPLETE_THE_PREVIO,
}
impl TCS3_3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TCS3_3R::INCOMPLETE_THE_PREV => false,
TCS3_3R::COMPLETE_THE_PREVIO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TCS3_3R {
match value {
false => TCS3_3R::INCOMPLETE_THE_PREV,
true => TCS3_3R::COMPLETE_THE_PREVIO,
}
}
#[doc = "Checks if the value of the field is `INCOMPLETE_THE_PREV`"]
#[inline]
pub fn is_incomplete_the_prev(&self) -> bool {
*self == TCS3_3R::INCOMPLETE_THE_PREV
}
#[doc = "Checks if the value of the field is `COMPLETE_THE_PREVIO`"]
#[inline]
pub fn is_complete_the_previo(&self) -> bool {
*self == TCS3_3R::COMPLETE_THE_PREVIO
}
}
#[doc = r" Value of the field"]
pub struct RS_3R {
bits: bool,
}
impl RS_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `TS3_3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TS3_3R {
#[doc = "Idle. There is no transmission from Tx Buffer 3."]
IDLE_THERE_IS_NO_TR,
#[doc = "Transmit. The CAN Controller is transmitting a message from Tx Buffer 3."]
TRANSMIT_THE_CAN_CO,
}
impl TS3_3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TS3_3R::IDLE_THERE_IS_NO_TR => false,
TS3_3R::TRANSMIT_THE_CAN_CO => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TS3_3R {
match value {
false => TS3_3R::IDLE_THERE_IS_NO_TR,
true => TS3_3R::TRANSMIT_THE_CAN_CO,
}
}
#[doc = "Checks if the value of the field is `IDLE_THERE_IS_NO_TR`"]
#[inline]
pub fn is_idle_there_is_no_tr(&self) -> bool {
*self == TS3_3R::IDLE_THERE_IS_NO_TR
}
#[doc = "Checks if the value of the field is `TRANSMIT_THE_CAN_CO`"]
#[inline]
pub fn is_transmit_the_can_co(&self) -> bool {
*self == TS3_3R::TRANSMIT_THE_CAN_CO
}
}
#[doc = r" Value of the field"]
pub struct ES_3R {
bits: bool,
}
impl ES_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BS_3R {
bits: bool,
}
impl BS_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR."]
#[inline]
pub fn rbs_1(&self) -> RBS_1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RBS_1R { bits }
}
#[doc = "Bit 1 - Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR."]
#[inline]
pub fn dos_1(&self) -> DOS_1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DOS_1R { bits }
}
#[doc = "Bit 2 - Transmit Buffer Status 1."]
#[inline]
pub fn tbs1_1(&self) -> TBS1_1R {
TBS1_1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Transmission Complete Status."]
#[inline]
pub fn tcs1_1(&self) -> TCS1_1R {
TCS1_1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Receive Status. This bit is identical to the RS bit in the GSR."]
#[inline]
pub fn rs_1(&self) -> RS_1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RS_1R { bits }
}
#[doc = "Bit 5 - Transmit Status 1."]
#[inline]
pub fn ts1_1(&self) -> TS1_1R {
TS1_1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Error Status. This bit is identical to the ES bit in the CANxGSR."]
#[inline]
pub fn es_1(&self) -> ES_1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ES_1R { bits }
}
#[doc = "Bit 7 - Bus Status. This bit is identical to the BS bit in the CANxGSR."]
#[inline]
pub fn bs_1(&self) -> BS_1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BS_1R { bits }
}
#[doc = "Bit 8 - Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR."]
#[inline]
pub fn rbs_2(&self) -> RBS_2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RBS_2R { bits }
}
#[doc = "Bit 9 - Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR."]
#[inline]
pub fn dos_2(&self) -> DOS_2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DOS_2R { bits }
}
#[doc = "Bit 10 - Transmit Buffer Status 2."]
#[inline]
pub fn tbs2_2(&self) -> TBS2_2R {
TBS2_2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Transmission Complete Status."]
#[inline]
pub fn tcs2_2(&self) -> TCS2_2R {
TCS2_2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Receive Status. This bit is identical to the RS bit in the GSR."]
#[inline]
pub fn rs_2(&self) -> RS_2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RS_2R { bits }
}
#[doc = "Bit 13 - Transmit Status 2."]
#[inline]
pub fn ts2_2(&self) -> TS2_2R {
TS2_2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Error Status. This bit is identical to the ES bit in the CANxGSR."]
#[inline]
pub fn es_2(&self) -> ES_2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ES_2R { bits }
}
#[doc = "Bit 15 - Bus Status. This bit is identical to the BS bit in the CANxGSR."]
#[inline]
pub fn bs_2(&self) -> BS_2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BS_2R { bits }
}
#[doc = "Bit 16 - Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR."]
#[inline]
pub fn rbs_3(&self) -> RBS_3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RBS_3R { bits }
}
#[doc = "Bit 17 - Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR."]
#[inline]
pub fn dos_3(&self) -> DOS_3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DOS_3R { bits }
}
#[doc = "Bit 18 - Transmit Buffer Status 3."]
#[inline]
pub fn tbs3_3(&self) -> TBS3_3R {
TBS3_3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 19 - Transmission Complete Status."]
#[inline]
pub fn tcs3_3(&self) -> TCS3_3R {
TCS3_3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 20 - Receive Status. This bit is identical to the RS bit in the GSR."]
#[inline]
pub fn rs_3(&self) -> RS_3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RS_3R { bits }
}
#[doc = "Bit 21 - Transmit Status 3."]
#[inline]
pub fn ts3_3(&self) -> TS3_3R {
TS3_3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Error Status. This bit is identical to the ES bit in the CANxGSR."]
#[inline]
pub fn es_3(&self) -> ES_3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ES_3R { bits }
}
#[doc = "Bit 23 - Bus Status. This bit is identical to the BS bit in the CANxGSR."]
#[inline]
pub fn bs_3(&self) -> BS_3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BS_3R { bits }
}
}
}
#[doc = "Receive frame status. Can only be written when RM in CANMOD is 1."]
pub struct RFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive frame status. Can only be written when RM in CANMOD is 1."]
pub mod rfs {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct IDINDEXR {
bits: u16,
}
impl IDINDEXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct BPR {
bits: bool,
}
impl BPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DLCR {
bits: u8,
}
impl DLCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct RTRR {
bits: bool,
}
impl RTRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct FFR {
bits: bool,
}
impl FFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _IDINDEXW<'a> {
w: &'a mut W,
}
impl<'a> _IDINDEXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BPW<'a> {
w: &'a mut W,
}
impl<'a> _BPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DLCW<'a> {
w: &'a mut W,
}
impl<'a> _DLCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTRW<'a> {
w: &'a mut W,
}
impl<'a> _RTRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FFW<'a> {
w: &'a mut W,
}
impl<'a> _FFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values."]
#[inline]
pub fn idindex(&self) -> IDINDEXR {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
IDINDEXR { bits }
}
#[doc = "Bit 10 - If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless."]
#[inline]
pub fn bp(&self) -> BPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BPR { bits }
}
#[doc = "Bits 16:19 - The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding."]
#[inline]
pub fn dlc(&self) -> DLCR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLCR { bits }
}
#[doc = "Bit 30 - This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier."]
#[inline]
pub fn rtr(&self) -> RTRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTRR { bits }
}
#[doc = "Bit 31 - A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below."]
#[inline]
pub fn ff(&self) -> FFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FFR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values."]
#[inline]
pub fn idindex(&mut self) -> _IDINDEXW {
_IDINDEXW { w: self }
}
#[doc = "Bit 10 - If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless."]
#[inline]
pub fn bp(&mut self) -> _BPW {
_BPW { w: self }
}
#[doc = "Bits 16:19 - The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding."]
#[inline]
pub fn dlc(&mut self) -> _DLCW {
_DLCW { w: self }
}
#[doc = "Bit 30 - This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier."]
#[inline]
pub fn rtr(&mut self) -> _RTRW {
_RTRW { w: self }
}
#[doc = "Bit 31 - A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below."]
#[inline]
pub fn ff(&mut self) -> _FFW {
_FFW { w: self }
}
}
}
#[doc = "Received Identifier. Can only be written when RM in CANMOD is 1."]
pub struct RID {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Received Identifier. Can only be written when RM in CANMOD is 1."]
pub mod rid {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RID {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct IDR {
bits: u16,
}
impl IDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _IDW<'a> {
w: &'a mut W,
}
impl<'a> _IDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x07ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:10 - The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18."]
#[inline]
pub fn id(&self) -> IDR {
let bits = {
const MASK: u16 = 0x07ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
IDR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:10 - The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18."]
#[inline]
pub fn id(&mut self) -> _IDW {
_IDW { w: self }
}
}
}
#[doc = "Received data bytes 1-4. Can only be written when RM in CANMOD is 1."]
pub struct RDA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Received data bytes 1-4. Can only be written when RM in CANMOD is 1."]
pub mod rda {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RDA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA1R {
bits: u8,
}
impl DATA1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA2R {
bits: u8,
}
impl DATA2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA3R {
bits: u8,
}
impl DATA3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA4R {
bits: u8,
}
impl DATA4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA1W<'a> {
w: &'a mut W,
}
impl<'a> _DATA1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA2W<'a> {
w: &'a mut W,
}
impl<'a> _DATA2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA3W<'a> {
w: &'a mut W,
}
impl<'a> _DATA3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA4W<'a> {
w: &'a mut W,
}
impl<'a> _DATA4W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message."]
#[inline]
pub fn data1(&self) -> DATA1R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA1R { bits }
}
#[doc = "Bits 8:15 - Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message."]
#[inline]
pub fn data2(&self) -> DATA2R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA2R { bits }
}
#[doc = "Bits 16:23 - Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message."]
#[inline]
pub fn data3(&self) -> DATA3R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA3R { bits }
}
#[doc = "Bits 24:31 - Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message."]
#[inline]
pub fn data4(&self) -> DATA4R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA4R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message."]
#[inline]
pub fn data1(&mut self) -> _DATA1W {
_DATA1W { w: self }
}
#[doc = "Bits 8:15 - Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message."]
#[inline]
pub fn data2(&mut self) -> _DATA2W {
_DATA2W { w: self }
}
#[doc = "Bits 16:23 - Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message."]
#[inline]
pub fn data3(&mut self) -> _DATA3W {
_DATA3W { w: self }
}
#[doc = "Bits 24:31 - Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message."]
#[inline]
pub fn data4(&mut self) -> _DATA4W {
_DATA4W { w: self }
}
}
}
#[doc = "Received data bytes 5-8. Can only be written when RM in CANMOD is 1."]
pub struct RDB {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Received data bytes 5-8. Can only be written when RM in CANMOD is 1."]
pub mod rdb {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RDB {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA5R {
bits: u8,
}
impl DATA5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA6R {
bits: u8,
}
impl DATA6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA7R {
bits: u8,
}
impl DATA7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA8R {
bits: u8,
}
impl DATA8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA5W<'a> {
w: &'a mut W,
}
impl<'a> _DATA5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA6W<'a> {
w: &'a mut W,
}
impl<'a> _DATA6W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA7W<'a> {
w: &'a mut W,
}
impl<'a> _DATA7W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA8W<'a> {
w: &'a mut W,
}
impl<'a> _DATA8W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message."]
#[inline]
pub fn data5(&self) -> DATA5R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA5R { bits }
}
#[doc = "Bits 8:15 - Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message."]
#[inline]
pub fn data6(&self) -> DATA6R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA6R { bits }
}
#[doc = "Bits 16:23 - Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message."]
#[inline]
pub fn data7(&self) -> DATA7R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA7R { bits }
}
#[doc = "Bits 24:31 - Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message."]
#[inline]
pub fn data8(&self) -> DATA8R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA8R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message."]
#[inline]
pub fn data5(&mut self) -> _DATA5W {
_DATA5W { w: self }
}
#[doc = "Bits 8:15 - Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message."]
#[inline]
pub fn data6(&mut self) -> _DATA6W {
_DATA6W { w: self }
}
#[doc = "Bits 16:23 - Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message."]
#[inline]
pub fn data7(&mut self) -> _DATA7W {
_DATA7W { w: self }
}
#[doc = "Bits 24:31 - Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message."]
#[inline]
pub fn data8(&mut self) -> _DATA8W {
_DATA8W { w: self }
}
}
}
#[doc = "Transmit frame info (Tx Buffer )"]
pub struct TFI {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit frame info (Tx Buffer )"]
pub mod tfi {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TFI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PRIOR {
bits: u8,
}
impl PRIOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DLCR {
bits: u8,
}
impl DLCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct RTRR {
bits: bool,
}
impl RTRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct FFR {
bits: bool,
}
impl FFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PRIOW<'a> {
w: &'a mut W,
}
impl<'a> _PRIOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DLCW<'a> {
w: &'a mut W,
}
impl<'a> _DLCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RTRW<'a> {
w: &'a mut W,
}
impl<'a> _RTRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FFW<'a> {
w: &'a mut W,
}
impl<'a> _FFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first."]
#[inline]
pub fn prio(&self) -> PRIOR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PRIOR { bits }
}
#[doc = "Bits 16:19 - Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes"]
#[inline]
pub fn dlc(&self) -> DLCR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DLCR { bits }
}
#[doc = "Bit 30 - This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes."]
#[inline]
pub fn rtr(&self) -> RTRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RTRR { bits }
}
#[doc = "Bit 31 - If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)."]
#[inline]
pub fn ff(&self) -> FFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FFR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first."]
#[inline]
pub fn prio(&mut self) -> _PRIOW {
_PRIOW { w: self }
}
#[doc = "Bits 16:19 - Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes"]
#[inline]
pub fn dlc(&mut self) -> _DLCW {
_DLCW { w: self }
}
#[doc = "Bit 30 - This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes."]
#[inline]
pub fn rtr(&mut self) -> _RTRW {
_RTRW { w: self }
}
#[doc = "Bit 31 - If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)."]
#[inline]
pub fn ff(&mut self) -> _FFW {
_FFW { w: self }
}
}
}
#[doc = "Transmit Identifier (Tx Buffer)"]
pub struct TID {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit Identifier (Tx Buffer)"]
pub mod tid {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TID {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct IDR {
bits: u16,
}
impl IDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _IDW<'a> {
w: &'a mut W,
}
impl<'a> _IDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x07ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:10 - The 11-bit Identifier to be sent in the next transmit message."]
#[inline]
pub fn id(&self) -> IDR {
let bits = {
const MASK: u16 = 0x07ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
IDR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:10 - The 11-bit Identifier to be sent in the next transmit message."]
#[inline]
pub fn id(&mut self) -> _IDW {
_IDW { w: self }
}
}
}
#[doc = "Transmit data bytes 1-4 (Tx Buffer)"]
pub struct TDA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit data bytes 1-4 (Tx Buffer)"]
pub mod tda {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TDA {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA1R {
bits: u8,
}
impl DATA1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA2R {
bits: u8,
}
impl DATA2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA3R {
bits: u8,
}
impl DATA3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA4R {
bits: u8,
}
impl DATA4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA1W<'a> {
w: &'a mut W,
}
impl<'a> _DATA1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA2W<'a> {
w: &'a mut W,
}
impl<'a> _DATA2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA3W<'a> {
w: &'a mut W,
}
impl<'a> _DATA3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA4W<'a> {
w: &'a mut W,
}
impl<'a> _DATA4W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message."]
#[inline]
pub fn data1(&self) -> DATA1R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA1R { bits }
}
#[doc = "Bits 8:15 - Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message."]
#[inline]
pub fn data2(&self) -> DATA2R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA2R { bits }
}
#[doc = "Bits 16:23 - Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message."]
#[inline]
pub fn data3(&self) -> DATA3R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA3R { bits }
}
#[doc = "Bits 24:31 - Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message."]
#[inline]
pub fn data4(&self) -> DATA4R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA4R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message."]
#[inline]
pub fn data1(&mut self) -> _DATA1W {
_DATA1W { w: self }
}
#[doc = "Bits 8:15 - Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message."]
#[inline]
pub fn data2(&mut self) -> _DATA2W {
_DATA2W { w: self }
}
#[doc = "Bits 16:23 - Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message."]
#[inline]
pub fn data3(&mut self) -> _DATA3W {
_DATA3W { w: self }
}
#[doc = "Bits 24:31 - Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message."]
#[inline]
pub fn data4(&mut self) -> _DATA4W {
_DATA4W { w: self }
}
}
}
#[doc = "Transmit data bytes 5-8 (Tx Buffer )"]
pub struct TDB {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit data bytes 5-8 (Tx Buffer )"]
pub mod tdb {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TDB {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA5R {
bits: u8,
}
impl DATA5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA6R {
bits: u8,
}
impl DATA6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA7R {
bits: u8,
}
impl DATA7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA8R {
bits: u8,
}
impl DATA8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA5W<'a> {
w: &'a mut W,
}
impl<'a> _DATA5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA6W<'a> {
w: &'a mut W,
}
impl<'a> _DATA6W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA7W<'a> {
w: &'a mut W,
}
impl<'a> _DATA7W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA8W<'a> {
w: &'a mut W,
}
impl<'a> _DATA8W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message."]
#[inline]
pub fn data5(&self) -> DATA5R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA5R { bits }
}
#[doc = "Bits 8:15 - Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message."]
#[inline]
pub fn data6(&self) -> DATA6R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA6R { bits }
}
#[doc = "Bits 16:23 - Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message."]
#[inline]
pub fn data7(&self) -> DATA7R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA7R { bits }
}
#[doc = "Bits 24:31 - Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message."]
#[inline]
pub fn data8(&self) -> DATA8R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA8R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message."]
#[inline]
pub fn data5(&mut self) -> _DATA5W {
_DATA5W { w: self }
}
#[doc = "Bits 8:15 - Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message."]
#[inline]
pub fn data6(&mut self) -> _DATA6W {
_DATA6W { w: self }
}
#[doc = "Bits 16:23 - Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message."]
#[inline]
pub fn data7(&mut self) -> _DATA7W {
_DATA7W { w: self }
}
#[doc = "Bits 24:31 - Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message."]
#[inline]
pub fn data8(&mut self) -> _DATA8W {
_DATA8W { w: self }
}
}
}
}
#[doc = "CAN2"]
pub struct CAN2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CAN2 {}
impl CAN2 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const can1::RegisterBlock {
0x4004_8000 as *const _
}
}
impl Deref for CAN2 {
type Target = can1::RegisterBlock;
fn deref(&self) -> &can1::RegisterBlock {
unsafe { &*CAN2::ptr() }
}
}
#[doc = "I2C1"]
pub struct I2C1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C1 {}
impl I2C1 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const i2c0::RegisterBlock {
0x4005_c000 as *const _
}
}
impl Deref for I2C1 {
type Target = i2c0::RegisterBlock;
fn deref(&self) -> &i2c0::RegisterBlock {
unsafe { &*I2C1::ptr() }
}
}
#[doc = "SSP controller"]
pub struct SSP0 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SSP0 {}
impl SSP0 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const ssp1::RegisterBlock {
0x4008_8000 as *const _
}
}
impl Deref for SSP0 {
type Target = ssp1::RegisterBlock;
fn deref(&self) -> &ssp1::RegisterBlock {
unsafe { &*SSP0::ptr() }
}
}
#[doc = "Digital-to-Analog Converter (DAC)"]
pub struct DAC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DAC {}
impl DAC {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const dac::RegisterBlock {
0x4008_c000 as *const _
}
}
impl Deref for DAC {
type Target = dac::RegisterBlock;
fn deref(&self) -> &dac::RegisterBlock {
unsafe { &*DAC::ptr() }
}
}
#[doc = "Digital-to-Analog Converter (DAC)"]
pub mod dac {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit."]
pub cr: CR,
#[doc = "0x04 - DAC Control register. This register controls DMA and timer operation."]
pub ctrl: CTRL,
#[doc = "0x08 - DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer."]
pub cntval: CNTVAL,
}
#[doc = "D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit."]
pub struct CR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit."]
pub mod cr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct VALUER {
bits: u16,
}
impl VALUER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = "Possible values of the field `BIAS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BIASR {
#[doc = "The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz."]
FAST,
#[doc = "The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz."]
SLOW,
}
impl BIASR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BIASR::FAST => false,
BIASR::SLOW => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BIASR {
match value {
false => BIASR::FAST,
true => BIASR::SLOW,
}
}
#[doc = "Checks if the value of the field is `FAST`"]
#[inline]
pub fn is_fast(&self) -> bool {
*self == BIASR::FAST
}
#[doc = "Checks if the value of the field is `SLOW`"]
#[inline]
pub fn is_slow(&self) -> bool {
*self == BIASR::SLOW
}
}
#[doc = r" Proxy"]
pub struct _VALUEW<'a> {
w: &'a mut W,
}
impl<'a> _VALUEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `BIAS`"]
pub enum BIASW {
#[doc = "The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz."]
FAST,
#[doc = "The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz."]
SLOW,
}
impl BIASW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BIASW::FAST => false,
BIASW::SLOW => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BIASW<'a> {
w: &'a mut W,
}
impl<'a> _BIASW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BIASW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz."]
#[inline]
pub fn fast(self) -> &'a mut W {
self.variant(BIASW::FAST)
}
#[doc = "The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz."]
#[inline]
pub fn slow(self) -> &'a mut W {
self.variant(BIASW::SLOW)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 6:15 - After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN."]
#[inline]
pub fn value(&self) -> VALUER {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u16
};
VALUER { bits }
}
#[doc = "Bit 16 - Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet."]
#[inline]
pub fn bias(&self) -> BIASR {
BIASR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 6:15 - After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN."]
#[inline]
pub fn value(&mut self) -> _VALUEW {
_VALUEW { w: self }
}
#[doc = "Bit 16 - Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet."]
#[inline]
pub fn bias(&mut self) -> _BIASW {
_BIASW { w: self }
}
}
}
#[doc = "DAC Control register. This register controls DMA and timer operation."]
pub struct CTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DAC Control register. This register controls DMA and timer operation."]
pub mod ctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `INT_DMA_REQ`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INT_DMA_REQR {
#[doc = "Clear on any write to the DACR register."]
CLEAR_ON_ANY_WRITE_T,
#[doc = "Set by hardware when the timer times out."]
SET_BY_HARDWARE_WHEN,
}
impl INT_DMA_REQR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
INT_DMA_REQR::CLEAR_ON_ANY_WRITE_T => false,
INT_DMA_REQR::SET_BY_HARDWARE_WHEN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> INT_DMA_REQR {
match value {
false => INT_DMA_REQR::CLEAR_ON_ANY_WRITE_T,
true => INT_DMA_REQR::SET_BY_HARDWARE_WHEN,
}
}
#[doc = "Checks if the value of the field is `CLEAR_ON_ANY_WRITE_T`"]
#[inline]
pub fn is_clear_on_any_write_t(&self) -> bool {
*self == INT_DMA_REQR::CLEAR_ON_ANY_WRITE_T
}
#[doc = "Checks if the value of the field is `SET_BY_HARDWARE_WHEN`"]
#[inline]
pub fn is_set_by_hardware_when(&self) -> bool {
*self == INT_DMA_REQR::SET_BY_HARDWARE_WHEN
}
}
#[doc = "Possible values of the field `DBLBUF_ENA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DBLBUF_ENAR {
#[doc = "Disable"]
DISABLE,
#[doc = "Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter."]
ENABLE_WHEN_THIS_BI,
}
impl DBLBUF_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DBLBUF_ENAR::DISABLE => false,
DBLBUF_ENAR::ENABLE_WHEN_THIS_BI => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DBLBUF_ENAR {
match value {
false => DBLBUF_ENAR::DISABLE,
true => DBLBUF_ENAR::ENABLE_WHEN_THIS_BI,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == DBLBUF_ENAR::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE_WHEN_THIS_BI`"]
#[inline]
pub fn is_enable_when_this_bi(&self) -> bool {
*self == DBLBUF_ENAR::ENABLE_WHEN_THIS_BI
}
}
#[doc = "Possible values of the field `CNT_ENA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CNT_ENAR {
#[doc = "Disable"]
DISABLE,
#[doc = "Enable"]
ENABLE,
}
impl CNT_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CNT_ENAR::DISABLE => false,
CNT_ENAR::ENABLE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CNT_ENAR {
match value {
false => CNT_ENAR::DISABLE,
true => CNT_ENAR::ENABLE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == CNT_ENAR::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline]
pub fn is_enable(&self) -> bool {
*self == CNT_ENAR::ENABLE
}
}
#[doc = "Possible values of the field `DMA_ENA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMA_ENAR {
#[doc = "Disable"]
DISABLE,
#[doc = "Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)."]
ENABLE_DMA_BURST_RE,
}
impl DMA_ENAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMA_ENAR::DISABLE => false,
DMA_ENAR::ENABLE_DMA_BURST_RE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMA_ENAR {
match value {
false => DMA_ENAR::DISABLE,
true => DMA_ENAR::ENABLE_DMA_BURST_RE,
}
}
#[doc = "Checks if the value of the field is `DISABLE`"]
#[inline]
pub fn is_disable(&self) -> bool {
*self == DMA_ENAR::DISABLE
}
#[doc = "Checks if the value of the field is `ENABLE_DMA_BURST_RE`"]
#[inline]
pub fn is_enable_dma_burst_re(&self) -> bool {
*self == DMA_ENAR::ENABLE_DMA_BURST_RE
}
}
#[doc = "Values that can be written to the field `INT_DMA_REQ`"]
pub enum INT_DMA_REQW {
#[doc = "Clear on any write to the DACR register."]
CLEAR_ON_ANY_WRITE_T,
#[doc = "Set by hardware when the timer times out."]
SET_BY_HARDWARE_WHEN,
}
impl INT_DMA_REQW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
INT_DMA_REQW::CLEAR_ON_ANY_WRITE_T => false,
INT_DMA_REQW::SET_BY_HARDWARE_WHEN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _INT_DMA_REQW<'a> {
w: &'a mut W,
}
impl<'a> _INT_DMA_REQW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: INT_DMA_REQW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clear on any write to the DACR register."]
#[inline]
pub fn clear_on_any_write_t(self) -> &'a mut W {
self.variant(INT_DMA_REQW::CLEAR_ON_ANY_WRITE_T)
}
#[doc = "Set by hardware when the timer times out."]
#[inline]
pub fn set_by_hardware_when(self) -> &'a mut W {
self.variant(INT_DMA_REQW::SET_BY_HARDWARE_WHEN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DBLBUF_ENA`"]
pub enum DBLBUF_ENAW {
#[doc = "Disable"]
DISABLE,
#[doc = "Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter."]
ENABLE_WHEN_THIS_BI,
}
impl DBLBUF_ENAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DBLBUF_ENAW::DISABLE => false,
DBLBUF_ENAW::ENABLE_WHEN_THIS_BI => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DBLBUF_ENAW<'a> {
w: &'a mut W,
}
impl<'a> _DBLBUF_ENAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DBLBUF_ENAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable"]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(DBLBUF_ENAW::DISABLE)
}
#[doc = "Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter."]
#[inline]
pub fn enable_when_this_bi(self) -> &'a mut W {
self.variant(DBLBUF_ENAW::ENABLE_WHEN_THIS_BI)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CNT_ENA`"]
pub enum CNT_ENAW {
#[doc = "Disable"]
DISABLE,
#[doc = "Enable"]
ENABLE,
}
impl CNT_ENAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CNT_ENAW::DISABLE => false,
CNT_ENAW::ENABLE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CNT_ENAW<'a> {
w: &'a mut W,
}
impl<'a> _CNT_ENAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CNT_ENAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable"]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(CNT_ENAW::DISABLE)
}
#[doc = "Enable"]
#[inline]
pub fn enable(self) -> &'a mut W {
self.variant(CNT_ENAW::ENABLE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMA_ENA`"]
pub enum DMA_ENAW {
#[doc = "Disable"]
DISABLE,
#[doc = "Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)."]
ENABLE_DMA_BURST_RE,
}
impl DMA_ENAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMA_ENAW::DISABLE => false,
DMA_ENAW::ENABLE_DMA_BURST_RE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMA_ENAW<'a> {
w: &'a mut W,
}
impl<'a> _DMA_ENAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMA_ENAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable"]
#[inline]
pub fn disable(self) -> &'a mut W {
self.variant(DMA_ENAW::DISABLE)
}
#[doc = "Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)."]
#[inline]
pub fn enable_dma_burst_re(self) -> &'a mut W {
self.variant(DMA_ENAW::ENABLE_DMA_BURST_RE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - DMA interrupt request"]
#[inline]
pub fn int_dma_req(&self) -> INT_DMA_REQR {
INT_DMA_REQR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Double buffering"]
#[inline]
pub fn dblbuf_ena(&self) -> DBLBUF_ENAR {
DBLBUF_ENAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Time-out counter operation"]
#[inline]
pub fn cnt_ena(&self) -> CNT_ENAR {
CNT_ENAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - DMA access"]
#[inline]
pub fn dma_ena(&self) -> DMA_ENAR {
DMA_ENAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - DMA interrupt request"]
#[inline]
pub fn int_dma_req(&mut self) -> _INT_DMA_REQW {
_INT_DMA_REQW { w: self }
}
#[doc = "Bit 1 - Double buffering"]
#[inline]
pub fn dblbuf_ena(&mut self) -> _DBLBUF_ENAW {
_DBLBUF_ENAW { w: self }
}
#[doc = "Bit 2 - Time-out counter operation"]
#[inline]
pub fn cnt_ena(&mut self) -> _CNT_ENAW {
_CNT_ENAW { w: self }
}
#[doc = "Bit 3 - DMA access"]
#[inline]
pub fn dma_ena(&mut self) -> _DMA_ENAW {
_DMA_ENAW { w: self }
}
}
}
#[doc = "DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer."]
pub struct CNTVAL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer."]
pub mod cntval {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CNTVAL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct VALUER {
bits: u16,
}
impl VALUER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _VALUEW<'a> {
w: &'a mut W,
}
impl<'a> _VALUEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - 16-bit reload value for the DAC interrupt/DMA timer."]
#[inline]
pub fn value(&self) -> VALUER {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
VALUER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - 16-bit reload value for the DAC interrupt/DMA timer."]
#[inline]
pub fn value(&mut self) -> _VALUEW {
_VALUEW { w: self }
}
}
}
}
#[doc = "TIMER2"]
pub struct TIMER2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMER2 {}
impl TIMER2 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const timer0::RegisterBlock {
0x4009_0000 as *const _
}
}
impl Deref for TIMER2 {
type Target = timer0::RegisterBlock;
fn deref(&self) -> &timer0::RegisterBlock {
unsafe { &*TIMER2::ptr() }
}
}
#[doc = "TIMER3"]
pub struct TIMER3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMER3 {}
impl TIMER3 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const timer0::RegisterBlock {
0x4009_4000 as *const _
}
}
impl Deref for TIMER3 {
type Target = timer0::RegisterBlock;
fn deref(&self) -> &timer0::RegisterBlock {
unsafe { &*TIMER3::ptr() }
}
}
#[doc = "UART2"]
pub struct UART2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART2 {}
impl UART2 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const uart0::RegisterBlock {
0x4009_8000 as *const _
}
}
impl Deref for UART2 {
type Target = uart0::RegisterBlock;
fn deref(&self) -> &uart0::RegisterBlock {
unsafe { &*UART2::ptr() }
}
}
#[doc = "UART3"]
pub struct UART3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART3 {}
impl UART3 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const uart0::RegisterBlock {
0x4009_c000 as *const _
}
}
impl Deref for UART3 {
type Target = uart0::RegisterBlock;
fn deref(&self) -> &uart0::RegisterBlock {
unsafe { &*UART3::ptr() }
}
}
#[doc = "I2C2"]
pub struct I2C2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C2 {}
impl I2C2 {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const i2c0::RegisterBlock {
0x400a_0000 as *const _
}
}
impl Deref for I2C2 {
type Target = i2c0::RegisterBlock;
fn deref(&self) -> &i2c0::RegisterBlock {
unsafe { &*I2C2::ptr() }
}
}
#[doc = "I2S interface"]
pub struct I2S {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2S {}
impl I2S {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const i2s::RegisterBlock {
0x400a_8000 as *const _
}
}
impl Deref for I2S {
type Target = i2s::RegisterBlock;
fn deref(&self) -> &i2s::RegisterBlock {
unsafe { &*I2S::ptr() }
}
}
#[doc = "I2S interface"]
pub mod i2s {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel."]
pub dao: DAO,
#[doc = "0x04 - I2S Digital Audio Input Register. Contains control bits for the I2S receive channel."]
pub dai: DAI,
#[doc = "0x08 - I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO."]
pub txfifo: TXFIFO,
#[doc = "0x0c - I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO."]
pub rxfifo: RXFIFO,
#[doc = "0x10 - I2S Status Feedback Register. Contains status information about the I2S interface."]
pub state: STATE,
#[doc = "0x14 - I2S DMA Configuration Register 1. Contains control information for DMA request 1."]
pub dma1: DMA1,
#[doc = "0x18 - I2S DMA Configuration Register 2. Contains control information for DMA request 2."]
pub dma2: DMA2,
#[doc = "0x1c - I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated."]
pub irq: IRQ,
#[doc = "0x20 - I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
pub txrate: TXRATE,
#[doc = "0x24 - I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
pub rxrate: RXRATE,
#[doc = "0x28 - I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock."]
pub txbitrate: TXBITRATE,
#[doc = "0x2c - I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock."]
pub rxbitrate: RXBITRATE,
#[doc = "0x30 - I2S Transmit mode control."]
pub txmode: TXMODE,
#[doc = "0x34 - I2S Receive mode control."]
pub rxmode: RXMODE,
}
#[doc = "I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel."]
pub struct DAO {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel."]
pub mod dao {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DAO {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `WORDWIDTH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WORDWIDTHR {
#[doc = "8-bit data"]
_8_BIT_DATA,
#[doc = "16-bit data"]
_16_BIT_DATA,
#[doc = "32-bit data"]
_32_BIT_DATA,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl WORDWIDTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
WORDWIDTHR::_8_BIT_DATA => 0,
WORDWIDTHR::_16_BIT_DATA => 0x01,
WORDWIDTHR::_32_BIT_DATA => 0x03,
WORDWIDTHR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> WORDWIDTHR {
match value {
0 => WORDWIDTHR::_8_BIT_DATA,
1 => WORDWIDTHR::_16_BIT_DATA,
3 => WORDWIDTHR::_32_BIT_DATA,
i => WORDWIDTHR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_8_BIT_DATA`"]
#[inline]
pub fn is_8_bit_data(&self) -> bool {
*self == WORDWIDTHR::_8_BIT_DATA
}
#[doc = "Checks if the value of the field is `_16_BIT_DATA`"]
#[inline]
pub fn is_16_bit_data(&self) -> bool {
*self == WORDWIDTHR::_16_BIT_DATA
}
#[doc = "Checks if the value of the field is `_32_BIT_DATA`"]
#[inline]
pub fn is_32_bit_data(&self) -> bool {
*self == WORDWIDTHR::_32_BIT_DATA
}
}
#[doc = r" Value of the field"]
pub struct MONOR {
bits: bool,
}
impl MONOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct STOPR {
bits: bool,
}
impl STOPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RESETR {
bits: bool,
}
impl RESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WS_SELR {
bits: bool,
}
impl WS_SELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WS_HALFPERIODR {
bits: u16,
}
impl WS_HALFPERIODR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MUTER {
bits: bool,
}
impl MUTER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `WORDWIDTH`"]
pub enum WORDWIDTHW {
#[doc = "8-bit data"]
_8_BIT_DATA,
#[doc = "16-bit data"]
_16_BIT_DATA,
#[doc = "32-bit data"]
_32_BIT_DATA,
}
impl WORDWIDTHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
WORDWIDTHW::_8_BIT_DATA => 0,
WORDWIDTHW::_16_BIT_DATA => 1,
WORDWIDTHW::_32_BIT_DATA => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _WORDWIDTHW<'a> {
w: &'a mut W,
}
impl<'a> _WORDWIDTHW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WORDWIDTHW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "8-bit data"]
#[inline]
pub fn _8_bit_data(self) -> &'a mut W {
self.variant(WORDWIDTHW::_8_BIT_DATA)
}
#[doc = "16-bit data"]
#[inline]
pub fn _16_bit_data(self) -> &'a mut W {
self.variant(WORDWIDTHW::_16_BIT_DATA)
}
#[doc = "32-bit data"]
#[inline]
pub fn _32_bit_data(self) -> &'a mut W {
self.variant(WORDWIDTHW::_32_BIT_DATA)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MONOW<'a> {
w: &'a mut W,
}
impl<'a> _MONOW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STOPW<'a> {
w: &'a mut W,
}
impl<'a> _STOPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETW<'a> {
w: &'a mut W,
}
impl<'a> _RESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WS_SELW<'a> {
w: &'a mut W,
}
impl<'a> _WS_SELW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WS_HALFPERIODW<'a> {
w: &'a mut W,
}
impl<'a> _WS_HALFPERIODW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MUTEW<'a> {
w: &'a mut W,
}
impl<'a> _MUTEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Selects the number of bytes in data as follows:"]
#[inline]
pub fn wordwidth(&self) -> WORDWIDTHR {
WORDWIDTHR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
#[inline]
pub fn mono(&self) -> MONOR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MONOR { bits }
}
#[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
#[inline]
pub fn stop(&self) -> STOPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
STOPR { bits }
}
#[doc = "Bit 4 - When 1, asynchronously resets the transmit channel and FIFO."]
#[inline]
pub fn reset(&self) -> RESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETR { bits }
}
#[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE."]
#[inline]
pub fn ws_sel(&self) -> WS_SELR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WS_SELR { bits }
}
#[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
#[inline]
pub fn ws_halfperiod(&self) -> WS_HALFPERIODR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u16
};
WS_HALFPERIODR { bits }
}
#[doc = "Bit 15 - When 1, the transmit channel sends only zeroes."]
#[inline]
pub fn mute(&self) -> MUTER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MUTER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x87e1 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Selects the number of bytes in data as follows:"]
#[inline]
pub fn wordwidth(&mut self) -> _WORDWIDTHW {
_WORDWIDTHW { w: self }
}
#[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
#[inline]
pub fn mono(&mut self) -> _MONOW {
_MONOW { w: self }
}
#[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
#[inline]
pub fn stop(&mut self) -> _STOPW {
_STOPW { w: self }
}
#[doc = "Bit 4 - When 1, asynchronously resets the transmit channel and FIFO."]
#[inline]
pub fn reset(&mut self) -> _RESETW {
_RESETW { w: self }
}
#[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE."]
#[inline]
pub fn ws_sel(&mut self) -> _WS_SELW {
_WS_SELW { w: self }
}
#[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
#[inline]
pub fn ws_halfperiod(&mut self) -> _WS_HALFPERIODW {
_WS_HALFPERIODW { w: self }
}
#[doc = "Bit 15 - When 1, the transmit channel sends only zeroes."]
#[inline]
pub fn mute(&mut self) -> _MUTEW {
_MUTEW { w: self }
}
}
}
#[doc = "I2S Digital Audio Input Register. Contains control bits for the I2S receive channel."]
pub struct DAI {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Digital Audio Input Register. Contains control bits for the I2S receive channel."]
pub mod dai {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DAI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `WORDWIDTH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WORDWIDTHR {
#[doc = "8-bit data"]
_8_BIT_DATA,
#[doc = "16-bit data"]
_16_BIT_DATA,
#[doc = "32-bit data"]
_32_BIT_DATA,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl WORDWIDTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
WORDWIDTHR::_8_BIT_DATA => 0,
WORDWIDTHR::_16_BIT_DATA => 0x01,
WORDWIDTHR::_32_BIT_DATA => 0x03,
WORDWIDTHR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> WORDWIDTHR {
match value {
0 => WORDWIDTHR::_8_BIT_DATA,
1 => WORDWIDTHR::_16_BIT_DATA,
3 => WORDWIDTHR::_32_BIT_DATA,
i => WORDWIDTHR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_8_BIT_DATA`"]
#[inline]
pub fn is_8_bit_data(&self) -> bool {
*self == WORDWIDTHR::_8_BIT_DATA
}
#[doc = "Checks if the value of the field is `_16_BIT_DATA`"]
#[inline]
pub fn is_16_bit_data(&self) -> bool {
*self == WORDWIDTHR::_16_BIT_DATA
}
#[doc = "Checks if the value of the field is `_32_BIT_DATA`"]
#[inline]
pub fn is_32_bit_data(&self) -> bool {
*self == WORDWIDTHR::_32_BIT_DATA
}
}
#[doc = r" Value of the field"]
pub struct MONOR {
bits: bool,
}
impl MONOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct STOPR {
bits: bool,
}
impl STOPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RESETR {
bits: bool,
}
impl RESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WS_SELR {
bits: bool,
}
impl WS_SELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WS_HALFPERIODR {
bits: u16,
}
impl WS_HALFPERIODR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = "Values that can be written to the field `WORDWIDTH`"]
pub enum WORDWIDTHW {
#[doc = "8-bit data"]
_8_BIT_DATA,
#[doc = "16-bit data"]
_16_BIT_DATA,
#[doc = "32-bit data"]
_32_BIT_DATA,
}
impl WORDWIDTHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
WORDWIDTHW::_8_BIT_DATA => 0,
WORDWIDTHW::_16_BIT_DATA => 1,
WORDWIDTHW::_32_BIT_DATA => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _WORDWIDTHW<'a> {
w: &'a mut W,
}
impl<'a> _WORDWIDTHW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WORDWIDTHW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "8-bit data"]
#[inline]
pub fn _8_bit_data(self) -> &'a mut W {
self.variant(WORDWIDTHW::_8_BIT_DATA)
}
#[doc = "16-bit data"]
#[inline]
pub fn _16_bit_data(self) -> &'a mut W {
self.variant(WORDWIDTHW::_16_BIT_DATA)
}
#[doc = "32-bit data"]
#[inline]
pub fn _32_bit_data(self) -> &'a mut W {
self.variant(WORDWIDTHW::_32_BIT_DATA)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MONOW<'a> {
w: &'a mut W,
}
impl<'a> _MONOW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STOPW<'a> {
w: &'a mut W,
}
impl<'a> _STOPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETW<'a> {
w: &'a mut W,
}
impl<'a> _RESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WS_SELW<'a> {
w: &'a mut W,
}
impl<'a> _WS_SELW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WS_HALFPERIODW<'a> {
w: &'a mut W,
}
impl<'a> _WS_HALFPERIODW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Selects the number of bytes in data as follows:"]
#[inline]
pub fn wordwidth(&self) -> WORDWIDTHR {
WORDWIDTHR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
#[inline]
pub fn mono(&self) -> MONOR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MONOR { bits }
}
#[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
#[inline]
pub fn stop(&self) -> STOPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
STOPR { bits }
}
#[doc = "Bit 4 - When 1, asynchronously reset the transmit channel and FIFO."]
#[inline]
pub fn reset(&self) -> RESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETR { bits }
}
#[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE."]
#[inline]
pub fn ws_sel(&self) -> WS_SELR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WS_SELR { bits }
}
#[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
#[inline]
pub fn ws_halfperiod(&self) -> WS_HALFPERIODR {
let bits = {
const MASK: u16 = 0x01ff;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u16
};
WS_HALFPERIODR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x07e1 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Selects the number of bytes in data as follows:"]
#[inline]
pub fn wordwidth(&mut self) -> _WORDWIDTHW {
_WORDWIDTHW { w: self }
}
#[doc = "Bit 2 - When 1, data is of monaural format. When 0, the data is in stereo format."]
#[inline]
pub fn mono(&mut self) -> _MONOW {
_MONOW { w: self }
}
#[doc = "Bit 3 - When 1, disables accesses on FIFOs, places the transmit channel in mute mode."]
#[inline]
pub fn stop(&mut self) -> _STOPW {
_STOPW { w: self }
}
#[doc = "Bit 4 - When 1, asynchronously reset the transmit channel and FIFO."]
#[inline]
pub fn reset(&mut self) -> _RESETW {
_RESETW { w: self }
}
#[doc = "Bit 5 - When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE."]
#[inline]
pub fn ws_sel(&mut self) -> _WS_SELW {
_WS_SELW { w: self }
}
#[doc = "Bits 6:14 - Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31."]
#[inline]
pub fn ws_halfperiod(&mut self) -> _WS_HALFPERIODW {
_WS_HALFPERIODW { w: self }
}
}
}
#[doc = "I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO."]
pub struct TXFIFO {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO."]
pub mod txfifo {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXFIFO {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _I2STXFIFOW<'a> {
w: &'a mut W,
}
impl<'a> _I2STXFIFOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - 8 x 32-bit transmit FIFO."]
#[inline]
pub fn i2stxfifo(&mut self) -> _I2STXFIFOW {
_I2STXFIFOW { w: self }
}
}
}
#[doc = "I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO."]
pub struct RXFIFO {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO."]
pub mod rxfifo {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RXFIFO {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct I2SRXFIFOR {
bits: u32,
}
impl I2SRXFIFOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - 8 x 32-bit transmit FIFO."]
#[inline]
pub fn i2srxfifo(&self) -> I2SRXFIFOR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
I2SRXFIFOR { bits }
}
}
}
#[doc = "I2S Status Feedback Register. Contains status information about the I2S interface."]
pub struct STATE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Status Feedback Register. Contains status information about the I2S interface."]
pub mod state {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct IRQR {
bits: bool,
}
impl IRQR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMAREQ1R {
bits: bool,
}
impl DMAREQ1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMAREQ2R {
bits: bool,
}
impl DMAREQ2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RX_LEVELR {
bits: u8,
}
impl RX_LEVELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TX_LEVELR {
bits: u8,
}
impl TX_LEVELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register."]
#[inline]
pub fn irq(&self) -> IRQR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IRQR { bits }
}
#[doc = "Bit 1 - This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register."]
#[inline]
pub fn dmareq1(&self) -> DMAREQ1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMAREQ1R { bits }
}
#[doc = "Bit 2 - This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register."]
#[inline]
pub fn dmareq2(&self) -> DMAREQ2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMAREQ2R { bits }
}
#[doc = "Bits 8:11 - Reflects the current level of the Receive FIFO."]
#[inline]
pub fn rx_level(&self) -> RX_LEVELR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RX_LEVELR { bits }
}
#[doc = "Bits 16:19 - Reflects the current level of the Transmit FIFO."]
#[inline]
pub fn tx_level(&self) -> TX_LEVELR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TX_LEVELR { bits }
}
}
}
#[doc = "I2S DMA Configuration Register 1. Contains control information for DMA request 1."]
pub struct DMA1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S DMA Configuration Register 1. Contains control information for DMA request 1."]
pub mod dma1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMA1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RX_DMA1_ENABLER {
bits: bool,
}
impl RX_DMA1_ENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TX_DMA1_ENABLER {
bits: bool,
}
impl TX_DMA1_ENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RX_DEPTH_DMA1R {
bits: u8,
}
impl RX_DEPTH_DMA1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TX_DEPTH_DMA1R {
bits: u8,
}
impl TX_DEPTH_DMA1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RX_DMA1_ENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _RX_DMA1_ENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX_DMA1_ENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _TX_DMA1_ENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RX_DEPTH_DMA1W<'a> {
w: &'a mut W,
}
impl<'a> _RX_DEPTH_DMA1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX_DEPTH_DMA1W<'a> {
w: &'a mut W,
}
impl<'a> _TX_DEPTH_DMA1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, enables DMA1 for I2S receive."]
#[inline]
pub fn rx_dma1_enable(&self) -> RX_DMA1_ENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RX_DMA1_ENABLER { bits }
}
#[doc = "Bit 1 - When 1, enables DMA1 for I2S transmit."]
#[inline]
pub fn tx_dma1_enable(&self) -> TX_DMA1_ENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TX_DMA1_ENABLER { bits }
}
#[doc = "Bits 8:11 - Set the FIFO level that triggers a receive DMA request on DMA1."]
#[inline]
pub fn rx_depth_dma1(&self) -> RX_DEPTH_DMA1R {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RX_DEPTH_DMA1R { bits }
}
#[doc = "Bits 16:19 - Set the FIFO level that triggers a transmit DMA request on DMA1."]
#[inline]
pub fn tx_depth_dma1(&self) -> TX_DEPTH_DMA1R {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TX_DEPTH_DMA1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When 1, enables DMA1 for I2S receive."]
#[inline]
pub fn rx_dma1_enable(&mut self) -> _RX_DMA1_ENABLEW {
_RX_DMA1_ENABLEW { w: self }
}
#[doc = "Bit 1 - When 1, enables DMA1 for I2S transmit."]
#[inline]
pub fn tx_dma1_enable(&mut self) -> _TX_DMA1_ENABLEW {
_TX_DMA1_ENABLEW { w: self }
}
#[doc = "Bits 8:11 - Set the FIFO level that triggers a receive DMA request on DMA1."]
#[inline]
pub fn rx_depth_dma1(&mut self) -> _RX_DEPTH_DMA1W {
_RX_DEPTH_DMA1W { w: self }
}
#[doc = "Bits 16:19 - Set the FIFO level that triggers a transmit DMA request on DMA1."]
#[inline]
pub fn tx_depth_dma1(&mut self) -> _TX_DEPTH_DMA1W {
_TX_DEPTH_DMA1W { w: self }
}
}
}
#[doc = "I2S DMA Configuration Register 2. Contains control information for DMA request 2."]
pub struct DMA2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S DMA Configuration Register 2. Contains control information for DMA request 2."]
pub mod dma2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMA2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RX_DMA2_ENABLER {
bits: bool,
}
impl RX_DMA2_ENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TX_DMA2_ENABLER {
bits: bool,
}
impl TX_DMA2_ENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RX_DEPTH_DMA2R {
bits: u8,
}
impl RX_DEPTH_DMA2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TX_DEPTH_DMA2R {
bits: u8,
}
impl TX_DEPTH_DMA2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RX_DMA2_ENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _RX_DMA2_ENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX_DMA2_ENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _TX_DMA2_ENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RX_DEPTH_DMA2W<'a> {
w: &'a mut W,
}
impl<'a> _RX_DEPTH_DMA2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX_DEPTH_DMA2W<'a> {
w: &'a mut W,
}
impl<'a> _TX_DEPTH_DMA2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, enables DMA1 for I2S receive."]
#[inline]
pub fn rx_dma2_enable(&self) -> RX_DMA2_ENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RX_DMA2_ENABLER { bits }
}
#[doc = "Bit 1 - When 1, enables DMA1 for I2S transmit."]
#[inline]
pub fn tx_dma2_enable(&self) -> TX_DMA2_ENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TX_DMA2_ENABLER { bits }
}
#[doc = "Bits 8:11 - Set the FIFO level that triggers a receive DMA request on DMA2."]
#[inline]
pub fn rx_depth_dma2(&self) -> RX_DEPTH_DMA2R {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RX_DEPTH_DMA2R { bits }
}
#[doc = "Bits 16:19 - Set the FIFO level that triggers a transmit DMA request on DMA2."]
#[inline]
pub fn tx_depth_dma2(&self) -> TX_DEPTH_DMA2R {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TX_DEPTH_DMA2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When 1, enables DMA1 for I2S receive."]
#[inline]
pub fn rx_dma2_enable(&mut self) -> _RX_DMA2_ENABLEW {
_RX_DMA2_ENABLEW { w: self }
}
#[doc = "Bit 1 - When 1, enables DMA1 for I2S transmit."]
#[inline]
pub fn tx_dma2_enable(&mut self) -> _TX_DMA2_ENABLEW {
_TX_DMA2_ENABLEW { w: self }
}
#[doc = "Bits 8:11 - Set the FIFO level that triggers a receive DMA request on DMA2."]
#[inline]
pub fn rx_depth_dma2(&mut self) -> _RX_DEPTH_DMA2W {
_RX_DEPTH_DMA2W { w: self }
}
#[doc = "Bits 16:19 - Set the FIFO level that triggers a transmit DMA request on DMA2."]
#[inline]
pub fn tx_depth_dma2(&mut self) -> _TX_DEPTH_DMA2W {
_TX_DEPTH_DMA2W { w: self }
}
}
}
#[doc = "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated."]
pub struct IRQ {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated."]
pub mod irq {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IRQ {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RX_IRQ_ENABLER {
bits: bool,
}
impl RX_IRQ_ENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TX_IRQ_ENABLER {
bits: bool,
}
impl TX_IRQ_ENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RX_DEPTH_IRQR {
bits: u8,
}
impl RX_DEPTH_IRQR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TX_DEPTH_IRQR {
bits: u8,
}
impl TX_DEPTH_IRQR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RX_IRQ_ENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _RX_IRQ_ENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX_IRQ_ENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _TX_IRQ_ENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RX_DEPTH_IRQW<'a> {
w: &'a mut W,
}
impl<'a> _RX_DEPTH_IRQW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX_DEPTH_IRQW<'a> {
w: &'a mut W,
}
impl<'a> _TX_DEPTH_IRQW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, enables I2S receive interrupt."]
#[inline]
pub fn rx_irq_enable(&self) -> RX_IRQ_ENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RX_IRQ_ENABLER { bits }
}
#[doc = "Bit 1 - When 1, enables I2S transmit interrupt."]
#[inline]
pub fn tx_irq_enable(&self) -> TX_IRQ_ENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TX_IRQ_ENABLER { bits }
}
#[doc = "Bits 8:11 - Set the FIFO level on which to create an irq request."]
#[inline]
pub fn rx_depth_irq(&self) -> RX_DEPTH_IRQR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RX_DEPTH_IRQR { bits }
}
#[doc = "Bits 16:19 - Set the FIFO level on which to create an irq request."]
#[inline]
pub fn tx_depth_irq(&self) -> TX_DEPTH_IRQR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TX_DEPTH_IRQR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When 1, enables I2S receive interrupt."]
#[inline]
pub fn rx_irq_enable(&mut self) -> _RX_IRQ_ENABLEW {
_RX_IRQ_ENABLEW { w: self }
}
#[doc = "Bit 1 - When 1, enables I2S transmit interrupt."]
#[inline]
pub fn tx_irq_enable(&mut self) -> _TX_IRQ_ENABLEW {
_TX_IRQ_ENABLEW { w: self }
}
#[doc = "Bits 8:11 - Set the FIFO level on which to create an irq request."]
#[inline]
pub fn rx_depth_irq(&mut self) -> _RX_DEPTH_IRQW {
_RX_DEPTH_IRQW { w: self }
}
#[doc = "Bits 16:19 - Set the FIFO level on which to create an irq request."]
#[inline]
pub fn tx_depth_irq(&mut self) -> _TX_DEPTH_IRQW {
_TX_DEPTH_IRQW { w: self }
}
}
}
#[doc = "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
pub struct TXRATE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
pub mod txrate {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXRATE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct Y_DIVIDERR {
bits: u8,
}
impl Y_DIVIDERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct X_DIVIDERR {
bits: u8,
}
impl X_DIVIDERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _Y_DIVIDERW<'a> {
w: &'a mut W,
}
impl<'a> _Y_DIVIDERW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _X_DIVIDERW<'a> {
w: &'a mut W,
}
impl<'a> _X_DIVIDERW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
#[inline]
pub fn y_divider(&self) -> Y_DIVIDERR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
Y_DIVIDERR { bits }
}
#[doc = "Bits 8:15 - I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
#[inline]
pub fn x_divider(&self) -> X_DIVIDERR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
X_DIVIDERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
#[inline]
pub fn y_divider(&mut self) -> _Y_DIVIDERW {
_Y_DIVIDERW { w: self }
}
#[doc = "Bits 8:15 - I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
#[inline]
pub fn x_divider(&mut self) -> _X_DIVIDERW {
_X_DIVIDERW { w: self }
}
}
}
#[doc = "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
pub struct RXRATE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK."]
pub mod rxrate {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXRATE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct Y_DIVIDERR {
bits: u8,
}
impl Y_DIVIDERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct X_DIVIDERR {
bits: u8,
}
impl X_DIVIDERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _Y_DIVIDERW<'a> {
w: &'a mut W,
}
impl<'a> _Y_DIVIDERW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _X_DIVIDERW<'a> {
w: &'a mut W,
}
impl<'a> _X_DIVIDERW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
#[inline]
pub fn y_divider(&self) -> Y_DIVIDERR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
Y_DIVIDERR { bits }
}
#[doc = "Bits 8:15 - I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
#[inline]
pub fn x_divider(&self) -> X_DIVIDERR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
X_DIVIDERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock."]
#[inline]
pub fn y_divider(&mut self) -> _Y_DIVIDERW {
_Y_DIVIDERW { w: self }
}
#[doc = "Bits 8:15 - I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2."]
#[inline]
pub fn x_divider(&mut self) -> _X_DIVIDERW {
_X_DIVIDERW { w: self }
}
}
}
#[doc = "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock."]
pub struct TXBITRATE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock."]
pub mod txbitrate {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXBITRATE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TX_BITRATER {
bits: u8,
}
impl TX_BITRATER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TX_BITRATEW<'a> {
w: &'a mut W,
}
impl<'a> _TX_BITRATEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock."]
#[inline]
pub fn tx_bitrate(&self) -> TX_BITRATER {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TX_BITRATER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock."]
#[inline]
pub fn tx_bitrate(&mut self) -> _TX_BITRATEW {
_TX_BITRATEW { w: self }
}
}
}
#[doc = "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock."]
pub struct RXBITRATE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock."]
pub mod rxbitrate {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXBITRATE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RX_BITRATER {
bits: u8,
}
impl RX_BITRATER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RX_BITRATEW<'a> {
w: &'a mut W,
}
impl<'a> _RX_BITRATEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock."]
#[inline]
pub fn rx_bitrate(&self) -> RX_BITRATER {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RX_BITRATER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock."]
#[inline]
pub fn rx_bitrate(&mut self) -> _RX_BITRATEW {
_RX_BITRATEW { w: self }
}
}
}
#[doc = "I2S Transmit mode control."]
pub struct TXMODE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Transmit mode control."]
pub mod txmode {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXMODE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TXCLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TXCLKSELR {
#[doc = "Select the TX fractional rate divider clock output as the source"]
SELECT_THE_TX_FRACTI,
#[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"]
SELECT_THE_RX_MCLK_S,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TXCLKSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TXCLKSELR::SELECT_THE_TX_FRACTI => 0,
TXCLKSELR::SELECT_THE_RX_MCLK_S => 0x02,
TXCLKSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TXCLKSELR {
match value {
0 => TXCLKSELR::SELECT_THE_TX_FRACTI,
2 => TXCLKSELR::SELECT_THE_RX_MCLK_S,
i => TXCLKSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `SELECT_THE_TX_FRACTI`"]
#[inline]
pub fn is_select_the_tx_fracti(&self) -> bool {
*self == TXCLKSELR::SELECT_THE_TX_FRACTI
}
#[doc = "Checks if the value of the field is `SELECT_THE_RX_MCLK_S`"]
#[inline]
pub fn is_select_the_rx_mclk_s(&self) -> bool {
*self == TXCLKSELR::SELECT_THE_RX_MCLK_S
}
}
#[doc = r" Value of the field"]
pub struct TX4PINR {
bits: bool,
}
impl TX4PINR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXMCENAR {
bits: bool,
}
impl TXMCENAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `TXCLKSEL`"]
pub enum TXCLKSELW {
#[doc = "Select the TX fractional rate divider clock output as the source"]
SELECT_THE_TX_FRACTI,
#[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"]
SELECT_THE_RX_MCLK_S,
}
impl TXCLKSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
TXCLKSELW::SELECT_THE_TX_FRACTI => 0,
TXCLKSELW::SELECT_THE_RX_MCLK_S => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _TXCLKSELW<'a> {
w: &'a mut W,
}
impl<'a> _TXCLKSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TXCLKSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Select the TX fractional rate divider clock output as the source"]
#[inline]
pub fn select_the_tx_fracti(self) -> &'a mut W {
self.variant(TXCLKSELW::SELECT_THE_TX_FRACTI)
}
#[doc = "Select the RX_MCLK signal as the TX_MCLK clock source"]
#[inline]
pub fn select_the_rx_mclk_s(self) -> &'a mut W {
self.variant(TXCLKSELW::SELECT_THE_RX_MCLK_S)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TX4PINW<'a> {
w: &'a mut W,
}
impl<'a> _TX4PINW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXMCENAW<'a> {
w: &'a mut W,
}
impl<'a> _TXMCENAW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Clock source selection for the transmit bit clock divider."]
#[inline]
pub fn txclksel(&self) -> TXCLKSELR {
TXCLKSELR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Transmit 4-pin mode selection. When 1, enables 4-pin mode."]
#[inline]
pub fn tx4pin(&self) -> TX4PINR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TX4PINR { bits }
}
#[doc = "Bit 3 - Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled."]
#[inline]
pub fn txmcena(&self) -> TXMCENAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXMCENAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Clock source selection for the transmit bit clock divider."]
#[inline]
pub fn txclksel(&mut self) -> _TXCLKSELW {
_TXCLKSELW { w: self }
}
#[doc = "Bit 2 - Transmit 4-pin mode selection. When 1, enables 4-pin mode."]
#[inline]
pub fn tx4pin(&mut self) -> _TX4PINW {
_TX4PINW { w: self }
}
#[doc = "Bit 3 - Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled."]
#[inline]
pub fn txmcena(&mut self) -> _TXMCENAW {
_TXMCENAW { w: self }
}
}
}
#[doc = "I2S Receive mode control."]
pub struct RXMODE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2S Receive mode control."]
pub mod rxmode {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXMODE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RXCLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RXCLKSELR {
#[doc = "Select the RX fractional rate divider clock output as the source"]
SELECT_THE_RX_FRACTI,
#[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"]
SELECT_THE_TX_MCLK_S,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl RXCLKSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
RXCLKSELR::SELECT_THE_RX_FRACTI => 0,
RXCLKSELR::SELECT_THE_TX_MCLK_S => 0x02,
RXCLKSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> RXCLKSELR {
match value {
0 => RXCLKSELR::SELECT_THE_RX_FRACTI,
2 => RXCLKSELR::SELECT_THE_TX_MCLK_S,
i => RXCLKSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `SELECT_THE_RX_FRACTI`"]
#[inline]
pub fn is_select_the_rx_fracti(&self) -> bool {
*self == RXCLKSELR::SELECT_THE_RX_FRACTI
}
#[doc = "Checks if the value of the field is `SELECT_THE_TX_MCLK_S`"]
#[inline]
pub fn is_select_the_tx_mclk_s(&self) -> bool {
*self == RXCLKSELR::SELECT_THE_TX_MCLK_S
}
}
#[doc = r" Value of the field"]
pub struct RX4PINR {
bits: bool,
}
impl RX4PINR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXMCENAR {
bits: bool,
}
impl RXMCENAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `RXCLKSEL`"]
pub enum RXCLKSELW {
#[doc = "Select the RX fractional rate divider clock output as the source"]
SELECT_THE_RX_FRACTI,
#[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"]
SELECT_THE_TX_MCLK_S,
}
impl RXCLKSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
RXCLKSELW::SELECT_THE_RX_FRACTI => 0,
RXCLKSELW::SELECT_THE_TX_MCLK_S => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _RXCLKSELW<'a> {
w: &'a mut W,
}
impl<'a> _RXCLKSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RXCLKSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Select the RX fractional rate divider clock output as the source"]
#[inline]
pub fn select_the_rx_fracti(self) -> &'a mut W {
self.variant(RXCLKSELW::SELECT_THE_RX_FRACTI)
}
#[doc = "Select the TX_MCLK signal as the RX_MCLK clock source"]
#[inline]
pub fn select_the_tx_mclk_s(self) -> &'a mut W {
self.variant(RXCLKSELW::SELECT_THE_TX_MCLK_S)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RX4PINW<'a> {
w: &'a mut W,
}
impl<'a> _RX4PINW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXMCENAW<'a> {
w: &'a mut W,
}
impl<'a> _RXMCENAW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Clock source selection for the receive bit clock divider."]
#[inline]
pub fn rxclksel(&self) -> RXCLKSELR {
RXCLKSELR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Receive 4-pin mode selection. When 1, enables 4-pin mode."]
#[inline]
pub fn rx4pin(&self) -> RX4PINR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RX4PINR { bits }
}
#[doc = "Bit 3 - Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled."]
#[inline]
pub fn rxmcena(&self) -> RXMCENAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXMCENAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Clock source selection for the receive bit clock divider."]
#[inline]
pub fn rxclksel(&mut self) -> _RXCLKSELW {
_RXCLKSELW { w: self }
}
#[doc = "Bit 2 - Receive 4-pin mode selection. When 1, enables 4-pin mode."]
#[inline]
pub fn rx4pin(&mut self) -> _RX4PINW {
_RX4PINW { w: self }
}
#[doc = "Bit 3 - Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled."]
#[inline]
pub fn rxmcena(&mut self) -> _RXMCENAW {
_RXMCENAW { w: self }
}
}
}
}
#[doc = "Repetitive Interrupt Timer (RIT)"]
pub struct RITIMER {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RITIMER {}
impl RITIMER {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const ritimer::RegisterBlock {
0x400b_0000 as *const _
}
}
impl Deref for RITIMER {
type Target = ritimer::RegisterBlock;
fn deref(&self) -> &ritimer::RegisterBlock {
unsafe { &*RITIMER::ptr() }
}
}
#[doc = "Repetitive Interrupt Timer (RIT)"]
pub mod ritimer {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Compare register"]
pub compval: COMPVAL,
#[doc = "0x04 - Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register."]
pub mask: MASK,
#[doc = "0x08 - Control register."]
pub ctrl: CTRL,
#[doc = "0x0c - 32-bit counter"]
pub counter: COUNTER,
}
#[doc = "Compare register"]
pub struct COMPVAL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Compare register"]
pub mod compval {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::COMPVAL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RICOMPR {
bits: u32,
}
impl RICOMPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RICOMPW<'a> {
w: &'a mut W,
}
impl<'a> _RICOMPW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Compare register. Holds the compare value which is compared to the counter."]
#[inline]
pub fn ricomp(&self) -> RICOMPR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
RICOMPR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xffff_ffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Compare register. Holds the compare value which is compared to the counter."]
#[inline]
pub fn ricomp(&mut self) -> _RICOMPW {
_RICOMPW { w: self }
}
}
}
#[doc = "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register."]
pub struct MASK {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register."]
pub mod mask {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MASK {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RIMASKR {
bits: u32,
}
impl RIMASKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RIMASKW<'a> {
w: &'a mut W,
}
impl<'a> _RIMASKW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)."]
#[inline]
pub fn rimask(&self) -> RIMASKR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
RIMASKR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)."]
#[inline]
pub fn rimask(&mut self) -> _RIMASKW {
_RIMASKW { w: self }
}
}
}
#[doc = "Control register."]
pub struct CTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control register."]
pub mod ctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RITINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RITINTR {
#[doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect."]
THIS_BIT_IS_SET_TO_1,
#[doc = "The counter value does not equal the masked compare value."]
THE_COUNTER_VALUE_DO,
}
impl RITINTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RITINTR::THIS_BIT_IS_SET_TO_1 => true,
RITINTR::THE_COUNTER_VALUE_DO => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RITINTR {
match value {
true => RITINTR::THIS_BIT_IS_SET_TO_1,
false => RITINTR::THE_COUNTER_VALUE_DO,
}
}
#[doc = "Checks if the value of the field is `THIS_BIT_IS_SET_TO_1`"]
#[inline]
pub fn is_this_bit_is_set_to_1(&self) -> bool {
*self == RITINTR::THIS_BIT_IS_SET_TO_1
}
#[doc = "Checks if the value of the field is `THE_COUNTER_VALUE_DO`"]
#[inline]
pub fn is_the_counter_value_do(&self) -> bool {
*self == RITINTR::THE_COUNTER_VALUE_DO
}
}
#[doc = "Possible values of the field `RITENCLR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RITENCLRR {
#[doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag."]
THE_TIMER_WILL_BE_CL,
#[doc = "The timer will not be cleared to 0."]
THE_TIMER_WILL_NOT_B,
}
impl RITENCLRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RITENCLRR::THE_TIMER_WILL_BE_CL => true,
RITENCLRR::THE_TIMER_WILL_NOT_B => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RITENCLRR {
match value {
true => RITENCLRR::THE_TIMER_WILL_BE_CL,
false => RITENCLRR::THE_TIMER_WILL_NOT_B,
}
}
#[doc = "Checks if the value of the field is `THE_TIMER_WILL_BE_CL`"]
#[inline]
pub fn is_the_timer_will_be_cl(&self) -> bool {
*self == RITENCLRR::THE_TIMER_WILL_BE_CL
}
#[doc = "Checks if the value of the field is `THE_TIMER_WILL_NOT_B`"]
#[inline]
pub fn is_the_timer_will_not_b(&self) -> bool {
*self == RITENCLRR::THE_TIMER_WILL_NOT_B
}
}
#[doc = "Possible values of the field `RITENBR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RITENBRR {
#[doc = "The timer is halted when the processor is halted for debugging."]
THE_TIMER_IS_HALTED_,
#[doc = "Debug has no effect on the timer operation."]
DEBUG_HAS_NO_EFFECT_,
}
impl RITENBRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RITENBRR::THE_TIMER_IS_HALTED_ => true,
RITENBRR::DEBUG_HAS_NO_EFFECT_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RITENBRR {
match value {
true => RITENBRR::THE_TIMER_IS_HALTED_,
false => RITENBRR::DEBUG_HAS_NO_EFFECT_,
}
}
#[doc = "Checks if the value of the field is `THE_TIMER_IS_HALTED_`"]
#[inline]
pub fn is_the_timer_is_halted_(&self) -> bool {
*self == RITENBRR::THE_TIMER_IS_HALTED_
}
#[doc = "Checks if the value of the field is `DEBUG_HAS_NO_EFFECT_`"]
#[inline]
pub fn is_debug_has_no_effect_(&self) -> bool {
*self == RITENBRR::DEBUG_HAS_NO_EFFECT_
}
}
#[doc = "Possible values of the field `RITEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RITENR {
#[doc = "Timer enabled. This can be overruled by a debug halt if enabled in bit 2."]
TIMER_ENABLED_THIS_,
#[doc = "Timer disabled."]
TIMER_DISABLED_,
}
impl RITENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RITENR::TIMER_ENABLED_THIS_ => true,
RITENR::TIMER_DISABLED_ => false,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RITENR {
match value {
true => RITENR::TIMER_ENABLED_THIS_,
false => RITENR::TIMER_DISABLED_,
}
}
#[doc = "Checks if the value of the field is `TIMER_ENABLED_THIS_`"]
#[inline]
pub fn is_timer_enabled_this_(&self) -> bool {
*self == RITENR::TIMER_ENABLED_THIS_
}
#[doc = "Checks if the value of the field is `TIMER_DISABLED_`"]
#[inline]
pub fn is_timer_disabled_(&self) -> bool {
*self == RITENR::TIMER_DISABLED_
}
}
#[doc = "Values that can be written to the field `RITINT`"]
pub enum RITINTW {
#[doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect."]
THIS_BIT_IS_SET_TO_1,
#[doc = "The counter value does not equal the masked compare value."]
THE_COUNTER_VALUE_DO,
}
impl RITINTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RITINTW::THIS_BIT_IS_SET_TO_1 => true,
RITINTW::THE_COUNTER_VALUE_DO => false,
}
}
}
#[doc = r" Proxy"]
pub struct _RITINTW<'a> {
w: &'a mut W,
}
impl<'a> _RITINTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RITINTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect."]
#[inline]
pub fn this_bit_is_set_to_1(self) -> &'a mut W {
self.variant(RITINTW::THIS_BIT_IS_SET_TO_1)
}
#[doc = "The counter value does not equal the masked compare value."]
#[inline]
pub fn the_counter_value_do(self) -> &'a mut W {
self.variant(RITINTW::THE_COUNTER_VALUE_DO)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RITENCLR`"]
pub enum RITENCLRW {
#[doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag."]
THE_TIMER_WILL_BE_CL,
#[doc = "The timer will not be cleared to 0."]
THE_TIMER_WILL_NOT_B,
}
impl RITENCLRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RITENCLRW::THE_TIMER_WILL_BE_CL => true,
RITENCLRW::THE_TIMER_WILL_NOT_B => false,
}
}
}
#[doc = r" Proxy"]
pub struct _RITENCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RITENCLRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RITENCLRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag."]
#[inline]
pub fn the_timer_will_be_cl(self) -> &'a mut W {
self.variant(RITENCLRW::THE_TIMER_WILL_BE_CL)
}
#[doc = "The timer will not be cleared to 0."]
#[inline]
pub fn the_timer_will_not_b(self) -> &'a mut W {
self.variant(RITENCLRW::THE_TIMER_WILL_NOT_B)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RITENBR`"]
pub enum RITENBRW {
#[doc = "The timer is halted when the processor is halted for debugging."]
THE_TIMER_IS_HALTED_,
#[doc = "Debug has no effect on the timer operation."]
DEBUG_HAS_NO_EFFECT_,
}
impl RITENBRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RITENBRW::THE_TIMER_IS_HALTED_ => true,
RITENBRW::DEBUG_HAS_NO_EFFECT_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _RITENBRW<'a> {
w: &'a mut W,
}
impl<'a> _RITENBRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RITENBRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The timer is halted when the processor is halted for debugging."]
#[inline]
pub fn the_timer_is_halted_(self) -> &'a mut W {
self.variant(RITENBRW::THE_TIMER_IS_HALTED_)
}
#[doc = "Debug has no effect on the timer operation."]
#[inline]
pub fn debug_has_no_effect_(self) -> &'a mut W {
self.variant(RITENBRW::DEBUG_HAS_NO_EFFECT_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RITEN`"]
pub enum RITENW {
#[doc = "Timer enabled. This can be overruled by a debug halt if enabled in bit 2."]
TIMER_ENABLED_THIS_,
#[doc = "Timer disabled."]
TIMER_DISABLED_,
}
impl RITENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RITENW::TIMER_ENABLED_THIS_ => true,
RITENW::TIMER_DISABLED_ => false,
}
}
}
#[doc = r" Proxy"]
pub struct _RITENW<'a> {
w: &'a mut W,
}
impl<'a> _RITENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RITENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Timer enabled. This can be overruled by a debug halt if enabled in bit 2."]
#[inline]
pub fn timer_enabled_this_(self) -> &'a mut W {
self.variant(RITENW::TIMER_ENABLED_THIS_)
}
#[doc = "Timer disabled."]
#[inline]
pub fn timer_disabled_(self) -> &'a mut W {
self.variant(RITENW::TIMER_DISABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt flag"]
#[inline]
pub fn ritint(&self) -> RITINTR {
RITINTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Timer enable clear"]
#[inline]
pub fn ritenclr(&self) -> RITENCLRR {
RITENCLRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Timer enable for debug"]
#[inline]
pub fn ritenbr(&self) -> RITENBRR {
RITENBRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Timer enable."]
#[inline]
pub fn riten(&self) -> RITENR {
RITENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x0c }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Interrupt flag"]
#[inline]
pub fn ritint(&mut self) -> _RITINTW {
_RITINTW { w: self }
}
#[doc = "Bit 1 - Timer enable clear"]
#[inline]
pub fn ritenclr(&mut self) -> _RITENCLRW {
_RITENCLRW { w: self }
}
#[doc = "Bit 2 - Timer enable for debug"]
#[inline]
pub fn ritenbr(&mut self) -> _RITENBRW {
_RITENBRW { w: self }
}
#[doc = "Bit 3 - Timer enable."]
#[inline]
pub fn riten(&mut self) -> _RITENW {
_RITENW { w: self }
}
}
}
#[doc = "32-bit counter"]
pub struct COUNTER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "32-bit counter"]
pub mod counter {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::COUNTER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RICOUNTERR {
bits: u32,
}
impl RICOUNTERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RICOUNTERW<'a> {
w: &'a mut W,
}
impl<'a> _RICOUNTERW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software."]
#[inline]
pub fn ricounter(&self) -> RICOUNTERR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
RICOUNTERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software."]
#[inline]
pub fn ricounter(&mut self) -> _RICOUNTERW {
_RICOUNTERW { w: self }
}
}
}
}
#[doc = "Motor Control PWM"]
pub struct MCPWM {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for MCPWM {}
impl MCPWM {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const mcpwm::RegisterBlock {
0x400b_8000 as *const _
}
}
impl Deref for MCPWM {
type Target = mcpwm::RegisterBlock;
fn deref(&self) -> &mcpwm::RegisterBlock {
unsafe { &*MCPWM::ptr() }
}
}
#[doc = "Motor Control PWM"]
pub mod mcpwm {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - PWM Control read address"]
pub con: CON,
#[doc = "0x04 - PWM Control set address"]
pub con_set: CON_SET,
#[doc = "0x08 - PWM Control clear address"]
pub con_clr: CON_CLR,
#[doc = "0x0c - Capture Control read address"]
pub capcon: CAPCON,
#[doc = "0x10 - Capture Control set address"]
pub capcon_set: CAPCON_SET,
#[doc = "0x14 - Event Control clear address"]
pub capcon_clr: CAPCON_CLR,
#[doc = "0x18 - Timer Counter register"]
pub tc: [TC; 3],
#[doc = "0x24 - Limit register"]
pub lim: [LIM; 3],
#[doc = "0x30 - Match register"]
pub mat: [MAT; 3],
#[doc = "0x3c - Dead time register"]
pub dt: DT,
#[doc = "0x40 - Communication Pattern register"]
pub cp: CP,
#[doc = "0x44 - Capture register"]
pub cap: [CAP; 3],
#[doc = "0x50 - Interrupt Enable read address"]
pub inten: INTEN,
#[doc = "0x54 - Interrupt Enable set address"]
pub inten_set: INTEN_SET,
#[doc = "0x58 - Interrupt Enable clear address"]
pub inten_clr: INTEN_CLR,
#[doc = "0x5c - Count Control read address"]
pub cntcon: CNTCON,
#[doc = "0x60 - Count Control set address"]
pub cntcon_set: CNTCON_SET,
#[doc = "0x64 - Count Control clear address"]
pub cntcon_clr: CNTCON_CLR,
#[doc = "0x68 - Interrupt flags read address"]
pub intf: INTF,
#[doc = "0x6c - Interrupt flags set address"]
pub intf_set: INTF_SET,
#[doc = "0x70 - Interrupt flags clear address"]
pub intf_clr: INTF_CLR,
#[doc = "0x74 - Capture clear address"]
pub cap_clr: CAP_CLR,
}
#[doc = "PWM Control read address"]
pub struct CON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWM Control read address"]
pub mod con {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CON {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `RUN0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RUN0R {
#[doc = "Stop."]
STOP_,
#[doc = "Run."]
RUN_,
}
impl RUN0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RUN0R::STOP_ => false,
RUN0R::RUN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RUN0R {
match value {
false => RUN0R::STOP_,
true => RUN0R::RUN_,
}
}
#[doc = "Checks if the value of the field is `STOP_`"]
#[inline]
pub fn is_stop_(&self) -> bool {
*self == RUN0R::STOP_
}
#[doc = "Checks if the value of the field is `RUN_`"]
#[inline]
pub fn is_run_(&self) -> bool {
*self == RUN0R::RUN_
}
}
#[doc = "Possible values of the field `CENTER0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CENTER0R {
#[doc = "Edge-aligned."]
EDGE_ALIGNED_,
#[doc = "Center-aligned."]
CENTER_ALIGNED_,
}
impl CENTER0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CENTER0R::EDGE_ALIGNED_ => false,
CENTER0R::CENTER_ALIGNED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CENTER0R {
match value {
false => CENTER0R::EDGE_ALIGNED_,
true => CENTER0R::CENTER_ALIGNED_,
}
}
#[doc = "Checks if the value of the field is `EDGE_ALIGNED_`"]
#[inline]
pub fn is_edge_aligned_(&self) -> bool {
*self == CENTER0R::EDGE_ALIGNED_
}
#[doc = "Checks if the value of the field is `CENTER_ALIGNED_`"]
#[inline]
pub fn is_center_aligned_(&self) -> bool {
*self == CENTER0R::CENTER_ALIGNED_
}
}
#[doc = "Possible values of the field `POLA0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POLA0R {
#[doc = "Passive state is LOW, active state is HIGH."]
PASSIVE_STATE_IS_LOW,
#[doc = "Passive state is HIGH, active state is LOW."]
PASSIVE_STATE_IS_HIG,
}
impl POLA0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
POLA0R::PASSIVE_STATE_IS_LOW => false,
POLA0R::PASSIVE_STATE_IS_HIG => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> POLA0R {
match value {
false => POLA0R::PASSIVE_STATE_IS_LOW,
true => POLA0R::PASSIVE_STATE_IS_HIG,
}
}
#[doc = "Checks if the value of the field is `PASSIVE_STATE_IS_LOW`"]
#[inline]
pub fn is_passive_state_is_low(&self) -> bool {
*self == POLA0R::PASSIVE_STATE_IS_LOW
}
#[doc = "Checks if the value of the field is `PASSIVE_STATE_IS_HIG`"]
#[inline]
pub fn is_passive_state_is_hig(&self) -> bool {
*self == POLA0R::PASSIVE_STATE_IS_HIG
}
}
#[doc = "Possible values of the field `DTE0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTE0R {
#[doc = "Dead-time disabled."]
DEAD_TIME_DISABLED_,
#[doc = "Dead-time enabled."]
DEAD_TIME_ENABLED_,
}
impl DTE0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DTE0R::DEAD_TIME_DISABLED_ => false,
DTE0R::DEAD_TIME_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DTE0R {
match value {
false => DTE0R::DEAD_TIME_DISABLED_,
true => DTE0R::DEAD_TIME_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DEAD_TIME_DISABLED_`"]
#[inline]
pub fn is_dead_time_disabled_(&self) -> bool {
*self == DTE0R::DEAD_TIME_DISABLED_
}
#[doc = "Checks if the value of the field is `DEAD_TIME_ENABLED_`"]
#[inline]
pub fn is_dead_time_enabled_(&self) -> bool {
*self == DTE0R::DEAD_TIME_ENABLED_
}
}
#[doc = "Possible values of the field `DISUP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DISUP0R {
#[doc = "Functional registers are updated from the write registers at the end of each PWM cycle."]
UPDATE,
#[doc = "Functional registers remain the same as long as the timer is running."]
NOUPDATE,
}
impl DISUP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DISUP0R::UPDATE => false,
DISUP0R::NOUPDATE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DISUP0R {
match value {
false => DISUP0R::UPDATE,
true => DISUP0R::NOUPDATE,
}
}
#[doc = "Checks if the value of the field is `UPDATE`"]
#[inline]
pub fn is_update(&self) -> bool {
*self == DISUP0R::UPDATE
}
#[doc = "Checks if the value of the field is `NOUPDATE`"]
#[inline]
pub fn is_noupdate(&self) -> bool {
*self == DISUP0R::NOUPDATE
}
}
#[doc = "Possible values of the field `RUN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RUN1R {
#[doc = "Stop."]
STOP_,
#[doc = "Run."]
RUN_,
}
impl RUN1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RUN1R::STOP_ => false,
RUN1R::RUN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RUN1R {
match value {
false => RUN1R::STOP_,
true => RUN1R::RUN_,
}
}
#[doc = "Checks if the value of the field is `STOP_`"]
#[inline]
pub fn is_stop_(&self) -> bool {
*self == RUN1R::STOP_
}
#[doc = "Checks if the value of the field is `RUN_`"]
#[inline]
pub fn is_run_(&self) -> bool {
*self == RUN1R::RUN_
}
}
#[doc = "Possible values of the field `CENTER1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CENTER1R {
#[doc = "Edge-aligned."]
EDGE_ALIGNED_,
#[doc = "Center-aligned."]
CENTER_ALIGNED_,
}
impl CENTER1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CENTER1R::EDGE_ALIGNED_ => false,
CENTER1R::CENTER_ALIGNED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CENTER1R {
match value {
false => CENTER1R::EDGE_ALIGNED_,
true => CENTER1R::CENTER_ALIGNED_,
}
}
#[doc = "Checks if the value of the field is `EDGE_ALIGNED_`"]
#[inline]
pub fn is_edge_aligned_(&self) -> bool {
*self == CENTER1R::EDGE_ALIGNED_
}
#[doc = "Checks if the value of the field is `CENTER_ALIGNED_`"]
#[inline]
pub fn is_center_aligned_(&self) -> bool {
*self == CENTER1R::CENTER_ALIGNED_
}
}
#[doc = "Possible values of the field `POLA1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POLA1R {
#[doc = "Passive state is LOW, active state is HIGH."]
PASSIVE_STATE_IS_LOW,
#[doc = "Passive state is HIGH, active state is LOW."]
PASSIVE_STATE_IS_HIG,
}
impl POLA1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
POLA1R::PASSIVE_STATE_IS_LOW => false,
POLA1R::PASSIVE_STATE_IS_HIG => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> POLA1R {
match value {
false => POLA1R::PASSIVE_STATE_IS_LOW,
true => POLA1R::PASSIVE_STATE_IS_HIG,
}
}
#[doc = "Checks if the value of the field is `PASSIVE_STATE_IS_LOW`"]
#[inline]
pub fn is_passive_state_is_low(&self) -> bool {
*self == POLA1R::PASSIVE_STATE_IS_LOW
}
#[doc = "Checks if the value of the field is `PASSIVE_STATE_IS_HIG`"]
#[inline]
pub fn is_passive_state_is_hig(&self) -> bool {
*self == POLA1R::PASSIVE_STATE_IS_HIG
}
}
#[doc = "Possible values of the field `DTE1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTE1R {
#[doc = "Dead-time disabled."]
DEAD_TIME_DISABLED_,
#[doc = "Dead-time enabled."]
DEAD_TIME_ENABLED_,
}
impl DTE1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DTE1R::DEAD_TIME_DISABLED_ => false,
DTE1R::DEAD_TIME_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DTE1R {
match value {
false => DTE1R::DEAD_TIME_DISABLED_,
true => DTE1R::DEAD_TIME_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DEAD_TIME_DISABLED_`"]
#[inline]
pub fn is_dead_time_disabled_(&self) -> bool {
*self == DTE1R::DEAD_TIME_DISABLED_
}
#[doc = "Checks if the value of the field is `DEAD_TIME_ENABLED_`"]
#[inline]
pub fn is_dead_time_enabled_(&self) -> bool {
*self == DTE1R::DEAD_TIME_ENABLED_
}
}
#[doc = "Possible values of the field `DISUP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DISUP1R {
#[doc = "Functional registers are updated from the write registers at the end of each PWM cycle."]
UPDATE,
#[doc = "Functional registers remain the same as long as the timer is running."]
NOUPDATE,
}
impl DISUP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DISUP1R::UPDATE => false,
DISUP1R::NOUPDATE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DISUP1R {
match value {
false => DISUP1R::UPDATE,
true => DISUP1R::NOUPDATE,
}
}
#[doc = "Checks if the value of the field is `UPDATE`"]
#[inline]
pub fn is_update(&self) -> bool {
*self == DISUP1R::UPDATE
}
#[doc = "Checks if the value of the field is `NOUPDATE`"]
#[inline]
pub fn is_noupdate(&self) -> bool {
*self == DISUP1R::NOUPDATE
}
}
#[doc = "Possible values of the field `RUN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RUN2R {
#[doc = "Stop."]
STOP_,
#[doc = "Run."]
RUN_,
}
impl RUN2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RUN2R::STOP_ => false,
RUN2R::RUN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RUN2R {
match value {
false => RUN2R::STOP_,
true => RUN2R::RUN_,
}
}
#[doc = "Checks if the value of the field is `STOP_`"]
#[inline]
pub fn is_stop_(&self) -> bool {
*self == RUN2R::STOP_
}
#[doc = "Checks if the value of the field is `RUN_`"]
#[inline]
pub fn is_run_(&self) -> bool {
*self == RUN2R::RUN_
}
}
#[doc = "Possible values of the field `CENTER2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CENTER2R {
#[doc = "Edge-aligned."]
EDGE_ALIGNED_,
#[doc = "Center-aligned."]
CENTER_ALIGNED_,
}
impl CENTER2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CENTER2R::EDGE_ALIGNED_ => false,
CENTER2R::CENTER_ALIGNED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CENTER2R {
match value {
false => CENTER2R::EDGE_ALIGNED_,
true => CENTER2R::CENTER_ALIGNED_,
}
}
#[doc = "Checks if the value of the field is `EDGE_ALIGNED_`"]
#[inline]
pub fn is_edge_aligned_(&self) -> bool {
*self == CENTER2R::EDGE_ALIGNED_
}
#[doc = "Checks if the value of the field is `CENTER_ALIGNED_`"]
#[inline]
pub fn is_center_aligned_(&self) -> bool {
*self == CENTER2R::CENTER_ALIGNED_
}
}
#[doc = "Possible values of the field `POLA2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum POLA2R {
#[doc = "Passive state is LOW, active state is HIGH."]
PASSIVE_STATE_IS_LOW,
#[doc = "Passive state is HIGH, active state is LOW."]
PASSIVE_STATE_IS_HIG,
}
impl POLA2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
POLA2R::PASSIVE_STATE_IS_LOW => false,
POLA2R::PASSIVE_STATE_IS_HIG => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> POLA2R {
match value {
false => POLA2R::PASSIVE_STATE_IS_LOW,
true => POLA2R::PASSIVE_STATE_IS_HIG,
}
}
#[doc = "Checks if the value of the field is `PASSIVE_STATE_IS_LOW`"]
#[inline]
pub fn is_passive_state_is_low(&self) -> bool {
*self == POLA2R::PASSIVE_STATE_IS_LOW
}
#[doc = "Checks if the value of the field is `PASSIVE_STATE_IS_HIG`"]
#[inline]
pub fn is_passive_state_is_hig(&self) -> bool {
*self == POLA2R::PASSIVE_STATE_IS_HIG
}
}
#[doc = "Possible values of the field `DTE2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DTE2R {
#[doc = "Dead-time disabled."]
DEAD_TIME_DISABLED_,
#[doc = "Dead-time enabled."]
DEAD_TIME_ENABLED_,
}
impl DTE2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DTE2R::DEAD_TIME_DISABLED_ => false,
DTE2R::DEAD_TIME_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DTE2R {
match value {
false => DTE2R::DEAD_TIME_DISABLED_,
true => DTE2R::DEAD_TIME_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DEAD_TIME_DISABLED_`"]
#[inline]
pub fn is_dead_time_disabled_(&self) -> bool {
*self == DTE2R::DEAD_TIME_DISABLED_
}
#[doc = "Checks if the value of the field is `DEAD_TIME_ENABLED_`"]
#[inline]
pub fn is_dead_time_enabled_(&self) -> bool {
*self == DTE2R::DEAD_TIME_ENABLED_
}
}
#[doc = "Possible values of the field `DISUP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DISUP2R {
#[doc = "Functional registers are updated from the write registers at the end of each PWM cycle."]
UPDATE,
#[doc = "Functional registers remain the same as long as the timer is running."]
NOUPDATE,
}
impl DISUP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DISUP2R::UPDATE => false,
DISUP2R::NOUPDATE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DISUP2R {
match value {
false => DISUP2R::UPDATE,
true => DISUP2R::NOUPDATE,
}
}
#[doc = "Checks if the value of the field is `UPDATE`"]
#[inline]
pub fn is_update(&self) -> bool {
*self == DISUP2R::UPDATE
}
#[doc = "Checks if the value of the field is `NOUPDATE`"]
#[inline]
pub fn is_noupdate(&self) -> bool {
*self == DISUP2R::NOUPDATE
}
}
#[doc = "Possible values of the field `INVBDC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum INVBDCR {
#[doc = "The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)."]
OPPOSITE,
#[doc = "The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)"]
SAME,
}
impl INVBDCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
INVBDCR::OPPOSITE => false,
INVBDCR::SAME => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> INVBDCR {
match value {
false => INVBDCR::OPPOSITE,
true => INVBDCR::SAME,
}
}
#[doc = "Checks if the value of the field is `OPPOSITE`"]
#[inline]
pub fn is_opposite(&self) -> bool {
*self == INVBDCR::OPPOSITE
}
#[doc = "Checks if the value of the field is `SAME`"]
#[inline]
pub fn is_same(&self) -> bool {
*self == INVBDCR::SAME
}
}
#[doc = "Possible values of the field `ACMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACMODER {
#[doc = "3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register."]
_3_PHASE_AC_MODE_OFF,
#[doc = "3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0."]
_3_PHASE_AC_MODE_ON_,
}
impl ACMODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ACMODER::_3_PHASE_AC_MODE_OFF => false,
ACMODER::_3_PHASE_AC_MODE_ON_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ACMODER {
match value {
false => ACMODER::_3_PHASE_AC_MODE_OFF,
true => ACMODER::_3_PHASE_AC_MODE_ON_,
}
}
#[doc = "Checks if the value of the field is `_3_PHASE_AC_MODE_OFF`"]
#[inline]
pub fn is_3_phase_ac_mode_off(&self) -> bool {
*self == ACMODER::_3_PHASE_AC_MODE_OFF
}
#[doc = "Checks if the value of the field is `_3_PHASE_AC_MODE_ON_`"]
#[inline]
pub fn is_3_phase_ac_mode_on_(&self) -> bool {
*self == ACMODER::_3_PHASE_AC_MODE_ON_
}
}
#[doc = "Possible values of the field `DCMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DCMODER {
#[doc = "3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)"]
_3_PHASE_DC_MODE_OFF,
#[doc = "3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs."]
_3_PHASE_DC_MODE_ON_,
}
impl DCMODER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DCMODER::_3_PHASE_DC_MODE_OFF => false,
DCMODER::_3_PHASE_DC_MODE_ON_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DCMODER {
match value {
false => DCMODER::_3_PHASE_DC_MODE_OFF,
true => DCMODER::_3_PHASE_DC_MODE_ON_,
}
}
#[doc = "Checks if the value of the field is `_3_PHASE_DC_MODE_OFF`"]
#[inline]
pub fn is_3_phase_dc_mode_off(&self) -> bool {
*self == DCMODER::_3_PHASE_DC_MODE_OFF
}
#[doc = "Checks if the value of the field is `_3_PHASE_DC_MODE_ON_`"]
#[inline]
pub fn is_3_phase_dc_mode_on_(&self) -> bool {
*self == DCMODER::_3_PHASE_DC_MODE_ON_
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Stops/starts timer channel 0."]
#[inline]
pub fn run0(&self) -> RUN0R {
RUN0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Edge/center aligned operation for channel 0."]
#[inline]
pub fn center0(&self) -> CENTER0R {
CENTER0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Selects polarity of the MCOA0 and MCOB0 pins."]
#[inline]
pub fn pola0(&self) -> POLA0R {
POLA0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Controls the dead-time feature for channel 0."]
#[inline]
pub fn dte0(&self) -> DTE0R {
DTE0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Enable/disable updates of functional registers for channel 0 (see Section 24.8.2)."]
#[inline]
pub fn disup0(&self) -> DISUP0R {
DISUP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Stops/starts timer channel 1."]
#[inline]
pub fn run1(&self) -> RUN1R {
RUN1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Edge/center aligned operation for channel 1."]
#[inline]
pub fn center1(&self) -> CENTER1R {
CENTER1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Selects polarity of the MCOA1 and MCOB1 pins."]
#[inline]
pub fn pola1(&self) -> POLA1R {
POLA1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Controls the dead-time feature for channel 1."]
#[inline]
pub fn dte1(&self) -> DTE1R {
DTE1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Enable/disable updates of functional registers for channel 1 (see Section 24.8.2)."]
#[inline]
pub fn disup1(&self) -> DISUP1R {
DISUP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Stops/starts timer channel 2."]
#[inline]
pub fn run2(&self) -> RUN2R {
RUN2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Edge/center aligned operation for channel 2."]
#[inline]
pub fn center2(&self) -> CENTER2R {
CENTER2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Selects polarity of the MCOA2 and MCOB2 pins."]
#[inline]
pub fn pola2(&self) -> POLA2R {
POLA2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 19 - Controls the dead-time feature for channel 1."]
#[inline]
pub fn dte2(&self) -> DTE2R {
DTE2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 20 - Enable/disable updates of functional registers for channel 2 (see Section 24.8.2)."]
#[inline]
pub fn disup2(&self) -> DISUP2R {
DISUP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode."]
#[inline]
pub fn invbdc(&self) -> INVBDCR {
INVBDCR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - 3-phase AC mode select (see Section 24.8.7)."]
#[inline]
pub fn acmode(&self) -> ACMODER {
ACMODER::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 31 - 3-phase DC mode select (see Section 24.8.6)."]
#[inline]
pub fn dcmode(&self) -> DCMODER {
DCMODER::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "PWM Control set address"]
pub struct CON_SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWM Control set address"]
pub mod con_set {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CON_SET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _RUN0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _RUN0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CENTER0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CENTER0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POLA0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _POLA0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DTE0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DTE0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DISUP0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DISUP0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RUN1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _RUN1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CENTER1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CENTER1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POLA1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _POLA1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DTE1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DTE1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DISUP1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DISUP1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RUN2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _RUN2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CENTER2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CENTER2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POLA2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _POLA2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DTE2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DTE2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DISUP2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DISUP2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INVBDC_SETW<'a> {
w: &'a mut W,
}
impl<'a> _INVBDC_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACMODE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ACMODE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DCMODE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _DCMODE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn run0_set(&mut self) -> _RUN0_SETW {
_RUN0_SETW { w: self }
}
#[doc = "Bit 1 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn center0_set(&mut self) -> _CENTER0_SETW {
_CENTER0_SETW { w: self }
}
#[doc = "Bit 2 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn pola0_set(&mut self) -> _POLA0_SETW {
_POLA0_SETW { w: self }
}
#[doc = "Bit 3 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn dte0_set(&mut self) -> _DTE0_SETW {
_DTE0_SETW { w: self }
}
#[doc = "Bit 4 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn disup0_set(&mut self) -> _DISUP0_SETW {
_DISUP0_SETW { w: self }
}
#[doc = "Bit 8 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn run1_set(&mut self) -> _RUN1_SETW {
_RUN1_SETW { w: self }
}
#[doc = "Bit 9 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn center1_set(&mut self) -> _CENTER1_SETW {
_CENTER1_SETW { w: self }
}
#[doc = "Bit 10 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn pola1_set(&mut self) -> _POLA1_SETW {
_POLA1_SETW { w: self }
}
#[doc = "Bit 11 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn dte1_set(&mut self) -> _DTE1_SETW {
_DTE1_SETW { w: self }
}
#[doc = "Bit 12 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn disup1_set(&mut self) -> _DISUP1_SETW {
_DISUP1_SETW { w: self }
}
#[doc = "Bit 16 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn run2_set(&mut self) -> _RUN2_SETW {
_RUN2_SETW { w: self }
}
#[doc = "Bit 17 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn center2_set(&mut self) -> _CENTER2_SETW {
_CENTER2_SETW { w: self }
}
#[doc = "Bit 18 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn pola2_set(&mut self) -> _POLA2_SETW {
_POLA2_SETW { w: self }
}
#[doc = "Bit 19 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn dte2_set(&mut self) -> _DTE2_SETW {
_DTE2_SETW { w: self }
}
#[doc = "Bit 20 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn disup2_set(&mut self) -> _DISUP2_SETW {
_DISUP2_SETW { w: self }
}
#[doc = "Bit 29 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn invbdc_set(&mut self) -> _INVBDC_SETW {
_INVBDC_SETW { w: self }
}
#[doc = "Bit 30 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn acmode_set(&mut self) -> _ACMODE_SETW {
_ACMODE_SETW { w: self }
}
#[doc = "Bit 31 - Writing a one sets the corresponding bit in the CON register."]
#[inline]
pub fn dcmode_set(&mut self) -> _DCMODE_SETW {
_DCMODE_SETW { w: self }
}
}
}
#[doc = "PWM Control clear address"]
pub struct CON_CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWM Control clear address"]
pub mod con_clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CON_CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _RUN0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _RUN0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CENTER0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CENTER0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POLA0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _POLA0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DTE0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DTE0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DISUP0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DISUP0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RUN1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _RUN1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CENTER1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CENTER1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POLA1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _POLA1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DTE1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DTE1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DISUP1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DISUP1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RUN2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _RUN2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CENTER2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CENTER2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POLA2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _POLA2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DTE2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DTE2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DISUP2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DISUP2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INVBDC_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _INVBDC_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACMOD_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ACMOD_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DCMODE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _DCMODE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn run0_clr(&mut self) -> _RUN0_CLRW {
_RUN0_CLRW { w: self }
}
#[doc = "Bit 1 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn center0_clr(&mut self) -> _CENTER0_CLRW {
_CENTER0_CLRW { w: self }
}
#[doc = "Bit 2 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn pola0_clr(&mut self) -> _POLA0_CLRW {
_POLA0_CLRW { w: self }
}
#[doc = "Bit 3 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn dte0_clr(&mut self) -> _DTE0_CLRW {
_DTE0_CLRW { w: self }
}
#[doc = "Bit 4 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn disup0_clr(&mut self) -> _DISUP0_CLRW {
_DISUP0_CLRW { w: self }
}
#[doc = "Bit 8 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn run1_clr(&mut self) -> _RUN1_CLRW {
_RUN1_CLRW { w: self }
}
#[doc = "Bit 9 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn center1_clr(&mut self) -> _CENTER1_CLRW {
_CENTER1_CLRW { w: self }
}
#[doc = "Bit 10 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn pola1_clr(&mut self) -> _POLA1_CLRW {
_POLA1_CLRW { w: self }
}
#[doc = "Bit 11 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn dte1_clr(&mut self) -> _DTE1_CLRW {
_DTE1_CLRW { w: self }
}
#[doc = "Bit 12 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn disup1_clr(&mut self) -> _DISUP1_CLRW {
_DISUP1_CLRW { w: self }
}
#[doc = "Bit 16 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn run2_clr(&mut self) -> _RUN2_CLRW {
_RUN2_CLRW { w: self }
}
#[doc = "Bit 17 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn center2_clr(&mut self) -> _CENTER2_CLRW {
_CENTER2_CLRW { w: self }
}
#[doc = "Bit 18 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn pola2_clr(&mut self) -> _POLA2_CLRW {
_POLA2_CLRW { w: self }
}
#[doc = "Bit 19 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn dte2_clr(&mut self) -> _DTE2_CLRW {
_DTE2_CLRW { w: self }
}
#[doc = "Bit 20 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn disup2_clr(&mut self) -> _DISUP2_CLRW {
_DISUP2_CLRW { w: self }
}
#[doc = "Bit 29 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn invbdc_clr(&mut self) -> _INVBDC_CLRW {
_INVBDC_CLRW { w: self }
}
#[doc = "Bit 30 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn acmod_clr(&mut self) -> _ACMOD_CLRW {
_ACMOD_CLRW { w: self }
}
#[doc = "Bit 31 - Writing a one clears the corresponding bit in the CON register."]
#[inline]
pub fn dcmode_clr(&mut self) -> _DCMODE_CLRW {
_DCMODE_CLRW { w: self }
}
}
}
#[doc = "Capture Control read address"]
pub struct CAPCON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture Control read address"]
pub mod capcon {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CAPCON {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CAP0MCI0_RER {
bits: bool,
}
impl CAP0MCI0_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP0MCI0_FER {
bits: bool,
}
impl CAP0MCI0_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP0MCI1_RER {
bits: bool,
}
impl CAP0MCI1_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP0MCI1_FER {
bits: bool,
}
impl CAP0MCI1_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP0MCI2_RER {
bits: bool,
}
impl CAP0MCI2_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP0MCI2_FER {
bits: bool,
}
impl CAP0MCI2_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP1MCI0_RER {
bits: bool,
}
impl CAP1MCI0_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP1MCI0_FER {
bits: bool,
}
impl CAP1MCI0_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP1MCI1_RER {
bits: bool,
}
impl CAP1MCI1_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP1MCI1_FER {
bits: bool,
}
impl CAP1MCI1_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP1MCI2_RER {
bits: bool,
}
impl CAP1MCI2_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP1MCI2_FER {
bits: bool,
}
impl CAP1MCI2_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP2MCI0_RER {
bits: bool,
}
impl CAP2MCI0_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP2MCI0_FER {
bits: bool,
}
impl CAP2MCI0_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP2MCI1_RER {
bits: bool,
}
impl CAP2MCI1_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP2MCI1_FER {
bits: bool,
}
impl CAP2MCI1_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP2MCI2_RER {
bits: bool,
}
impl CAP2MCI2_RER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAP2MCI2_FER {
bits: bool,
}
impl CAP2MCI2_FER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RT0R {
bits: bool,
}
impl RT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RT1R {
bits: bool,
}
impl RT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RT2R {
bits: bool,
}
impl RT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0."]
#[inline]
pub fn cap0mci0_re(&self) -> CAP0MCI0_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP0MCI0_RER { bits }
}
#[doc = "Bit 1 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0."]
#[inline]
pub fn cap0mci0_fe(&self) -> CAP0MCI0_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP0MCI0_FER { bits }
}
#[doc = "Bit 2 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1."]
#[inline]
pub fn cap0mci1_re(&self) -> CAP0MCI1_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP0MCI1_RER { bits }
}
#[doc = "Bit 3 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1."]
#[inline]
pub fn cap0mci1_fe(&self) -> CAP0MCI1_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP0MCI1_FER { bits }
}
#[doc = "Bit 4 - A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2."]
#[inline]
pub fn cap0mci2_re(&self) -> CAP0MCI2_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP0MCI2_RER { bits }
}
#[doc = "Bit 5 - A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2."]
#[inline]
pub fn cap0mci2_fe(&self) -> CAP0MCI2_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP0MCI2_FER { bits }
}
#[doc = "Bit 6 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0."]
#[inline]
pub fn cap1mci0_re(&self) -> CAP1MCI0_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP1MCI0_RER { bits }
}
#[doc = "Bit 7 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0."]
#[inline]
pub fn cap1mci0_fe(&self) -> CAP1MCI0_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP1MCI0_FER { bits }
}
#[doc = "Bit 8 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1."]
#[inline]
pub fn cap1mci1_re(&self) -> CAP1MCI1_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP1MCI1_RER { bits }
}
#[doc = "Bit 9 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1."]
#[inline]
pub fn cap1mci1_fe(&self) -> CAP1MCI1_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP1MCI1_FER { bits }
}
#[doc = "Bit 10 - A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2."]
#[inline]
pub fn cap1mci2_re(&self) -> CAP1MCI2_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP1MCI2_RER { bits }
}
#[doc = "Bit 11 - A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2."]
#[inline]
pub fn cap1mci2_fe(&self) -> CAP1MCI2_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP1MCI2_FER { bits }
}
#[doc = "Bit 12 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0."]
#[inline]
pub fn cap2mci0_re(&self) -> CAP2MCI0_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP2MCI0_RER { bits }
}
#[doc = "Bit 13 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0."]
#[inline]
pub fn cap2mci0_fe(&self) -> CAP2MCI0_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP2MCI0_FER { bits }
}
#[doc = "Bit 14 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1."]
#[inline]
pub fn cap2mci1_re(&self) -> CAP2MCI1_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP2MCI1_RER { bits }
}
#[doc = "Bit 15 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1."]
#[inline]
pub fn cap2mci1_fe(&self) -> CAP2MCI1_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP2MCI1_FER { bits }
}
#[doc = "Bit 16 - A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2."]
#[inline]
pub fn cap2mci2_re(&self) -> CAP2MCI2_RER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP2MCI2_RER { bits }
}
#[doc = "Bit 17 - A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2."]
#[inline]
pub fn cap2mci2_fe(&self) -> CAP2MCI2_FER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAP2MCI2_FER { bits }
}
#[doc = "Bit 18 - If this bit is 1, TC0 is reset by a channel 0 capture event."]
#[inline]
pub fn rt0(&self) -> RT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RT0R { bits }
}
#[doc = "Bit 19 - If this bit is 1, TC1 is reset by a channel 1 capture event."]
#[inline]
pub fn rt1(&self) -> RT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RT1R { bits }
}
#[doc = "Bit 20 - If this bit is 1, TC2 is reset by a channel 2 capture event."]
#[inline]
pub fn rt2(&self) -> RT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RT2R { bits }
}
}
}
#[doc = "Capture Control set address"]
pub struct CAPCON_SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture Control set address"]
pub mod capcon_set {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CAPCON_SET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI0_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI0_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI0_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI0_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI1_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI1_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI1_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI1_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI2_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI2_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI2_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI2_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI0_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI0_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI0_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI0_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI1_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI1_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI1_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI1_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI2_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI2_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI2_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI2_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI0_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI0_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI0_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI0_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI1_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI1_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI1_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI1_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI2_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI2_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI2_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI2_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RT0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _RT0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RT1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _RT1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RT2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _RT2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci0_re_set(&mut self) -> _CAP0MCI0_RE_SETW {
_CAP0MCI0_RE_SETW { w: self }
}
#[doc = "Bit 1 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci0_fe_set(&mut self) -> _CAP0MCI0_FE_SETW {
_CAP0MCI0_FE_SETW { w: self }
}
#[doc = "Bit 2 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci1_re_set(&mut self) -> _CAP0MCI1_RE_SETW {
_CAP0MCI1_RE_SETW { w: self }
}
#[doc = "Bit 3 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci1_fe_set(&mut self) -> _CAP0MCI1_FE_SETW {
_CAP0MCI1_FE_SETW { w: self }
}
#[doc = "Bit 4 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci2_re_set(&mut self) -> _CAP0MCI2_RE_SETW {
_CAP0MCI2_RE_SETW { w: self }
}
#[doc = "Bit 5 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci2_fe_set(&mut self) -> _CAP0MCI2_FE_SETW {
_CAP0MCI2_FE_SETW { w: self }
}
#[doc = "Bit 6 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci0_re_set(&mut self) -> _CAP1MCI0_RE_SETW {
_CAP1MCI0_RE_SETW { w: self }
}
#[doc = "Bit 7 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci0_fe_set(&mut self) -> _CAP1MCI0_FE_SETW {
_CAP1MCI0_FE_SETW { w: self }
}
#[doc = "Bit 8 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci1_re_set(&mut self) -> _CAP1MCI1_RE_SETW {
_CAP1MCI1_RE_SETW { w: self }
}
#[doc = "Bit 9 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci1_fe_set(&mut self) -> _CAP1MCI1_FE_SETW {
_CAP1MCI1_FE_SETW { w: self }
}
#[doc = "Bit 10 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci2_re_set(&mut self) -> _CAP1MCI2_RE_SETW {
_CAP1MCI2_RE_SETW { w: self }
}
#[doc = "Bit 11 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci2_fe_set(&mut self) -> _CAP1MCI2_FE_SETW {
_CAP1MCI2_FE_SETW { w: self }
}
#[doc = "Bit 12 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci0_re_set(&mut self) -> _CAP2MCI0_RE_SETW {
_CAP2MCI0_RE_SETW { w: self }
}
#[doc = "Bit 13 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci0_fe_set(&mut self) -> _CAP2MCI0_FE_SETW {
_CAP2MCI0_FE_SETW { w: self }
}
#[doc = "Bit 14 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci1_re_set(&mut self) -> _CAP2MCI1_RE_SETW {
_CAP2MCI1_RE_SETW { w: self }
}
#[doc = "Bit 15 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci1_fe_set(&mut self) -> _CAP2MCI1_FE_SETW {
_CAP2MCI1_FE_SETW { w: self }
}
#[doc = "Bit 16 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci2_re_set(&mut self) -> _CAP2MCI2_RE_SETW {
_CAP2MCI2_RE_SETW { w: self }
}
#[doc = "Bit 17 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci2_fe_set(&mut self) -> _CAP2MCI2_FE_SETW {
_CAP2MCI2_FE_SETW { w: self }
}
#[doc = "Bit 18 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn rt0_set(&mut self) -> _RT0_SETW {
_RT0_SETW { w: self }
}
#[doc = "Bit 19 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn rt1_set(&mut self) -> _RT1_SETW {
_RT1_SETW { w: self }
}
#[doc = "Bit 20 - Writing a one sets the corresponding bits in the CAPCON register."]
#[inline]
pub fn rt2_set(&mut self) -> _RT2_SETW {
_RT2_SETW { w: self }
}
}
}
#[doc = "Event Control clear address"]
pub struct CAPCON_CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Event Control clear address"]
pub mod capcon_clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CAPCON_CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI0_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI0_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI0_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI0_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI1_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI1_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI1_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI1_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI2_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI2_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP0MCI2_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP0MCI2_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI0_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI0_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI0_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI0_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI1_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI1_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI1_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI1_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI2_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI2_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP1MCI2_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP1MCI2_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI0_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI0_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI0_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI0_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI1_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI1_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI1_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI1_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI2_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI2_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP2MCI2_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CAP2MCI2_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RT0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _RT0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RT1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _RT1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RT2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _RT2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci0_re_clr(&mut self) -> _CAP0MCI0_RE_CLRW {
_CAP0MCI0_RE_CLRW { w: self }
}
#[doc = "Bit 1 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci0_fe_clr(&mut self) -> _CAP0MCI0_FE_CLRW {
_CAP0MCI0_FE_CLRW { w: self }
}
#[doc = "Bit 2 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci1_re_clr(&mut self) -> _CAP0MCI1_RE_CLRW {
_CAP0MCI1_RE_CLRW { w: self }
}
#[doc = "Bit 3 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci1_fe_clr(&mut self) -> _CAP0MCI1_FE_CLRW {
_CAP0MCI1_FE_CLRW { w: self }
}
#[doc = "Bit 4 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci2_re_clr(&mut self) -> _CAP0MCI2_RE_CLRW {
_CAP0MCI2_RE_CLRW { w: self }
}
#[doc = "Bit 5 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap0mci2_fe_clr(&mut self) -> _CAP0MCI2_FE_CLRW {
_CAP0MCI2_FE_CLRW { w: self }
}
#[doc = "Bit 6 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci0_re_clr(&mut self) -> _CAP1MCI0_RE_CLRW {
_CAP1MCI0_RE_CLRW { w: self }
}
#[doc = "Bit 7 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci0_fe_clr(&mut self) -> _CAP1MCI0_FE_CLRW {
_CAP1MCI0_FE_CLRW { w: self }
}
#[doc = "Bit 8 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci1_re_clr(&mut self) -> _CAP1MCI1_RE_CLRW {
_CAP1MCI1_RE_CLRW { w: self }
}
#[doc = "Bit 9 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci1_fe_clr(&mut self) -> _CAP1MCI1_FE_CLRW {
_CAP1MCI1_FE_CLRW { w: self }
}
#[doc = "Bit 10 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci2_re_clr(&mut self) -> _CAP1MCI2_RE_CLRW {
_CAP1MCI2_RE_CLRW { w: self }
}
#[doc = "Bit 11 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap1mci2_fe_clr(&mut self) -> _CAP1MCI2_FE_CLRW {
_CAP1MCI2_FE_CLRW { w: self }
}
#[doc = "Bit 12 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci0_re_clr(&mut self) -> _CAP2MCI0_RE_CLRW {
_CAP2MCI0_RE_CLRW { w: self }
}
#[doc = "Bit 13 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci0_fe_clr(&mut self) -> _CAP2MCI0_FE_CLRW {
_CAP2MCI0_FE_CLRW { w: self }
}
#[doc = "Bit 14 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci1_re_clr(&mut self) -> _CAP2MCI1_RE_CLRW {
_CAP2MCI1_RE_CLRW { w: self }
}
#[doc = "Bit 15 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci1_fe_clr(&mut self) -> _CAP2MCI1_FE_CLRW {
_CAP2MCI1_FE_CLRW { w: self }
}
#[doc = "Bit 16 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci2_re_clr(&mut self) -> _CAP2MCI2_RE_CLRW {
_CAP2MCI2_RE_CLRW { w: self }
}
#[doc = "Bit 17 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn cap2mci2_fe_clr(&mut self) -> _CAP2MCI2_FE_CLRW {
_CAP2MCI2_FE_CLRW { w: self }
}
#[doc = "Bit 18 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn rt0_clr(&mut self) -> _RT0_CLRW {
_RT0_CLRW { w: self }
}
#[doc = "Bit 19 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn rt1_clr(&mut self) -> _RT1_CLRW {
_RT1_CLRW { w: self }
}
#[doc = "Bit 20 - Writing a one clears the corresponding bits in the CAPCON register."]
#[inline]
pub fn rt2_clr(&mut self) -> _RT2_CLRW {
_RT2_CLRW { w: self }
}
}
}
#[doc = "Timer Counter register"]
pub struct TC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Timer Counter register"]
pub mod tc {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MCTCR {
bits: u32,
}
impl MCTCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MCTCW<'a> {
w: &'a mut W,
}
impl<'a> _MCTCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Timer/Counter value."]
#[inline]
pub fn mctc(&self) -> MCTCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MCTCR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Timer/Counter value."]
#[inline]
pub fn mctc(&mut self) -> _MCTCW {
_MCTCW { w: self }
}
}
}
#[doc = "Limit register"]
pub struct LIM {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Limit register"]
pub mod lim {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::LIM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MCLIMR {
bits: u32,
}
impl MCLIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MCLIMW<'a> {
w: &'a mut W,
}
impl<'a> _MCLIMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Limit value."]
#[inline]
pub fn mclim(&self) -> MCLIMR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MCLIMR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Limit value."]
#[inline]
pub fn mclim(&mut self) -> _MCLIMW {
_MCLIMW { w: self }
}
}
}
#[doc = "Match register"]
pub struct MAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Match register"]
pub mod mat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MAT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MCMATR {
bits: u32,
}
impl MCMATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MCMATW<'a> {
w: &'a mut W,
}
impl<'a> _MCMATW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Match value."]
#[inline]
pub fn mcmat(&self) -> MCMATR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MCMATR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Match value."]
#[inline]
pub fn mcmat(&mut self) -> _MCMATW {
_MCMATW { w: self }
}
}
}
#[doc = "Dead time register"]
pub struct DT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Dead time register"]
pub mod dt {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DT0R {
bits: u16,
}
impl DT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DT1R {
bits: u16,
}
impl DT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DT2R {
bits: u16,
}
impl DT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DT0W<'a> {
w: &'a mut W,
}
impl<'a> _DT0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DT1W<'a> {
w: &'a mut W,
}
impl<'a> _DT1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DT2W<'a> {
w: &'a mut W,
}
impl<'a> _DT2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Dead time for channel 0.\\[1\\]"]
#[inline]
pub fn dt0(&self) -> DT0R {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DT0R { bits }
}
#[doc = "Bits 10:19 - Dead time for channel 1.\\[2\\]"]
#[inline]
pub fn dt1(&self) -> DT1R {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DT1R { bits }
}
#[doc = "Bits 20:29 - Dead time for channel 2.\\[2\\]"]
#[inline]
pub fn dt2(&self) -> DT2R {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DT2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x3fff_ffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Dead time for channel 0.\\[1\\]"]
#[inline]
pub fn dt0(&mut self) -> _DT0W {
_DT0W { w: self }
}
#[doc = "Bits 10:19 - Dead time for channel 1.\\[2\\]"]
#[inline]
pub fn dt1(&mut self) -> _DT1W {
_DT1W { w: self }
}
#[doc = "Bits 20:29 - Dead time for channel 2.\\[2\\]"]
#[inline]
pub fn dt2(&mut self) -> _DT2W {
_DT2W { w: self }
}
}
}
#[doc = "Communication Pattern register"]
pub struct CP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Communication Pattern register"]
pub mod cp {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CP {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CCPA0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCPA0R {
#[doc = "MCOA0 passive."]
MCOA0_PASSIVE_,
#[doc = "internal MCOA0."]
INTERNAL_MCOA0_,
}
impl CCPA0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCPA0R::MCOA0_PASSIVE_ => false,
CCPA0R::INTERNAL_MCOA0_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCPA0R {
match value {
false => CCPA0R::MCOA0_PASSIVE_,
true => CCPA0R::INTERNAL_MCOA0_,
}
}
#[doc = "Checks if the value of the field is `MCOA0_PASSIVE_`"]
#[inline]
pub fn is_mcoa0_passive_(&self) -> bool {
*self == CCPA0R::MCOA0_PASSIVE_
}
#[doc = "Checks if the value of the field is `INTERNAL_MCOA0_`"]
#[inline]
pub fn is_internal_mcoa0_(&self) -> bool {
*self == CCPA0R::INTERNAL_MCOA0_
}
}
#[doc = "Possible values of the field `CCPB0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCPB0R {
#[doc = "MCOB0 passive."]
MCOB0_PASSIVE_,
#[doc = "MCOB0 tracks internal MCOA0."]
MCOB0_TRACKS_INTERNA,
}
impl CCPB0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCPB0R::MCOB0_PASSIVE_ => false,
CCPB0R::MCOB0_TRACKS_INTERNA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCPB0R {
match value {
false => CCPB0R::MCOB0_PASSIVE_,
true => CCPB0R::MCOB0_TRACKS_INTERNA,
}
}
#[doc = "Checks if the value of the field is `MCOB0_PASSIVE_`"]
#[inline]
pub fn is_mcob0_passive_(&self) -> bool {
*self == CCPB0R::MCOB0_PASSIVE_
}
#[doc = "Checks if the value of the field is `MCOB0_TRACKS_INTERNA`"]
#[inline]
pub fn is_mcob0_tracks_interna(&self) -> bool {
*self == CCPB0R::MCOB0_TRACKS_INTERNA
}
}
#[doc = "Possible values of the field `CCPA1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCPA1R {
#[doc = "MCOA1 passive."]
MCOA1_PASSIVE_,
#[doc = "MCOA1 tracks internal MCOA0."]
MCOA1_TRACKS_INTERNA,
}
impl CCPA1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCPA1R::MCOA1_PASSIVE_ => false,
CCPA1R::MCOA1_TRACKS_INTERNA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCPA1R {
match value {
false => CCPA1R::MCOA1_PASSIVE_,
true => CCPA1R::MCOA1_TRACKS_INTERNA,
}
}
#[doc = "Checks if the value of the field is `MCOA1_PASSIVE_`"]
#[inline]
pub fn is_mcoa1_passive_(&self) -> bool {
*self == CCPA1R::MCOA1_PASSIVE_
}
#[doc = "Checks if the value of the field is `MCOA1_TRACKS_INTERNA`"]
#[inline]
pub fn is_mcoa1_tracks_interna(&self) -> bool {
*self == CCPA1R::MCOA1_TRACKS_INTERNA
}
}
#[doc = "Possible values of the field `CCPB1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCPB1R {
#[doc = "MCOB1 passive."]
MCOB1_PASSIVE_,
#[doc = "MCOB1 tracks internal MCOA0."]
MCOB1_TRACKS_INTERNA,
}
impl CCPB1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCPB1R::MCOB1_PASSIVE_ => false,
CCPB1R::MCOB1_TRACKS_INTERNA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCPB1R {
match value {
false => CCPB1R::MCOB1_PASSIVE_,
true => CCPB1R::MCOB1_TRACKS_INTERNA,
}
}
#[doc = "Checks if the value of the field is `MCOB1_PASSIVE_`"]
#[inline]
pub fn is_mcob1_passive_(&self) -> bool {
*self == CCPB1R::MCOB1_PASSIVE_
}
#[doc = "Checks if the value of the field is `MCOB1_TRACKS_INTERNA`"]
#[inline]
pub fn is_mcob1_tracks_interna(&self) -> bool {
*self == CCPB1R::MCOB1_TRACKS_INTERNA
}
}
#[doc = "Possible values of the field `CCPA2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCPA2R {
#[doc = "MCOA2 passive."]
MCOA2_PASSIVE_,
#[doc = "MCOA2 tracks internal MCOA0."]
MCOA2_TRACKS_INTERNA,
}
impl CCPA2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCPA2R::MCOA2_PASSIVE_ => false,
CCPA2R::MCOA2_TRACKS_INTERNA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCPA2R {
match value {
false => CCPA2R::MCOA2_PASSIVE_,
true => CCPA2R::MCOA2_TRACKS_INTERNA,
}
}
#[doc = "Checks if the value of the field is `MCOA2_PASSIVE_`"]
#[inline]
pub fn is_mcoa2_passive_(&self) -> bool {
*self == CCPA2R::MCOA2_PASSIVE_
}
#[doc = "Checks if the value of the field is `MCOA2_TRACKS_INTERNA`"]
#[inline]
pub fn is_mcoa2_tracks_interna(&self) -> bool {
*self == CCPA2R::MCOA2_TRACKS_INTERNA
}
}
#[doc = "Possible values of the field `CCPB2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCPB2R {
#[doc = "MCOB2 passive."]
MCOB2_PASSIVE_,
#[doc = "MCOB2 tracks internal MCOA0."]
MCOB2_TRACKS_INTERNA,
}
impl CCPB2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CCPB2R::MCOB2_PASSIVE_ => false,
CCPB2R::MCOB2_TRACKS_INTERNA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CCPB2R {
match value {
false => CCPB2R::MCOB2_PASSIVE_,
true => CCPB2R::MCOB2_TRACKS_INTERNA,
}
}
#[doc = "Checks if the value of the field is `MCOB2_PASSIVE_`"]
#[inline]
pub fn is_mcob2_passive_(&self) -> bool {
*self == CCPB2R::MCOB2_PASSIVE_
}
#[doc = "Checks if the value of the field is `MCOB2_TRACKS_INTERNA`"]
#[inline]
pub fn is_mcob2_tracks_interna(&self) -> bool {
*self == CCPB2R::MCOB2_TRACKS_INTERNA
}
}
#[doc = "Values that can be written to the field `CCPA0`"]
pub enum CCPA0W {
#[doc = "MCOA0 passive."]
MCOA0_PASSIVE_,
#[doc = "internal MCOA0."]
INTERNAL_MCOA0_,
}
impl CCPA0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCPA0W::MCOA0_PASSIVE_ => false,
CCPA0W::INTERNAL_MCOA0_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CCPA0W<'a> {
w: &'a mut W,
}
impl<'a> _CCPA0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCPA0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MCOA0 passive."]
#[inline]
pub fn mcoa0_passive_(self) -> &'a mut W {
self.variant(CCPA0W::MCOA0_PASSIVE_)
}
#[doc = "internal MCOA0."]
#[inline]
pub fn internal_mcoa0_(self) -> &'a mut W {
self.variant(CCPA0W::INTERNAL_MCOA0_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CCPB0`"]
pub enum CCPB0W {
#[doc = "MCOB0 passive."]
MCOB0_PASSIVE_,
#[doc = "MCOB0 tracks internal MCOA0."]
MCOB0_TRACKS_INTERNA,
}
impl CCPB0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCPB0W::MCOB0_PASSIVE_ => false,
CCPB0W::MCOB0_TRACKS_INTERNA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CCPB0W<'a> {
w: &'a mut W,
}
impl<'a> _CCPB0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCPB0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MCOB0 passive."]
#[inline]
pub fn mcob0_passive_(self) -> &'a mut W {
self.variant(CCPB0W::MCOB0_PASSIVE_)
}
#[doc = "MCOB0 tracks internal MCOA0."]
#[inline]
pub fn mcob0_tracks_interna(self) -> &'a mut W {
self.variant(CCPB0W::MCOB0_TRACKS_INTERNA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CCPA1`"]
pub enum CCPA1W {
#[doc = "MCOA1 passive."]
MCOA1_PASSIVE_,
#[doc = "MCOA1 tracks internal MCOA0."]
MCOA1_TRACKS_INTERNA,
}
impl CCPA1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCPA1W::MCOA1_PASSIVE_ => false,
CCPA1W::MCOA1_TRACKS_INTERNA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CCPA1W<'a> {
w: &'a mut W,
}
impl<'a> _CCPA1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCPA1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MCOA1 passive."]
#[inline]
pub fn mcoa1_passive_(self) -> &'a mut W {
self.variant(CCPA1W::MCOA1_PASSIVE_)
}
#[doc = "MCOA1 tracks internal MCOA0."]
#[inline]
pub fn mcoa1_tracks_interna(self) -> &'a mut W {
self.variant(CCPA1W::MCOA1_TRACKS_INTERNA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CCPB1`"]
pub enum CCPB1W {
#[doc = "MCOB1 passive."]
MCOB1_PASSIVE_,
#[doc = "MCOB1 tracks internal MCOA0."]
MCOB1_TRACKS_INTERNA,
}
impl CCPB1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCPB1W::MCOB1_PASSIVE_ => false,
CCPB1W::MCOB1_TRACKS_INTERNA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CCPB1W<'a> {
w: &'a mut W,
}
impl<'a> _CCPB1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCPB1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MCOB1 passive."]
#[inline]
pub fn mcob1_passive_(self) -> &'a mut W {
self.variant(CCPB1W::MCOB1_PASSIVE_)
}
#[doc = "MCOB1 tracks internal MCOA0."]
#[inline]
pub fn mcob1_tracks_interna(self) -> &'a mut W {
self.variant(CCPB1W::MCOB1_TRACKS_INTERNA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CCPA2`"]
pub enum CCPA2W {
#[doc = "MCOA2 passive."]
MCOA2_PASSIVE_,
#[doc = "MCOA2 tracks internal MCOA0."]
MCOA2_TRACKS_INTERNA,
}
impl CCPA2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCPA2W::MCOA2_PASSIVE_ => false,
CCPA2W::MCOA2_TRACKS_INTERNA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CCPA2W<'a> {
w: &'a mut W,
}
impl<'a> _CCPA2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCPA2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MCOA2 passive."]
#[inline]
pub fn mcoa2_passive_(self) -> &'a mut W {
self.variant(CCPA2W::MCOA2_PASSIVE_)
}
#[doc = "MCOA2 tracks internal MCOA0."]
#[inline]
pub fn mcoa2_tracks_interna(self) -> &'a mut W {
self.variant(CCPA2W::MCOA2_TRACKS_INTERNA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CCPB2`"]
pub enum CCPB2W {
#[doc = "MCOB2 passive."]
MCOB2_PASSIVE_,
#[doc = "MCOB2 tracks internal MCOA0."]
MCOB2_TRACKS_INTERNA,
}
impl CCPB2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CCPB2W::MCOB2_PASSIVE_ => false,
CCPB2W::MCOB2_TRACKS_INTERNA => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CCPB2W<'a> {
w: &'a mut W,
}
impl<'a> _CCPB2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CCPB2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MCOB2 passive."]
#[inline]
pub fn mcob2_passive_(self) -> &'a mut W {
self.variant(CCPB2W::MCOB2_PASSIVE_)
}
#[doc = "MCOB2 tracks internal MCOA0."]
#[inline]
pub fn mcob2_tracks_interna(self) -> &'a mut W {
self.variant(CCPB2W::MCOB2_TRACKS_INTERNA)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Communication pattern output A, channel 0."]
#[inline]
pub fn ccpa0(&self) -> CCPA0R {
CCPA0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Communication pattern output B, channel 0."]
#[inline]
pub fn ccpb0(&self) -> CCPB0R {
CCPB0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Communication pattern output A, channel 1."]
#[inline]
pub fn ccpa1(&self) -> CCPA1R {
CCPA1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Communication pattern output B, channel 1."]
#[inline]
pub fn ccpb1(&self) -> CCPB1R {
CCPB1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Communication pattern output A, channel 2."]
#[inline]
pub fn ccpa2(&self) -> CCPA2R {
CCPA2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Communication pattern output B, channel 2."]
#[inline]
pub fn ccpb2(&self) -> CCPB2R {
CCPB2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Communication pattern output A, channel 0."]
#[inline]
pub fn ccpa0(&mut self) -> _CCPA0W {
_CCPA0W { w: self }
}
#[doc = "Bit 1 - Communication pattern output B, channel 0."]
#[inline]
pub fn ccpb0(&mut self) -> _CCPB0W {
_CCPB0W { w: self }
}
#[doc = "Bit 2 - Communication pattern output A, channel 1."]
#[inline]
pub fn ccpa1(&mut self) -> _CCPA1W {
_CCPA1W { w: self }
}
#[doc = "Bit 3 - Communication pattern output B, channel 1."]
#[inline]
pub fn ccpb1(&mut self) -> _CCPB1W {
_CCPB1W { w: self }
}
#[doc = "Bit 4 - Communication pattern output A, channel 2."]
#[inline]
pub fn ccpa2(&mut self) -> _CCPA2W {
_CCPA2W { w: self }
}
#[doc = "Bit 5 - Communication pattern output B, channel 2."]
#[inline]
pub fn ccpb2(&mut self) -> _CCPB2W {
_CCPB2W { w: self }
}
}
}
#[doc = "Capture register"]
pub struct CAP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture register"]
pub mod cap {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CAP {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CAPR {
bits: u32,
}
impl CAPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current TC value at a capture event."]
#[inline]
pub fn cap(&self) -> CAPR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
CAPR { bits }
}
}
}
#[doc = "Interrupt Enable read address"]
pub struct INTEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable read address"]
pub mod inten {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTEN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `ILIM0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ILIM0R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ILIM0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ILIM0R::INTERRUPT_DISABLED_ => false,
ILIM0R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ILIM0R {
match value {
false => ILIM0R::INTERRUPT_DISABLED_,
true => ILIM0R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ILIM0R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ILIM0R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `IMAT0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMAT0R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl IMAT0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMAT0R::INTERRUPT_DISABLED_ => false,
IMAT0R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMAT0R {
match value {
false => IMAT0R::INTERRUPT_DISABLED_,
true => IMAT0R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == IMAT0R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == IMAT0R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `ICAP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICAP0R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ICAP0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ICAP0R::INTERRUPT_DISABLED_ => false,
ICAP0R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ICAP0R {
match value {
false => ICAP0R::INTERRUPT_DISABLED_,
true => ICAP0R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ICAP0R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ICAP0R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `ILIM1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ILIM1R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ILIM1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ILIM1R::INTERRUPT_DISABLED_ => false,
ILIM1R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ILIM1R {
match value {
false => ILIM1R::INTERRUPT_DISABLED_,
true => ILIM1R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ILIM1R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ILIM1R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `IMAT1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMAT1R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl IMAT1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMAT1R::INTERRUPT_DISABLED_ => false,
IMAT1R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMAT1R {
match value {
false => IMAT1R::INTERRUPT_DISABLED_,
true => IMAT1R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == IMAT1R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == IMAT1R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `ICAP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICAP1R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ICAP1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ICAP1R::INTERRUPT_DISABLED_ => false,
ICAP1R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ICAP1R {
match value {
false => ICAP1R::INTERRUPT_DISABLED_,
true => ICAP1R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ICAP1R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ICAP1R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `ILIM2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ILIM2R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ILIM2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ILIM2R::INTERRUPT_DISABLED_ => false,
ILIM2R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ILIM2R {
match value {
false => ILIM2R::INTERRUPT_DISABLED_,
true => ILIM2R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ILIM2R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ILIM2R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `IMAT2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMAT2R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl IMAT2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMAT2R::INTERRUPT_DISABLED_ => false,
IMAT2R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMAT2R {
match value {
false => IMAT2R::INTERRUPT_DISABLED_,
true => IMAT2R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == IMAT2R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == IMAT2R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `ICAP2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICAP2R {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ICAP2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ICAP2R::INTERRUPT_DISABLED_ => false,
ICAP2R::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ICAP2R {
match value {
false => ICAP2R::INTERRUPT_DISABLED_,
true => ICAP2R::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ICAP2R::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ICAP2R::INTERRUPT_ENABLED_
}
}
#[doc = "Possible values of the field `ABORT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABORTR {
#[doc = "Interrupt disabled."]
INTERRUPT_DISABLED_,
#[doc = "Interrupt enabled."]
INTERRUPT_ENABLED_,
}
impl ABORTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABORTR::INTERRUPT_DISABLED_ => false,
ABORTR::INTERRUPT_ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABORTR {
match value {
false => ABORTR::INTERRUPT_DISABLED_,
true => ABORTR::INTERRUPT_ENABLED_,
}
}
#[doc = "Checks if the value of the field is `INTERRUPT_DISABLED_`"]
#[inline]
pub fn is_interrupt_disabled_(&self) -> bool {
*self == ABORTR::INTERRUPT_DISABLED_
}
#[doc = "Checks if the value of the field is `INTERRUPT_ENABLED_`"]
#[inline]
pub fn is_interrupt_enabled_(&self) -> bool {
*self == ABORTR::INTERRUPT_ENABLED_
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Limit interrupt for channel 0."]
#[inline]
pub fn ilim0(&self) -> ILIM0R {
ILIM0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Match interrupt for channel 0."]
#[inline]
pub fn imat0(&self) -> IMAT0R {
IMAT0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Capture interrupt for channel 0."]
#[inline]
pub fn icap0(&self) -> ICAP0R {
ICAP0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Limit interrupt for channel 1."]
#[inline]
pub fn ilim1(&self) -> ILIM1R {
ILIM1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Match interrupt for channel 1."]
#[inline]
pub fn imat1(&self) -> IMAT1R {
IMAT1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Capture interrupt for channel 1."]
#[inline]
pub fn icap1(&self) -> ICAP1R {
ICAP1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Limit interrupt for channel 2."]
#[inline]
pub fn ilim2(&self) -> ILIM2R {
ILIM2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Match interrupt for channel 2."]
#[inline]
pub fn imat2(&self) -> IMAT2R {
IMAT2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Capture interrupt for channel 2."]
#[inline]
pub fn icap2(&self) -> ICAP2R {
ICAP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Fast abort interrupt."]
#[inline]
pub fn abort(&self) -> ABORTR {
ABORTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "Interrupt Enable set address"]
pub struct INTEN_SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable set address"]
pub mod inten_set {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTEN_SET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _ILIM0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ABORT_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ABORT_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn ilim0_set(&mut self) -> _ILIM0_SETW {
_ILIM0_SETW { w: self }
}
#[doc = "Bit 1 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn imat0_set(&mut self) -> _IMAT0_SETW {
_IMAT0_SETW { w: self }
}
#[doc = "Bit 2 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn icap0_set(&mut self) -> _ICAP0_SETW {
_ICAP0_SETW { w: self }
}
#[doc = "Bit 4 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn ilim1_set(&mut self) -> _ILIM1_SETW {
_ILIM1_SETW { w: self }
}
#[doc = "Bit 5 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn imat1_set(&mut self) -> _IMAT1_SETW {
_IMAT1_SETW { w: self }
}
#[doc = "Bit 6 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn icap1_set(&mut self) -> _ICAP1_SETW {
_ICAP1_SETW { w: self }
}
#[doc = "Bit 9 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn ilim2_set(&mut self) -> _ILIM2_SETW {
_ILIM2_SETW { w: self }
}
#[doc = "Bit 10 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn imat2_set(&mut self) -> _IMAT2_SETW {
_IMAT2_SETW { w: self }
}
#[doc = "Bit 11 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn icap2_set(&mut self) -> _ICAP2_SETW {
_ICAP2_SETW { w: self }
}
#[doc = "Bit 15 - Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt."]
#[inline]
pub fn abort_set(&mut self) -> _ABORT_SETW {
_ABORT_SETW { w: self }
}
}
}
#[doc = "Interrupt Enable clear address"]
pub struct INTEN_CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt Enable clear address"]
pub mod inten_clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTEN_CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _ILIM0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ABORT_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABORT_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn ilim0_clr(&mut self) -> _ILIM0_CLRW {
_ILIM0_CLRW { w: self }
}
#[doc = "Bit 1 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn imat0_clr(&mut self) -> _IMAT0_CLRW {
_IMAT0_CLRW { w: self }
}
#[doc = "Bit 2 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn icap0_clr(&mut self) -> _ICAP0_CLRW {
_ICAP0_CLRW { w: self }
}
#[doc = "Bit 4 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn ilim1_clr(&mut self) -> _ILIM1_CLRW {
_ILIM1_CLRW { w: self }
}
#[doc = "Bit 5 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn imat1_clr(&mut self) -> _IMAT1_CLRW {
_IMAT1_CLRW { w: self }
}
#[doc = "Bit 6 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn icap1_clr(&mut self) -> _ICAP1_CLRW {
_ICAP1_CLRW { w: self }
}
#[doc = "Bit 8 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn ilim2_clr(&mut self) -> _ILIM2_CLRW {
_ILIM2_CLRW { w: self }
}
#[doc = "Bit 9 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn imat2_clr(&mut self) -> _IMAT2_CLRW {
_IMAT2_CLRW { w: self }
}
#[doc = "Bit 10 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn icap2_clr(&mut self) -> _ICAP2_CLRW {
_ICAP2_CLRW { w: self }
}
#[doc = "Bit 15 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn abort_clr(&mut self) -> _ABORT_CLRW {
_ABORT_CLRW { w: self }
}
}
}
#[doc = "Interrupt flags read address"]
pub struct INTF {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt flags read address"]
pub mod intf {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTF {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `ILIM0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ILIM0_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ILIM0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ILIM0_FR::THIS_INTERRUPT_SOURC => false,
ILIM0_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ILIM0_FR {
match value {
false => ILIM0_FR::THIS_INTERRUPT_SOURC,
true => ILIM0_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ILIM0_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ILIM0_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `IMAT0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMAT0_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl IMAT0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMAT0_FR::THIS_INTERRUPT_SOURC => false,
IMAT0_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMAT0_FR {
match value {
false => IMAT0_FR::THIS_INTERRUPT_SOURC,
true => IMAT0_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == IMAT0_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == IMAT0_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `ICAP0_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICAP0_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ICAP0_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ICAP0_FR::THIS_INTERRUPT_SOURC => false,
ICAP0_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ICAP0_FR {
match value {
false => ICAP0_FR::THIS_INTERRUPT_SOURC,
true => ICAP0_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ICAP0_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ICAP0_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `ILIM1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ILIM1_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ILIM1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ILIM1_FR::THIS_INTERRUPT_SOURC => false,
ILIM1_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ILIM1_FR {
match value {
false => ILIM1_FR::THIS_INTERRUPT_SOURC,
true => ILIM1_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ILIM1_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ILIM1_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `IMAT1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMAT1_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl IMAT1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMAT1_FR::THIS_INTERRUPT_SOURC => false,
IMAT1_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMAT1_FR {
match value {
false => IMAT1_FR::THIS_INTERRUPT_SOURC,
true => IMAT1_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == IMAT1_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == IMAT1_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `ICAP1_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICAP1_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ICAP1_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ICAP1_FR::THIS_INTERRUPT_SOURC => false,
ICAP1_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ICAP1_FR {
match value {
false => ICAP1_FR::THIS_INTERRUPT_SOURC,
true => ICAP1_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ICAP1_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ICAP1_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `ILIM2_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ILIM2_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ILIM2_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ILIM2_FR::THIS_INTERRUPT_SOURC => false,
ILIM2_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ILIM2_FR {
match value {
false => ILIM2_FR::THIS_INTERRUPT_SOURC,
true => ILIM2_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ILIM2_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ILIM2_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `IMAT2_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMAT2_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl IMAT2_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMAT2_FR::THIS_INTERRUPT_SOURC => false,
IMAT2_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMAT2_FR {
match value {
false => IMAT2_FR::THIS_INTERRUPT_SOURC,
true => IMAT2_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == IMAT2_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == IMAT2_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `ICAP2_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ICAP2_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ICAP2_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ICAP2_FR::THIS_INTERRUPT_SOURC => false,
ICAP2_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ICAP2_FR {
match value {
false => ICAP2_FR::THIS_INTERRUPT_SOURC,
true => ICAP2_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ICAP2_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ICAP2_FR::IF_THE_CORRESPONDING
}
}
#[doc = "Possible values of the field `ABORT_F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ABORT_FR {
#[doc = "This interrupt source is not contributing to the MCPWM interrupt request."]
THIS_INTERRUPT_SOURC,
#[doc = "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller."]
IF_THE_CORRESPONDING,
}
impl ABORT_FR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ABORT_FR::THIS_INTERRUPT_SOURC => false,
ABORT_FR::IF_THE_CORRESPONDING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ABORT_FR {
match value {
false => ABORT_FR::THIS_INTERRUPT_SOURC,
true => ABORT_FR::IF_THE_CORRESPONDING,
}
}
#[doc = "Checks if the value of the field is `THIS_INTERRUPT_SOURC`"]
#[inline]
pub fn is_this_interrupt_sourc(&self) -> bool {
*self == ABORT_FR::THIS_INTERRUPT_SOURC
}
#[doc = "Checks if the value of the field is `IF_THE_CORRESPONDING`"]
#[inline]
pub fn is_if_the_corresponding(&self) -> bool {
*self == ABORT_FR::IF_THE_CORRESPONDING
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Limit interrupt flag for channel 0."]
#[inline]
pub fn ilim0_f(&self) -> ILIM0_FR {
ILIM0_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Match interrupt flag for channel 0."]
#[inline]
pub fn imat0_f(&self) -> IMAT0_FR {
IMAT0_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Capture interrupt flag for channel 0."]
#[inline]
pub fn icap0_f(&self) -> ICAP0_FR {
ICAP0_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Limit interrupt flag for channel 1."]
#[inline]
pub fn ilim1_f(&self) -> ILIM1_FR {
ILIM1_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Match interrupt flag for channel 1."]
#[inline]
pub fn imat1_f(&self) -> IMAT1_FR {
IMAT1_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Capture interrupt flag for channel 1."]
#[inline]
pub fn icap1_f(&self) -> ICAP1_FR {
ICAP1_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Limit interrupt flag for channel 2."]
#[inline]
pub fn ilim2_f(&self) -> ILIM2_FR {
ILIM2_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Match interrupt flag for channel 2."]
#[inline]
pub fn imat2_f(&self) -> IMAT2_FR {
IMAT2_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Capture interrupt flag for channel 2."]
#[inline]
pub fn icap2_f(&self) -> ICAP2_FR {
ICAP2_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Fast abort interrupt flag."]
#[inline]
pub fn abort_f(&self) -> ABORT_FR {
ABORT_FR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "Interrupt flags set address"]
pub struct INTF_SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt flags set address"]
pub mod intf_set {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTF_SET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _ILIM0_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM0_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT0_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT0_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP0_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP0_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM1_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM1_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT1_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT1_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP1_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP1_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM2_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM2_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT2_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT2_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP2_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP2_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ABORT_F_SETW<'a> {
w: &'a mut W,
}
impl<'a> _ABORT_F_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn ilim0_f_set(&mut self) -> _ILIM0_F_SETW {
_ILIM0_F_SETW { w: self }
}
#[doc = "Bit 1 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn imat0_f_set(&mut self) -> _IMAT0_F_SETW {
_IMAT0_F_SETW { w: self }
}
#[doc = "Bit 2 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn icap0_f_set(&mut self) -> _ICAP0_F_SETW {
_ICAP0_F_SETW { w: self }
}
#[doc = "Bit 4 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn ilim1_f_set(&mut self) -> _ILIM1_F_SETW {
_ILIM1_F_SETW { w: self }
}
#[doc = "Bit 5 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn imat1_f_set(&mut self) -> _IMAT1_F_SETW {
_IMAT1_F_SETW { w: self }
}
#[doc = "Bit 6 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn icap1_f_set(&mut self) -> _ICAP1_F_SETW {
_ICAP1_F_SETW { w: self }
}
#[doc = "Bit 8 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn ilim2_f_set(&mut self) -> _ILIM2_F_SETW {
_ILIM2_F_SETW { w: self }
}
#[doc = "Bit 9 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn imat2_f_set(&mut self) -> _IMAT2_F_SETW {
_IMAT2_F_SETW { w: self }
}
#[doc = "Bit 10 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn icap2_f_set(&mut self) -> _ICAP2_F_SETW {
_ICAP2_F_SETW { w: self }
}
#[doc = "Bit 15 - Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt."]
#[inline]
pub fn abort_f_set(&mut self) -> _ABORT_F_SETW {
_ABORT_F_SETW { w: self }
}
}
}
#[doc = "Interrupt flags clear address"]
pub struct INTF_CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt flags clear address"]
pub mod intf_clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTF_CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _ILIM0_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM0_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT0_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT0_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP0_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP0_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM1_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM1_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT1_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT1_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP1_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP1_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ILIM2_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ILIM2_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IMAT2_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _IMAT2_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ICAP2_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ICAP2_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ABORT_F_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABORT_F_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request."]
#[inline]
pub fn ilim0_f_clr(&mut self) -> _ILIM0_F_CLRW {
_ILIM0_F_CLRW { w: self }
}
#[doc = "Bit 1 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn imat0_f_clr(&mut self) -> _IMAT0_F_CLRW {
_IMAT0_F_CLRW { w: self }
}
#[doc = "Bit 2 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn icap0_f_clr(&mut self) -> _ICAP0_F_CLRW {
_ICAP0_F_CLRW { w: self }
}
#[doc = "Bit 4 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn ilim1_f_clr(&mut self) -> _ILIM1_F_CLRW {
_ILIM1_F_CLRW { w: self }
}
#[doc = "Bit 5 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn imat1_f_clr(&mut self) -> _IMAT1_F_CLRW {
_IMAT1_F_CLRW { w: self }
}
#[doc = "Bit 6 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn icap1_f_clr(&mut self) -> _ICAP1_F_CLRW {
_ICAP1_F_CLRW { w: self }
}
#[doc = "Bit 8 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn ilim2_f_clr(&mut self) -> _ILIM2_F_CLRW {
_ILIM2_F_CLRW { w: self }
}
#[doc = "Bit 9 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn imat2_f_clr(&mut self) -> _IMAT2_F_CLRW {
_IMAT2_F_CLRW { w: self }
}
#[doc = "Bit 10 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn icap2_f_clr(&mut self) -> _ICAP2_F_CLRW {
_ICAP2_F_CLRW { w: self }
}
#[doc = "Bit 15 - Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt."]
#[inline]
pub fn abort_f_clr(&mut self) -> _ABORT_F_CLRW {
_ABORT_F_CLRW { w: self }
}
}
}
#[doc = "Count Control read address"]
pub struct CNTCON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Count Control read address"]
pub mod cntcon {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CNTCON {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `TC0MCI0_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI0_RER {
#[doc = "A rising edge on MCI0 does not affect counter 0."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI0."]
RISING,
}
impl TC0MCI0_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC0MCI0_RER::A_RISING_EDGE_ON_MCI => false,
TC0MCI0_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC0MCI0_RER {
match value {
false => TC0MCI0_RER::A_RISING_EDGE_ON_MCI,
true => TC0MCI0_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC0MCI0_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC0MCI0_RER::RISING
}
}
#[doc = "Possible values of the field `TC0MCI0_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI0_FER {
#[doc = "A falling edge on MCI0 does not affect counter 0."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI0."]
FALLING,
}
impl TC0MCI0_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC0MCI0_FER::A_FALLING_EDGE_ON_MC => false,
TC0MCI0_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC0MCI0_FER {
match value {
false => TC0MCI0_FER::A_FALLING_EDGE_ON_MC,
true => TC0MCI0_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC0MCI0_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC0MCI0_FER::FALLING
}
}
#[doc = "Possible values of the field `TC0MCI1_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI1_RER {
#[doc = "A rising edge on MCI1 does not affect counter 0."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI1."]
RISING,
}
impl TC0MCI1_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC0MCI1_RER::A_RISING_EDGE_ON_MCI => false,
TC0MCI1_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC0MCI1_RER {
match value {
false => TC0MCI1_RER::A_RISING_EDGE_ON_MCI,
true => TC0MCI1_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC0MCI1_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC0MCI1_RER::RISING
}
}
#[doc = "Possible values of the field `TC0MCI1_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI1_FER {
#[doc = "A falling edge on MCI1 does not affect counter 0."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI1."]
FALLING,
}
impl TC0MCI1_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC0MCI1_FER::A_FALLING_EDGE_ON_MC => false,
TC0MCI1_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC0MCI1_FER {
match value {
false => TC0MCI1_FER::A_FALLING_EDGE_ON_MC,
true => TC0MCI1_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC0MCI1_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC0MCI1_FER::FALLING
}
}
#[doc = "Possible values of the field `TC0MCI2_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI2_RER {
#[doc = "A rising edge on MCI0 does not affect counter 0."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE0 is 1, counter 0 advances on a rising edge on MCI2."]
RISING,
}
impl TC0MCI2_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC0MCI2_RER::A_RISING_EDGE_ON_MCI => false,
TC0MCI2_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC0MCI2_RER {
match value {
false => TC0MCI2_RER::A_RISING_EDGE_ON_MCI,
true => TC0MCI2_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC0MCI2_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC0MCI2_RER::RISING
}
}
#[doc = "Possible values of the field `TC0MCI2_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC0MCI2_FER {
#[doc = "A falling edge on MCI0 does not affect counter 0."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE0 is 1, counter 0 advances on a falling edge on MCI2."]
FALLLING,
}
impl TC0MCI2_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC0MCI2_FER::A_FALLING_EDGE_ON_MC => false,
TC0MCI2_FER::FALLLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC0MCI2_FER {
match value {
false => TC0MCI2_FER::A_FALLING_EDGE_ON_MC,
true => TC0MCI2_FER::FALLLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC0MCI2_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLLING`"]
#[inline]
pub fn is_fallling(&self) -> bool {
*self == TC0MCI2_FER::FALLLING
}
}
#[doc = "Possible values of the field `TC1MCI0_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI0_RER {
#[doc = "A rising edge on MCI0 does not affect counter 1."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI0."]
RISING,
}
impl TC1MCI0_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC1MCI0_RER::A_RISING_EDGE_ON_MCI => false,
TC1MCI0_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC1MCI0_RER {
match value {
false => TC1MCI0_RER::A_RISING_EDGE_ON_MCI,
true => TC1MCI0_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC1MCI0_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC1MCI0_RER::RISING
}
}
#[doc = "Possible values of the field `TC1MCI0_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI0_FER {
#[doc = "A falling edge on MCI0 does not affect counter 1."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI0."]
FALLING,
}
impl TC1MCI0_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC1MCI0_FER::A_FALLING_EDGE_ON_MC => false,
TC1MCI0_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC1MCI0_FER {
match value {
false => TC1MCI0_FER::A_FALLING_EDGE_ON_MC,
true => TC1MCI0_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC1MCI0_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC1MCI0_FER::FALLING
}
}
#[doc = "Possible values of the field `TC1MCI1_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI1_RER {
#[doc = "A rising edge on MCI1 does not affect counter 1."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI1."]
RISING,
}
impl TC1MCI1_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC1MCI1_RER::A_RISING_EDGE_ON_MCI => false,
TC1MCI1_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC1MCI1_RER {
match value {
false => TC1MCI1_RER::A_RISING_EDGE_ON_MCI,
true => TC1MCI1_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC1MCI1_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC1MCI1_RER::RISING
}
}
#[doc = "Possible values of the field `TC1MCI1_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI1_FER {
#[doc = "A falling edge on MCI0 does not affect counter 1."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI1."]
FALLING,
}
impl TC1MCI1_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC1MCI1_FER::A_FALLING_EDGE_ON_MC => false,
TC1MCI1_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC1MCI1_FER {
match value {
false => TC1MCI1_FER::A_FALLING_EDGE_ON_MC,
true => TC1MCI1_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC1MCI1_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC1MCI1_FER::FALLING
}
}
#[doc = "Possible values of the field `TC1MCI2_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI2_RER {
#[doc = "A rising edge on MCI2 does not affect counter 1."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE1 is 1, counter 1 advances on a rising edge on MCI2."]
RISING,
}
impl TC1MCI2_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC1MCI2_RER::A_RISING_EDGE_ON_MCI => false,
TC1MCI2_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC1MCI2_RER {
match value {
false => TC1MCI2_RER::A_RISING_EDGE_ON_MCI,
true => TC1MCI2_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC1MCI2_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC1MCI2_RER::RISING
}
}
#[doc = "Possible values of the field `TC1MCI2_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC1MCI2_FER {
#[doc = "A falling edge on MCI2 does not affect counter 1."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE1 is 1, counter 1 advances on a falling edge on MCI2."]
FALLING,
}
impl TC1MCI2_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC1MCI2_FER::A_FALLING_EDGE_ON_MC => false,
TC1MCI2_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC1MCI2_FER {
match value {
false => TC1MCI2_FER::A_FALLING_EDGE_ON_MC,
true => TC1MCI2_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC1MCI2_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC1MCI2_FER::FALLING
}
}
#[doc = "Possible values of the field `TC2MCI0_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI0_RER {
#[doc = "A rising edge on MCI0 does not affect counter 2."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI0."]
RISING,
}
impl TC2MCI0_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC2MCI0_RER::A_RISING_EDGE_ON_MCI => false,
TC2MCI0_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC2MCI0_RER {
match value {
false => TC2MCI0_RER::A_RISING_EDGE_ON_MCI,
true => TC2MCI0_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC2MCI0_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC2MCI0_RER::RISING
}
}
#[doc = "Possible values of the field `TC2MCI0_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI0_FER {
#[doc = "A falling edge on MCI0 does not affect counter 2."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI0."]
FALLING,
}
impl TC2MCI0_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC2MCI0_FER::A_FALLING_EDGE_ON_MC => false,
TC2MCI0_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC2MCI0_FER {
match value {
false => TC2MCI0_FER::A_FALLING_EDGE_ON_MC,
true => TC2MCI0_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC2MCI0_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC2MCI0_FER::FALLING
}
}
#[doc = "Possible values of the field `TC2MCI1_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI1_RER {
#[doc = "A rising edge on MCI1 does not affect counter 2."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI1."]
RISING,
}
impl TC2MCI1_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC2MCI1_RER::A_RISING_EDGE_ON_MCI => false,
TC2MCI1_RER::RISING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC2MCI1_RER {
match value {
false => TC2MCI1_RER::A_RISING_EDGE_ON_MCI,
true => TC2MCI1_RER::RISING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC2MCI1_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline]
pub fn is_rising(&self) -> bool {
*self == TC2MCI1_RER::RISING
}
}
#[doc = "Possible values of the field `TC2MCI1_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI1_FER {
#[doc = "A falling edge on MCI1 does not affect counter 2."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI1."]
FALLING,
}
impl TC2MCI1_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC2MCI1_FER::A_FALLING_EDGE_ON_MC => false,
TC2MCI1_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC2MCI1_FER {
match value {
false => TC2MCI1_FER::A_FALLING_EDGE_ON_MC,
true => TC2MCI1_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC2MCI1_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC2MCI1_FER::FALLING
}
}
#[doc = "Possible values of the field `TC2MCI2_RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI2_RER {
#[doc = "A rising edge on MCI2 does not affect counter 2."]
A_RISING_EDGE_ON_MCI,
#[doc = "If MODE2 is 1, counter 2 advances on a rising edge on MCI2."]
RISIING,
}
impl TC2MCI2_RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC2MCI2_RER::A_RISING_EDGE_ON_MCI => false,
TC2MCI2_RER::RISIING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC2MCI2_RER {
match value {
false => TC2MCI2_RER::A_RISING_EDGE_ON_MCI,
true => TC2MCI2_RER::RISIING,
}
}
#[doc = "Checks if the value of the field is `A_RISING_EDGE_ON_MCI`"]
#[inline]
pub fn is_a_rising_edge_on_mci(&self) -> bool {
*self == TC2MCI2_RER::A_RISING_EDGE_ON_MCI
}
#[doc = "Checks if the value of the field is `RISIING`"]
#[inline]
pub fn is_risiing(&self) -> bool {
*self == TC2MCI2_RER::RISIING
}
}
#[doc = "Possible values of the field `TC2MCI2_FE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TC2MCI2_FER {
#[doc = "A falling edge on MCI2 does not affect counter 2."]
A_FALLING_EDGE_ON_MC,
#[doc = "If MODE2 is 1, counter 2 advances on a falling edge on MCI2."]
FALLING,
}
impl TC2MCI2_FER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TC2MCI2_FER::A_FALLING_EDGE_ON_MC => false,
TC2MCI2_FER::FALLING => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TC2MCI2_FER {
match value {
false => TC2MCI2_FER::A_FALLING_EDGE_ON_MC,
true => TC2MCI2_FER::FALLING,
}
}
#[doc = "Checks if the value of the field is `A_FALLING_EDGE_ON_MC`"]
#[inline]
pub fn is_a_falling_edge_on_mc(&self) -> bool {
*self == TC2MCI2_FER::A_FALLING_EDGE_ON_MC
}
#[doc = "Checks if the value of the field is `FALLING`"]
#[inline]
pub fn is_falling(&self) -> bool {
*self == TC2MCI2_FER::FALLING
}
}
#[doc = "Possible values of the field `CNTR0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CNTR0R {
#[doc = "Channel 0 is in timer mode."]
CHANNEL_0_IS_IN_TIME,
#[doc = "Channel 0 is in counter mode."]
CHANNEL_0_IS_IN_COUN,
}
impl CNTR0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CNTR0R::CHANNEL_0_IS_IN_TIME => false,
CNTR0R::CHANNEL_0_IS_IN_COUN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CNTR0R {
match value {
false => CNTR0R::CHANNEL_0_IS_IN_TIME,
true => CNTR0R::CHANNEL_0_IS_IN_COUN,
}
}
#[doc = "Checks if the value of the field is `CHANNEL_0_IS_IN_TIME`"]
#[inline]
pub fn is_channel_0_is_in_time(&self) -> bool {
*self == CNTR0R::CHANNEL_0_IS_IN_TIME
}
#[doc = "Checks if the value of the field is `CHANNEL_0_IS_IN_COUN`"]
#[inline]
pub fn is_channel_0_is_in_coun(&self) -> bool {
*self == CNTR0R::CHANNEL_0_IS_IN_COUN
}
}
#[doc = "Possible values of the field `CNTR1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CNTR1R {
#[doc = "Channel 1 is in timer mode."]
CHANNEL_1_IS_IN_TIME,
#[doc = "Channel 1 is in counter mode."]
CHANNEL_1_IS_IN_COUN,
}
impl CNTR1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CNTR1R::CHANNEL_1_IS_IN_TIME => false,
CNTR1R::CHANNEL_1_IS_IN_COUN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CNTR1R {
match value {
false => CNTR1R::CHANNEL_1_IS_IN_TIME,
true => CNTR1R::CHANNEL_1_IS_IN_COUN,
}
}
#[doc = "Checks if the value of the field is `CHANNEL_1_IS_IN_TIME`"]
#[inline]
pub fn is_channel_1_is_in_time(&self) -> bool {
*self == CNTR1R::CHANNEL_1_IS_IN_TIME
}
#[doc = "Checks if the value of the field is `CHANNEL_1_IS_IN_COUN`"]
#[inline]
pub fn is_channel_1_is_in_coun(&self) -> bool {
*self == CNTR1R::CHANNEL_1_IS_IN_COUN
}
}
#[doc = "Possible values of the field `CNTR2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CNTR2R {
#[doc = "Channel 2 is in timer mode."]
CHANNEL_2_IS_IN_TIME,
#[doc = "Channel 2 is in counter mode."]
CHANNEL_2_IS_IN_COUN,
}
impl CNTR2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CNTR2R::CHANNEL_2_IS_IN_TIME => false,
CNTR2R::CHANNEL_2_IS_IN_COUN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CNTR2R {
match value {
false => CNTR2R::CHANNEL_2_IS_IN_TIME,
true => CNTR2R::CHANNEL_2_IS_IN_COUN,
}
}
#[doc = "Checks if the value of the field is `CHANNEL_2_IS_IN_TIME`"]
#[inline]
pub fn is_channel_2_is_in_time(&self) -> bool {
*self == CNTR2R::CHANNEL_2_IS_IN_TIME
}
#[doc = "Checks if the value of the field is `CHANNEL_2_IS_IN_COUN`"]
#[inline]
pub fn is_channel_2_is_in_coun(&self) -> bool {
*self == CNTR2R::CHANNEL_2_IS_IN_COUN
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Counter 0 rising edge mode, channel 0."]
#[inline]
pub fn tc0mci0_re(&self) -> TC0MCI0_RER {
TC0MCI0_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Counter 0 falling edge mode, channel 0."]
#[inline]
pub fn tc0mci0_fe(&self) -> TC0MCI0_FER {
TC0MCI0_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Counter 0 rising edge mode, channel 1."]
#[inline]
pub fn tc0mci1_re(&self) -> TC0MCI1_RER {
TC0MCI1_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Counter 0 falling edge mode, channel 1."]
#[inline]
pub fn tc0mci1_fe(&self) -> TC0MCI1_FER {
TC0MCI1_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Counter 0 rising edge mode, channel 2."]
#[inline]
pub fn tc0mci2_re(&self) -> TC0MCI2_RER {
TC0MCI2_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Counter 0 falling edge mode, channel 2."]
#[inline]
pub fn tc0mci2_fe(&self) -> TC0MCI2_FER {
TC0MCI2_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Counter 1 rising edge mode, channel 0."]
#[inline]
pub fn tc1mci0_re(&self) -> TC1MCI0_RER {
TC1MCI0_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Counter 1 falling edge mode, channel 0."]
#[inline]
pub fn tc1mci0_fe(&self) -> TC1MCI0_FER {
TC1MCI0_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Counter 1 rising edge mode, channel 1."]
#[inline]
pub fn tc1mci1_re(&self) -> TC1MCI1_RER {
TC1MCI1_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Counter 1 falling edge mode, channel 1."]
#[inline]
pub fn tc1mci1_fe(&self) -> TC1MCI1_FER {
TC1MCI1_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Counter 1 rising edge mode, channel 2."]
#[inline]
pub fn tc1mci2_re(&self) -> TC1MCI2_RER {
TC1MCI2_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Counter 1 falling edge mode, channel 2."]
#[inline]
pub fn tc1mci2_fe(&self) -> TC1MCI2_FER {
TC1MCI2_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Counter 2 rising edge mode, channel 0."]
#[inline]
pub fn tc2mci0_re(&self) -> TC2MCI0_RER {
TC2MCI0_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 13 - Counter 2 falling edge mode, channel 0."]
#[inline]
pub fn tc2mci0_fe(&self) -> TC2MCI0_FER {
TC2MCI0_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Counter 2 rising edge mode, channel 1."]
#[inline]
pub fn tc2mci1_re(&self) -> TC2MCI1_RER {
TC2MCI1_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Counter 2 falling edge mode, channel 1."]
#[inline]
pub fn tc2mci1_fe(&self) -> TC2MCI1_FER {
TC2MCI1_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Counter 2 rising edge mode, channel 2."]
#[inline]
pub fn tc2mci2_re(&self) -> TC2MCI2_RER {
TC2MCI2_RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Counter 2 falling edge mode, channel 2."]
#[inline]
pub fn tc2mci2_fe(&self) -> TC2MCI2_FER {
TC2MCI2_FER::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 29 - Channel 0 counter/timer mode."]
#[inline]
pub fn cntr0(&self) -> CNTR0R {
CNTR0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - Channel 1 counter/timer mode."]
#[inline]
pub fn cntr1(&self) -> CNTR1R {
CNTR1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 31 - Channel 2 counter/timer mode."]
#[inline]
pub fn cntr2(&self) -> CNTR2R {
CNTR2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "Count Control set address"]
pub struct CNTCON_SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Count Control set address"]
pub mod cntcon_set {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CNTCON_SET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI0_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI0_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI0_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI0_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI1_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI1_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI1_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI1_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI2_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI2_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI2_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI2_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI0_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI0_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI0_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI0_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI1_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI1_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI1_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI1_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI2_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI2_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI2_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI2_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI0_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI0_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI0_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI0_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI1_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI1_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI1_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI1_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI2_RE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI2_RE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI2_FE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI2_FE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CNTR0_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CNTR0_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CNTR1_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CNTR1_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CNTR2_SETW<'a> {
w: &'a mut W,
}
impl<'a> _CNTR2_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci0_re_set(&mut self) -> _TC0MCI0_RE_SETW {
_TC0MCI0_RE_SETW { w: self }
}
#[doc = "Bit 1 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci0_fe_set(&mut self) -> _TC0MCI0_FE_SETW {
_TC0MCI0_FE_SETW { w: self }
}
#[doc = "Bit 2 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci1_re_set(&mut self) -> _TC0MCI1_RE_SETW {
_TC0MCI1_RE_SETW { w: self }
}
#[doc = "Bit 3 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci1_fe_set(&mut self) -> _TC0MCI1_FE_SETW {
_TC0MCI1_FE_SETW { w: self }
}
#[doc = "Bit 4 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci2_re_set(&mut self) -> _TC0MCI2_RE_SETW {
_TC0MCI2_RE_SETW { w: self }
}
#[doc = "Bit 5 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci2_fe_set(&mut self) -> _TC0MCI2_FE_SETW {
_TC0MCI2_FE_SETW { w: self }
}
#[doc = "Bit 6 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci0_re_set(&mut self) -> _TC1MCI0_RE_SETW {
_TC1MCI0_RE_SETW { w: self }
}
#[doc = "Bit 7 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci0_fe_set(&mut self) -> _TC1MCI0_FE_SETW {
_TC1MCI0_FE_SETW { w: self }
}
#[doc = "Bit 8 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci1_re_set(&mut self) -> _TC1MCI1_RE_SETW {
_TC1MCI1_RE_SETW { w: self }
}
#[doc = "Bit 9 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci1_fe_set(&mut self) -> _TC1MCI1_FE_SETW {
_TC1MCI1_FE_SETW { w: self }
}
#[doc = "Bit 10 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci2_re_set(&mut self) -> _TC1MCI2_RE_SETW {
_TC1MCI2_RE_SETW { w: self }
}
#[doc = "Bit 11 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci2_fe_set(&mut self) -> _TC1MCI2_FE_SETW {
_TC1MCI2_FE_SETW { w: self }
}
#[doc = "Bit 12 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci0_re_set(&mut self) -> _TC2MCI0_RE_SETW {
_TC2MCI0_RE_SETW { w: self }
}
#[doc = "Bit 13 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci0_fe_set(&mut self) -> _TC2MCI0_FE_SETW {
_TC2MCI0_FE_SETW { w: self }
}
#[doc = "Bit 14 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci1_re_set(&mut self) -> _TC2MCI1_RE_SETW {
_TC2MCI1_RE_SETW { w: self }
}
#[doc = "Bit 15 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci1_fe_set(&mut self) -> _TC2MCI1_FE_SETW {
_TC2MCI1_FE_SETW { w: self }
}
#[doc = "Bit 16 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci2_re_set(&mut self) -> _TC2MCI2_RE_SETW {
_TC2MCI2_RE_SETW { w: self }
}
#[doc = "Bit 17 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci2_fe_set(&mut self) -> _TC2MCI2_FE_SETW {
_TC2MCI2_FE_SETW { w: self }
}
#[doc = "Bit 29 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn cntr0_set(&mut self) -> _CNTR0_SETW {
_CNTR0_SETW { w: self }
}
#[doc = "Bit 30 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn cntr1_set(&mut self) -> _CNTR1_SETW {
_CNTR1_SETW { w: self }
}
#[doc = "Bit 31 - Writing a one sets the corresponding bit in the CNTCON register."]
#[inline]
pub fn cntr2_set(&mut self) -> _CNTR2_SETW {
_CNTR2_SETW { w: self }
}
}
}
#[doc = "Count Control clear address"]
pub struct CNTCON_CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Count Control clear address"]
pub mod cntcon_clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CNTCON_CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI0_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI0_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI0_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI0_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI1_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI1_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI1_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI1_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI2_REW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI2_REW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC0MCI2_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC0MCI2_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI0_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI0_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI0_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI0_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI1_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI1_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI1_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI1_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI2_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI2_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC1MCI2_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC1MCI2_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI0_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI0_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI0_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI0_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI1_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI1_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI1_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI1_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI2_RE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI2_RE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TC2MCI2_FE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TC2MCI2_FE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CNTR0_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CNTR0_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CNTR1_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CNTR1_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CNTR2_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _CNTR2_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci0_re_clr(&mut self) -> _TC0MCI0_RE_CLRW {
_TC0MCI0_RE_CLRW { w: self }
}
#[doc = "Bit 1 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci0_fe_clr(&mut self) -> _TC0MCI0_FE_CLRW {
_TC0MCI0_FE_CLRW { w: self }
}
#[doc = "Bit 2 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci1_re_clr(&mut self) -> _TC0MCI1_RE_CLRW {
_TC0MCI1_RE_CLRW { w: self }
}
#[doc = "Bit 3 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci1_fe_clr(&mut self) -> _TC0MCI1_FE_CLRW {
_TC0MCI1_FE_CLRW { w: self }
}
#[doc = "Bit 4 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci2_re(&mut self) -> _TC0MCI2_REW {
_TC0MCI2_REW { w: self }
}
#[doc = "Bit 5 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc0mci2_fe_clr(&mut self) -> _TC0MCI2_FE_CLRW {
_TC0MCI2_FE_CLRW { w: self }
}
#[doc = "Bit 6 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci0_re_clr(&mut self) -> _TC1MCI0_RE_CLRW {
_TC1MCI0_RE_CLRW { w: self }
}
#[doc = "Bit 7 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci0_fe_clr(&mut self) -> _TC1MCI0_FE_CLRW {
_TC1MCI0_FE_CLRW { w: self }
}
#[doc = "Bit 8 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci1_re_clr(&mut self) -> _TC1MCI1_RE_CLRW {
_TC1MCI1_RE_CLRW { w: self }
}
#[doc = "Bit 9 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci1_fe_clr(&mut self) -> _TC1MCI1_FE_CLRW {
_TC1MCI1_FE_CLRW { w: self }
}
#[doc = "Bit 10 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci2_re_clr(&mut self) -> _TC1MCI2_RE_CLRW {
_TC1MCI2_RE_CLRW { w: self }
}
#[doc = "Bit 11 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc1mci2_fe_clr(&mut self) -> _TC1MCI2_FE_CLRW {
_TC1MCI2_FE_CLRW { w: self }
}
#[doc = "Bit 12 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci0_re_clr(&mut self) -> _TC2MCI0_RE_CLRW {
_TC2MCI0_RE_CLRW { w: self }
}
#[doc = "Bit 13 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci0_fe_clr(&mut self) -> _TC2MCI0_FE_CLRW {
_TC2MCI0_FE_CLRW { w: self }
}
#[doc = "Bit 14 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci1_re_clr(&mut self) -> _TC2MCI1_RE_CLRW {
_TC2MCI1_RE_CLRW { w: self }
}
#[doc = "Bit 15 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci1_fe_clr(&mut self) -> _TC2MCI1_FE_CLRW {
_TC2MCI1_FE_CLRW { w: self }
}
#[doc = "Bit 16 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci2_re_clr(&mut self) -> _TC2MCI2_RE_CLRW {
_TC2MCI2_RE_CLRW { w: self }
}
#[doc = "Bit 17 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn tc2mci2_fe_clr(&mut self) -> _TC2MCI2_FE_CLRW {
_TC2MCI2_FE_CLRW { w: self }
}
#[doc = "Bit 29 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn cntr0_clr(&mut self) -> _CNTR0_CLRW {
_CNTR0_CLRW { w: self }
}
#[doc = "Bit 30 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn cntr1_clr(&mut self) -> _CNTR1_CLRW {
_CNTR1_CLRW { w: self }
}
#[doc = "Bit 31 - Writing a one clears the corresponding bit in the CNTCON register."]
#[inline]
pub fn cntr2_clr(&mut self) -> _CNTR2_CLRW {
_CNTR2_CLRW { w: self }
}
}
}
#[doc = "Capture clear address"]
pub struct CAP_CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Capture clear address"]
pub mod cap_clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CAP_CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _CAP_CLR0W<'a> {
w: &'a mut W,
}
impl<'a> _CAP_CLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP_CLR1W<'a> {
w: &'a mut W,
}
impl<'a> _CAP_CLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAP_CLR2W<'a> {
w: &'a mut W,
}
impl<'a> _CAP_CLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 to this bit clears the CAP0 register."]
#[inline]
pub fn cap_clr0(&mut self) -> _CAP_CLR0W {
_CAP_CLR0W { w: self }
}
#[doc = "Bit 1 - Writing a 1 to this bit clears the CAP1 register."]
#[inline]
pub fn cap_clr1(&mut self) -> _CAP_CLR1W {
_CAP_CLR1W { w: self }
}
#[doc = "Bit 2 - Writing a 1 to this bit clears the CAP2 register."]
#[inline]
pub fn cap_clr2(&mut self) -> _CAP_CLR2W {
_CAP_CLR2W { w: self }
}
}
}
}
#[doc = "Quadrature Encoder Interface (QEI)"]
pub struct QEI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for QEI {}
impl QEI {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const qei::RegisterBlock {
0x400b_c000 as *const _
}
}
impl Deref for QEI {
type Target = qei::RegisterBlock;
fn deref(&self) -> &qei::RegisterBlock {
unsafe { &*QEI::ptr() }
}
}
#[doc = "Quadrature Encoder Interface (QEI)"]
pub mod qei {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control register"]
pub con: CON,
#[doc = "0x04 - Status register"]
pub stat: STAT,
#[doc = "0x08 - Configuration register"]
pub conf: CONF,
#[doc = "0x0c - Position register"]
pub pos: POS,
#[doc = "0x10 - Maximum position register"]
pub maxpos: MAXPOS,
#[doc = "0x14 - Position compare register 0"]
pub cmpos0: CMPOS0,
#[doc = "0x18 - Position compare register 1"]
pub cmpos1: CMPOS1,
#[doc = "0x1c - Position compare register 2"]
pub cmpos2: CMPOS2,
#[doc = "0x20 - Index count register 0"]
pub inxcnt: INXCNT,
#[doc = "0x24 - Index compare register 0"]
pub inxcmp0: INXCMP0,
#[doc = "0x28 - Velocity timer reload register"]
pub load: LOAD,
#[doc = "0x2c - Velocity timer register"]
pub time: TIME,
#[doc = "0x30 - Velocity counter register"]
pub vel: VEL,
#[doc = "0x34 - Velocity capture register"]
pub cap: CAP,
#[doc = "0x38 - Velocity compare register"]
pub velcomp: VELCOMP,
#[doc = "0x3c - Digital filter register"]
pub filter: FILTER,
_reserved16: [u8; 3992usize],
#[doc = "0xfd8 - Interrupt enable clear register"]
pub iec: IEC,
#[doc = "0xfdc - Interrupt enable set register"]
pub ies: IES,
#[doc = "0xfe0 - Interrupt status register"]
pub intstat: INTSTAT,
#[doc = "0xfe4 - Interrupt enable register"]
pub ie: IE,
#[doc = "0xfe8 - Interrupt status clear register"]
pub clr: CLR,
#[doc = "0xfec - Interrupt status set register"]
pub set: SET,
}
#[doc = "Control register"]
pub struct CON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Control register"]
pub mod con {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CON {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _RESPW<'a> {
w: &'a mut W,
}
impl<'a> _RESPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESPIW<'a> {
w: &'a mut W,
}
impl<'a> _RESPIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESVW<'a> {
w: &'a mut W,
}
impl<'a> _RESVW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESIW<'a> {
w: &'a mut W,
}
impl<'a> _RESIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared."]
#[inline]
pub fn resp(&mut self) -> _RESPW {
_RESPW { w: self }
}
#[doc = "Bit 1 - Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared."]
#[inline]
pub fn respi(&mut self) -> _RESPIW {
_RESPIW { w: self }
}
#[doc = "Bit 2 - Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared."]
#[inline]
pub fn resv(&mut self) -> _RESVW {
_RESVW { w: self }
}
#[doc = "Bit 3 - Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared."]
#[inline]
pub fn resi(&mut self) -> _RESIW {
_RESIW { w: self }
}
}
}
#[doc = "Configuration register"]
pub struct CONF {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Configuration register"]
pub mod conf {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CONF {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DIRINVR {
bits: bool,
}
impl DIRINVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SIGMODER {
bits: bool,
}
impl SIGMODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAPMODER {
bits: bool,
}
impl CAPMODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INVINXR {
bits: bool,
}
impl INVINXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CRESPIR {
bits: bool,
}
impl CRESPIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INXGATER {
bits: u8,
}
impl INXGATER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DIRINVW<'a> {
w: &'a mut W,
}
impl<'a> _DIRINVW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SIGMODEW<'a> {
w: &'a mut W,
}
impl<'a> _SIGMODEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAPMODEW<'a> {
w: &'a mut W,
}
impl<'a> _CAPMODEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INVINXW<'a> {
w: &'a mut W,
}
impl<'a> _INVINXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CRESPIW<'a> {
w: &'a mut W,
}
impl<'a> _CRESPIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INXGATEW<'a> {
w: &'a mut W,
}
impl<'a> _INXGATEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Direction invert. When 1, complements the DIR bit."]
#[inline]
pub fn dirinv(&self) -> DIRINVR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DIRINVR { bits }
}
#[doc = "Bit 1 - Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal."]
#[inline]
pub fn sigmode(&self) -> SIGMODER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SIGMODER { bits }
}
#[doc = "Bit 2 - Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range."]
#[inline]
pub fn capmode(&self) -> CAPMODER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAPMODER { bits }
}
#[doc = "Bit 3 - Invert Index. When 1, inverts the sense of the index input."]
#[inline]
pub fn invinx(&self) -> INVINXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INVINXR { bits }
}
#[doc = "Bit 4 - Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)."]
#[inline]
pub fn crespi(&self) -> CRESPIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CRESPIR { bits }
}
#[doc = "Bits 16:19 - Index gating configuration: When INXGATE\\[16\\] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE\\[17\\] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE\\[18\\] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE\\[19\\] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index."]
#[inline]
pub fn inxgate(&self) -> INXGATER {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
INXGATER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Direction invert. When 1, complements the DIR bit."]
#[inline]
pub fn dirinv(&mut self) -> _DIRINVW {
_DIRINVW { w: self }
}
#[doc = "Bit 1 - Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal."]
#[inline]
pub fn sigmode(&mut self) -> _SIGMODEW {
_SIGMODEW { w: self }
}
#[doc = "Bit 2 - Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range."]
#[inline]
pub fn capmode(&mut self) -> _CAPMODEW {
_CAPMODEW { w: self }
}
#[doc = "Bit 3 - Invert Index. When 1, inverts the sense of the index input."]
#[inline]
pub fn invinx(&mut self) -> _INVINXW {
_INVINXW { w: self }
}
#[doc = "Bit 4 - Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)."]
#[inline]
pub fn crespi(&mut self) -> _CRESPIW {
_CRESPIW { w: self }
}
#[doc = "Bits 16:19 - Index gating configuration: When INXGATE\\[16\\] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE\\[17\\] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE\\[18\\] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE\\[19\\] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index."]
#[inline]
pub fn inxgate(&mut self) -> _INXGATEW {
_INXGATEW { w: self }
}
}
}
#[doc = "Status register"]
pub struct STAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status register"]
pub mod stat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DIRR {
bits: bool,
}
impl DIRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597."]
#[inline]
pub fn dir(&self) -> DIRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DIRR { bits }
}
}
}
#[doc = "Position register"]
pub struct POS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Position register"]
pub mod pos {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::POS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct POSR {
bits: u32,
}
impl POSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current position value."]
#[inline]
pub fn pos(&self) -> POSR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
POSR { bits }
}
}
}
#[doc = "Maximum position register"]
pub struct MAXPOS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Maximum position register"]
pub mod maxpos {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MAXPOS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MAXPOSR {
bits: u32,
}
impl MAXPOSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MAXPOSW<'a> {
w: &'a mut W,
}
impl<'a> _MAXPOSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current maximum position value."]
#[inline]
pub fn maxpos(&self) -> MAXPOSR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
MAXPOSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Current maximum position value."]
#[inline]
pub fn maxpos(&mut self) -> _MAXPOSW {
_MAXPOSW { w: self }
}
}
}
#[doc = "Position compare register 0"]
pub struct CMPOS0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Position compare register 0"]
pub mod cmpos0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CMPOS0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PCMP0R {
bits: u32,
}
impl PCMP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PCMP0W<'a> {
w: &'a mut W,
}
impl<'a> _PCMP0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Position compare value 0."]
#[inline]
pub fn pcmp0(&self) -> PCMP0R {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PCMP0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xffff_ffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Position compare value 0."]
#[inline]
pub fn pcmp0(&mut self) -> _PCMP0W {
_PCMP0W { w: self }
}
}
}
#[doc = "Position compare register 1"]
pub struct CMPOS1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Position compare register 1"]
pub mod cmpos1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CMPOS1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PCMP1R {
bits: u32,
}
impl PCMP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PCMP1W<'a> {
w: &'a mut W,
}
impl<'a> _PCMP1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Position compare value 1."]
#[inline]
pub fn pcmp1(&self) -> PCMP1R {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PCMP1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xffff_ffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Position compare value 1."]
#[inline]
pub fn pcmp1(&mut self) -> _PCMP1W {
_PCMP1W { w: self }
}
}
}
#[doc = "Position compare register 2"]
pub struct CMPOS2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Position compare register 2"]
pub mod cmpos2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CMPOS2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PCMP2R {
bits: u32,
}
impl PCMP2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PCMP2W<'a> {
w: &'a mut W,
}
impl<'a> _PCMP2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Position compare value 2."]
#[inline]
pub fn pcmp2(&self) -> PCMP2R {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
PCMP2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xffff_ffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Position compare value 2."]
#[inline]
pub fn pcmp2(&mut self) -> _PCMP2W {
_PCMP2W { w: self }
}
}
}
#[doc = "Index count register 0"]
pub struct INXCNT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Index count register 0"]
pub mod inxcnt {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INXCNT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct ENCPOSR {
bits: u32,
}
impl ENCPOSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current index counter value."]
#[inline]
pub fn encpos(&self) -> ENCPOSR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
ENCPOSR { bits }
}
}
}
#[doc = "Index compare register 0"]
pub struct INXCMP0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Index compare register 0"]
pub mod inxcmp0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INXCMP0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ICMP0R {
bits: u32,
}
impl ICMP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _ICMP0W<'a> {
w: &'a mut W,
}
impl<'a> _ICMP0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Index compare value 0."]
#[inline]
pub fn icmp0(&self) -> ICMP0R {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
ICMP0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xffff_ffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Index compare value 0."]
#[inline]
pub fn icmp0(&mut self) -> _ICMP0W {
_ICMP0W { w: self }
}
}
}
#[doc = "Velocity timer reload register"]
pub struct LOAD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Velocity timer reload register"]
pub mod load {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::LOAD {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct VELLOADR {
bits: u32,
}
impl VELLOADR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _VELLOADW<'a> {
w: &'a mut W,
}
impl<'a> _VELLOADW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current velocity timer load value."]
#[inline]
pub fn velload(&self) -> VELLOADR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VELLOADR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Current velocity timer load value."]
#[inline]
pub fn velload(&mut self) -> _VELLOADW {
_VELLOADW { w: self }
}
}
}
#[doc = "Velocity timer register"]
pub struct TIME {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Velocity timer register"]
pub mod time {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::TIME {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct VELVALR {
bits: u32,
}
impl VELVALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current velocity timer value."]
#[inline]
pub fn velval(&self) -> VELVALR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VELVALR { bits }
}
}
}
#[doc = "Velocity counter register"]
pub struct VEL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Velocity counter register"]
pub mod vel {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::VEL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct VELPCR {
bits: u32,
}
impl VELPCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Current velocity pulse count."]
#[inline]
pub fn velpc(&self) -> VELPCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VELPCR { bits }
}
}
}
#[doc = "Velocity capture register"]
pub struct CAP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Velocity capture register"]
pub mod cap {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CAP {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct VELCAPR {
bits: u32,
}
impl VELCAPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Last velocity capture."]
#[inline]
pub fn velcap(&self) -> VELCAPR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VELCAPR { bits }
}
}
}
#[doc = "Velocity compare register"]
pub struct VELCOMP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Velocity compare register"]
pub mod velcomp {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::VELCOMP {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct VELPCR {
bits: u32,
}
impl VELPCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _VELPCW<'a> {
w: &'a mut W,
}
impl<'a> _VELPCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Compare velocity pulse count."]
#[inline]
pub fn velpc(&self) -> VELPCR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VELPCR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Compare velocity pulse count."]
#[inline]
pub fn velpc(&mut self) -> _VELPCW {
_VELPCW { w: self }
}
}
}
#[doc = "Digital filter register"]
pub struct FILTER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Digital filter register"]
pub mod filter {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FILTER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FILTAR {
bits: u32,
}
impl FILTAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _FILTAW<'a> {
w: &'a mut W,
}
impl<'a> _FILTAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Digital filter sampling delay."]
#[inline]
pub fn filta(&self) -> FILTAR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FILTAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Digital filter sampling delay."]
#[inline]
pub fn filta(&mut self) -> _FILTAW {
_FILTAW { w: self }
}
}
}
#[doc = "Interrupt status register"]
pub struct INTSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt status register"]
pub mod intstat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTSTAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct INX_INTR {
bits: bool,
}
impl INX_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TIM_INTR {
bits: bool,
}
impl TIM_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct VELC_INTR {
bits: bool,
}
impl VELC_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DIR_INTR {
bits: bool,
}
impl DIR_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ERR_INTR {
bits: bool,
}
impl ERR_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENCLK_INTR {
bits: bool,
}
impl ENCLK_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS0_INTR {
bits: bool,
}
impl POS0_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS1_INTR {
bits: bool,
}
impl POS1_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS2_INTR {
bits: bool,
}
impl POS2_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REV0_INTR {
bits: bool,
}
impl REV0_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS0REV_INTR {
bits: bool,
}
impl POS0REV_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS1REV_INTR {
bits: bool,
}
impl POS1REV_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS2REV_INTR {
bits: bool,
}
impl POS2REV_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REV1_INTR {
bits: bool,
}
impl REV1_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REV2_INTR {
bits: bool,
}
impl REV2_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAXPOS_INTR {
bits: bool,
}
impl MAXPOS_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Indicates that an index pulse was detected."]
#[inline]
pub fn inx_int(&self) -> INX_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INX_INTR { bits }
}
#[doc = "Bit 1 - Indicates that a velocity timer overflow occurred"]
#[inline]
pub fn tim_int(&self) -> TIM_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TIM_INTR { bits }
}
#[doc = "Bit 2 - Indicates that captured velocity is less than compare velocity."]
#[inline]
pub fn velc_int(&self) -> VELC_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
VELC_INTR { bits }
}
#[doc = "Bit 3 - Indicates that a change of direction was detected."]
#[inline]
pub fn dir_int(&self) -> DIR_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DIR_INTR { bits }
}
#[doc = "Bit 4 - Indicates that an encoder phase error was detected."]
#[inline]
pub fn err_int(&self) -> ERR_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ERR_INTR { bits }
}
#[doc = "Bit 5 - Indicates that and encoder clock pulse was detected."]
#[inline]
pub fn enclk_int(&self) -> ENCLK_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENCLK_INTR { bits }
}
#[doc = "Bit 6 - Indicates that the position 0 compare value is equal to the current position."]
#[inline]
pub fn pos0_int(&self) -> POS0_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS0_INTR { bits }
}
#[doc = "Bit 7 - Indicates that the position 1compare value is equal to the current position."]
#[inline]
pub fn pos1_int(&self) -> POS1_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS1_INTR { bits }
}
#[doc = "Bit 8 - Indicates that the position 2 compare value is equal to the current position."]
#[inline]
pub fn pos2_int(&self) -> POS2_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS2_INTR { bits }
}
#[doc = "Bit 9 - Indicates that the index compare 0 value is equal to the current index count."]
#[inline]
pub fn rev0_int(&self) -> REV0_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REV0_INTR { bits }
}
#[doc = "Bit 10 - Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set."]
#[inline]
pub fn pos0rev_int(&self) -> POS0REV_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS0REV_INTR { bits }
}
#[doc = "Bit 11 - Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set."]
#[inline]
pub fn pos1rev_int(&self) -> POS1REV_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS1REV_INTR { bits }
}
#[doc = "Bit 12 - Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set."]
#[inline]
pub fn pos2rev_int(&self) -> POS2REV_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS2REV_INTR { bits }
}
#[doc = "Bit 13 - Indicates that the index compare 1value is equal to the current index count."]
#[inline]
pub fn rev1_int(&self) -> REV1_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REV1_INTR { bits }
}
#[doc = "Bit 14 - Indicates that the index compare 2 value is equal to the current index count."]
#[inline]
pub fn rev2_int(&self) -> REV2_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REV2_INTR { bits }
}
#[doc = "Bit 15 - Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction."]
#[inline]
pub fn maxpos_int(&self) -> MAXPOS_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAXPOS_INTR { bits }
}
}
}
#[doc = "Interrupt status set register"]
pub struct SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt status set register"]
pub mod set {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _INX_INTW<'a> {
w: &'a mut W,
}
impl<'a> _INX_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIM_INTW<'a> {
w: &'a mut W,
}
impl<'a> _TIM_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _VELC_INTW<'a> {
w: &'a mut W,
}
impl<'a> _VELC_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DIR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _DIR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ENCLK_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ENCLK_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAXPOS_INTW<'a> {
w: &'a mut W,
}
impl<'a> _MAXPOS_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 sets the INX_Int bit in QEIINTSTAT."]
#[inline]
pub fn inx_int(&mut self) -> _INX_INTW {
_INX_INTW { w: self }
}
#[doc = "Bit 1 - Writing a 1 sets the TIN_Int bit in QEIINTSTAT."]
#[inline]
pub fn tim_int(&mut self) -> _TIM_INTW {
_TIM_INTW { w: self }
}
#[doc = "Bit 2 - Writing a 1 sets the VELC_Int bit in QEIINTSTAT."]
#[inline]
pub fn velc_int(&mut self) -> _VELC_INTW {
_VELC_INTW { w: self }
}
#[doc = "Bit 3 - Writing a 1 sets the DIR_Int bit in QEIINTSTAT."]
#[inline]
pub fn dir_int(&mut self) -> _DIR_INTW {
_DIR_INTW { w: self }
}
#[doc = "Bit 4 - Writing a 1 sets the ERR_Int bit in QEIINTSTAT."]
#[inline]
pub fn err_int(&mut self) -> _ERR_INTW {
_ERR_INTW { w: self }
}
#[doc = "Bit 5 - Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT."]
#[inline]
pub fn enclk_int(&mut self) -> _ENCLK_INTW {
_ENCLK_INTW { w: self }
}
#[doc = "Bit 6 - Writing a 1 sets the POS0_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
#[doc = "Bit 7 - Writing a 1 sets the POS1_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
#[doc = "Bit 8 - Writing a 1 sets the POS2_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
#[doc = "Bit 9 - Writing a 1 sets the REV0_Int bit in QEIINTSTAT."]
#[inline]
pub fn rev0_int(&mut self) -> _REV0_INTW {
_REV0_INTW { w: self }
}
#[doc = "Bit 10 - Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
#[doc = "Bit 11 - Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
#[doc = "Bit 12 - Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
#[doc = "Bit 13 - Writing a 1 sets the REV1_Int bit in QEIINTSTAT."]
#[inline]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
#[doc = "Bit 14 - Writing a 1 sets the REV2_Int bit in QEIINTSTAT."]
#[inline]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
#[doc = "Bit 15 - Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT."]
#[inline]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
}
}
#[doc = "Interrupt status clear register"]
pub struct CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt status clear register"]
pub mod clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _INX_INTW<'a> {
w: &'a mut W,
}
impl<'a> _INX_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIM_INTW<'a> {
w: &'a mut W,
}
impl<'a> _TIM_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _VELC_INTW<'a> {
w: &'a mut W,
}
impl<'a> _VELC_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DIR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _DIR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ENCLK_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ENCLK_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAXPOS_INTW<'a> {
w: &'a mut W,
}
impl<'a> _MAXPOS_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 clears the INX_Int bit in QEIINTSTAT."]
#[inline]
pub fn inx_int(&mut self) -> _INX_INTW {
_INX_INTW { w: self }
}
#[doc = "Bit 1 - Writing a 1 clears the TIN_Int bit in QEIINTSTAT."]
#[inline]
pub fn tim_int(&mut self) -> _TIM_INTW {
_TIM_INTW { w: self }
}
#[doc = "Bit 2 - Writing a 1 clears the VELC_Int bit in QEIINTSTAT."]
#[inline]
pub fn velc_int(&mut self) -> _VELC_INTW {
_VELC_INTW { w: self }
}
#[doc = "Bit 3 - Writing a 1 clears the DIR_Int bit in QEIINTSTAT."]
#[inline]
pub fn dir_int(&mut self) -> _DIR_INTW {
_DIR_INTW { w: self }
}
#[doc = "Bit 4 - Writing a 1 clears the ERR_Int bit in QEIINTSTAT."]
#[inline]
pub fn err_int(&mut self) -> _ERR_INTW {
_ERR_INTW { w: self }
}
#[doc = "Bit 5 - Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT."]
#[inline]
pub fn enclk_int(&mut self) -> _ENCLK_INTW {
_ENCLK_INTW { w: self }
}
#[doc = "Bit 6 - Writing a 1 clears the POS0_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
#[doc = "Bit 7 - Writing a 1 clears the POS1_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
#[doc = "Bit 8 - Writing a 1 clears the POS2_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
#[doc = "Bit 9 - Writing a 1 clears the REV0_Int bit in QEIINTSTAT."]
#[inline]
pub fn rev0_int(&mut self) -> _REV0_INTW {
_REV0_INTW { w: self }
}
#[doc = "Bit 10 - Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
#[doc = "Bit 11 - Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
#[doc = "Bit 12 - Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT."]
#[inline]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
#[doc = "Bit 13 - Writing a 1 clears the REV1_Int bit in QEIINTSTAT."]
#[inline]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
#[doc = "Bit 14 - Writing a 1 clears the REV2_Int bit in QEIINTSTAT."]
#[inline]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
#[doc = "Bit 15 - Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT."]
#[inline]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
}
}
#[doc = "Interrupt enable register"]
pub struct IE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt enable register"]
pub mod ie {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::IE {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct INX_INTR {
bits: bool,
}
impl INX_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TIM_INTR {
bits: bool,
}
impl TIM_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct VELC_INTR {
bits: bool,
}
impl VELC_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DIR_INTR {
bits: bool,
}
impl DIR_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ERR_INTR {
bits: bool,
}
impl ERR_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENCLK_INTR {
bits: bool,
}
impl ENCLK_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS0_INTR {
bits: bool,
}
impl POS0_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS1_INTR {
bits: bool,
}
impl POS1_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS2_INTR {
bits: bool,
}
impl POS2_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REV0_INTR {
bits: bool,
}
impl REV0_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS0REV_INTR {
bits: bool,
}
impl POS0REV_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS1REV_INTR {
bits: bool,
}
impl POS1REV_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct POS2REV_INTR {
bits: bool,
}
impl POS2REV_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REV1_INTR {
bits: bool,
}
impl REV1_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REV2_INTR {
bits: bool,
}
impl REV2_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MAXPOS_INTR {
bits: bool,
}
impl MAXPOS_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1, the INX_Int interrupt is enabled."]
#[inline]
pub fn inx_int(&self) -> INX_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INX_INTR { bits }
}
#[doc = "Bit 1 - When 1, the TIN_Int interrupt is enabled."]
#[inline]
pub fn tim_int(&self) -> TIM_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TIM_INTR { bits }
}
#[doc = "Bit 2 - When 1, the VELC_Int interrupt is enabled."]
#[inline]
pub fn velc_int(&self) -> VELC_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
VELC_INTR { bits }
}
#[doc = "Bit 3 - When 1, the DIR_Int interrupt is enabled."]
#[inline]
pub fn dir_int(&self) -> DIR_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DIR_INTR { bits }
}
#[doc = "Bit 4 - When 1, the ERR_Int interrupt is enabled."]
#[inline]
pub fn err_int(&self) -> ERR_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ERR_INTR { bits }
}
#[doc = "Bit 5 - When 1, the ENCLK_Int interrupt is enabled."]
#[inline]
pub fn enclk_int(&self) -> ENCLK_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENCLK_INTR { bits }
}
#[doc = "Bit 6 - When 1, the POS0_Int interrupt is enabled."]
#[inline]
pub fn pos0_int(&self) -> POS0_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS0_INTR { bits }
}
#[doc = "Bit 7 - When 1, the POS1_Int interrupt is enabled."]
#[inline]
pub fn pos1_int(&self) -> POS1_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS1_INTR { bits }
}
#[doc = "Bit 8 - When 1, the POS2_Int interrupt is enabled."]
#[inline]
pub fn pos2_int(&self) -> POS2_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS2_INTR { bits }
}
#[doc = "Bit 9 - When 1, the REV0_Int interrupt is enabled."]
#[inline]
pub fn rev0_int(&self) -> REV0_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REV0_INTR { bits }
}
#[doc = "Bit 10 - When 1, the POS0REV_Int interrupt is enabled."]
#[inline]
pub fn pos0rev_int(&self) -> POS0REV_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS0REV_INTR { bits }
}
#[doc = "Bit 11 - When 1, the POS1REV_Int interrupt is enabled."]
#[inline]
pub fn pos1rev_int(&self) -> POS1REV_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS1REV_INTR { bits }
}
#[doc = "Bit 12 - When 1, the POS2REV_Int interrupt is enabled."]
#[inline]
pub fn pos2rev_int(&self) -> POS2REV_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
POS2REV_INTR { bits }
}
#[doc = "Bit 13 - When 1, the REV1_Int interrupt is enabled."]
#[inline]
pub fn rev1_int(&self) -> REV1_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REV1_INTR { bits }
}
#[doc = "Bit 14 - When 1, the REV2_Int interrupt is enabled."]
#[inline]
pub fn rev2_int(&self) -> REV2_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REV2_INTR { bits }
}
#[doc = "Bit 15 - When 1, the MAXPOS_Int interrupt is enabled."]
#[inline]
pub fn maxpos_int(&self) -> MAXPOS_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MAXPOS_INTR { bits }
}
}
}
#[doc = "Interrupt enable set register"]
pub struct IES {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt enable set register"]
pub mod ies {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IES {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _INX_INTW<'a> {
w: &'a mut W,
}
impl<'a> _INX_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIM_INTW<'a> {
w: &'a mut W,
}
impl<'a> _TIM_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _VELC_INTW<'a> {
w: &'a mut W,
}
impl<'a> _VELC_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DIR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _DIR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ENCLK_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ENCLK_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAXPOS_INTW<'a> {
w: &'a mut W,
}
impl<'a> _MAXPOS_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 enables the INX_Int interrupt in the QEIIE register."]
#[inline]
pub fn inx_int(&mut self) -> _INX_INTW {
_INX_INTW { w: self }
}
#[doc = "Bit 1 - Writing a 1 enables the TIN_Int interrupt in the QEIIE register."]
#[inline]
pub fn tim_int(&mut self) -> _TIM_INTW {
_TIM_INTW { w: self }
}
#[doc = "Bit 2 - Writing a 1 enables the VELC_Int interrupt in the QEIIE register."]
#[inline]
pub fn velc_int(&mut self) -> _VELC_INTW {
_VELC_INTW { w: self }
}
#[doc = "Bit 3 - Writing a 1 enables the DIR_Int interrupt in the QEIIE register."]
#[inline]
pub fn dir_int(&mut self) -> _DIR_INTW {
_DIR_INTW { w: self }
}
#[doc = "Bit 4 - Writing a 1 enables the ERR_Int interrupt in the QEIIE register."]
#[inline]
pub fn err_int(&mut self) -> _ERR_INTW {
_ERR_INTW { w: self }
}
#[doc = "Bit 5 - Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register."]
#[inline]
pub fn enclk_int(&mut self) -> _ENCLK_INTW {
_ENCLK_INTW { w: self }
}
#[doc = "Bit 6 - Writing a 1 enables the POS0_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
#[doc = "Bit 7 - Writing a 1 enables the POS1_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
#[doc = "Bit 8 - Writing a 1 enables the POS2_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
#[doc = "Bit 9 - Writing a 1 enables the REV0_Int interrupt in the QEIIE register."]
#[inline]
pub fn rev0_int(&mut self) -> _REV0_INTW {
_REV0_INTW { w: self }
}
#[doc = "Bit 10 - Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
#[doc = "Bit 11 - Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
#[doc = "Bit 12 - Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
#[doc = "Bit 13 - Writing a 1 enables the REV1_Int interrupt in the QEIIE register."]
#[inline]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
#[doc = "Bit 14 - Writing a 1 enables the REV2_Int interrupt in the QEIIE register."]
#[inline]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
#[doc = "Bit 15 - Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register."]
#[inline]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
}
}
#[doc = "Interrupt enable clear register"]
pub struct IEC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt enable clear register"]
pub mod iec {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IEC {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _INX_INTW<'a> {
w: &'a mut W,
}
impl<'a> _INX_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TIM_INTW<'a> {
w: &'a mut W,
}
impl<'a> _TIM_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _VELC_INTW<'a> {
w: &'a mut W,
}
impl<'a> _VELC_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DIR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _DIR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ENCLK_INTW<'a> {
w: &'a mut W,
}
impl<'a> _ENCLK_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV0_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV0_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS0REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS0REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS1REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS1REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _POS2REV_INTW<'a> {
w: &'a mut W,
}
impl<'a> _POS2REV_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV1_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV1_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REV2_INTW<'a> {
w: &'a mut W,
}
impl<'a> _REV2_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MAXPOS_INTW<'a> {
w: &'a mut W,
}
impl<'a> _MAXPOS_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 disables the INX_Int interrupt in the QEIIE register."]
#[inline]
pub fn inx_int(&mut self) -> _INX_INTW {
_INX_INTW { w: self }
}
#[doc = "Bit 1 - Writing a 1 disables the TIN_Int interrupt in the QEIIE register."]
#[inline]
pub fn tim_int(&mut self) -> _TIM_INTW {
_TIM_INTW { w: self }
}
#[doc = "Bit 2 - Writing a 1 disables the VELC_Int interrupt in the QEIIE register."]
#[inline]
pub fn velc_int(&mut self) -> _VELC_INTW {
_VELC_INTW { w: self }
}
#[doc = "Bit 3 - Writing a 1 disables the DIR_Int interrupt in the QEIIE register."]
#[inline]
pub fn dir_int(&mut self) -> _DIR_INTW {
_DIR_INTW { w: self }
}
#[doc = "Bit 4 - Writing a 1 disables the ERR_Int interrupt in the QEIIE register."]
#[inline]
pub fn err_int(&mut self) -> _ERR_INTW {
_ERR_INTW { w: self }
}
#[doc = "Bit 5 - Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register."]
#[inline]
pub fn enclk_int(&mut self) -> _ENCLK_INTW {
_ENCLK_INTW { w: self }
}
#[doc = "Bit 6 - Writing a 1 disables the POS0_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos0_int(&mut self) -> _POS0_INTW {
_POS0_INTW { w: self }
}
#[doc = "Bit 7 - Writing a 1 disables the POS1_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos1_int(&mut self) -> _POS1_INTW {
_POS1_INTW { w: self }
}
#[doc = "Bit 8 - Writing a 1 disables the POS2_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos2_int(&mut self) -> _POS2_INTW {
_POS2_INTW { w: self }
}
#[doc = "Bit 9 - Writing a 1 disables the REV0_Int interrupt in the QEIIE register."]
#[inline]
pub fn rev0_int(&mut self) -> _REV0_INTW {
_REV0_INTW { w: self }
}
#[doc = "Bit 10 - Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos0rev_int(&mut self) -> _POS0REV_INTW {
_POS0REV_INTW { w: self }
}
#[doc = "Bit 11 - Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos1rev_int(&mut self) -> _POS1REV_INTW {
_POS1REV_INTW { w: self }
}
#[doc = "Bit 12 - Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register."]
#[inline]
pub fn pos2rev_int(&mut self) -> _POS2REV_INTW {
_POS2REV_INTW { w: self }
}
#[doc = "Bit 13 - Writing a 1 disables the REV1_Int interrupt in the QEIIE register."]
#[inline]
pub fn rev1_int(&mut self) -> _REV1_INTW {
_REV1_INTW { w: self }
}
#[doc = "Bit 14 - Writing a 1 disables the REV2_Int interrupt in the QEIIE register."]
#[inline]
pub fn rev2_int(&mut self) -> _REV2_INTW {
_REV2_INTW { w: self }
}
#[doc = "Bit 15 - Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register."]
#[inline]
pub fn maxpos_int(&mut self) -> _MAXPOS_INTW {
_MAXPOS_INTW { w: self }
}
}
}
}
#[doc = "System and clock control"]
pub struct SYSCON {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SYSCON {}
impl SYSCON {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const syscon::RegisterBlock {
0x400f_c000 as *const _
}
}
impl Deref for SYSCON {
type Target = syscon::RegisterBlock;
fn deref(&self) -> &syscon::RegisterBlock {
unsafe { &*SYSCON::ptr() }
}
}
#[doc = "System and clock control"]
pub mod syscon {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Flash Accelerator Configuration Register. Controls flash access timing."]
pub flashcfg: FLASHCFG,
_reserved1: [u8; 124usize],
#[doc = "0x80 - PLL0 Control Register"]
pub pll0con: PLL0CON,
#[doc = "0x84 - PLL0 Configuration Register"]
pub pll0cfg: PLL0CFG,
#[doc = "0x88 - PLL0 Status Register"]
pub pll0stat: PLL0STAT,
#[doc = "0x8c - PLL0 Feed Register"]
pub pll0feed: PLL0FEED,
_reserved5: [u8; 16usize],
#[doc = "0xa0 - PLL1 Control Register"]
pub pll1con: PLL1CON,
#[doc = "0xa4 - PLL1 Configuration Register"]
pub pll1cfg: PLL1CFG,
#[doc = "0xa8 - PLL1 Status Register"]
pub pll1stat: PLL1STAT,
#[doc = "0xac - PLL1 Feed Register"]
pub pll1feed: PLL1FEED,
_reserved9: [u8; 16usize],
#[doc = "0xc0 - Power Control Register"]
pub pcon: PCON,
#[doc = "0xc4 - Power Control for Peripherals Register"]
pub pconp: PCONP,
_reserved11: [u8; 60usize],
#[doc = "0x104 - CPU Clock Configuration Register"]
pub cclkcfg: CCLKCFG,
#[doc = "0x108 - USB Clock Configuration Register"]
pub usbclkcfg: USBCLKCFG,
#[doc = "0x10c - Clock Source Select Register"]
pub clksrcsel: CLKSRCSEL,
#[doc = "0x110 - Allows clearing the current CAN channel sleep state as well as reading that state."]
pub cansleepclr: CANSLEEPCLR,
#[doc = "0x114 - Allows reading the wake-up state of the CAN channels."]
pub canwakeflags: CANWAKEFLAGS,
_reserved16: [u8; 40usize],
#[doc = "0x140 - External Interrupt Flag Register"]
pub extint: EXTINT,
_reserved17: [u8; 4usize],
#[doc = "0x148 - External Interrupt Mode register"]
pub extmode: EXTMODE,
#[doc = "0x14c - External Interrupt Polarity Register"]
pub extpolar: EXTPOLAR,
_reserved19: [u8; 48usize],
#[doc = "0x180 - Reset Source Identification Register"]
pub rsid: RSID,
_reserved20: [u8; 28usize],
#[doc = "0x1a0 - System control and status"]
pub scs: SCS,
_reserved21: [u8; 4usize],
#[doc = "0x1a8 - Peripheral Clock Selection register 0."]
pub pclksel0: PCLKSEL0,
#[doc = "0x1ac - Peripheral Clock Selection register 1."]
pub pclksel1: PCLKSEL1,
_reserved23: [u8; 16usize],
#[doc = "0x1c0 - USB Interrupt Status"]
pub usbintst: USBINTST,
#[doc = "0x1c4 - Selects between alternative requests on DMA channels 0 through 7 and 10 through 15"]
pub dmacreqsel: DMACREQSEL,
#[doc = "0x1c8 - Clock Output Configuration Register"]
pub clkoutcfg: CLKOUTCFG,
}
#[doc = "Flash Accelerator Configuration Register. Controls flash access timing."]
pub struct FLASHCFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Flash Accelerator Configuration Register. Controls flash access timing."]
pub mod flashcfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FLASHCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `FLASHTIM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLASHTIMR {
#[doc = "Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock."]
_1CLK,
#[doc = "Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock."]
_2CLK,
#[doc = "Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock."]
_3CLK,
#[doc = "Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock."]
_4CLK,
#[doc = "Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only."]
_5CLK,
#[doc = "Flash accesses use 6 CPU clocks. This safe setting will work under any conditions."]
_6CLK,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FLASHTIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
FLASHTIMR::_1CLK => 0,
FLASHTIMR::_2CLK => 0x01,
FLASHTIMR::_3CLK => 0x02,
FLASHTIMR::_4CLK => 0x03,
FLASHTIMR::_5CLK => 0x04,
FLASHTIMR::_6CLK => 0x05,
FLASHTIMR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> FLASHTIMR {
match value {
0 => FLASHTIMR::_1CLK,
1 => FLASHTIMR::_2CLK,
2 => FLASHTIMR::_3CLK,
3 => FLASHTIMR::_4CLK,
4 => FLASHTIMR::_5CLK,
5 => FLASHTIMR::_6CLK,
i => FLASHTIMR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_1CLK`"]
#[inline]
pub fn is_1clk(&self) -> bool {
*self == FLASHTIMR::_1CLK
}
#[doc = "Checks if the value of the field is `_2CLK`"]
#[inline]
pub fn is_2clk(&self) -> bool {
*self == FLASHTIMR::_2CLK
}
#[doc = "Checks if the value of the field is `_3CLK`"]
#[inline]
pub fn is_3clk(&self) -> bool {
*self == FLASHTIMR::_3CLK
}
#[doc = "Checks if the value of the field is `_4CLK`"]
#[inline]
pub fn is_4clk(&self) -> bool {
*self == FLASHTIMR::_4CLK
}
#[doc = "Checks if the value of the field is `_5CLK`"]
#[inline]
pub fn is_5clk(&self) -> bool {
*self == FLASHTIMR::_5CLK
}
#[doc = "Checks if the value of the field is `_6CLK`"]
#[inline]
pub fn is_6clk(&self) -> bool {
*self == FLASHTIMR::_6CLK
}
}
#[doc = "Values that can be written to the field `FLASHTIM`"]
pub enum FLASHTIMW {
#[doc = "Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock."]
_1CLK,
#[doc = "Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock."]
_2CLK,
#[doc = "Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock."]
_3CLK,
#[doc = "Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock."]
_4CLK,
#[doc = "Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only."]
_5CLK,
#[doc = "Flash accesses use 6 CPU clocks. This safe setting will work under any conditions."]
_6CLK,
}
impl FLASHTIMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
FLASHTIMW::_1CLK => 0,
FLASHTIMW::_2CLK => 1,
FLASHTIMW::_3CLK => 2,
FLASHTIMW::_4CLK => 3,
FLASHTIMW::_5CLK => 4,
FLASHTIMW::_6CLK => 5,
}
}
}
#[doc = r" Proxy"]
pub struct _FLASHTIMW<'a> {
w: &'a mut W,
}
impl<'a> _FLASHTIMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FLASHTIMW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock."]
#[inline]
pub fn _1clk(self) -> &'a mut W {
self.variant(FLASHTIMW::_1CLK)
}
#[doc = "Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock."]
#[inline]
pub fn _2clk(self) -> &'a mut W {
self.variant(FLASHTIMW::_2CLK)
}
#[doc = "Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock."]
#[inline]
pub fn _3clk(self) -> &'a mut W {
self.variant(FLASHTIMW::_3CLK)
}
#[doc = "Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock."]
#[inline]
pub fn _4clk(self) -> &'a mut W {
self.variant(FLASHTIMW::_4CLK)
}
#[doc = "Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only."]
#[inline]
pub fn _5clk(self) -> &'a mut W {
self.variant(FLASHTIMW::_5CLK)
}
#[doc = "Flash accesses use 6 CPU clocks. This safe setting will work under any conditions."]
#[inline]
pub fn _6clk(self) -> &'a mut W {
self.variant(FLASHTIMW::_6CLK)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved."]
#[inline]
pub fn flashtim(&self) -> FLASHTIMR {
FLASHTIMR::_from({
const MASK: u8 = 0x0f;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x303a }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 12:15 - Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved."]
#[inline]
pub fn flashtim(&mut self) -> _FLASHTIMW {
_FLASHTIMW { w: self }
}
}
}
#[doc = "PLL0 Control Register"]
pub struct PLL0CON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL0 Control Register"]
pub mod pll0con {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLL0CON {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PLLE0R {
bits: bool,
}
impl PLLE0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PLLC0R {
bits: bool,
}
impl PLLC0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PLLE0W<'a> {
w: &'a mut W,
}
impl<'a> _PLLE0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PLLC0W<'a> {
w: &'a mut W,
}
impl<'a> _PLLC0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register."]
#[inline]
pub fn plle0(&self) -> PLLE0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLE0R { bits }
}
#[doc = "Bit 1 - PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register."]
#[inline]
pub fn pllc0(&self) -> PLLC0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLC0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register."]
#[inline]
pub fn plle0(&mut self) -> _PLLE0W {
_PLLE0W { w: self }
}
#[doc = "Bit 1 - PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register."]
#[inline]
pub fn pllc0(&mut self) -> _PLLC0W {
_PLLC0W { w: self }
}
}
}
#[doc = "PLL0 Configuration Register"]
pub struct PLL0CFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL0 Configuration Register"]
pub mod pll0cfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLL0CFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MSEL0R {
bits: u16,
}
impl MSEL0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct NSEL0R {
bits: u8,
}
impl NSEL0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MSEL0W<'a> {
w: &'a mut W,
}
impl<'a> _MSEL0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x7fff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _NSEL0W<'a> {
w: &'a mut W,
}
impl<'a> _NSEL0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:14 - PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware."]
#[inline]
pub fn msel0(&self) -> MSEL0R {
let bits = {
const MASK: u16 = 0x7fff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MSEL0R { bits }
}
#[doc = "Bits 16:23 - PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32."]
#[inline]
pub fn nsel0(&self) -> NSEL0R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
NSEL0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:14 - PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware."]
#[inline]
pub fn msel0(&mut self) -> _MSEL0W {
_MSEL0W { w: self }
}
#[doc = "Bits 16:23 - PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32."]
#[inline]
pub fn nsel0(&mut self) -> _NSEL0W {
_NSEL0W { w: self }
}
}
}
#[doc = "PLL0 Status Register"]
pub struct PLL0STAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL0 Status Register"]
pub mod pll0stat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::PLL0STAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct MSEL0R {
bits: u16,
}
impl MSEL0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct NSEL0R {
bits: u8,
}
impl NSEL0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PLLE0_STATR {
bits: bool,
}
impl PLLE0_STATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PLLC0_STATR {
bits: bool,
}
impl PLLC0_STATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PLOCK0R {
bits: bool,
}
impl PLOCK0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:14 - Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier."]
#[inline]
pub fn msel0(&self) -> MSEL0R {
let bits = {
const MASK: u16 = 0x7fff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MSEL0R { bits }
}
#[doc = "Bits 16:23 - Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider."]
#[inline]
pub fn nsel0(&self) -> NSEL0R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
NSEL0R { bits }
}
#[doc = "Bit 24 - Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered."]
#[inline]
pub fn plle0_stat(&self) -> PLLE0_STATR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLE0_STATR { bits }
}
#[doc = "Bit 25 - Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered."]
#[inline]
pub fn pllc0_stat(&self) -> PLLC0_STATR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLC0_STATR { bits }
}
#[doc = "Bit 26 - Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details."]
#[inline]
pub fn plock0(&self) -> PLOCK0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLOCK0R { bits }
}
}
}
#[doc = "PLL0 Feed Register"]
pub struct PLL0FEED {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL0 Feed Register"]
pub mod pll0feed {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLL0FEED {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _PLL0FEEDW<'a> {
w: &'a mut W,
}
impl<'a> _PLL0FEEDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect."]
#[inline]
pub fn pll0feed(&mut self) -> _PLL0FEEDW {
_PLL0FEEDW { w: self }
}
}
}
#[doc = "PLL1 Control Register"]
pub struct PLL1CON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL1 Control Register"]
pub mod pll1con {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLL1CON {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PLLE1R {
bits: bool,
}
impl PLLE1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PLLC1R {
bits: bool,
}
impl PLLC1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PLLE1W<'a> {
w: &'a mut W,
}
impl<'a> _PLLE1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PLLC1W<'a> {
w: &'a mut W,
}
impl<'a> _PLLC1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency."]
#[inline]
pub fn plle1(&self) -> PLLE1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLE1R { bits }
}
#[doc = "Bit 1 - PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register."]
#[inline]
pub fn pllc1(&self) -> PLLC1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLC1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency."]
#[inline]
pub fn plle1(&mut self) -> _PLLE1W {
_PLLE1W { w: self }
}
#[doc = "Bit 1 - PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register."]
#[inline]
pub fn pllc1(&mut self) -> _PLLC1W {
_PLLC1W { w: self }
}
}
}
#[doc = "PLL1 Configuration Register"]
pub struct PLL1CFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL1 Configuration Register"]
pub mod pll1cfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLL1CFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MSEL1R {
bits: u8,
}
impl MSEL1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PSEL1R {
bits: u8,
}
impl PSEL1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MSEL1W<'a> {
w: &'a mut W,
}
impl<'a> _MSEL1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PSEL1W<'a> {
w: &'a mut W,
}
impl<'a> _PSEL1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations."]
#[inline]
pub fn msel1(&self) -> MSEL1R {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MSEL1R { bits }
}
#[doc = "Bits 5:6 - PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations."]
#[inline]
pub fn psel1(&self) -> PSEL1R {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PSEL1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations."]
#[inline]
pub fn msel1(&mut self) -> _MSEL1W {
_MSEL1W { w: self }
}
#[doc = "Bits 5:6 - PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations."]
#[inline]
pub fn psel1(&mut self) -> _PSEL1W {
_PSEL1W { w: self }
}
}
}
#[doc = "PLL1 Status Register"]
pub struct PLL1STAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL1 Status Register"]
pub mod pll1stat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::PLL1STAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct MSEL1R {
bits: u8,
}
impl MSEL1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PSEL1R {
bits: u8,
}
impl PSEL1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PLLE1_STATR {
bits: bool,
}
impl PLLE1_STATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PLLC1_STATR {
bits: bool,
}
impl PLLC1_STATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PLOCK1R {
bits: bool,
}
impl PLOCK1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1."]
#[inline]
pub fn msel1(&self) -> MSEL1R {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MSEL1R { bits }
}
#[doc = "Bits 5:6 - Read-back for the PLL1 Divider value. This is the value currently used by PLL1."]
#[inline]
pub fn psel1(&self) -> PSEL1R {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PSEL1R { bits }
}
#[doc = "Bit 8 - Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated."]
#[inline]
pub fn plle1_stat(&self) -> PLLE1_STATR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLE1_STATR { bits }
}
#[doc = "Bit 9 - Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated."]
#[inline]
pub fn pllc1_stat(&self) -> PLLC1_STATR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLLC1_STATR { bits }
}
#[doc = "Bit 10 - Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency."]
#[inline]
pub fn plock1(&self) -> PLOCK1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PLOCK1R { bits }
}
}
}
#[doc = "PLL1 Feed Register"]
pub struct PLL1FEED {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PLL1 Feed Register"]
pub mod pll1feed {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PLL1FEED {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _PLL1FEEDW<'a> {
w: &'a mut W,
}
impl<'a> _PLL1FEEDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect."]
#[inline]
pub fn pll1feed(&mut self) -> _PLL1FEEDW {
_PLL1FEEDW { w: self }
}
}
}
#[doc = "Power Control Register"]
pub struct PCON {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Power Control Register"]
pub mod pcon {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PCON {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PM0R {
bits: bool,
}
impl PM0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PM1R {
bits: bool,
}
impl PM1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BODRPMR {
bits: bool,
}
impl BODRPMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BOGDR {
bits: bool,
}
impl BOGDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BORDR {
bits: bool,
}
impl BORDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SMFLAGR {
bits: bool,
}
impl SMFLAGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DSFLAGR {
bits: bool,
}
impl DSFLAGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PDFLAGR {
bits: bool,
}
impl PDFLAGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DPDFLAGR {
bits: bool,
}
impl DPDFLAGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PM0W<'a> {
w: &'a mut W,
}
impl<'a> _PM0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PM1W<'a> {
w: &'a mut W,
}
impl<'a> _PM1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BODRPMW<'a> {
w: &'a mut W,
}
impl<'a> _BODRPMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BOGDW<'a> {
w: &'a mut W,
}
impl<'a> _BOGDW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BORDW<'a> {
w: &'a mut W,
}
impl<'a> _BORDW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SMFLAGW<'a> {
w: &'a mut W,
}
impl<'a> _SMFLAGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DSFLAGW<'a> {
w: &'a mut W,
}
impl<'a> _DSFLAGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PDFLAGW<'a> {
w: &'a mut W,
}
impl<'a> _PDFLAGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DPDFLAGW<'a> {
w: &'a mut W,
}
impl<'a> _DPDFLAGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Power mode control bit 0. This bit controls entry to the Power-down mode."]
#[inline]
pub fn pm0(&self) -> PM0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PM0R { bits }
}
#[doc = "Bit 1 - Power mode control bit 1. This bit controls entry to the Deep Power-down mode."]
#[inline]
pub fn pm1(&self) -> PM1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PM1R { bits }
}
#[doc = "Bit 2 - Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection."]
#[inline]
pub fn bodrpm(&self) -> BODRPMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BODRPMR { bits }
}
#[doc = "Bit 3 - Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit."]
#[inline]
pub fn bogd(&self) -> BOGDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BOGDR { bits }
}
#[doc = "Bit 4 - Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled."]
#[inline]
pub fn bord(&self) -> BORDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BORDR { bits }
}
#[doc = "Bit 8 - Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn smflag(&self) -> SMFLAGR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SMFLAGR { bits }
}
#[doc = "Bit 9 - Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn dsflag(&self) -> DSFLAGR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DSFLAGR { bits }
}
#[doc = "Bit 10 - Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn pdflag(&self) -> PDFLAGR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PDFLAGR { bits }
}
#[doc = "Bit 11 - Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn dpdflag(&self) -> DPDFLAGR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DPDFLAGR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Power mode control bit 0. This bit controls entry to the Power-down mode."]
#[inline]
pub fn pm0(&mut self) -> _PM0W {
_PM0W { w: self }
}
#[doc = "Bit 1 - Power mode control bit 1. This bit controls entry to the Deep Power-down mode."]
#[inline]
pub fn pm1(&mut self) -> _PM1W {
_PM1W { w: self }
}
#[doc = "Bit 2 - Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection."]
#[inline]
pub fn bodrpm(&mut self) -> _BODRPMW {
_BODRPMW { w: self }
}
#[doc = "Bit 3 - Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit."]
#[inline]
pub fn bogd(&mut self) -> _BOGDW {
_BOGDW { w: self }
}
#[doc = "Bit 4 - Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled."]
#[inline]
pub fn bord(&mut self) -> _BORDW {
_BORDW { w: self }
}
#[doc = "Bit 8 - Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn smflag(&mut self) -> _SMFLAGW {
_SMFLAGW { w: self }
}
#[doc = "Bit 9 - Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn dsflag(&mut self) -> _DSFLAGW {
_DSFLAGW { w: self }
}
#[doc = "Bit 10 - Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn pdflag(&mut self) -> _PDFLAGW {
_PDFLAGW { w: self }
}
#[doc = "Bit 11 - Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit."]
#[inline]
pub fn dpdflag(&mut self) -> _DPDFLAGW {
_DPDFLAGW { w: self }
}
}
}
#[doc = "Power Control for Peripherals Register"]
pub struct PCONP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Power Control for Peripherals Register"]
pub mod pconp {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PCONP {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PCTIM0R {
bits: bool,
}
impl PCTIM0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCTIM1R {
bits: bool,
}
impl PCTIM1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCUART0R {
bits: bool,
}
impl PCUART0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCUART1R {
bits: bool,
}
impl PCUART1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCPWM1R {
bits: bool,
}
impl PCPWM1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCI2C0R {
bits: bool,
}
impl PCI2C0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCSPIR {
bits: bool,
}
impl PCSPIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCRTCR {
bits: bool,
}
impl PCRTCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCSSP1R {
bits: bool,
}
impl PCSSP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCADCR {
bits: bool,
}
impl PCADCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCCAN1R {
bits: bool,
}
impl PCCAN1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCCAN2R {
bits: bool,
}
impl PCCAN2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCGPIOR {
bits: bool,
}
impl PCGPIOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCRITR {
bits: bool,
}
impl PCRITR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCMCPWMR {
bits: bool,
}
impl PCMCPWMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCQEIR {
bits: bool,
}
impl PCQEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCI2C1R {
bits: bool,
}
impl PCI2C1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCSSP0R {
bits: bool,
}
impl PCSSP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCTIM2R {
bits: bool,
}
impl PCTIM2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCTIM3R {
bits: bool,
}
impl PCTIM3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCUART2R {
bits: bool,
}
impl PCUART2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCUART3R {
bits: bool,
}
impl PCUART3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCI2C2R {
bits: bool,
}
impl PCI2C2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCI2SR {
bits: bool,
}
impl PCI2SR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCGPDMAR {
bits: bool,
}
impl PCGPDMAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCENETR {
bits: bool,
}
impl PCENETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PCUSBR {
bits: bool,
}
impl PCUSBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PCTIM0W<'a> {
w: &'a mut W,
}
impl<'a> _PCTIM0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCTIM1W<'a> {
w: &'a mut W,
}
impl<'a> _PCTIM1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCUART0W<'a> {
w: &'a mut W,
}
impl<'a> _PCUART0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCUART1W<'a> {
w: &'a mut W,
}
impl<'a> _PCUART1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCPWM1W<'a> {
w: &'a mut W,
}
impl<'a> _PCPWM1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCI2C0W<'a> {
w: &'a mut W,
}
impl<'a> _PCI2C0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCSPIW<'a> {
w: &'a mut W,
}
impl<'a> _PCSPIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCRTCW<'a> {
w: &'a mut W,
}
impl<'a> _PCRTCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCSSP1W<'a> {
w: &'a mut W,
}
impl<'a> _PCSSP1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCADCW<'a> {
w: &'a mut W,
}
impl<'a> _PCADCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCCAN1W<'a> {
w: &'a mut W,
}
impl<'a> _PCCAN1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCCAN2W<'a> {
w: &'a mut W,
}
impl<'a> _PCCAN2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCGPIOW<'a> {
w: &'a mut W,
}
impl<'a> _PCGPIOW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCRITW<'a> {
w: &'a mut W,
}
impl<'a> _PCRITW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCMCPWMW<'a> {
w: &'a mut W,
}
impl<'a> _PCMCPWMW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCQEIW<'a> {
w: &'a mut W,
}
impl<'a> _PCQEIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCI2C1W<'a> {
w: &'a mut W,
}
impl<'a> _PCI2C1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCSSP0W<'a> {
w: &'a mut W,
}
impl<'a> _PCSSP0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCTIM2W<'a> {
w: &'a mut W,
}
impl<'a> _PCTIM2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCTIM3W<'a> {
w: &'a mut W,
}
impl<'a> _PCTIM3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCUART2W<'a> {
w: &'a mut W,
}
impl<'a> _PCUART2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCUART3W<'a> {
w: &'a mut W,
}
impl<'a> _PCUART3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCI2C2W<'a> {
w: &'a mut W,
}
impl<'a> _PCI2C2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCI2SW<'a> {
w: &'a mut W,
}
impl<'a> _PCI2SW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCGPDMAW<'a> {
w: &'a mut W,
}
impl<'a> _PCGPDMAW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCENETW<'a> {
w: &'a mut W,
}
impl<'a> _PCENETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PCUSBW<'a> {
w: &'a mut W,
}
impl<'a> _PCUSBW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Timer/Counter 0 power/clock control bit."]
#[inline]
pub fn pctim0(&self) -> PCTIM0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCTIM0R { bits }
}
#[doc = "Bit 2 - Timer/Counter 1 power/clock control bit."]
#[inline]
pub fn pctim1(&self) -> PCTIM1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCTIM1R { bits }
}
#[doc = "Bit 3 - UART0 power/clock control bit."]
#[inline]
pub fn pcuart0(&self) -> PCUART0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCUART0R { bits }
}
#[doc = "Bit 4 - UART1 power/clock control bit."]
#[inline]
pub fn pcuart1(&self) -> PCUART1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCUART1R { bits }
}
#[doc = "Bit 6 - PWM1 power/clock control bit."]
#[inline]
pub fn pcpwm1(&self) -> PCPWM1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCPWM1R { bits }
}
#[doc = "Bit 7 - The I2C0 interface power/clock control bit."]
#[inline]
pub fn pci2c0(&self) -> PCI2C0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCI2C0R { bits }
}
#[doc = "Bit 8 - The SPI interface power/clock control bit."]
#[inline]
pub fn pcspi(&self) -> PCSPIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCSPIR { bits }
}
#[doc = "Bit 9 - The RTC power/clock control bit."]
#[inline]
pub fn pcrtc(&self) -> PCRTCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCRTCR { bits }
}
#[doc = "Bit 10 - The SSP 1 interface power/clock control bit."]
#[inline]
pub fn pcssp1(&self) -> PCSSP1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCSSP1R { bits }
}
#[doc = "Bit 12 - A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN."]
#[inline]
pub fn pcadc(&self) -> PCADCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCADCR { bits }
}
#[doc = "Bit 13 - CAN Controller 1 power/clock control bit."]
#[inline]
pub fn pccan1(&self) -> PCCAN1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCCAN1R { bits }
}
#[doc = "Bit 14 - CAN Controller 2 power/clock control bit."]
#[inline]
pub fn pccan2(&self) -> PCCAN2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCCAN2R { bits }
}
#[doc = "Bit 15 - Power/clock control bit for IOCON, GPIO, and GPIO interrupts."]
#[inline]
pub fn pcgpio(&self) -> PCGPIOR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCGPIOR { bits }
}
#[doc = "Bit 16 - Repetitive Interrupt Timer power/clock control bit."]
#[inline]
pub fn pcrit(&self) -> PCRITR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCRITR { bits }
}
#[doc = "Bit 17 - Motor Control PWM"]
#[inline]
pub fn pcmcpwm(&self) -> PCMCPWMR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCMCPWMR { bits }
}
#[doc = "Bit 18 - Quadrature Encoder Interface power/clock control bit."]
#[inline]
pub fn pcqei(&self) -> PCQEIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCQEIR { bits }
}
#[doc = "Bit 19 - The I2C1 interface power/clock control bit."]
#[inline]
pub fn pci2c1(&self) -> PCI2C1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCI2C1R { bits }
}
#[doc = "Bit 21 - The SSP0 interface power/clock control bit."]
#[inline]
pub fn pcssp0(&self) -> PCSSP0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCSSP0R { bits }
}
#[doc = "Bit 22 - Timer 2 power/clock control bit."]
#[inline]
pub fn pctim2(&self) -> PCTIM2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCTIM2R { bits }
}
#[doc = "Bit 23 - Timer 3 power/clock control bit."]
#[inline]
pub fn pctim3(&self) -> PCTIM3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCTIM3R { bits }
}
#[doc = "Bit 24 - UART 2 power/clock control bit."]
#[inline]
pub fn pcuart2(&self) -> PCUART2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCUART2R { bits }
}
#[doc = "Bit 25 - UART 3 power/clock control bit."]
#[inline]
pub fn pcuart3(&self) -> PCUART3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCUART3R { bits }
}
#[doc = "Bit 26 - I2C interface 2 power/clock control bit."]
#[inline]
pub fn pci2c2(&self) -> PCI2C2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCI2C2R { bits }
}
#[doc = "Bit 27 - I2S interface power/clock control bit."]
#[inline]
pub fn pci2s(&self) -> PCI2SR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCI2SR { bits }
}
#[doc = "Bit 29 - GPDMA function power/clock control bit."]
#[inline]
pub fn pcgpdma(&self) -> PCGPDMAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCGPDMAR { bits }
}
#[doc = "Bit 30 - Ethernet block power/clock control bit."]
#[inline]
pub fn pcenet(&self) -> PCENETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCENETR { bits }
}
#[doc = "Bit 31 - USB interface power/clock control bit."]
#[inline]
pub fn pcusb(&self) -> PCUSBR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PCUSBR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x03be }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 1 - Timer/Counter 0 power/clock control bit."]
#[inline]
pub fn pctim0(&mut self) -> _PCTIM0W {
_PCTIM0W { w: self }
}
#[doc = "Bit 2 - Timer/Counter 1 power/clock control bit."]
#[inline]
pub fn pctim1(&mut self) -> _PCTIM1W {
_PCTIM1W { w: self }
}
#[doc = "Bit 3 - UART0 power/clock control bit."]
#[inline]
pub fn pcuart0(&mut self) -> _PCUART0W {
_PCUART0W { w: self }
}
#[doc = "Bit 4 - UART1 power/clock control bit."]
#[inline]
pub fn pcuart1(&mut self) -> _PCUART1W {
_PCUART1W { w: self }
}
#[doc = "Bit 6 - PWM1 power/clock control bit."]
#[inline]
pub fn pcpwm1(&mut self) -> _PCPWM1W {
_PCPWM1W { w: self }
}
#[doc = "Bit 7 - The I2C0 interface power/clock control bit."]
#[inline]
pub fn pci2c0(&mut self) -> _PCI2C0W {
_PCI2C0W { w: self }
}
#[doc = "Bit 8 - The SPI interface power/clock control bit."]
#[inline]
pub fn pcspi(&mut self) -> _PCSPIW {
_PCSPIW { w: self }
}
#[doc = "Bit 9 - The RTC power/clock control bit."]
#[inline]
pub fn pcrtc(&mut self) -> _PCRTCW {
_PCRTCW { w: self }
}
#[doc = "Bit 10 - The SSP 1 interface power/clock control bit."]
#[inline]
pub fn pcssp1(&mut self) -> _PCSSP1W {
_PCSSP1W { w: self }
}
#[doc = "Bit 12 - A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN."]
#[inline]
pub fn pcadc(&mut self) -> _PCADCW {
_PCADCW { w: self }
}
#[doc = "Bit 13 - CAN Controller 1 power/clock control bit."]
#[inline]
pub fn pccan1(&mut self) -> _PCCAN1W {
_PCCAN1W { w: self }
}
#[doc = "Bit 14 - CAN Controller 2 power/clock control bit."]
#[inline]
pub fn pccan2(&mut self) -> _PCCAN2W {
_PCCAN2W { w: self }
}
#[doc = "Bit 15 - Power/clock control bit for IOCON, GPIO, and GPIO interrupts."]
#[inline]
pub fn pcgpio(&mut self) -> _PCGPIOW {
_PCGPIOW { w: self }
}
#[doc = "Bit 16 - Repetitive Interrupt Timer power/clock control bit."]
#[inline]
pub fn pcrit(&mut self) -> _PCRITW {
_PCRITW { w: self }
}
#[doc = "Bit 17 - Motor Control PWM"]
#[inline]
pub fn pcmcpwm(&mut self) -> _PCMCPWMW {
_PCMCPWMW { w: self }
}
#[doc = "Bit 18 - Quadrature Encoder Interface power/clock control bit."]
#[inline]
pub fn pcqei(&mut self) -> _PCQEIW {
_PCQEIW { w: self }
}
#[doc = "Bit 19 - The I2C1 interface power/clock control bit."]
#[inline]
pub fn pci2c1(&mut self) -> _PCI2C1W {
_PCI2C1W { w: self }
}
#[doc = "Bit 21 - The SSP0 interface power/clock control bit."]
#[inline]
pub fn pcssp0(&mut self) -> _PCSSP0W {
_PCSSP0W { w: self }
}
#[doc = "Bit 22 - Timer 2 power/clock control bit."]
#[inline]
pub fn pctim2(&mut self) -> _PCTIM2W {
_PCTIM2W { w: self }
}
#[doc = "Bit 23 - Timer 3 power/clock control bit."]
#[inline]
pub fn pctim3(&mut self) -> _PCTIM3W {
_PCTIM3W { w: self }
}
#[doc = "Bit 24 - UART 2 power/clock control bit."]
#[inline]
pub fn pcuart2(&mut self) -> _PCUART2W {
_PCUART2W { w: self }
}
#[doc = "Bit 25 - UART 3 power/clock control bit."]
#[inline]
pub fn pcuart3(&mut self) -> _PCUART3W {
_PCUART3W { w: self }
}
#[doc = "Bit 26 - I2C interface 2 power/clock control bit."]
#[inline]
pub fn pci2c2(&mut self) -> _PCI2C2W {
_PCI2C2W { w: self }
}
#[doc = "Bit 27 - I2S interface power/clock control bit."]
#[inline]
pub fn pci2s(&mut self) -> _PCI2SW {
_PCI2SW { w: self }
}
#[doc = "Bit 29 - GPDMA function power/clock control bit."]
#[inline]
pub fn pcgpdma(&mut self) -> _PCGPDMAW {
_PCGPDMAW { w: self }
}
#[doc = "Bit 30 - Ethernet block power/clock control bit."]
#[inline]
pub fn pcenet(&mut self) -> _PCENETW {
_PCENETW { w: self }
}
#[doc = "Bit 31 - USB interface power/clock control bit."]
#[inline]
pub fn pcusb(&mut self) -> _PCUSBW {
_PCUSBW { w: self }
}
}
}
#[doc = "CPU Clock Configuration Register"]
pub struct CCLKCFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "CPU Clock Configuration Register"]
pub mod cclkcfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCLKCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CCLKSELR {
bits: u8,
}
impl CCLKSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CCLKSELW<'a> {
w: &'a mut W,
}
impl<'a> _CCLKSELW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock."]
#[inline]
pub fn cclksel(&self) -> CCLKSELR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CCLKSELR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock."]
#[inline]
pub fn cclksel(&mut self) -> _CCLKSELW {
_CCLKSELW { w: self }
}
}
}
#[doc = "USB Clock Configuration Register"]
pub struct USBCLKCFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Clock Configuration Register"]
pub mod usbclkcfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::USBCLKCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct USBSELR {
bits: u8,
}
impl USBSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _USBSELW<'a> {
w: &'a mut W,
}
impl<'a> _USBSELW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz."]
#[inline]
pub fn usbsel(&self) -> USBSELR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
USBSELR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz."]
#[inline]
pub fn usbsel(&mut self) -> _USBSELW {
_USBSELW { w: self }
}
}
}
#[doc = "Clock Source Select Register"]
pub struct CLKSRCSEL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clock Source Select Register"]
pub mod clksrcsel {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLKSRCSEL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CLKSRC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKSRCR {
#[doc = "Selects the Internal RC oscillator as the PLL0 clock source (default)."]
SELECTS_THE_INTERNAL,
#[doc = "Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s."]
SELECTS_THE_MAIN_OSC,
#[doc = "Selects the RTC oscillator as the PLL0 clock source."]
SELECTS_THE_RTC_OSCI,
}
impl CLKSRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CLKSRCR::SELECTS_THE_INTERNAL => 0,
CLKSRCR::SELECTS_THE_MAIN_OSC => 0x01,
CLKSRCR::SELECTS_THE_RTC_OSCI => 0x02,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CLKSRCR {
match value {
0 => CLKSRCR::SELECTS_THE_INTERNAL,
1 => CLKSRCR::SELECTS_THE_MAIN_OSC,
2 => CLKSRCR::SELECTS_THE_RTC_OSCI,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `SELECTS_THE_INTERNAL`"]
#[inline]
pub fn is_selects_the_internal(&self) -> bool {
*self == CLKSRCR::SELECTS_THE_INTERNAL
}
#[doc = "Checks if the value of the field is `SELECTS_THE_MAIN_OSC`"]
#[inline]
pub fn is_selects_the_main_osc(&self) -> bool {
*self == CLKSRCR::SELECTS_THE_MAIN_OSC
}
#[doc = "Checks if the value of the field is `SELECTS_THE_RTC_OSCI`"]
#[inline]
pub fn is_selects_the_rtc_osci(&self) -> bool {
*self == CLKSRCR::SELECTS_THE_RTC_OSCI
}
}
#[doc = "Values that can be written to the field `CLKSRC`"]
pub enum CLKSRCW {
#[doc = "Selects the Internal RC oscillator as the PLL0 clock source (default)."]
SELECTS_THE_INTERNAL,
#[doc = "Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s."]
SELECTS_THE_MAIN_OSC,
#[doc = "Selects the RTC oscillator as the PLL0 clock source."]
SELECTS_THE_RTC_OSCI,
}
impl CLKSRCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CLKSRCW::SELECTS_THE_INTERNAL => 0,
CLKSRCW::SELECTS_THE_MAIN_OSC => 1,
CLKSRCW::SELECTS_THE_RTC_OSCI => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _CLKSRCW<'a> {
w: &'a mut W,
}
impl<'a> _CLKSRCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLKSRCW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Selects the Internal RC oscillator as the PLL0 clock source (default)."]
#[inline]
pub fn selects_the_internal(self) -> &'a mut W {
self.variant(CLKSRCW::SELECTS_THE_INTERNAL)
}
#[doc = "Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s."]
#[inline]
pub fn selects_the_main_osc(self) -> &'a mut W {
self.variant(CLKSRCW::SELECTS_THE_MAIN_OSC)
}
#[doc = "Selects the RTC oscillator as the PLL0 clock source."]
#[inline]
pub fn selects_the_rtc_osci(self) -> &'a mut W {
self.variant(CLKSRCW::SELECTS_THE_RTC_OSCI)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device."]
#[inline]
pub fn clksrc(&self) -> CLKSRCR {
CLKSRCR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device."]
#[inline]
pub fn clksrc(&mut self) -> _CLKSRCW {
_CLKSRCW { w: self }
}
}
}
#[doc = "Allows clearing the current CAN channel sleep state as well as reading that state."]
pub struct CANSLEEPCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Allows clearing the current CAN channel sleep state as well as reading that state."]
pub mod cansleepclr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CANSLEEPCLR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CAN1SLEEPR {
bits: bool,
}
impl CAN1SLEEPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAN2SLEEPR {
bits: bool,
}
impl CAN2SLEEPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _CAN1SLEEPW<'a> {
w: &'a mut W,
}
impl<'a> _CAN1SLEEPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAN2SLEEPW<'a> {
w: &'a mut W,
}
impl<'a> _CAN2SLEEPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1."]
#[inline]
pub fn can1sleep(&self) -> CAN1SLEEPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAN1SLEEPR { bits }
}
#[doc = "Bit 2 - Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2."]
#[inline]
pub fn can2sleep(&self) -> CAN2SLEEPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAN2SLEEPR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 1 - Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1."]
#[inline]
pub fn can1sleep(&mut self) -> _CAN1SLEEPW {
_CAN1SLEEPW { w: self }
}
#[doc = "Bit 2 - Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2."]
#[inline]
pub fn can2sleep(&mut self) -> _CAN2SLEEPW {
_CAN2SLEEPW { w: self }
}
}
}
#[doc = "Allows reading the wake-up state of the CAN channels."]
pub struct CANWAKEFLAGS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Allows reading the wake-up state of the CAN channels."]
pub mod canwakeflags {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CANWAKEFLAGS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CAN1WAKER {
bits: bool,
}
impl CAN1WAKER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CAN2WAKER {
bits: bool,
}
impl CAN2WAKER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _CAN1WAKEW<'a> {
w: &'a mut W,
}
impl<'a> _CAN1WAKEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CAN2WAKEW<'a> {
w: &'a mut W,
}
impl<'a> _CAN2WAKEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit."]
#[inline]
pub fn can1wake(&self) -> CAN1WAKER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAN1WAKER { bits }
}
#[doc = "Bit 2 - Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit."]
#[inline]
pub fn can2wake(&self) -> CAN2WAKER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CAN2WAKER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 1 - Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit."]
#[inline]
pub fn can1wake(&mut self) -> _CAN1WAKEW {
_CAN1WAKEW { w: self }
}
#[doc = "Bit 2 - Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit."]
#[inline]
pub fn can2wake(&mut self) -> _CAN2WAKEW {
_CAN2WAKEW { w: self }
}
}
}
#[doc = "External Interrupt Flag Register"]
pub struct EXTINT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "External Interrupt Flag Register"]
pub mod extint {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EXTINT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EINT0R {
bits: bool,
}
impl EINT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EINT1R {
bits: bool,
}
impl EINT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EINT2R {
bits: bool,
}
impl EINT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EINT3R {
bits: bool,
}
impl EINT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _EINT0W<'a> {
w: &'a mut W,
}
impl<'a> _EINT0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EINT1W<'a> {
w: &'a mut W,
}
impl<'a> _EINT1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EINT2W<'a> {
w: &'a mut W,
}
impl<'a> _EINT2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EINT3W<'a> {
w: &'a mut W,
}
impl<'a> _EINT3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint0(&self) -> EINT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EINT0R { bits }
}
#[doc = "Bit 1 - In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint1(&self) -> EINT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EINT1R { bits }
}
#[doc = "Bit 2 - In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint2(&self) -> EINT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EINT2R { bits }
}
#[doc = "Bit 3 - In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint3(&self) -> EINT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EINT3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint0(&mut self) -> _EINT0W {
_EINT0W { w: self }
}
#[doc = "Bit 1 - In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint1(&mut self) -> _EINT1W {
_EINT1W { w: self }
}
#[doc = "Bit 2 - In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint2(&mut self) -> _EINT2W {
_EINT2W { w: self }
}
#[doc = "Bit 3 - In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state."]
#[inline]
pub fn eint3(&mut self) -> _EINT3W {
_EINT3W { w: self }
}
}
}
#[doc = "External Interrupt Mode register"]
pub struct EXTMODE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "External Interrupt Mode register"]
pub mod extmode {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EXTMODE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `EXTMODE0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTMODE0R {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT0."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT0 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTMODE0R::LEVEL_SENSITIVE => false,
EXTMODE0R::EDGE_SENSITIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTMODE0R {
match value {
false => EXTMODE0R::LEVEL_SENSITIVE,
true => EXTMODE0R::EDGE_SENSITIVE,
}
}
#[doc = "Checks if the value of the field is `LEVEL_SENSITIVE`"]
#[inline]
pub fn is_level_sensitive(&self) -> bool {
*self == EXTMODE0R::LEVEL_SENSITIVE
}
#[doc = "Checks if the value of the field is `EDGE_SENSITIVE`"]
#[inline]
pub fn is_edge_sensitive(&self) -> bool {
*self == EXTMODE0R::EDGE_SENSITIVE
}
}
#[doc = "Possible values of the field `EXTMODE1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTMODE1R {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT1."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT1 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTMODE1R::LEVEL_SENSITIVE => false,
EXTMODE1R::EDGE_SENSITIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTMODE1R {
match value {
false => EXTMODE1R::LEVEL_SENSITIVE,
true => EXTMODE1R::EDGE_SENSITIVE,
}
}
#[doc = "Checks if the value of the field is `LEVEL_SENSITIVE`"]
#[inline]
pub fn is_level_sensitive(&self) -> bool {
*self == EXTMODE1R::LEVEL_SENSITIVE
}
#[doc = "Checks if the value of the field is `EDGE_SENSITIVE`"]
#[inline]
pub fn is_edge_sensitive(&self) -> bool {
*self == EXTMODE1R::EDGE_SENSITIVE
}
}
#[doc = "Possible values of the field `EXTMODE2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTMODE2R {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT2."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT2 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTMODE2R::LEVEL_SENSITIVE => false,
EXTMODE2R::EDGE_SENSITIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTMODE2R {
match value {
false => EXTMODE2R::LEVEL_SENSITIVE,
true => EXTMODE2R::EDGE_SENSITIVE,
}
}
#[doc = "Checks if the value of the field is `LEVEL_SENSITIVE`"]
#[inline]
pub fn is_level_sensitive(&self) -> bool {
*self == EXTMODE2R::LEVEL_SENSITIVE
}
#[doc = "Checks if the value of the field is `EDGE_SENSITIVE`"]
#[inline]
pub fn is_edge_sensitive(&self) -> bool {
*self == EXTMODE2R::EDGE_SENSITIVE
}
}
#[doc = "Possible values of the field `EXTMODE3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTMODE3R {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT3."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT3 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTMODE3R::LEVEL_SENSITIVE => false,
EXTMODE3R::EDGE_SENSITIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTMODE3R {
match value {
false => EXTMODE3R::LEVEL_SENSITIVE,
true => EXTMODE3R::EDGE_SENSITIVE,
}
}
#[doc = "Checks if the value of the field is `LEVEL_SENSITIVE`"]
#[inline]
pub fn is_level_sensitive(&self) -> bool {
*self == EXTMODE3R::LEVEL_SENSITIVE
}
#[doc = "Checks if the value of the field is `EDGE_SENSITIVE`"]
#[inline]
pub fn is_edge_sensitive(&self) -> bool {
*self == EXTMODE3R::EDGE_SENSITIVE
}
}
#[doc = "Values that can be written to the field `EXTMODE0`"]
pub enum EXTMODE0W {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT0."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT0 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTMODE0W::LEVEL_SENSITIVE => false,
EXTMODE0W::EDGE_SENSITIVE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTMODE0W<'a> {
w: &'a mut W,
}
impl<'a> _EXTMODE0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTMODE0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT0."]
#[inline]
pub fn level_sensitive(self) -> &'a mut W {
self.variant(EXTMODE0W::LEVEL_SENSITIVE)
}
#[doc = "Edge-sensitive. EINT0 is edge sensitive."]
#[inline]
pub fn edge_sensitive(self) -> &'a mut W {
self.variant(EXTMODE0W::EDGE_SENSITIVE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTMODE1`"]
pub enum EXTMODE1W {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT1."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT1 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTMODE1W::LEVEL_SENSITIVE => false,
EXTMODE1W::EDGE_SENSITIVE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTMODE1W<'a> {
w: &'a mut W,
}
impl<'a> _EXTMODE1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTMODE1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT1."]
#[inline]
pub fn level_sensitive(self) -> &'a mut W {
self.variant(EXTMODE1W::LEVEL_SENSITIVE)
}
#[doc = "Edge-sensitive. EINT1 is edge sensitive."]
#[inline]
pub fn edge_sensitive(self) -> &'a mut W {
self.variant(EXTMODE1W::EDGE_SENSITIVE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTMODE2`"]
pub enum EXTMODE2W {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT2."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT2 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTMODE2W::LEVEL_SENSITIVE => false,
EXTMODE2W::EDGE_SENSITIVE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTMODE2W<'a> {
w: &'a mut W,
}
impl<'a> _EXTMODE2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTMODE2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT2."]
#[inline]
pub fn level_sensitive(self) -> &'a mut W {
self.variant(EXTMODE2W::LEVEL_SENSITIVE)
}
#[doc = "Edge-sensitive. EINT2 is edge sensitive."]
#[inline]
pub fn edge_sensitive(self) -> &'a mut W {
self.variant(EXTMODE2W::EDGE_SENSITIVE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTMODE3`"]
pub enum EXTMODE3W {
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT3."]
LEVEL_SENSITIVE,
#[doc = "Edge-sensitive. EINT3 is edge sensitive."]
EDGE_SENSITIVE,
}
impl EXTMODE3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTMODE3W::LEVEL_SENSITIVE => false,
EXTMODE3W::EDGE_SENSITIVE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTMODE3W<'a> {
w: &'a mut W,
}
impl<'a> _EXTMODE3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTMODE3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Level-sensitive. Level-sensitivity is selected for EINT3."]
#[inline]
pub fn level_sensitive(self) -> &'a mut W {
self.variant(EXTMODE3W::LEVEL_SENSITIVE)
}
#[doc = "Edge-sensitive. EINT3 is edge sensitive."]
#[inline]
pub fn edge_sensitive(self) -> &'a mut W {
self.variant(EXTMODE3W::EDGE_SENSITIVE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - External interrupt 0 EINT0 mode."]
#[inline]
pub fn extmode0(&self) -> EXTMODE0R {
EXTMODE0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - External interrupt 1 EINT1 mode."]
#[inline]
pub fn extmode1(&self) -> EXTMODE1R {
EXTMODE1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - External interrupt 2 EINT2 mode."]
#[inline]
pub fn extmode2(&self) -> EXTMODE2R {
EXTMODE2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - External interrupt 3 EINT3 mode."]
#[inline]
pub fn extmode3(&self) -> EXTMODE3R {
EXTMODE3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - External interrupt 0 EINT0 mode."]
#[inline]
pub fn extmode0(&mut self) -> _EXTMODE0W {
_EXTMODE0W { w: self }
}
#[doc = "Bit 1 - External interrupt 1 EINT1 mode."]
#[inline]
pub fn extmode1(&mut self) -> _EXTMODE1W {
_EXTMODE1W { w: self }
}
#[doc = "Bit 2 - External interrupt 2 EINT2 mode."]
#[inline]
pub fn extmode2(&mut self) -> _EXTMODE2W {
_EXTMODE2W { w: self }
}
#[doc = "Bit 3 - External interrupt 3 EINT3 mode."]
#[inline]
pub fn extmode3(&mut self) -> _EXTMODE3W {
_EXTMODE3W { w: self }
}
}
}
#[doc = "External Interrupt Polarity Register"]
pub struct EXTPOLAR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "External Interrupt Polarity Register"]
pub mod extpolar {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EXTPOLAR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `EXTPOLAR0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTPOLAR0R {
#[doc = "Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)."]
RISING_EDGE,
}
impl EXTPOLAR0R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTPOLAR0R::FALLING_EDGE => false,
EXTPOLAR0R::RISING_EDGE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTPOLAR0R {
match value {
false => EXTPOLAR0R::FALLING_EDGE,
true => EXTPOLAR0R::RISING_EDGE,
}
}
#[doc = "Checks if the value of the field is `FALLING_EDGE`"]
#[inline]
pub fn is_falling_edge(&self) -> bool {
*self == EXTPOLAR0R::FALLING_EDGE
}
#[doc = "Checks if the value of the field is `RISING_EDGE`"]
#[inline]
pub fn is_rising_edge(&self) -> bool {
*self == EXTPOLAR0R::RISING_EDGE
}
}
#[doc = "Possible values of the field `EXTPOLAR1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTPOLAR1R {
#[doc = "Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)."]
RISING_EDGE,
}
impl EXTPOLAR1R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTPOLAR1R::FALLING_EDGE => false,
EXTPOLAR1R::RISING_EDGE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTPOLAR1R {
match value {
false => EXTPOLAR1R::FALLING_EDGE,
true => EXTPOLAR1R::RISING_EDGE,
}
}
#[doc = "Checks if the value of the field is `FALLING_EDGE`"]
#[inline]
pub fn is_falling_edge(&self) -> bool {
*self == EXTPOLAR1R::FALLING_EDGE
}
#[doc = "Checks if the value of the field is `RISING_EDGE`"]
#[inline]
pub fn is_rising_edge(&self) -> bool {
*self == EXTPOLAR1R::RISING_EDGE
}
}
#[doc = "Possible values of the field `EXTPOLAR2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTPOLAR2R {
#[doc = "Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)."]
RISING_EDGE,
}
impl EXTPOLAR2R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTPOLAR2R::FALLING_EDGE => false,
EXTPOLAR2R::RISING_EDGE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTPOLAR2R {
match value {
false => EXTPOLAR2R::FALLING_EDGE,
true => EXTPOLAR2R::RISING_EDGE,
}
}
#[doc = "Checks if the value of the field is `FALLING_EDGE`"]
#[inline]
pub fn is_falling_edge(&self) -> bool {
*self == EXTPOLAR2R::FALLING_EDGE
}
#[doc = "Checks if the value of the field is `RISING_EDGE`"]
#[inline]
pub fn is_rising_edge(&self) -> bool {
*self == EXTPOLAR2R::RISING_EDGE
}
}
#[doc = "Possible values of the field `EXTPOLAR3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTPOLAR3R {
#[doc = "Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)."]
RISING_EDGE,
}
impl EXTPOLAR3R {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EXTPOLAR3R::FALLING_EDGE => false,
EXTPOLAR3R::RISING_EDGE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EXTPOLAR3R {
match value {
false => EXTPOLAR3R::FALLING_EDGE,
true => EXTPOLAR3R::RISING_EDGE,
}
}
#[doc = "Checks if the value of the field is `FALLING_EDGE`"]
#[inline]
pub fn is_falling_edge(&self) -> bool {
*self == EXTPOLAR3R::FALLING_EDGE
}
#[doc = "Checks if the value of the field is `RISING_EDGE`"]
#[inline]
pub fn is_rising_edge(&self) -> bool {
*self == EXTPOLAR3R::RISING_EDGE
}
}
#[doc = "Values that can be written to the field `EXTPOLAR0`"]
pub enum EXTPOLAR0W {
#[doc = "Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)."]
RISING_EDGE,
}
impl EXTPOLAR0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTPOLAR0W::FALLING_EDGE => false,
EXTPOLAR0W::RISING_EDGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTPOLAR0W<'a> {
w: &'a mut W,
}
impl<'a> _EXTPOLAR0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTPOLAR0W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)."]
#[inline]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTPOLAR0W::FALLING_EDGE)
}
#[doc = "Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)."]
#[inline]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTPOLAR0W::RISING_EDGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTPOLAR1`"]
pub enum EXTPOLAR1W {
#[doc = "Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)."]
RISING_EDGE,
}
impl EXTPOLAR1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTPOLAR1W::FALLING_EDGE => false,
EXTPOLAR1W::RISING_EDGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTPOLAR1W<'a> {
w: &'a mut W,
}
impl<'a> _EXTPOLAR1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTPOLAR1W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)."]
#[inline]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTPOLAR1W::FALLING_EDGE)
}
#[doc = "Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)."]
#[inline]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTPOLAR1W::RISING_EDGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTPOLAR2`"]
pub enum EXTPOLAR2W {
#[doc = "Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)."]
RISING_EDGE,
}
impl EXTPOLAR2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTPOLAR2W::FALLING_EDGE => false,
EXTPOLAR2W::RISING_EDGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTPOLAR2W<'a> {
w: &'a mut W,
}
impl<'a> _EXTPOLAR2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTPOLAR2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)."]
#[inline]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTPOLAR2W::FALLING_EDGE)
}
#[doc = "Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)."]
#[inline]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTPOLAR2W::RISING_EDGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTPOLAR3`"]
pub enum EXTPOLAR3W {
#[doc = "Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)."]
FALLING_EDGE,
#[doc = "Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)."]
RISING_EDGE,
}
impl EXTPOLAR3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EXTPOLAR3W::FALLING_EDGE => false,
EXTPOLAR3W::RISING_EDGE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTPOLAR3W<'a> {
w: &'a mut W,
}
impl<'a> _EXTPOLAR3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTPOLAR3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)."]
#[inline]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTPOLAR3W::FALLING_EDGE)
}
#[doc = "Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)."]
#[inline]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTPOLAR3W::RISING_EDGE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - External interrupt 0 EINT0 polarity."]
#[inline]
pub fn extpolar0(&self) -> EXTPOLAR0R {
EXTPOLAR0R::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - External interrupt 1 EINT1 polarity."]
#[inline]
pub fn extpolar1(&self) -> EXTPOLAR1R {
EXTPOLAR1R::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - External interrupt 2 EINT2 polarity."]
#[inline]
pub fn extpolar2(&self) -> EXTPOLAR2R {
EXTPOLAR2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - External interrupt 3 EINT3 polarity."]
#[inline]
pub fn extpolar3(&self) -> EXTPOLAR3R {
EXTPOLAR3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - External interrupt 0 EINT0 polarity."]
#[inline]
pub fn extpolar0(&mut self) -> _EXTPOLAR0W {
_EXTPOLAR0W { w: self }
}
#[doc = "Bit 1 - External interrupt 1 EINT1 polarity."]
#[inline]
pub fn extpolar1(&mut self) -> _EXTPOLAR1W {
_EXTPOLAR1W { w: self }
}
#[doc = "Bit 2 - External interrupt 2 EINT2 polarity."]
#[inline]
pub fn extpolar2(&mut self) -> _EXTPOLAR2W {
_EXTPOLAR2W { w: self }
}
#[doc = "Bit 3 - External interrupt 3 EINT3 polarity."]
#[inline]
pub fn extpolar3(&mut self) -> _EXTPOLAR3W {
_EXTPOLAR3W { w: self }
}
}
}
#[doc = "Reset Source Identification Register"]
pub struct RSID {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Reset Source Identification Register"]
pub mod rsid {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RSID {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PORR {
bits: bool,
}
impl PORR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EXTRR {
bits: bool,
}
impl EXTRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WDTRR {
bits: bool,
}
impl WDTRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BODRR {
bits: bool,
}
impl BODRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PORW<'a> {
w: &'a mut W,
}
impl<'a> _PORW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EXTRW<'a> {
w: &'a mut W,
}
impl<'a> _EXTRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WDTRW<'a> {
w: &'a mut W,
}
impl<'a> _WDTRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BODRW<'a> {
w: &'a mut W,
}
impl<'a> _BODRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset."]
#[inline]
pub fn por(&self) -> PORR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PORR { bits }
}
#[doc = "Bit 1 - Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR."]
#[inline]
pub fn extr(&self) -> EXTRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EXTRR { bits }
}
#[doc = "Bit 2 - This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR."]
#[inline]
pub fn wdtr(&self) -> WDTRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WDTRR { bits }
}
#[doc = "Bit 3 - This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not."]
#[inline]
pub fn bodr(&self) -> BODRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BODRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset."]
#[inline]
pub fn por(&mut self) -> _PORW {
_PORW { w: self }
}
#[doc = "Bit 1 - Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR."]
#[inline]
pub fn extr(&mut self) -> _EXTRW {
_EXTRW { w: self }
}
#[doc = "Bit 2 - This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR."]
#[inline]
pub fn wdtr(&mut self) -> _WDTRW {
_WDTRW { w: self }
}
#[doc = "Bit 3 - This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not."]
#[inline]
pub fn bodr(&mut self) -> _BODRW {
_BODRW { w: self }
}
}
}
#[doc = "System control and status"]
pub struct SCS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "System control and status"]
pub mod scs {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `OSCRANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OSCRANGER {
#[doc = "Low. The frequency range of the main oscillator is 1 MHz to 20 MHz."]
LOW,
#[doc = "High. The frequency range of the main oscillator is 15 MHz to 25 MHz."]
HIGH,
}
impl OSCRANGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OSCRANGER::LOW => false,
OSCRANGER::HIGH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OSCRANGER {
match value {
false => OSCRANGER::LOW,
true => OSCRANGER::HIGH,
}
}
#[doc = "Checks if the value of the field is `LOW`"]
#[inline]
pub fn is_low(&self) -> bool {
*self == OSCRANGER::LOW
}
#[doc = "Checks if the value of the field is `HIGH`"]
#[inline]
pub fn is_high(&self) -> bool {
*self == OSCRANGER::HIGH
}
}
#[doc = "Possible values of the field `OSCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OSCENR {
#[doc = "Disabled. The main oscillator is disabled."]
DISABLED,
#[doc = "Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins."]
ENABLED,
}
impl OSCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OSCENR::DISABLED => false,
OSCENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OSCENR {
match value {
false => OSCENR::DISABLED,
true => OSCENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == OSCENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == OSCENR::ENABLED
}
}
#[doc = "Possible values of the field `OSCSTAT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OSCSTATR {
#[doc = "Not ready. The main oscillator is not ready to be used as a clock source."]
NOT_READY,
#[doc = "Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit."]
READY,
}
impl OSCSTATR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OSCSTATR::NOT_READY => false,
OSCSTATR::READY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OSCSTATR {
match value {
false => OSCSTATR::NOT_READY,
true => OSCSTATR::READY,
}
}
#[doc = "Checks if the value of the field is `NOT_READY`"]
#[inline]
pub fn is_not_ready(&self) -> bool {
*self == OSCSTATR::NOT_READY
}
#[doc = "Checks if the value of the field is `READY`"]
#[inline]
pub fn is_ready(&self) -> bool {
*self == OSCSTATR::READY
}
}
#[doc = "Values that can be written to the field `OSCRANGE`"]
pub enum OSCRANGEW {
#[doc = "Low. The frequency range of the main oscillator is 1 MHz to 20 MHz."]
LOW,
#[doc = "High. The frequency range of the main oscillator is 15 MHz to 25 MHz."]
HIGH,
}
impl OSCRANGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OSCRANGEW::LOW => false,
OSCRANGEW::HIGH => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OSCRANGEW<'a> {
w: &'a mut W,
}
impl<'a> _OSCRANGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OSCRANGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Low. The frequency range of the main oscillator is 1 MHz to 20 MHz."]
#[inline]
pub fn low(self) -> &'a mut W {
self.variant(OSCRANGEW::LOW)
}
#[doc = "High. The frequency range of the main oscillator is 15 MHz to 25 MHz."]
#[inline]
pub fn high(self) -> &'a mut W {
self.variant(OSCRANGEW::HIGH)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `OSCEN`"]
pub enum OSCENW {
#[doc = "Disabled. The main oscillator is disabled."]
DISABLED,
#[doc = "Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins."]
ENABLED,
}
impl OSCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OSCENW::DISABLED => false,
OSCENW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OSCENW<'a> {
w: &'a mut W,
}
impl<'a> _OSCENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OSCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled. The main oscillator is disabled."]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(OSCENW::DISABLED)
}
#[doc = "Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins."]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(OSCENW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `OSCSTAT`"]
pub enum OSCSTATW {
#[doc = "Not ready. The main oscillator is not ready to be used as a clock source."]
NOT_READY,
#[doc = "Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit."]
READY,
}
impl OSCSTATW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OSCSTATW::NOT_READY => false,
OSCSTATW::READY => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OSCSTATW<'a> {
w: &'a mut W,
}
impl<'a> _OSCSTATW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OSCSTATW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Not ready. The main oscillator is not ready to be used as a clock source."]
#[inline]
pub fn not_ready(self) -> &'a mut W {
self.variant(OSCSTATW::NOT_READY)
}
#[doc = "Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit."]
#[inline]
pub fn ready(self) -> &'a mut W {
self.variant(OSCSTATW::READY)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 4 - Main oscillator range select."]
#[inline]
pub fn oscrange(&self) -> OSCRANGER {
OSCRANGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Main oscillator enable."]
#[inline]
pub fn oscen(&self) -> OSCENR {
OSCENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Main oscillator status."]
#[inline]
pub fn oscstat(&self) -> OSCSTATR {
OSCSTATR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 4 - Main oscillator range select."]
#[inline]
pub fn oscrange(&mut self) -> _OSCRANGEW {
_OSCRANGEW { w: self }
}
#[doc = "Bit 5 - Main oscillator enable."]
#[inline]
pub fn oscen(&mut self) -> _OSCENW {
_OSCENW { w: self }
}
#[doc = "Bit 6 - Main oscillator status."]
#[inline]
pub fn oscstat(&mut self) -> _OSCSTATW {
_OSCSTATW { w: self }
}
}
}
#[doc = "Peripheral Clock Selection register 0."]
pub struct PCLKSEL0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Clock Selection register 0."]
pub mod pclksel0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PCLKSEL0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `PCLK_WDT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_WDTR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_WDTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_WDTR::CCLK_DIV_4 => 0,
PCLK_WDTR::CCLK => 0x01,
PCLK_WDTR::CCLK_DIV_2 => 0x02,
PCLK_WDTR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_WDTR {
match value {
0 => PCLK_WDTR::CCLK_DIV_4,
1 => PCLK_WDTR::CCLK,
2 => PCLK_WDTR::CCLK_DIV_2,
3 => PCLK_WDTR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_WDTR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_WDTR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_WDTR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_WDTR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_TIMER0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_TIMER0R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_TIMER0R::CCLK_DIV_4 => 0,
PCLK_TIMER0R::CCLK => 0x01,
PCLK_TIMER0R::CCLK_DIV_2 => 0x02,
PCLK_TIMER0R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_TIMER0R {
match value {
0 => PCLK_TIMER0R::CCLK_DIV_4,
1 => PCLK_TIMER0R::CCLK,
2 => PCLK_TIMER0R::CCLK_DIV_2,
3 => PCLK_TIMER0R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_TIMER0R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_TIMER0R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_TIMER0R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_TIMER0R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_TIMER1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_TIMER1R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_TIMER1R::CCLK_DIV_4 => 0,
PCLK_TIMER1R::CCLK => 0x01,
PCLK_TIMER1R::CCLK_DIV_2 => 0x02,
PCLK_TIMER1R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_TIMER1R {
match value {
0 => PCLK_TIMER1R::CCLK_DIV_4,
1 => PCLK_TIMER1R::CCLK,
2 => PCLK_TIMER1R::CCLK_DIV_2,
3 => PCLK_TIMER1R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_TIMER1R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_TIMER1R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_TIMER1R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_TIMER1R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_UART0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_UART0R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_UART0R::CCLK_DIV_4 => 0,
PCLK_UART0R::CCLK => 0x01,
PCLK_UART0R::CCLK_DIV_2 => 0x02,
PCLK_UART0R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_UART0R {
match value {
0 => PCLK_UART0R::CCLK_DIV_4,
1 => PCLK_UART0R::CCLK,
2 => PCLK_UART0R::CCLK_DIV_2,
3 => PCLK_UART0R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_UART0R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_UART0R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_UART0R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_UART0R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_UART1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_UART1R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_UART1R::CCLK_DIV_4 => 0,
PCLK_UART1R::CCLK => 0x01,
PCLK_UART1R::CCLK_DIV_2 => 0x02,
PCLK_UART1R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_UART1R {
match value {
0 => PCLK_UART1R::CCLK_DIV_4,
1 => PCLK_UART1R::CCLK,
2 => PCLK_UART1R::CCLK_DIV_2,
3 => PCLK_UART1R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_UART1R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_UART1R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_UART1R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_UART1R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_PWM1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_PWM1R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_PWM1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_PWM1R::CCLK_DIV_4 => 0,
PCLK_PWM1R::CCLK => 0x01,
PCLK_PWM1R::CCLK_DIV_2 => 0x02,
PCLK_PWM1R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_PWM1R {
match value {
0 => PCLK_PWM1R::CCLK_DIV_4,
1 => PCLK_PWM1R::CCLK,
2 => PCLK_PWM1R::CCLK_DIV_2,
3 => PCLK_PWM1R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_PWM1R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_PWM1R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_PWM1R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_PWM1R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_I2C0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_I2C0R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2C0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_I2C0R::CCLK_DIV_4 => 0,
PCLK_I2C0R::CCLK => 0x01,
PCLK_I2C0R::CCLK_DIV_2 => 0x02,
PCLK_I2C0R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_I2C0R {
match value {
0 => PCLK_I2C0R::CCLK_DIV_4,
1 => PCLK_I2C0R::CCLK,
2 => PCLK_I2C0R::CCLK_DIV_2,
3 => PCLK_I2C0R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_I2C0R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_I2C0R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_I2C0R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_I2C0R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_SPI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_SPIR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SPIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_SPIR::CCLK_DIV_4 => 0,
PCLK_SPIR::CCLK => 0x01,
PCLK_SPIR::CCLK_DIV_2 => 0x02,
PCLK_SPIR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_SPIR {
match value {
0 => PCLK_SPIR::CCLK_DIV_4,
1 => PCLK_SPIR::CCLK,
2 => PCLK_SPIR::CCLK_DIV_2,
3 => PCLK_SPIR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_SPIR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_SPIR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_SPIR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_SPIR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_SSP1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_SSP1R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SSP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_SSP1R::CCLK_DIV_4 => 0,
PCLK_SSP1R::CCLK => 0x01,
PCLK_SSP1R::CCLK_DIV_2 => 0x02,
PCLK_SSP1R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_SSP1R {
match value {
0 => PCLK_SSP1R::CCLK_DIV_4,
1 => PCLK_SSP1R::CCLK,
2 => PCLK_SSP1R::CCLK_DIV_2,
3 => PCLK_SSP1R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_SSP1R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_SSP1R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_SSP1R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_SSP1R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_DAC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_DACR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_DACR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_DACR::CCLK_DIV_4 => 0,
PCLK_DACR::CCLK => 0x01,
PCLK_DACR::CCLK_DIV_2 => 0x02,
PCLK_DACR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_DACR {
match value {
0 => PCLK_DACR::CCLK_DIV_4,
1 => PCLK_DACR::CCLK,
2 => PCLK_DACR::CCLK_DIV_2,
3 => PCLK_DACR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_DACR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_DACR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_DACR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_DACR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_ADC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_ADCR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_ADCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_ADCR::CCLK_DIV_4 => 0,
PCLK_ADCR::CCLK => 0x01,
PCLK_ADCR::CCLK_DIV_2 => 0x02,
PCLK_ADCR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_ADCR {
match value {
0 => PCLK_ADCR::CCLK_DIV_4,
1 => PCLK_ADCR::CCLK,
2 => PCLK_ADCR::CCLK_DIV_2,
3 => PCLK_ADCR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_ADCR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_ADCR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_ADCR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_ADCR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_CAN1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_CAN1R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6."]
CCLK_DIV_6,
}
impl PCLK_CAN1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_CAN1R::CCLK_DIV_4 => 0,
PCLK_CAN1R::CCLK => 0x01,
PCLK_CAN1R::CCLK_DIV_2 => 0x02,
PCLK_CAN1R::CCLK_DIV_6 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_CAN1R {
match value {
0 => PCLK_CAN1R::CCLK_DIV_4,
1 => PCLK_CAN1R::CCLK,
2 => PCLK_CAN1R::CCLK_DIV_2,
3 => PCLK_CAN1R::CCLK_DIV_6,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_CAN1R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_CAN1R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_CAN1R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_6`"]
#[inline]
pub fn is_cclk_div_6(&self) -> bool {
*self == PCLK_CAN1R::CCLK_DIV_6
}
}
#[doc = "Possible values of the field `PCLK_CAN2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_CAN2R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6,"]
CCLK_DIV_6,
}
impl PCLK_CAN2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_CAN2R::CCLK_DIV_4 => 0,
PCLK_CAN2R::CCLK => 0x01,
PCLK_CAN2R::CCLK_DIV_2 => 0x02,
PCLK_CAN2R::CCLK_DIV_6 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_CAN2R {
match value {
0 => PCLK_CAN2R::CCLK_DIV_4,
1 => PCLK_CAN2R::CCLK,
2 => PCLK_CAN2R::CCLK_DIV_2,
3 => PCLK_CAN2R::CCLK_DIV_6,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_CAN2R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_CAN2R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_CAN2R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_6`"]
#[inline]
pub fn is_cclk_div_6(&self) -> bool {
*self == PCLK_CAN2R::CCLK_DIV_6
}
}
#[doc = "Possible values of the field `PCLK_ACF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_ACFR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6"]
CCLK_DIV_6,
}
impl PCLK_ACFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_ACFR::CCLK_DIV_4 => 0,
PCLK_ACFR::CCLK => 0x01,
PCLK_ACFR::CCLK_DIV_2 => 0x02,
PCLK_ACFR::CCLK_DIV_6 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_ACFR {
match value {
0 => PCLK_ACFR::CCLK_DIV_4,
1 => PCLK_ACFR::CCLK,
2 => PCLK_ACFR::CCLK_DIV_2,
3 => PCLK_ACFR::CCLK_DIV_6,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_ACFR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_ACFR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_ACFR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_6`"]
#[inline]
pub fn is_cclk_div_6(&self) -> bool {
*self == PCLK_ACFR::CCLK_DIV_6
}
}
#[doc = "Values that can be written to the field `PCLK_WDT`"]
pub enum PCLK_WDTW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_WDTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_WDTW::CCLK_DIV_4 => 0,
PCLK_WDTW::CCLK => 1,
PCLK_WDTW::CCLK_DIV_2 => 2,
PCLK_WDTW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_WDTW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_WDTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_WDTW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_WDTW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_WDTW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_WDTW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_WDTW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_TIMER0`"]
pub enum PCLK_TIMER0W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_TIMER0W::CCLK_DIV_4 => 0,
PCLK_TIMER0W::CCLK => 1,
PCLK_TIMER0W::CCLK_DIV_2 => 2,
PCLK_TIMER0W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_TIMER0W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_TIMER0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_TIMER0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_TIMER0W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_TIMER0W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_TIMER0W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_TIMER0W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_TIMER1`"]
pub enum PCLK_TIMER1W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_TIMER1W::CCLK_DIV_4 => 0,
PCLK_TIMER1W::CCLK => 1,
PCLK_TIMER1W::CCLK_DIV_2 => 2,
PCLK_TIMER1W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_TIMER1W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_TIMER1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_TIMER1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_TIMER1W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_TIMER1W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_TIMER1W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_TIMER1W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_UART0`"]
pub enum PCLK_UART0W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_UART0W::CCLK_DIV_4 => 0,
PCLK_UART0W::CCLK => 1,
PCLK_UART0W::CCLK_DIV_2 => 2,
PCLK_UART0W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_UART0W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_UART0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_UART0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_UART0W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_UART0W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_UART0W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_UART0W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_UART1`"]
pub enum PCLK_UART1W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_UART1W::CCLK_DIV_4 => 0,
PCLK_UART1W::CCLK => 1,
PCLK_UART1W::CCLK_DIV_2 => 2,
PCLK_UART1W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_UART1W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_UART1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_UART1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_UART1W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_UART1W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_UART1W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_UART1W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_PWM1`"]
pub enum PCLK_PWM1W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_PWM1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_PWM1W::CCLK_DIV_4 => 0,
PCLK_PWM1W::CCLK => 1,
PCLK_PWM1W::CCLK_DIV_2 => 2,
PCLK_PWM1W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_PWM1W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_PWM1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_PWM1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_PWM1W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_PWM1W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_PWM1W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_PWM1W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_I2C0`"]
pub enum PCLK_I2C0W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2C0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_I2C0W::CCLK_DIV_4 => 0,
PCLK_I2C0W::CCLK => 1,
PCLK_I2C0W::CCLK_DIV_2 => 2,
PCLK_I2C0W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_I2C0W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_I2C0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_I2C0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_I2C0W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_I2C0W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_I2C0W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_I2C0W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_SPI`"]
pub enum PCLK_SPIW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SPIW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_SPIW::CCLK_DIV_4 => 0,
PCLK_SPIW::CCLK => 1,
PCLK_SPIW::CCLK_DIV_2 => 2,
PCLK_SPIW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_SPIW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_SPIW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_SPIW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_SPIW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_SPIW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_SPIW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_SPIW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_SSP1`"]
pub enum PCLK_SSP1W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SSP1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_SSP1W::CCLK_DIV_4 => 0,
PCLK_SSP1W::CCLK => 1,
PCLK_SSP1W::CCLK_DIV_2 => 2,
PCLK_SSP1W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_SSP1W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_SSP1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_SSP1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_SSP1W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_SSP1W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_SSP1W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_SSP1W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_DAC`"]
pub enum PCLK_DACW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_DACW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_DACW::CCLK_DIV_4 => 0,
PCLK_DACW::CCLK => 1,
PCLK_DACW::CCLK_DIV_2 => 2,
PCLK_DACW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_DACW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_DACW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_DACW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_DACW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_DACW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_DACW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_DACW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_ADC`"]
pub enum PCLK_ADCW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_ADCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_ADCW::CCLK_DIV_4 => 0,
PCLK_ADCW::CCLK => 1,
PCLK_ADCW::CCLK_DIV_2 => 2,
PCLK_ADCW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_ADCW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_ADCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_ADCW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_ADCW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_ADCW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_ADCW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_ADCW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_CAN1`"]
pub enum PCLK_CAN1W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6."]
CCLK_DIV_6,
}
impl PCLK_CAN1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_CAN1W::CCLK_DIV_4 => 0,
PCLK_CAN1W::CCLK => 1,
PCLK_CAN1W::CCLK_DIV_2 => 2,
PCLK_CAN1W::CCLK_DIV_6 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_CAN1W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_CAN1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_CAN1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_CAN1W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_CAN1W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_CAN1W::CCLK_DIV_2)
}
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6."]
#[inline]
pub fn cclk_div_6(self) -> &'a mut W {
self.variant(PCLK_CAN1W::CCLK_DIV_6)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_CAN2`"]
pub enum PCLK_CAN2W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6,"]
CCLK_DIV_6,
}
impl PCLK_CAN2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_CAN2W::CCLK_DIV_4 => 0,
PCLK_CAN2W::CCLK => 1,
PCLK_CAN2W::CCLK_DIV_2 => 2,
PCLK_CAN2W::CCLK_DIV_6 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_CAN2W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_CAN2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_CAN2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_CAN2W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_CAN2W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_CAN2W::CCLK_DIV_2)
}
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6,"]
#[inline]
pub fn cclk_div_6(self) -> &'a mut W {
self.variant(PCLK_CAN2W::CCLK_DIV_6)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_ACF`"]
pub enum PCLK_ACFW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6"]
CCLK_DIV_6,
}
impl PCLK_ACFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_ACFW::CCLK_DIV_4 => 0,
PCLK_ACFW::CCLK => 1,
PCLK_ACFW::CCLK_DIV_2 => 2,
PCLK_ACFW::CCLK_DIV_6 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_ACFW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_ACFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_ACFW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_ACFW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_ACFW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_ACFW::CCLK_DIV_2)
}
#[doc = "CCLK div 6. PCLK_peripheral = CCLK/6"]
#[inline]
pub fn cclk_div_6(self) -> &'a mut W {
self.variant(PCLK_ACFW::CCLK_DIV_6)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Peripheral clock selection for WDT."]
#[inline]
pub fn pclk_wdt(&self) -> PCLK_WDTR {
PCLK_WDTR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Peripheral clock selection for TIMER0."]
#[inline]
pub fn pclk_timer0(&self) -> PCLK_TIMER0R {
PCLK_TIMER0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Peripheral clock selection for TIMER1."]
#[inline]
pub fn pclk_timer1(&self) -> PCLK_TIMER1R {
PCLK_TIMER1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Peripheral clock selection for UART0."]
#[inline]
pub fn pclk_uart0(&self) -> PCLK_UART0R {
PCLK_UART0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:9 - Peripheral clock selection for UART1."]
#[inline]
pub fn pclk_uart1(&self) -> PCLK_UART1R {
PCLK_UART1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Peripheral clock selection for PWM1."]
#[inline]
pub fn pclk_pwm1(&self) -> PCLK_PWM1R {
PCLK_PWM1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Peripheral clock selection for I2C0."]
#[inline]
pub fn pclk_i2c0(&self) -> PCLK_I2C0R {
PCLK_I2C0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Peripheral clock selection for SPI."]
#[inline]
pub fn pclk_spi(&self) -> PCLK_SPIR {
PCLK_SPIR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Peripheral clock selection for SSP1."]
#[inline]
pub fn pclk_ssp1(&self) -> PCLK_SSP1R {
PCLK_SSP1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Peripheral clock selection for DAC."]
#[inline]
pub fn pclk_dac(&self) -> PCLK_DACR {
PCLK_DACR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:25 - Peripheral clock selection for ADC."]
#[inline]
pub fn pclk_adc(&self) -> PCLK_ADCR {
PCLK_ADCR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."]
#[inline]
pub fn pclk_can1(&self) -> PCLK_CAN1R {
PCLK_CAN1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 28:29 - Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."]
#[inline]
pub fn pclk_can2(&self) -> PCLK_CAN2R {
PCLK_CAN2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."]
#[inline]
pub fn pclk_acf(&self) -> PCLK_ACFR {
PCLK_ACFR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Peripheral clock selection for WDT."]
#[inline]
pub fn pclk_wdt(&mut self) -> _PCLK_WDTW {
_PCLK_WDTW { w: self }
}
#[doc = "Bits 2:3 - Peripheral clock selection for TIMER0."]
#[inline]
pub fn pclk_timer0(&mut self) -> _PCLK_TIMER0W {
_PCLK_TIMER0W { w: self }
}
#[doc = "Bits 4:5 - Peripheral clock selection for TIMER1."]
#[inline]
pub fn pclk_timer1(&mut self) -> _PCLK_TIMER1W {
_PCLK_TIMER1W { w: self }
}
#[doc = "Bits 6:7 - Peripheral clock selection for UART0."]
#[inline]
pub fn pclk_uart0(&mut self) -> _PCLK_UART0W {
_PCLK_UART0W { w: self }
}
#[doc = "Bits 8:9 - Peripheral clock selection for UART1."]
#[inline]
pub fn pclk_uart1(&mut self) -> _PCLK_UART1W {
_PCLK_UART1W { w: self }
}
#[doc = "Bits 12:13 - Peripheral clock selection for PWM1."]
#[inline]
pub fn pclk_pwm1(&mut self) -> _PCLK_PWM1W {
_PCLK_PWM1W { w: self }
}
#[doc = "Bits 14:15 - Peripheral clock selection for I2C0."]
#[inline]
pub fn pclk_i2c0(&mut self) -> _PCLK_I2C0W {
_PCLK_I2C0W { w: self }
}
#[doc = "Bits 16:17 - Peripheral clock selection for SPI."]
#[inline]
pub fn pclk_spi(&mut self) -> _PCLK_SPIW {
_PCLK_SPIW { w: self }
}
#[doc = "Bits 20:21 - Peripheral clock selection for SSP1."]
#[inline]
pub fn pclk_ssp1(&mut self) -> _PCLK_SSP1W {
_PCLK_SSP1W { w: self }
}
#[doc = "Bits 22:23 - Peripheral clock selection for DAC."]
#[inline]
pub fn pclk_dac(&mut self) -> _PCLK_DACW {
_PCLK_DACW { w: self }
}
#[doc = "Bits 24:25 - Peripheral clock selection for ADC."]
#[inline]
pub fn pclk_adc(&mut self) -> _PCLK_ADCW {
_PCLK_ADCW { w: self }
}
#[doc = "Bits 26:27 - Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."]
#[inline]
pub fn pclk_can1(&mut self) -> _PCLK_CAN1W {
_PCLK_CAN1W { w: self }
}
#[doc = "Bits 28:29 - Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."]
#[inline]
pub fn pclk_can2(&mut self) -> _PCLK_CAN2W {
_PCLK_CAN2W { w: self }
}
#[doc = "Bits 30:31 - Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used."]
#[inline]
pub fn pclk_acf(&mut self) -> _PCLK_ACFW {
_PCLK_ACFW { w: self }
}
}
}
#[doc = "Peripheral Clock Selection register 1."]
pub struct PCLKSEL1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Clock Selection register 1."]
pub mod pclksel1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PCLKSEL1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `PCLK_QEI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_QEIR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_QEIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_QEIR::CCLK_DIV_4 => 0,
PCLK_QEIR::CCLK => 0x01,
PCLK_QEIR::CCLK_DIV_2 => 0x02,
PCLK_QEIR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_QEIR {
match value {
0 => PCLK_QEIR::CCLK_DIV_4,
1 => PCLK_QEIR::CCLK,
2 => PCLK_QEIR::CCLK_DIV_2,
3 => PCLK_QEIR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_QEIR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_QEIR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_QEIR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_QEIR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_GPIOINT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_GPIOINTR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_GPIOINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_GPIOINTR::CCLK_DIV_4 => 0,
PCLK_GPIOINTR::CCLK => 0x01,
PCLK_GPIOINTR::CCLK_DIV_2 => 0x02,
PCLK_GPIOINTR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_GPIOINTR {
match value {
0 => PCLK_GPIOINTR::CCLK_DIV_4,
1 => PCLK_GPIOINTR::CCLK,
2 => PCLK_GPIOINTR::CCLK_DIV_2,
3 => PCLK_GPIOINTR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_GPIOINTR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_GPIOINTR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_GPIOINTR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_GPIOINTR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_PCB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_PCBR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_PCBR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_PCBR::CCLK_DIV_4 => 0,
PCLK_PCBR::CCLK => 0x01,
PCLK_PCBR::CCLK_DIV_2 => 0x02,
PCLK_PCBR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_PCBR {
match value {
0 => PCLK_PCBR::CCLK_DIV_4,
1 => PCLK_PCBR::CCLK,
2 => PCLK_PCBR::CCLK_DIV_2,
3 => PCLK_PCBR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_PCBR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_PCBR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_PCBR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_PCBR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_I2C1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_I2C1R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2C1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_I2C1R::CCLK_DIV_4 => 0,
PCLK_I2C1R::CCLK => 0x01,
PCLK_I2C1R::CCLK_DIV_2 => 0x02,
PCLK_I2C1R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_I2C1R {
match value {
0 => PCLK_I2C1R::CCLK_DIV_4,
1 => PCLK_I2C1R::CCLK,
2 => PCLK_I2C1R::CCLK_DIV_2,
3 => PCLK_I2C1R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_I2C1R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_I2C1R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_I2C1R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_I2C1R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_SSP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_SSP0R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SSP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_SSP0R::CCLK_DIV_4 => 0,
PCLK_SSP0R::CCLK => 0x01,
PCLK_SSP0R::CCLK_DIV_2 => 0x02,
PCLK_SSP0R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_SSP0R {
match value {
0 => PCLK_SSP0R::CCLK_DIV_4,
1 => PCLK_SSP0R::CCLK,
2 => PCLK_SSP0R::CCLK_DIV_2,
3 => PCLK_SSP0R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_SSP0R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_SSP0R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_SSP0R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_SSP0R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_TIMER2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_TIMER2R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_TIMER2R::CCLK_DIV_4 => 0,
PCLK_TIMER2R::CCLK => 0x01,
PCLK_TIMER2R::CCLK_DIV_2 => 0x02,
PCLK_TIMER2R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_TIMER2R {
match value {
0 => PCLK_TIMER2R::CCLK_DIV_4,
1 => PCLK_TIMER2R::CCLK,
2 => PCLK_TIMER2R::CCLK_DIV_2,
3 => PCLK_TIMER2R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_TIMER2R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_TIMER2R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_TIMER2R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_TIMER2R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_TIMER3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_TIMER3R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_TIMER3R::CCLK_DIV_4 => 0,
PCLK_TIMER3R::CCLK => 0x01,
PCLK_TIMER3R::CCLK_DIV_2 => 0x02,
PCLK_TIMER3R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_TIMER3R {
match value {
0 => PCLK_TIMER3R::CCLK_DIV_4,
1 => PCLK_TIMER3R::CCLK,
2 => PCLK_TIMER3R::CCLK_DIV_2,
3 => PCLK_TIMER3R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_TIMER3R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_TIMER3R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_TIMER3R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_TIMER3R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_UART2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_UART2R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_UART2R::CCLK_DIV_4 => 0,
PCLK_UART2R::CCLK => 0x01,
PCLK_UART2R::CCLK_DIV_2 => 0x02,
PCLK_UART2R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_UART2R {
match value {
0 => PCLK_UART2R::CCLK_DIV_4,
1 => PCLK_UART2R::CCLK,
2 => PCLK_UART2R::CCLK_DIV_2,
3 => PCLK_UART2R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_UART2R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_UART2R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_UART2R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_UART2R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_UART3`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_UART3R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_UART3R::CCLK_DIV_4 => 0,
PCLK_UART3R::CCLK => 0x01,
PCLK_UART3R::CCLK_DIV_2 => 0x02,
PCLK_UART3R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_UART3R {
match value {
0 => PCLK_UART3R::CCLK_DIV_4,
1 => PCLK_UART3R::CCLK,
2 => PCLK_UART3R::CCLK_DIV_2,
3 => PCLK_UART3R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_UART3R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_UART3R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_UART3R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_UART3R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_I2C2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_I2C2R {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2C2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_I2C2R::CCLK_DIV_4 => 0,
PCLK_I2C2R::CCLK => 0x01,
PCLK_I2C2R::CCLK_DIV_2 => 0x02,
PCLK_I2C2R::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_I2C2R {
match value {
0 => PCLK_I2C2R::CCLK_DIV_4,
1 => PCLK_I2C2R::CCLK,
2 => PCLK_I2C2R::CCLK_DIV_2,
3 => PCLK_I2C2R::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_I2C2R::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_I2C2R::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_I2C2R::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_I2C2R::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_I2S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_I2SR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2SR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_I2SR::CCLK_DIV_4 => 0,
PCLK_I2SR::CCLK => 0x01,
PCLK_I2SR::CCLK_DIV_2 => 0x02,
PCLK_I2SR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_I2SR {
match value {
0 => PCLK_I2SR::CCLK_DIV_4,
1 => PCLK_I2SR::CCLK,
2 => PCLK_I2SR::CCLK_DIV_2,
3 => PCLK_I2SR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_I2SR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_I2SR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_I2SR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_I2SR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_RIT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_RITR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_RITR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_RITR::CCLK_DIV_4 => 0,
PCLK_RITR::CCLK => 0x01,
PCLK_RITR::CCLK_DIV_2 => 0x02,
PCLK_RITR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_RITR {
match value {
0 => PCLK_RITR::CCLK_DIV_4,
1 => PCLK_RITR::CCLK,
2 => PCLK_RITR::CCLK_DIV_2,
3 => PCLK_RITR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_RITR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_RITR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_RITR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_RITR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_SYSCON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_SYSCONR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SYSCONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_SYSCONR::CCLK_DIV_4 => 0,
PCLK_SYSCONR::CCLK => 0x01,
PCLK_SYSCONR::CCLK_DIV_2 => 0x02,
PCLK_SYSCONR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_SYSCONR {
match value {
0 => PCLK_SYSCONR::CCLK_DIV_4,
1 => PCLK_SYSCONR::CCLK,
2 => PCLK_SYSCONR::CCLK_DIV_2,
3 => PCLK_SYSCONR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_SYSCONR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_SYSCONR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_SYSCONR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_SYSCONR::CCLK_DIV_8
}
}
#[doc = "Possible values of the field `PCLK_MC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCLK_MCR {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_MCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PCLK_MCR::CCLK_DIV_4 => 0,
PCLK_MCR::CCLK => 0x01,
PCLK_MCR::CCLK_DIV_2 => 0x02,
PCLK_MCR::CCLK_DIV_8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PCLK_MCR {
match value {
0 => PCLK_MCR::CCLK_DIV_4,
1 => PCLK_MCR::CCLK,
2 => PCLK_MCR::CCLK_DIV_2,
3 => PCLK_MCR::CCLK_DIV_8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CCLK_DIV_4`"]
#[inline]
pub fn is_cclk_div_4(&self) -> bool {
*self == PCLK_MCR::CCLK_DIV_4
}
#[doc = "Checks if the value of the field is `CCLK`"]
#[inline]
pub fn is_cclk(&self) -> bool {
*self == PCLK_MCR::CCLK
}
#[doc = "Checks if the value of the field is `CCLK_DIV_2`"]
#[inline]
pub fn is_cclk_div_2(&self) -> bool {
*self == PCLK_MCR::CCLK_DIV_2
}
#[doc = "Checks if the value of the field is `CCLK_DIV_8`"]
#[inline]
pub fn is_cclk_div_8(&self) -> bool {
*self == PCLK_MCR::CCLK_DIV_8
}
}
#[doc = "Values that can be written to the field `PCLK_QEI`"]
pub enum PCLK_QEIW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_QEIW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_QEIW::CCLK_DIV_4 => 0,
PCLK_QEIW::CCLK => 1,
PCLK_QEIW::CCLK_DIV_2 => 2,
PCLK_QEIW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_QEIW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_QEIW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_QEIW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_QEIW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_QEIW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_QEIW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_QEIW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_GPIOINT`"]
pub enum PCLK_GPIOINTW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_GPIOINTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_GPIOINTW::CCLK_DIV_4 => 0,
PCLK_GPIOINTW::CCLK => 1,
PCLK_GPIOINTW::CCLK_DIV_2 => 2,
PCLK_GPIOINTW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_GPIOINTW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_GPIOINTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_GPIOINTW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_GPIOINTW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_GPIOINTW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_GPIOINTW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_GPIOINTW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_PCB`"]
pub enum PCLK_PCBW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_PCBW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_PCBW::CCLK_DIV_4 => 0,
PCLK_PCBW::CCLK => 1,
PCLK_PCBW::CCLK_DIV_2 => 2,
PCLK_PCBW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_PCBW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_PCBW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_PCBW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_PCBW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_PCBW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_PCBW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_PCBW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_I2C1`"]
pub enum PCLK_I2C1W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2C1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_I2C1W::CCLK_DIV_4 => 0,
PCLK_I2C1W::CCLK => 1,
PCLK_I2C1W::CCLK_DIV_2 => 2,
PCLK_I2C1W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_I2C1W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_I2C1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_I2C1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_I2C1W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_I2C1W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_I2C1W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_I2C1W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_SSP0`"]
pub enum PCLK_SSP0W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SSP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_SSP0W::CCLK_DIV_4 => 0,
PCLK_SSP0W::CCLK => 1,
PCLK_SSP0W::CCLK_DIV_2 => 2,
PCLK_SSP0W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_SSP0W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_SSP0W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_SSP0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_SSP0W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_SSP0W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_SSP0W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_SSP0W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_TIMER2`"]
pub enum PCLK_TIMER2W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_TIMER2W::CCLK_DIV_4 => 0,
PCLK_TIMER2W::CCLK => 1,
PCLK_TIMER2W::CCLK_DIV_2 => 2,
PCLK_TIMER2W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_TIMER2W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_TIMER2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_TIMER2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_TIMER2W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_TIMER2W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_TIMER2W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_TIMER2W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_TIMER3`"]
pub enum PCLK_TIMER3W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_TIMER3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_TIMER3W::CCLK_DIV_4 => 0,
PCLK_TIMER3W::CCLK => 1,
PCLK_TIMER3W::CCLK_DIV_2 => 2,
PCLK_TIMER3W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_TIMER3W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_TIMER3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_TIMER3W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_TIMER3W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_TIMER3W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_TIMER3W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_TIMER3W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_UART2`"]
pub enum PCLK_UART2W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_UART2W::CCLK_DIV_4 => 0,
PCLK_UART2W::CCLK => 1,
PCLK_UART2W::CCLK_DIV_2 => 2,
PCLK_UART2W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_UART2W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_UART2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_UART2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_UART2W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_UART2W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_UART2W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_UART2W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_UART3`"]
pub enum PCLK_UART3W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_UART3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_UART3W::CCLK_DIV_4 => 0,
PCLK_UART3W::CCLK => 1,
PCLK_UART3W::CCLK_DIV_2 => 2,
PCLK_UART3W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_UART3W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_UART3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_UART3W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_UART3W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_UART3W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_UART3W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_UART3W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_I2C2`"]
pub enum PCLK_I2C2W {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2C2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_I2C2W::CCLK_DIV_4 => 0,
PCLK_I2C2W::CCLK => 1,
PCLK_I2C2W::CCLK_DIV_2 => 2,
PCLK_I2C2W::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_I2C2W<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_I2C2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_I2C2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_I2C2W::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_I2C2W::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_I2C2W::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_I2C2W::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_I2S`"]
pub enum PCLK_I2SW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_I2SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_I2SW::CCLK_DIV_4 => 0,
PCLK_I2SW::CCLK => 1,
PCLK_I2SW::CCLK_DIV_2 => 2,
PCLK_I2SW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_I2SW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_I2SW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_I2SW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_I2SW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_I2SW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_I2SW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_I2SW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_RIT`"]
pub enum PCLK_RITW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_RITW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_RITW::CCLK_DIV_4 => 0,
PCLK_RITW::CCLK => 1,
PCLK_RITW::CCLK_DIV_2 => 2,
PCLK_RITW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_RITW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_RITW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_RITW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_RITW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_RITW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_RITW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_RITW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_SYSCON`"]
pub enum PCLK_SYSCONW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_SYSCONW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_SYSCONW::CCLK_DIV_4 => 0,
PCLK_SYSCONW::CCLK => 1,
PCLK_SYSCONW::CCLK_DIV_2 => 2,
PCLK_SYSCONW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_SYSCONW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_SYSCONW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_SYSCONW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_SYSCONW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_SYSCONW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_SYSCONW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_SYSCONW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PCLK_MC`"]
pub enum PCLK_MCW {
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
CCLK_DIV_4,
#[doc = "CCLK. PCLK_peripheral = CCLK"]
CCLK,
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
CCLK_DIV_2,
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
CCLK_DIV_8,
}
impl PCLK_MCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PCLK_MCW::CCLK_DIV_4 => 0,
PCLK_MCW::CCLK => 1,
PCLK_MCW::CCLK_DIV_2 => 2,
PCLK_MCW::CCLK_DIV_8 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PCLK_MCW<'a> {
w: &'a mut W,
}
impl<'a> _PCLK_MCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PCLK_MCW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "CCLK div 4. PCLK_peripheral = CCLK/4"]
#[inline]
pub fn cclk_div_4(self) -> &'a mut W {
self.variant(PCLK_MCW::CCLK_DIV_4)
}
#[doc = "CCLK. PCLK_peripheral = CCLK"]
#[inline]
pub fn cclk(self) -> &'a mut W {
self.variant(PCLK_MCW::CCLK)
}
#[doc = "CCLK div 2. PCLK_peripheral = CCLK/2"]
#[inline]
pub fn cclk_div_2(self) -> &'a mut W {
self.variant(PCLK_MCW::CCLK_DIV_2)
}
#[doc = "CCLK div 8. PCLK_peripheral = CCLK/8"]
#[inline]
pub fn cclk_div_8(self) -> &'a mut W {
self.variant(PCLK_MCW::CCLK_DIV_8)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Peripheral clock selection for the Quadrature Encoder Interface."]
#[inline]
pub fn pclk_qei(&self) -> PCLK_QEIR {
PCLK_QEIR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Peripheral clock selection for GPIO interrupts."]
#[inline]
pub fn pclk_gpioint(&self) -> PCLK_GPIOINTR {
PCLK_GPIOINTR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:5 - Peripheral clock selection for the Pin Connect block."]
#[inline]
pub fn pclk_pcb(&self) -> PCLK_PCBR {
PCLK_PCBR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:7 - Peripheral clock selection for I2C1."]
#[inline]
pub fn pclk_i2c1(&self) -> PCLK_I2C1R {
PCLK_I2C1R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 10:11 - Peripheral clock selection for SSP0."]
#[inline]
pub fn pclk_ssp0(&self) -> PCLK_SSP0R {
PCLK_SSP0R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 12:13 - Peripheral clock selection for TIMER2."]
#[inline]
pub fn pclk_timer2(&self) -> PCLK_TIMER2R {
PCLK_TIMER2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 14:15 - Peripheral clock selection for TIMER3."]
#[inline]
pub fn pclk_timer3(&self) -> PCLK_TIMER3R {
PCLK_TIMER3R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:17 - Peripheral clock selection for UART2."]
#[inline]
pub fn pclk_uart2(&self) -> PCLK_UART2R {
PCLK_UART2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 18:19 - Peripheral clock selection for UART3."]
#[inline]
pub fn pclk_uart3(&self) -> PCLK_UART3R {
PCLK_UART3R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 20:21 - Peripheral clock selection for I2C2."]
#[inline]
pub fn pclk_i2c2(&self) -> PCLK_I2C2R {
PCLK_I2C2R::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 22:23 - Peripheral clock selection for I2S."]
#[inline]
pub fn pclk_i2s(&self) -> PCLK_I2SR {
PCLK_I2SR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 26:27 - Peripheral clock selection for Repetitive Interrupt Timer."]
#[inline]
pub fn pclk_rit(&self) -> PCLK_RITR {
PCLK_RITR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 28:29 - Peripheral clock selection for the System Control block."]
#[inline]
pub fn pclk_syscon(&self) -> PCLK_SYSCONR {
PCLK_SYSCONR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 30:31 - Peripheral clock selection for the Motor Control PWM."]
#[inline]
pub fn pclk_mc(&self) -> PCLK_MCR {
PCLK_MCR::_from({
const MASK: u8 = 0x03;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Peripheral clock selection for the Quadrature Encoder Interface."]
#[inline]
pub fn pclk_qei(&mut self) -> _PCLK_QEIW {
_PCLK_QEIW { w: self }
}
#[doc = "Bits 2:3 - Peripheral clock selection for GPIO interrupts."]
#[inline]
pub fn pclk_gpioint(&mut self) -> _PCLK_GPIOINTW {
_PCLK_GPIOINTW { w: self }
}
#[doc = "Bits 4:5 - Peripheral clock selection for the Pin Connect block."]
#[inline]
pub fn pclk_pcb(&mut self) -> _PCLK_PCBW {
_PCLK_PCBW { w: self }
}
#[doc = "Bits 6:7 - Peripheral clock selection for I2C1."]
#[inline]
pub fn pclk_i2c1(&mut self) -> _PCLK_I2C1W {
_PCLK_I2C1W { w: self }
}
#[doc = "Bits 10:11 - Peripheral clock selection for SSP0."]
#[inline]
pub fn pclk_ssp0(&mut self) -> _PCLK_SSP0W {
_PCLK_SSP0W { w: self }
}
#[doc = "Bits 12:13 - Peripheral clock selection for TIMER2."]
#[inline]
pub fn pclk_timer2(&mut self) -> _PCLK_TIMER2W {
_PCLK_TIMER2W { w: self }
}
#[doc = "Bits 14:15 - Peripheral clock selection for TIMER3."]
#[inline]
pub fn pclk_timer3(&mut self) -> _PCLK_TIMER3W {
_PCLK_TIMER3W { w: self }
}
#[doc = "Bits 16:17 - Peripheral clock selection for UART2."]
#[inline]
pub fn pclk_uart2(&mut self) -> _PCLK_UART2W {
_PCLK_UART2W { w: self }
}
#[doc = "Bits 18:19 - Peripheral clock selection for UART3."]
#[inline]
pub fn pclk_uart3(&mut self) -> _PCLK_UART3W {
_PCLK_UART3W { w: self }
}
#[doc = "Bits 20:21 - Peripheral clock selection for I2C2."]
#[inline]
pub fn pclk_i2c2(&mut self) -> _PCLK_I2C2W {
_PCLK_I2C2W { w: self }
}
#[doc = "Bits 22:23 - Peripheral clock selection for I2S."]
#[inline]
pub fn pclk_i2s(&mut self) -> _PCLK_I2SW {
_PCLK_I2SW { w: self }
}
#[doc = "Bits 26:27 - Peripheral clock selection for Repetitive Interrupt Timer."]
#[inline]
pub fn pclk_rit(&mut self) -> _PCLK_RITW {
_PCLK_RITW { w: self }
}
#[doc = "Bits 28:29 - Peripheral clock selection for the System Control block."]
#[inline]
pub fn pclk_syscon(&mut self) -> _PCLK_SYSCONW {
_PCLK_SYSCONW { w: self }
}
#[doc = "Bits 30:31 - Peripheral clock selection for the Motor Control PWM."]
#[inline]
pub fn pclk_mc(&mut self) -> _PCLK_MCW {
_PCLK_MCW { w: self }
}
}
}
#[doc = "USB Interrupt Status"]
pub struct USBINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Interrupt Status"]
pub mod usbintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::USBINTST {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct USB_INT_REQ_LPR {
bits: bool,
}
impl USB_INT_REQ_LPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_INT_REQ_HPR {
bits: bool,
}
impl USB_INT_REQ_HPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_INT_REQ_DMAR {
bits: bool,
}
impl USB_INT_REQ_DMAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_HOST_INTR {
bits: bool,
}
impl USB_HOST_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_ATX_INTR {
bits: bool,
}
impl USB_ATX_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_OTG_INTR {
bits: bool,
}
impl USB_OTG_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_I2C_INTR {
bits: bool,
}
impl USB_I2C_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct USB_NEED_CLKR {
bits: bool,
}
impl USB_NEED_CLKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EN_USB_INTSR {
bits: bool,
}
impl EN_USB_INTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _USB_INT_REQ_LPW<'a> {
w: &'a mut W,
}
impl<'a> _USB_INT_REQ_LPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_INT_REQ_HPW<'a> {
w: &'a mut W,
}
impl<'a> _USB_INT_REQ_HPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_INT_REQ_DMAW<'a> {
w: &'a mut W,
}
impl<'a> _USB_INT_REQ_DMAW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_HOST_INTW<'a> {
w: &'a mut W,
}
impl<'a> _USB_HOST_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_ATX_INTW<'a> {
w: &'a mut W,
}
impl<'a> _USB_ATX_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_OTG_INTW<'a> {
w: &'a mut W,
}
impl<'a> _USB_OTG_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_I2C_INTW<'a> {
w: &'a mut W,
}
impl<'a> _USB_I2C_INTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _USB_NEED_CLKW<'a> {
w: &'a mut W,
}
impl<'a> _USB_NEED_CLKW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EN_USB_INTSW<'a> {
w: &'a mut W,
}
impl<'a> _EN_USB_INTSW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Low priority interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_int_req_lp(&self) -> USB_INT_REQ_LPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_INT_REQ_LPR { bits }
}
#[doc = "Bit 1 - High priority interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_int_req_hp(&self) -> USB_INT_REQ_HPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_INT_REQ_HPR { bits }
}
#[doc = "Bit 2 - DMA interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_int_req_dma(&self) -> USB_INT_REQ_DMAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_INT_REQ_DMAR { bits }
}
#[doc = "Bit 3 - USB host interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_host_int(&self) -> USB_HOST_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_HOST_INTR { bits }
}
#[doc = "Bit 4 - External ATX interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_atx_int(&self) -> USB_ATX_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_ATX_INTR { bits }
}
#[doc = "Bit 5 - OTG interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_otg_int(&self) -> USB_OTG_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_OTG_INTR { bits }
}
#[doc = "Bit 6 - I2C module interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_i2c_int(&self) -> USB_I2C_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_I2C_INTR { bits }
}
#[doc = "Bit 8 - USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only."]
#[inline]
pub fn usb_need_clk(&self) -> USB_NEED_CLKR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
USB_NEED_CLKR { bits }
}
#[doc = "Bit 31 - Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines."]
#[inline]
pub fn en_usb_ints(&self) -> EN_USB_INTSR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EN_USB_INTSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x8000_0000 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Low priority interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_int_req_lp(&mut self) -> _USB_INT_REQ_LPW {
_USB_INT_REQ_LPW { w: self }
}
#[doc = "Bit 1 - High priority interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_int_req_hp(&mut self) -> _USB_INT_REQ_HPW {
_USB_INT_REQ_HPW { w: self }
}
#[doc = "Bit 2 - DMA interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_int_req_dma(&mut self) -> _USB_INT_REQ_DMAW {
_USB_INT_REQ_DMAW { w: self }
}
#[doc = "Bit 3 - USB host interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_host_int(&mut self) -> _USB_HOST_INTW {
_USB_HOST_INTW { w: self }
}
#[doc = "Bit 4 - External ATX interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_atx_int(&mut self) -> _USB_ATX_INTW {
_USB_ATX_INTW { w: self }
}
#[doc = "Bit 5 - OTG interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_otg_int(&mut self) -> _USB_OTG_INTW {
_USB_OTG_INTW { w: self }
}
#[doc = "Bit 6 - I2C module interrupt line status. This bit is read-only."]
#[inline]
pub fn usb_i2c_int(&mut self) -> _USB_I2C_INTW {
_USB_I2C_INTW { w: self }
}
#[doc = "Bit 8 - USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only."]
#[inline]
pub fn usb_need_clk(&mut self) -> _USB_NEED_CLKW {
_USB_NEED_CLKW { w: self }
}
#[doc = "Bit 31 - Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines."]
#[inline]
pub fn en_usb_ints(&mut self) -> _EN_USB_INTSW {
_EN_USB_INTSW { w: self }
}
}
}
#[doc = "Selects between alternative requests on DMA channels 0 through 7 and 10 through 15"]
pub struct DMACREQSEL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Selects between alternative requests on DMA channels 0 through 7 and 10 through 15"]
pub mod dmacreqsel {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMACREQSEL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DMASEL08R {
bits: bool,
}
impl DMASEL08R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL09R {
bits: bool,
}
impl DMASEL09R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL10R {
bits: bool,
}
impl DMASEL10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL11R {
bits: bool,
}
impl DMASEL11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL12R {
bits: bool,
}
impl DMASEL12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL13R {
bits: bool,
}
impl DMASEL13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL14R {
bits: bool,
}
impl DMASEL14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMASEL15R {
bits: bool,
}
impl DMASEL15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _DMASEL08W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL08W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL09W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL09W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL10W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL11W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL12W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL13W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL14W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMASEL15W<'a> {
w: &'a mut W,
}
impl<'a> _DMASEL15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected."]
#[inline]
pub fn dmasel08(&self) -> DMASEL08R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL08R { bits }
}
#[doc = "Bit 1 - Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected."]
#[inline]
pub fn dmasel09(&self) -> DMASEL09R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL09R { bits }
}
#[doc = "Bit 2 - Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected."]
#[inline]
pub fn dmasel10(&self) -> DMASEL10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL10R { bits }
}
#[doc = "Bit 3 - Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected."]
#[inline]
pub fn dmasel11(&self) -> DMASEL11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL11R { bits }
}
#[doc = "Bit 4 - Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected."]
#[inline]
pub fn dmasel12(&self) -> DMASEL12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL12R { bits }
}
#[doc = "Bit 5 - Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected."]
#[inline]
pub fn dmasel13(&self) -> DMASEL13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL13R { bits }
}
#[doc = "Bit 6 - Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected."]
#[inline]
pub fn dmasel14(&self) -> DMASEL14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL14R { bits }
}
#[doc = "Bit 7 - Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected."]
#[inline]
pub fn dmasel15(&self) -> DMASEL15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMASEL15R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected."]
#[inline]
pub fn dmasel08(&mut self) -> _DMASEL08W {
_DMASEL08W { w: self }
}
#[doc = "Bit 1 - Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected."]
#[inline]
pub fn dmasel09(&mut self) -> _DMASEL09W {
_DMASEL09W { w: self }
}
#[doc = "Bit 2 - Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected."]
#[inline]
pub fn dmasel10(&mut self) -> _DMASEL10W {
_DMASEL10W { w: self }
}
#[doc = "Bit 3 - Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected."]
#[inline]
pub fn dmasel11(&mut self) -> _DMASEL11W {
_DMASEL11W { w: self }
}
#[doc = "Bit 4 - Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected."]
#[inline]
pub fn dmasel12(&mut self) -> _DMASEL12W {
_DMASEL12W { w: self }
}
#[doc = "Bit 5 - Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected."]
#[inline]
pub fn dmasel13(&mut self) -> _DMASEL13W {
_DMASEL13W { w: self }
}
#[doc = "Bit 6 - Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected."]
#[inline]
pub fn dmasel14(&mut self) -> _DMASEL14W {
_DMASEL14W { w: self }
}
#[doc = "Bit 7 - Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected."]
#[inline]
pub fn dmasel15(&mut self) -> _DMASEL15W {
_DMASEL15W { w: self }
}
}
}
#[doc = "Clock Output Configuration Register"]
pub struct CLKOUTCFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Clock Output Configuration Register"]
pub mod clkoutcfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLKOUTCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CLKOUTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKOUTSELR {
#[doc = "Selects the CPU clock as the CLKOUT source."]
SELECTS_THE_CPU_CLOC,
#[doc = "Selects the main oscillator as the CLKOUT source."]
SELECTS_THE_MAIN_OSC,
#[doc = "Selects the Internal RC oscillator as the CLKOUT source."]
SELECTS_THE_INTERNAL,
#[doc = "Selects the USB clock as the CLKOUT source."]
SELECTS_THE_USB_CLOC,
#[doc = "Selects the RTC oscillator as the CLKOUT source."]
SELECTS_THE_RTC_OSCI,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl CLKOUTSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CLKOUTSELR::SELECTS_THE_CPU_CLOC => 0,
CLKOUTSELR::SELECTS_THE_MAIN_OSC => 0x01,
CLKOUTSELR::SELECTS_THE_INTERNAL => 0x02,
CLKOUTSELR::SELECTS_THE_USB_CLOC => 0x03,
CLKOUTSELR::SELECTS_THE_RTC_OSCI => 0x04,
CLKOUTSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CLKOUTSELR {
match value {
0 => CLKOUTSELR::SELECTS_THE_CPU_CLOC,
1 => CLKOUTSELR::SELECTS_THE_MAIN_OSC,
2 => CLKOUTSELR::SELECTS_THE_INTERNAL,
3 => CLKOUTSELR::SELECTS_THE_USB_CLOC,
4 => CLKOUTSELR::SELECTS_THE_RTC_OSCI,
i => CLKOUTSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `SELECTS_THE_CPU_CLOC`"]
#[inline]
pub fn is_selects_the_cpu_cloc(&self) -> bool {
*self == CLKOUTSELR::SELECTS_THE_CPU_CLOC
}
#[doc = "Checks if the value of the field is `SELECTS_THE_MAIN_OSC`"]
#[inline]
pub fn is_selects_the_main_osc(&self) -> bool {
*self == CLKOUTSELR::SELECTS_THE_MAIN_OSC
}
#[doc = "Checks if the value of the field is `SELECTS_THE_INTERNAL`"]
#[inline]
pub fn is_selects_the_internal(&self) -> bool {
*self == CLKOUTSELR::SELECTS_THE_INTERNAL
}
#[doc = "Checks if the value of the field is `SELECTS_THE_USB_CLOC`"]
#[inline]
pub fn is_selects_the_usb_cloc(&self) -> bool {
*self == CLKOUTSELR::SELECTS_THE_USB_CLOC
}
#[doc = "Checks if the value of the field is `SELECTS_THE_RTC_OSCI`"]
#[inline]
pub fn is_selects_the_rtc_osci(&self) -> bool {
*self == CLKOUTSELR::SELECTS_THE_RTC_OSCI
}
}
#[doc = r" Value of the field"]
pub struct CLKOUTDIVR {
bits: u8,
}
impl CLKOUTDIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct CLKOUT_ENR {
bits: bool,
}
impl CLKOUT_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CLKOUT_ACTR {
bits: bool,
}
impl CLKOUT_ACTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `CLKOUTSEL`"]
pub enum CLKOUTSELW {
#[doc = "Selects the CPU clock as the CLKOUT source."]
SELECTS_THE_CPU_CLOC,
#[doc = "Selects the main oscillator as the CLKOUT source."]
SELECTS_THE_MAIN_OSC,
#[doc = "Selects the Internal RC oscillator as the CLKOUT source."]
SELECTS_THE_INTERNAL,
#[doc = "Selects the USB clock as the CLKOUT source."]
SELECTS_THE_USB_CLOC,
#[doc = "Selects the RTC oscillator as the CLKOUT source."]
SELECTS_THE_RTC_OSCI,
}
impl CLKOUTSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CLKOUTSELW::SELECTS_THE_CPU_CLOC => 0,
CLKOUTSELW::SELECTS_THE_MAIN_OSC => 1,
CLKOUTSELW::SELECTS_THE_INTERNAL => 2,
CLKOUTSELW::SELECTS_THE_USB_CLOC => 3,
CLKOUTSELW::SELECTS_THE_RTC_OSCI => 4,
}
}
}
#[doc = r" Proxy"]
pub struct _CLKOUTSELW<'a> {
w: &'a mut W,
}
impl<'a> _CLKOUTSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLKOUTSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Selects the CPU clock as the CLKOUT source."]
#[inline]
pub fn selects_the_cpu_cloc(self) -> &'a mut W {
self.variant(CLKOUTSELW::SELECTS_THE_CPU_CLOC)
}
#[doc = "Selects the main oscillator as the CLKOUT source."]
#[inline]
pub fn selects_the_main_osc(self) -> &'a mut W {
self.variant(CLKOUTSELW::SELECTS_THE_MAIN_OSC)
}
#[doc = "Selects the Internal RC oscillator as the CLKOUT source."]
#[inline]
pub fn selects_the_internal(self) -> &'a mut W {
self.variant(CLKOUTSELW::SELECTS_THE_INTERNAL)
}
#[doc = "Selects the USB clock as the CLKOUT source."]
#[inline]
pub fn selects_the_usb_cloc(self) -> &'a mut W {
self.variant(CLKOUTSELW::SELECTS_THE_USB_CLOC)
}
#[doc = "Selects the RTC oscillator as the CLKOUT source."]
#[inline]
pub fn selects_the_rtc_osci(self) -> &'a mut W {
self.variant(CLKOUTSELW::SELECTS_THE_RTC_OSCI)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLKOUTDIVW<'a> {
w: &'a mut W,
}
impl<'a> _CLKOUTDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLKOUT_ENW<'a> {
w: &'a mut W,
}
impl<'a> _CLKOUT_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLKOUT_ACTW<'a> {
w: &'a mut W,
}
impl<'a> _CLKOUT_ACTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Selects the clock source for the CLKOUT function. Other values are reserved. Do not use."]
#[inline]
pub fn clkoutsel(&self) -> CLKOUTSELR {
CLKOUTSELR::_from({
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:7 - Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16."]
#[inline]
pub fn clkoutdiv(&self) -> CLKOUTDIVR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLKOUTDIVR { bits }
}
#[doc = "Bit 8 - CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT."]
#[inline]
pub fn clkout_en(&self) -> CLKOUT_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CLKOUT_ENR { bits }
}
#[doc = "Bit 9 - CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped."]
#[inline]
pub fn clkout_act(&self) -> CLKOUT_ACTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CLKOUT_ACTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Selects the clock source for the CLKOUT function. Other values are reserved. Do not use."]
#[inline]
pub fn clkoutsel(&mut self) -> _CLKOUTSELW {
_CLKOUTSELW { w: self }
}
#[doc = "Bits 4:7 - Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16."]
#[inline]
pub fn clkoutdiv(&mut self) -> _CLKOUTDIVW {
_CLKOUTDIVW { w: self }
}
#[doc = "Bit 8 - CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT."]
#[inline]
pub fn clkout_en(&mut self) -> _CLKOUT_ENW {
_CLKOUT_ENW { w: self }
}
#[doc = "Bit 9 - CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped."]
#[inline]
pub fn clkout_act(&mut self) -> _CLKOUT_ACTW {
_CLKOUT_ACTW { w: self }
}
}
}
}
#[doc = "Ethernet"]
pub struct EMAC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for EMAC {}
impl EMAC {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const emac::RegisterBlock {
0x5000_0000 as *const _
}
}
impl Deref for EMAC {
type Target = emac::RegisterBlock;
fn deref(&self) -> &emac::RegisterBlock {
unsafe { &*EMAC::ptr() }
}
}
#[doc = "Ethernet"]
pub mod emac {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - MAC configuration register 1."]
pub mac1: MAC1,
#[doc = "0x04 - MAC configuration register 2."]
pub mac2: MAC2,
#[doc = "0x08 - Back-to-Back Inter-Packet-Gap register."]
pub ipgt: IPGT,
#[doc = "0x0c - Non Back-to-Back Inter-Packet-Gap register."]
pub ipgr: IPGR,
#[doc = "0x10 - Collision window / Retry register."]
pub clrt: CLRT,
#[doc = "0x14 - Maximum Frame register."]
pub maxf: MAXF,
#[doc = "0x18 - PHY Support register."]
pub supp: SUPP,
#[doc = "0x1c - Test register."]
pub test: TEST,
#[doc = "0x20 - MII Mgmt Configuration register."]
pub mcfg: MCFG,
#[doc = "0x24 - MII Mgmt Command register."]
pub mcmd: MCMD,
#[doc = "0x28 - MII Mgmt Address register."]
pub madr: MADR,
#[doc = "0x2c - MII Mgmt Write Data register."]
pub mwtd: MWTD,
#[doc = "0x30 - MII Mgmt Read Data register."]
pub mrdd: MRDD,
#[doc = "0x34 - MII Mgmt Indicators register."]
pub mind: MIND,
_reserved14: [u8; 8usize],
#[doc = "0x40 - Station Address 0 register."]
pub sa0: SA0,
#[doc = "0x44 - Station Address 1 register."]
pub sa1: SA1,
#[doc = "0x48 - Station Address 2 register."]
pub sa2: SA2,
_reserved17: [u8; 180usize],
#[doc = "0x100 - Command register."]
pub command: COMMAND,
#[doc = "0x104 - Status register."]
pub status: STATUS,
#[doc = "0x108 - Receive descriptor base address register."]
pub rxdescriptor: RXDESCRIPTOR,
#[doc = "0x10c - Receive status base address register."]
pub rxstatus: RXSTATUS,
#[doc = "0x110 - Receive number of descriptors register."]
pub rxdescriptornumber: RXDESCRIPTORNUMBER,
#[doc = "0x114 - Receive produce index register."]
pub rxproduceindex: RXPRODUCEINDEX,
#[doc = "0x118 - Receive consume index register."]
pub rxconsumeindex: RXCONSUMEINDEX,
#[doc = "0x11c - Transmit descriptor base address register."]
pub txdescriptor: TXDESCRIPTOR,
#[doc = "0x120 - Transmit status base address register."]
pub txstatus: TXSTATUS,
#[doc = "0x124 - Transmit number of descriptors register."]
pub txdescriptornumber: TXDESCRIPTORNUMBER,
#[doc = "0x128 - Transmit produce index register."]
pub txproduceindex: TXPRODUCEINDEX,
#[doc = "0x12c - Transmit consume index register."]
pub txconsumeindex: TXCONSUMEINDEX,
_reserved29: [u8; 40usize],
#[doc = "0x158 - Transmit status vector 0 register."]
pub tsv0: TSV0,
#[doc = "0x15c - Transmit status vector 1 register."]
pub tsv1: TSV1,
#[doc = "0x160 - Receive status vector register."]
pub rsv: RSV,
_reserved32: [u8; 12usize],
#[doc = "0x170 - Flow control counter register."]
pub flowcontrolcounter: FLOWCONTROLCOUNTER,
#[doc = "0x174 - Flow control status register."]
pub flowcontrolstatus: FLOWCONTROLSTATUS,
_reserved34: [u8; 136usize],
#[doc = "0x200 - Receive filter control register."]
pub rxfilterctrl: RXFILTERCTRL,
#[doc = "0x204 - Receive filter WoL status register."]
pub rxfilterwolstatus: RXFILTERWOLSTATUS,
#[doc = "0x208 - Receive filter WoL clear register."]
pub rxfilterwolclear: RXFILTERWOLCLEAR,
_reserved37: [u8; 4usize],
#[doc = "0x210 - Hash filter table LSBs register."]
pub hashfilterl: HASHFILTERL,
#[doc = "0x214 - Hash filter table MSBs register."]
pub hashfilterh: HASHFILTERH,
_reserved39: [u8; 3528usize],
#[doc = "0xfe0 - Interrupt status register."]
pub intstatus: INTSTATUS,
#[doc = "0xfe4 - Interrupt enable register."]
pub intenable: INTENABLE,
#[doc = "0xfe8 - Interrupt clear register."]
pub intclear: INTCLEAR,
#[doc = "0xfec - Interrupt set register."]
pub intset: INTSET,
_reserved43: [u8; 4usize],
#[doc = "0xff4 - Power-down register."]
pub powerdown: POWERDOWN,
}
#[doc = "MAC configuration register 1."]
pub struct MAC1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MAC configuration register 1."]
pub mod mac1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MAC1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXENABLER {
bits: bool,
}
impl RXENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PARFR {
bits: bool,
}
impl PARFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXFLOWCTRLR {
bits: bool,
}
impl RXFLOWCTRLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXFLOWCTRLR {
bits: bool,
}
impl TXFLOWCTRLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LOOPBACKR {
bits: bool,
}
impl LOOPBACKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RESETTXR {
bits: bool,
}
impl RESETTXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RESETMCSTXR {
bits: bool,
}
impl RESETMCSTXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RESETRXR {
bits: bool,
}
impl RESETRXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RESETMCSRXR {
bits: bool,
}
impl RESETMCSRXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SIMRESETR {
bits: bool,
}
impl SIMRESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTRESETR {
bits: bool,
}
impl SOFTRESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RXENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _RXENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PARFW<'a> {
w: &'a mut W,
}
impl<'a> _PARFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXFLOWCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _RXFLOWCTRLW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXFLOWCTRLW<'a> {
w: &'a mut W,
}
impl<'a> _TXFLOWCTRLW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _LOOPBACKW<'a> {
w: &'a mut W,
}
impl<'a> _LOOPBACKW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETTXW<'a> {
w: &'a mut W,
}
impl<'a> _RESETTXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETMCSTXW<'a> {
w: &'a mut W,
}
impl<'a> _RESETMCSTXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETRXW<'a> {
w: &'a mut W,
}
impl<'a> _RESETRXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETMCSRXW<'a> {
w: &'a mut W,
}
impl<'a> _RESETMCSRXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SIMRESETW<'a> {
w: &'a mut W,
}
impl<'a> _SIMRESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTRESETW<'a> {
w: &'a mut W,
}
impl<'a> _SOFTRESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream."]
#[inline]
pub fn rxenable(&self) -> RXENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXENABLER { bits }
}
#[doc = "Bit 1 - PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames."]
#[inline]
pub fn parf(&self) -> PARFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PARFR { bits }
}
#[doc = "Bit 2 - RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored."]
#[inline]
pub fn rxflowctrl(&self) -> RXFLOWCTRLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXFLOWCTRLR { bits }
}
#[doc = "Bit 3 - TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked."]
#[inline]
pub fn txflowctrl(&self) -> TXFLOWCTRLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXFLOWCTRLR { bits }
}
#[doc = "Bit 4 - Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation."]
#[inline]
pub fn loopback(&self) -> LOOPBACKR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LOOPBACKR { bits }
}
#[doc = "Bit 8 - Setting this bit will put the Transmit Function logic in reset."]
#[inline]
pub fn resettx(&self) -> RESETTXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETTXR { bits }
}
#[doc = "Bit 9 - Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control."]
#[inline]
pub fn resetmcstx(&self) -> RESETMCSTXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETMCSTXR { bits }
}
#[doc = "Bit 10 - Setting this bit will put the Ethernet receive logic in reset."]
#[inline]
pub fn resetrx(&self) -> RESETRXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETRXR { bits }
}
#[doc = "Bit 11 - Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control."]
#[inline]
pub fn resetmcsrx(&self) -> RESETMCSRXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETMCSRXR { bits }
}
#[doc = "Bit 14 - SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function."]
#[inline]
pub fn simreset(&self) -> SIMRESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SIMRESETR { bits }
}
#[doc = "Bit 15 - SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface."]
#[inline]
pub fn softreset(&self) -> SOFTRESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTRESETR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x8000 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream."]
#[inline]
pub fn rxenable(&mut self) -> _RXENABLEW {
_RXENABLEW { w: self }
}
#[doc = "Bit 1 - PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames."]
#[inline]
pub fn parf(&mut self) -> _PARFW {
_PARFW { w: self }
}
#[doc = "Bit 2 - RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored."]
#[inline]
pub fn rxflowctrl(&mut self) -> _RXFLOWCTRLW {
_RXFLOWCTRLW { w: self }
}
#[doc = "Bit 3 - TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked."]
#[inline]
pub fn txflowctrl(&mut self) -> _TXFLOWCTRLW {
_TXFLOWCTRLW { w: self }
}
#[doc = "Bit 4 - Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation."]
#[inline]
pub fn loopback(&mut self) -> _LOOPBACKW {
_LOOPBACKW { w: self }
}
#[doc = "Bit 8 - Setting this bit will put the Transmit Function logic in reset."]
#[inline]
pub fn resettx(&mut self) -> _RESETTXW {
_RESETTXW { w: self }
}
#[doc = "Bit 9 - Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control."]
#[inline]
pub fn resetmcstx(&mut self) -> _RESETMCSTXW {
_RESETMCSTXW { w: self }
}
#[doc = "Bit 10 - Setting this bit will put the Ethernet receive logic in reset."]
#[inline]
pub fn resetrx(&mut self) -> _RESETRXW {
_RESETRXW { w: self }
}
#[doc = "Bit 11 - Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control."]
#[inline]
pub fn resetmcsrx(&mut self) -> _RESETMCSRXW {
_RESETMCSRXW { w: self }
}
#[doc = "Bit 14 - SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function."]
#[inline]
pub fn simreset(&mut self) -> _SIMRESETW {
_SIMRESETW { w: self }
}
#[doc = "Bit 15 - SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface."]
#[inline]
pub fn softreset(&mut self) -> _SOFTRESETW {
_SOFTRESETW { w: self }
}
}
}
#[doc = "MAC configuration register 2."]
pub struct MAC2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MAC configuration register 2."]
pub mod mac2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MAC2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FULLDUPLEXR {
bits: bool,
}
impl FULLDUPLEXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct FLCR {
bits: bool,
}
impl FLCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct HFENR {
bits: bool,
}
impl HFENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DELAYEDCRCR {
bits: bool,
}
impl DELAYEDCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CRCENR {
bits: bool,
}
impl CRCENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PADCRCENR {
bits: bool,
}
impl PADCRCENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct VLANPADENR {
bits: bool,
}
impl VLANPADENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AUTODETPADENR {
bits: bool,
}
impl AUTODETPADENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PPENFR {
bits: bool,
}
impl PPENFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LPENFR {
bits: bool,
}
impl LPENFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct NOBACKOFFR {
bits: bool,
}
impl NOBACKOFFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BP_NOBACKOFFR {
bits: bool,
}
impl BP_NOBACKOFFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EXCESSDEFERR {
bits: bool,
}
impl EXCESSDEFERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _FULLDUPLEXW<'a> {
w: &'a mut W,
}
impl<'a> _FULLDUPLEXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FLCW<'a> {
w: &'a mut W,
}
impl<'a> _FLCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HFENW<'a> {
w: &'a mut W,
}
impl<'a> _HFENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DELAYEDCRCW<'a> {
w: &'a mut W,
}
impl<'a> _DELAYEDCRCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CRCENW<'a> {
w: &'a mut W,
}
impl<'a> _CRCENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PADCRCENW<'a> {
w: &'a mut W,
}
impl<'a> _PADCRCENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _VLANPADENW<'a> {
w: &'a mut W,
}
impl<'a> _VLANPADENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AUTODETPADENW<'a> {
w: &'a mut W,
}
impl<'a> _AUTODETPADENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PPENFW<'a> {
w: &'a mut W,
}
impl<'a> _PPENFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _LPENFW<'a> {
w: &'a mut W,
}
impl<'a> _LPENFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _NOBACKOFFW<'a> {
w: &'a mut W,
}
impl<'a> _NOBACKOFFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BP_NOBACKOFFW<'a> {
w: &'a mut W,
}
impl<'a> _BP_NOBACKOFFW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EXCESSDEFERW<'a> {
w: &'a mut W,
}
impl<'a> _EXCESSDEFERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode."]
#[inline]
pub fn fullduplex(&self) -> FULLDUPLEXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FULLDUPLEXR { bits }
}
#[doc = "Bit 1 - FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame."]
#[inline]
pub fn flc(&self) -> FLCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FLCR { bits }
}
#[doc = "Bit 2 - HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received."]
#[inline]
pub fn hfen(&self) -> HFENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
HFENR { bits }
}
#[doc = "Bit 3 - DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header."]
#[inline]
pub fn delayedcrc(&self) -> DELAYEDCRCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DELAYEDCRCR { bits }
}
#[doc = "Bit 4 - CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC."]
#[inline]
pub fn crcen(&self) -> CRCENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CRCENR { bits }
}
#[doc = "Bit 5 - PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function."]
#[inline]
pub fn padcrcen(&self) -> PADCRCENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PADCRCENR { bits }
}
#[doc = "Bit 6 - VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared."]
#[inline]
pub fn vlanpaden(&self) -> VLANPADENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
VLANPADENR { bits }
}
#[doc = "Bit 7 - AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared."]
#[inline]
pub fn autodetpaden(&self) -> AUTODETPADENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AUTODETPADENR { bits }
}
#[doc = "Bit 8 - PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed."]
#[inline]
pub fn ppenf(&self) -> PPENFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PPENFR { bits }
}
#[doc = "Bit 9 - LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard."]
#[inline]
pub fn lpenf(&self) -> LPENFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LPENFR { bits }
}
#[doc = "Bit 12 - When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard."]
#[inline]
pub fn nobackoff(&self) -> NOBACKOFFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
NOBACKOFFR { bits }
}
#[doc = "Bit 13 - BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent."]
#[inline]
pub fn bp_nobackoff(&self) -> BP_NOBACKOFFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BP_NOBACKOFFR { bits }
}
#[doc = "Bit 14 - When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached."]
#[inline]
pub fn excessdefer(&self) -> EXCESSDEFERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EXCESSDEFERR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode."]
#[inline]
pub fn fullduplex(&mut self) -> _FULLDUPLEXW {
_FULLDUPLEXW { w: self }
}
#[doc = "Bit 1 - FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame."]
#[inline]
pub fn flc(&mut self) -> _FLCW {
_FLCW { w: self }
}
#[doc = "Bit 2 - HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received."]
#[inline]
pub fn hfen(&mut self) -> _HFENW {
_HFENW { w: self }
}
#[doc = "Bit 3 - DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header."]
#[inline]
pub fn delayedcrc(&mut self) -> _DELAYEDCRCW {
_DELAYEDCRCW { w: self }
}
#[doc = "Bit 4 - CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC."]
#[inline]
pub fn crcen(&mut self) -> _CRCENW {
_CRCENW { w: self }
}
#[doc = "Bit 5 - PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function."]
#[inline]
pub fn padcrcen(&mut self) -> _PADCRCENW {
_PADCRCENW { w: self }
}
#[doc = "Bit 6 - VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared."]
#[inline]
pub fn vlanpaden(&mut self) -> _VLANPADENW {
_VLANPADENW { w: self }
}
#[doc = "Bit 7 - AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared."]
#[inline]
pub fn autodetpaden(&mut self) -> _AUTODETPADENW {
_AUTODETPADENW { w: self }
}
#[doc = "Bit 8 - PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed."]
#[inline]
pub fn ppenf(&mut self) -> _PPENFW {
_PPENFW { w: self }
}
#[doc = "Bit 9 - LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard."]
#[inline]
pub fn lpenf(&mut self) -> _LPENFW {
_LPENFW { w: self }
}
#[doc = "Bit 12 - When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard."]
#[inline]
pub fn nobackoff(&mut self) -> _NOBACKOFFW {
_NOBACKOFFW { w: self }
}
#[doc = "Bit 13 - BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent."]
#[inline]
pub fn bp_nobackoff(&mut self) -> _BP_NOBACKOFFW {
_BP_NOBACKOFFW { w: self }
}
#[doc = "Bit 14 - When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached."]
#[inline]
pub fn excessdefer(&mut self) -> _EXCESSDEFERW {
_EXCESSDEFERW { w: self }
}
}
}
#[doc = "Back-to-Back Inter-Packet-Gap register."]
pub struct IPGT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Back-to-Back Inter-Packet-Gap register."]
pub mod ipgt {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IPGT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct BTOBINTEGAPR {
bits: u8,
}
impl BTOBINTEGAPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BTOBINTEGAPW<'a> {
w: &'a mut W,
}
impl<'a> _BTOBINTEGAPW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)."]
#[inline]
pub fn btobintegap(&self) -> BTOBINTEGAPR {
let bits = {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BTOBINTEGAPR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)."]
#[inline]
pub fn btobintegap(&mut self) -> _BTOBINTEGAPW {
_BTOBINTEGAPW { w: self }
}
}
}
#[doc = "Non Back-to-Back Inter-Packet-Gap register."]
pub struct IPGR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Non Back-to-Back Inter-Packet-Gap register."]
pub mod ipgr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::IPGR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct NBTOBINTEGAP2R {
bits: u8,
}
impl NBTOBINTEGAP2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct NBTOBINTEGAP1R {
bits: u8,
}
impl NBTOBINTEGAP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _NBTOBINTEGAP2W<'a> {
w: &'a mut W,
}
impl<'a> _NBTOBINTEGAP2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _NBTOBINTEGAP1W<'a> {
w: &'a mut W,
}
impl<'a> _NBTOBINTEGAP1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)."]
#[inline]
pub fn nbtobintegap2(&self) -> NBTOBINTEGAP2R {
let bits = {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
NBTOBINTEGAP2R { bits }
}
#[doc = "Bits 8:14 - NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)"]
#[inline]
pub fn nbtobintegap1(&self) -> NBTOBINTEGAP1R {
let bits = {
const MASK: u8 = 0x7f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
NBTOBINTEGAP1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)."]
#[inline]
pub fn nbtobintegap2(&mut self) -> _NBTOBINTEGAP2W {
_NBTOBINTEGAP2W { w: self }
}
#[doc = "Bits 8:14 - NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)"]
#[inline]
pub fn nbtobintegap1(&mut self) -> _NBTOBINTEGAP1W {
_NBTOBINTEGAP1W { w: self }
}
}
}
#[doc = "Collision window / Retry register."]
pub struct CLRT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Collision window / Retry register."]
pub mod clrt {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLRT {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RETRANSMAXR {
bits: u8,
}
impl RETRANSMAXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct COLLWINR {
bits: u8,
}
impl COLLWINR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RETRANSMAXW<'a> {
w: &'a mut W,
}
impl<'a> _RETRANSMAXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _COLLWINW<'a> {
w: &'a mut W,
}
impl<'a> _COLLWINW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5."]
#[inline]
pub fn retransmax(&self) -> RETRANSMAXR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RETRANSMAXR { bits }
}
#[doc = "Bits 8:13 - COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD."]
#[inline]
pub fn collwin(&self) -> COLLWINR {
let bits = {
const MASK: u8 = 0x3f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
COLLWINR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x370f }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5."]
#[inline]
pub fn retransmax(&mut self) -> _RETRANSMAXW {
_RETRANSMAXW { w: self }
}
#[doc = "Bits 8:13 - COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD."]
#[inline]
pub fn collwin(&mut self) -> _COLLWINW {
_COLLWINW { w: self }
}
}
}
#[doc = "Maximum Frame register."]
pub struct MAXF {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Maximum Frame register."]
pub mod maxf {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MAXF {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MAXFLENR {
bits: u16,
}
impl MAXFLENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MAXFLENW<'a> {
w: &'a mut W,
}
impl<'a> _MAXFLENW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field."]
#[inline]
pub fn maxflen(&self) -> MAXFLENR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MAXFLENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x0600 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field."]
#[inline]
pub fn maxflen(&mut self) -> _MAXFLENW {
_MAXFLENW { w: self }
}
}
}
#[doc = "PHY Support register."]
pub struct SUPP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "PHY Support register."]
pub mod supp {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SUPP {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SPEEDR {
bits: bool,
}
impl SPEEDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SPEEDW<'a> {
w: &'a mut W,
}
impl<'a> _SPEEDW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 8 - This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected."]
#[inline]
pub fn speed(&self) -> SPEEDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SPEEDR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 8 - This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected."]
#[inline]
pub fn speed(&mut self) -> _SPEEDW {
_SPEEDW { w: self }
}
}
}
#[doc = "Test register."]
pub struct TEST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Test register."]
pub mod test {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TEST {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SCPQR {
bits: bool,
}
impl SCPQR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TESTPAUSER {
bits: bool,
}
impl TESTPAUSER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TESTBPR {
bits: bool,
}
impl TESTBPR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SCPQW<'a> {
w: &'a mut W,
}
impl<'a> _SCPQW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TESTPAUSEW<'a> {
w: &'a mut W,
}
impl<'a> _TESTPAUSEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TESTBPW<'a> {
w: &'a mut W,
}
impl<'a> _TESTBPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time."]
#[inline]
pub fn scpq(&self) -> SCPQR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SCPQR { bits }
}
#[doc = "Bit 1 - This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received."]
#[inline]
pub fn testpause(&self) -> TESTPAUSER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TESTPAUSER { bits }
}
#[doc = "Bit 2 - TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure."]
#[inline]
pub fn testbp(&self) -> TESTBPR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TESTBPR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time."]
#[inline]
pub fn scpq(&mut self) -> _SCPQW {
_SCPQW { w: self }
}
#[doc = "Bit 1 - This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received."]
#[inline]
pub fn testpause(&mut self) -> _TESTPAUSEW {
_TESTPAUSEW { w: self }
}
#[doc = "Bit 2 - TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure."]
#[inline]
pub fn testbp(&mut self) -> _TESTBPW {
_TESTBPW { w: self }
}
}
}
#[doc = "MII Mgmt Configuration register."]
pub struct MCFG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MII Mgmt Configuration register."]
pub mod mcfg {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SCANINCR {
bits: bool,
}
impl SCANINCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SUPPPREAMBLER {
bits: bool,
}
impl SUPPPREAMBLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CLOCKSELR {
bits: u8,
}
impl CLOCKSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct RESETMIIMGMTR {
bits: bool,
}
impl RESETMIIMGMTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SCANINCW<'a> {
w: &'a mut W,
}
impl<'a> _SCANINCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SUPPPREAMBLEW<'a> {
w: &'a mut W,
}
impl<'a> _SUPPPREAMBLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLOCKSELW<'a> {
w: &'a mut W,
}
impl<'a> _CLOCKSELW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RESETMIIMGMTW<'a> {
w: &'a mut W,
}
impl<'a> _RESETMIIMGMTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS\\[4:0\\]. Clear this bit to allow continuous reads of the same PHY."]
#[inline]
pub fn scaninc(&self) -> SCANINCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SCANINCR { bits }
}
#[doc = "Bit 1 - SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble."]
#[inline]
pub fn supppreamble(&self) -> SUPPPREAMBLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SUPPPREAMBLER { bits }
}
#[doc = "Bits 2:5 - CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field."]
#[inline]
pub fn clocksel(&self) -> CLOCKSELR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLOCKSELR { bits }
}
#[doc = "Bit 15 - RESET MII MGMT. This bit resets the MII Management hardware."]
#[inline]
pub fn resetmiimgmt(&self) -> RESETMIIMGMTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RESETMIIMGMTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS\\[4:0\\]. Clear this bit to allow continuous reads of the same PHY."]
#[inline]
pub fn scaninc(&mut self) -> _SCANINCW {
_SCANINCW { w: self }
}
#[doc = "Bit 1 - SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble."]
#[inline]
pub fn supppreamble(&mut self) -> _SUPPPREAMBLEW {
_SUPPPREAMBLEW { w: self }
}
#[doc = "Bits 2:5 - CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field."]
#[inline]
pub fn clocksel(&mut self) -> _CLOCKSELW {
_CLOCKSELW { w: self }
}
#[doc = "Bit 15 - RESET MII MGMT. This bit resets the MII Management hardware."]
#[inline]
pub fn resetmiimgmt(&mut self) -> _RESETMIIMGMTW {
_RESETMIIMGMTW { w: self }
}
}
}
#[doc = "MII Mgmt Command register."]
pub struct MCMD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MII Mgmt Command register."]
pub mod mcmd {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MCMD {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct READR {
bits: bool,
}
impl READR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SCANR {
bits: bool,
}
impl SCANR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _READW<'a> {
w: &'a mut W,
}
impl<'a> _READW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SCANW<'a> {
w: &'a mut W,
}
impl<'a> _SCANW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)."]
#[inline]
pub fn read(&self) -> READR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
READR { bits }
}
#[doc = "Bit 1 - This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example."]
#[inline]
pub fn scan(&self) -> SCANR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SCANR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)."]
#[inline]
pub fn read(&mut self) -> _READW {
_READW { w: self }
}
#[doc = "Bit 1 - This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example."]
#[inline]
pub fn scan(&mut self) -> _SCANW {
_SCANW { w: self }
}
}
}
#[doc = "MII Mgmt Address register."]
pub struct MADR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MII Mgmt Address register."]
pub mod madr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MADR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct REGADDRR {
bits: u8,
}
impl REGADDRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PHYADDRR {
bits: u8,
}
impl PHYADDRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _REGADDRW<'a> {
w: &'a mut W,
}
impl<'a> _REGADDRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PHYADDRW<'a> {
w: &'a mut W,
}
impl<'a> _PHYADDRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed."]
#[inline]
pub fn regaddr(&self) -> REGADDRR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
REGADDRR { bits }
}
#[doc = "Bits 8:12 - PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)."]
#[inline]
pub fn phyaddr(&self) -> PHYADDRR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PHYADDRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed."]
#[inline]
pub fn regaddr(&mut self) -> _REGADDRW {
_REGADDRW { w: self }
}
#[doc = "Bits 8:12 - PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)."]
#[inline]
pub fn phyaddr(&mut self) -> _PHYADDRW {
_PHYADDRW { w: self }
}
}
}
#[doc = "MII Mgmt Write Data register."]
pub struct MWTD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MII Mgmt Write Data register."]
pub mod mwtd {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MWTD {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _WRITEDATAW<'a> {
w: &'a mut W,
}
impl<'a> _WRITEDATAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)."]
#[inline]
pub fn writedata(&mut self) -> _WRITEDATAW {
_WRITEDATAW { w: self }
}
}
}
#[doc = "MII Mgmt Read Data register."]
pub struct MRDD {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MII Mgmt Read Data register."]
pub mod mrdd {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::MRDD {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct READDATAR {
bits: u16,
}
impl READDATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location."]
#[inline]
pub fn readdata(&self) -> READDATAR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
READDATAR { bits }
}
}
}
#[doc = "MII Mgmt Indicators register."]
pub struct MIND {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "MII Mgmt Indicators register."]
pub mod mind {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::MIND {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct BUSYR {
bits: bool,
}
impl BUSYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SCANNINGR {
bits: bool,
}
impl SCANNINGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct NOTVALIDR {
bits: bool,
}
impl NOTVALIDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MIILINKFAILR {
bits: bool,
}
impl MIILINKFAILR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle."]
#[inline]
pub fn busy(&self) -> BUSYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BUSYR { bits }
}
#[doc = "Bit 1 - When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress."]
#[inline]
pub fn scanning(&self) -> SCANNINGR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SCANNINGR { bits }
}
#[doc = "Bit 2 - When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid."]
#[inline]
pub fn notvalid(&self) -> NOTVALIDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
NOTVALIDR { bits }
}
#[doc = "Bit 3 - When 1 is returned - indicates that an MII Mgmt link fail has occurred."]
#[inline]
pub fn miilinkfail(&self) -> MIILINKFAILR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MIILINKFAILR { bits }
}
}
}
#[doc = "Station Address 0 register."]
pub struct SA0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Station Address 0 register."]
pub mod sa0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SA0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SADDR2R {
bits: u8,
}
impl SADDR2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SADDR1R {
bits: u8,
}
impl SADDR1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SADDR2W<'a> {
w: &'a mut W,
}
impl<'a> _SADDR2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SADDR1W<'a> {
w: &'a mut W,
}
impl<'a> _SADDR1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - STATION ADDRESS, 2nd octet. This field holds the second octet of the station address."]
#[inline]
pub fn saddr2(&self) -> SADDR2R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SADDR2R { bits }
}
#[doc = "Bits 8:15 - STATION ADDRESS, 1st octet. This field holds the first octet of the station address."]
#[inline]
pub fn saddr1(&self) -> SADDR1R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SADDR1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - STATION ADDRESS, 2nd octet. This field holds the second octet of the station address."]
#[inline]
pub fn saddr2(&mut self) -> _SADDR2W {
_SADDR2W { w: self }
}
#[doc = "Bits 8:15 - STATION ADDRESS, 1st octet. This field holds the first octet of the station address."]
#[inline]
pub fn saddr1(&mut self) -> _SADDR1W {
_SADDR1W { w: self }
}
}
}
#[doc = "Station Address 1 register."]
pub struct SA1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Station Address 1 register."]
pub mod sa1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SA1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SADDR4R {
bits: u8,
}
impl SADDR4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SADDR3R {
bits: u8,
}
impl SADDR3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SADDR4W<'a> {
w: &'a mut W,
}
impl<'a> _SADDR4W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SADDR3W<'a> {
w: &'a mut W,
}
impl<'a> _SADDR3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address."]
#[inline]
pub fn saddr4(&self) -> SADDR4R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SADDR4R { bits }
}
#[doc = "Bits 8:15 - STATION ADDRESS, 3rd octet. This field holds the third octet of the station address."]
#[inline]
pub fn saddr3(&self) -> SADDR3R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SADDR3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address."]
#[inline]
pub fn saddr4(&mut self) -> _SADDR4W {
_SADDR4W { w: self }
}
#[doc = "Bits 8:15 - STATION ADDRESS, 3rd octet. This field holds the third octet of the station address."]
#[inline]
pub fn saddr3(&mut self) -> _SADDR3W {
_SADDR3W { w: self }
}
}
}
#[doc = "Station Address 2 register."]
pub struct SA2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Station Address 2 register."]
pub mod sa2 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SA2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SADDR6R {
bits: u8,
}
impl SADDR6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SADDR5R {
bits: u8,
}
impl SADDR5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SADDR6W<'a> {
w: &'a mut W,
}
impl<'a> _SADDR6W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SADDR5W<'a> {
w: &'a mut W,
}
impl<'a> _SADDR5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address."]
#[inline]
pub fn saddr6(&self) -> SADDR6R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SADDR6R { bits }
}
#[doc = "Bits 8:15 - STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address."]
#[inline]
pub fn saddr5(&self) -> SADDR5R {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SADDR5R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address."]
#[inline]
pub fn saddr6(&mut self) -> _SADDR6W {
_SADDR6W { w: self }
}
#[doc = "Bits 8:15 - STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address."]
#[inline]
pub fn saddr5(&mut self) -> _SADDR5W {
_SADDR5W { w: self }
}
}
}
#[doc = "Command register."]
pub struct COMMAND {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Command register."]
pub mod command {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::COMMAND {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXENABLER {
bits: bool,
}
impl RXENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXENABLER {
bits: bool,
}
impl TXENABLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REGRESETR {
bits: bool,
}
impl REGRESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXRESETR {
bits: bool,
}
impl TXRESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXRESETR {
bits: bool,
}
impl RXRESETR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PASSRUNTFRAMER {
bits: bool,
}
impl PASSRUNTFRAMER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PASSRXFILTERR {
bits: bool,
}
impl PASSRXFILTERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXFLOWCONTROLR {
bits: bool,
}
impl TXFLOWCONTROLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RMIIR {
bits: bool,
}
impl RMIIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct FULLDUPLEXR {
bits: bool,
}
impl FULLDUPLEXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RXENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _RXENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXENABLEW<'a> {
w: &'a mut W,
}
impl<'a> _TXENABLEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REGRESETW<'a> {
w: &'a mut W,
}
impl<'a> _REGRESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXRESETW<'a> {
w: &'a mut W,
}
impl<'a> _TXRESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXRESETW<'a> {
w: &'a mut W,
}
impl<'a> _RXRESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PASSRUNTFRAMEW<'a> {
w: &'a mut W,
}
impl<'a> _PASSRUNTFRAMEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PASSRXFILTERW<'a> {
w: &'a mut W,
}
impl<'a> _PASSRXFILTERW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXFLOWCONTROLW<'a> {
w: &'a mut W,
}
impl<'a> _TXFLOWCONTROLW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RMIIW<'a> {
w: &'a mut W,
}
impl<'a> _RMIIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FULLDUPLEXW<'a> {
w: &'a mut W,
}
impl<'a> _FULLDUPLEXW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable receive."]
#[inline]
pub fn rxenable(&self) -> RXENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXENABLER { bits }
}
#[doc = "Bit 1 - Enable transmit."]
#[inline]
pub fn txenable(&self) -> TXENABLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXENABLER { bits }
}
#[doc = "Bit 3 - When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately."]
#[inline]
pub fn regreset(&self) -> REGRESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REGRESETR { bits }
}
#[doc = "Bit 4 - When a 1 is written, the transmit datapath is reset."]
#[inline]
pub fn txreset(&self) -> TXRESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXRESETR { bits }
}
#[doc = "Bit 5 - When a 1 is written, the receive datapath is reset."]
#[inline]
pub fn rxreset(&self) -> RXRESETR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXRESETR { bits }
}
#[doc = "Bit 6 - When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out."]
#[inline]
pub fn passruntframe(&self) -> PASSRUNTFRAMER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PASSRUNTFRAMER { bits }
}
#[doc = "Bit 7 - When set to 1 , disables receive filtering i.e. all frames received are written to memory."]
#[inline]
pub fn passrxfilter(&self) -> PASSRXFILTERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PASSRXFILTERR { bits }
}
#[doc = "Bit 8 - Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex."]
#[inline]
pub fn txflowcontrol(&self) -> TXFLOWCONTROLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXFLOWCONTROLR { bits }
}
#[doc = "Bit 9 - When set to 1 , RMII mode is selected; if 0, MII mode is selected."]
#[inline]
pub fn rmii(&self) -> RMIIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RMIIR { bits }
}
#[doc = "Bit 10 - When set to 1 , indicates full duplex operation."]
#[inline]
pub fn fullduplex(&self) -> FULLDUPLEXR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FULLDUPLEXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable receive."]
#[inline]
pub fn rxenable(&mut self) -> _RXENABLEW {
_RXENABLEW { w: self }
}
#[doc = "Bit 1 - Enable transmit."]
#[inline]
pub fn txenable(&mut self) -> _TXENABLEW {
_TXENABLEW { w: self }
}
#[doc = "Bit 3 - When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately."]
#[inline]
pub fn regreset(&mut self) -> _REGRESETW {
_REGRESETW { w: self }
}
#[doc = "Bit 4 - When a 1 is written, the transmit datapath is reset."]
#[inline]
pub fn txreset(&mut self) -> _TXRESETW {
_TXRESETW { w: self }
}
#[doc = "Bit 5 - When a 1 is written, the receive datapath is reset."]
#[inline]
pub fn rxreset(&mut self) -> _RXRESETW {
_RXRESETW { w: self }
}
#[doc = "Bit 6 - When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out."]
#[inline]
pub fn passruntframe(&mut self) -> _PASSRUNTFRAMEW {
_PASSRUNTFRAMEW { w: self }
}
#[doc = "Bit 7 - When set to 1 , disables receive filtering i.e. all frames received are written to memory."]
#[inline]
pub fn passrxfilter(&mut self) -> _PASSRXFILTERW {
_PASSRXFILTERW { w: self }
}
#[doc = "Bit 8 - Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex."]
#[inline]
pub fn txflowcontrol(&mut self) -> _TXFLOWCONTROLW {
_TXFLOWCONTROLW { w: self }
}
#[doc = "Bit 9 - When set to 1 , RMII mode is selected; if 0, MII mode is selected."]
#[inline]
pub fn rmii(&mut self) -> _RMIIW {
_RMIIW { w: self }
}
#[doc = "Bit 10 - When set to 1 , indicates full duplex operation."]
#[inline]
pub fn fullduplex(&mut self) -> _FULLDUPLEXW {
_FULLDUPLEXW { w: self }
}
}
}
#[doc = "Status register."]
pub struct STATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status register."]
pub mod status {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::STATUS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RXSTATUSR {
bits: bool,
}
impl RXSTATUSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXSTATUSR {
bits: bool,
}
impl TXSTATUSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - If 1, the receive channel is active. If 0, the receive channel is inactive."]
#[inline]
pub fn rxstatus(&self) -> RXSTATUSR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXSTATUSR { bits }
}
#[doc = "Bit 1 - If 1, the transmit channel is active. If 0, the transmit channel is inactive."]
#[inline]
pub fn txstatus(&self) -> TXSTATUSR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXSTATUSR { bits }
}
}
}
#[doc = "Receive descriptor base address register."]
pub struct RXDESCRIPTOR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive descriptor base address register."]
pub mod rxdescriptor {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXDESCRIPTOR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXDESCRIPTORR {
bits: u32,
}
impl RXDESCRIPTORR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RXDESCRIPTORW<'a> {
w: &'a mut W,
}
impl<'a> _RXDESCRIPTORW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:31 - MSBs of receive descriptor base address."]
#[inline]
pub fn rxdescriptor(&self) -> RXDESCRIPTORR {
let bits = {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u32
};
RXDESCRIPTORR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:31 - MSBs of receive descriptor base address."]
#[inline]
pub fn rxdescriptor(&mut self) -> _RXDESCRIPTORW {
_RXDESCRIPTORW { w: self }
}
}
}
#[doc = "Receive status base address register."]
pub struct RXSTATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive status base address register."]
pub mod rxstatus {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXSTATUS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXSTATUSR {
bits: u32,
}
impl RXSTATUSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RXSTATUSW<'a> {
w: &'a mut W,
}
impl<'a> _RXSTATUSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x1fff_ffff;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 3:31 - MSBs of receive status base address."]
#[inline]
pub fn rxstatus(&self) -> RXSTATUSR {
let bits = {
const MASK: u32 = 0x1fff_ffff;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) as u32
};
RXSTATUSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 3:31 - MSBs of receive status base address."]
#[inline]
pub fn rxstatus(&mut self) -> _RXSTATUSW {
_RXSTATUSW { w: self }
}
}
}
#[doc = "Receive number of descriptors register."]
pub struct RXDESCRIPTORNUMBER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive number of descriptors register."]
pub mod rxdescriptornumber {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXDESCRIPTORNUMBER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXDESCRIPTORNR {
bits: u16,
}
impl RXDESCRIPTORNR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RXDESCRIPTORNW<'a> {
w: &'a mut W,
}
impl<'a> _RXDESCRIPTORNW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded."]
#[inline]
pub fn rxdescriptorn(&self) -> RXDESCRIPTORNR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RXDESCRIPTORNR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded."]
#[inline]
pub fn rxdescriptorn(&mut self) -> _RXDESCRIPTORNW {
_RXDESCRIPTORNW { w: self }
}
}
}
#[doc = "Receive produce index register."]
pub struct RXPRODUCEINDEX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive produce index register."]
pub mod rxproduceindex {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RXPRODUCEINDEX {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RXPRODUCEIXR {
bits: u16,
}
impl RXPRODUCEIXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Index of the descriptor that is going to be filled next by the receive datapath."]
#[inline]
pub fn rxproduceix(&self) -> RXPRODUCEIXR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RXPRODUCEIXR { bits }
}
}
}
#[doc = "Receive consume index register."]
pub struct RXCONSUMEINDEX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive consume index register."]
pub mod rxconsumeindex {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXCONSUMEINDEX {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXCONSUMEIXR {
bits: u16,
}
impl RXCONSUMEIXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _RXCONSUMEIXW<'a> {
w: &'a mut W,
}
impl<'a> _RXCONSUMEIXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Index of the descriptor that is going to be processed next by the receive"]
#[inline]
pub fn rxconsumeix(&self) -> RXCONSUMEIXR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RXCONSUMEIXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Index of the descriptor that is going to be processed next by the receive"]
#[inline]
pub fn rxconsumeix(&mut self) -> _RXCONSUMEIXW {
_RXCONSUMEIXW { w: self }
}
}
}
#[doc = "Transmit descriptor base address register."]
pub struct TXDESCRIPTOR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit descriptor base address register."]
pub mod txdescriptor {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXDESCRIPTOR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXDR {
bits: u32,
}
impl TXDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TXDW<'a> {
w: &'a mut W,
}
impl<'a> _TXDW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:31 - TxDescriptor. MSBs of transmit descriptor base address."]
#[inline]
pub fn txd(&self) -> TXDR {
let bits = {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u32
};
TXDR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:31 - TxDescriptor. MSBs of transmit descriptor base address."]
#[inline]
pub fn txd(&mut self) -> _TXDW {
_TXDW { w: self }
}
}
}
#[doc = "Transmit status base address register."]
pub struct TXSTATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit status base address register."]
pub mod txstatus {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXSTATUS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXSTATR {
bits: u32,
}
impl TXSTATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TXSTATW<'a> {
w: &'a mut W,
}
impl<'a> _TXSTATW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:31 - TxStatus. MSBs of transmit status base address."]
#[inline]
pub fn txstat(&self) -> TXSTATR {
let bits = {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u32
};
TXSTATR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:31 - TxStatus. MSBs of transmit status base address."]
#[inline]
pub fn txstat(&mut self) -> _TXSTATW {
_TXSTATW { w: self }
}
}
}
#[doc = "Transmit number of descriptors register."]
pub struct TXDESCRIPTORNUMBER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit number of descriptors register."]
pub mod txdescriptornumber {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXDESCRIPTORNUMBER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXDNR {
bits: u16,
}
impl TXDNR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TXDNW<'a> {
w: &'a mut W,
}
impl<'a> _TXDNW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded."]
#[inline]
pub fn txdn(&self) -> TXDNR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TXDNR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded."]
#[inline]
pub fn txdn(&mut self) -> _TXDNW {
_TXDNW { w: self }
}
}
}
#[doc = "Transmit produce index register."]
pub struct TXPRODUCEINDEX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit produce index register."]
pub mod txproduceindex {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXPRODUCEINDEX {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TXPIR {
bits: u16,
}
impl TXPIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TXPIW<'a> {
w: &'a mut W,
}
impl<'a> _TXPIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver."]
#[inline]
pub fn txpi(&self) -> TXPIR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TXPIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver."]
#[inline]
pub fn txpi(&mut self) -> _TXPIW {
_TXPIW { w: self }
}
}
}
#[doc = "Transmit consume index register."]
pub struct TXCONSUMEINDEX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit consume index register."]
pub mod txconsumeindex {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::TXCONSUMEINDEX {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct TXCIR {
bits: u16,
}
impl TXCIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath."]
#[inline]
pub fn txci(&self) -> TXCIR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TXCIR { bits }
}
}
}
#[doc = "Transmit status vector 0 register."]
pub struct TSV0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit status vector 0 register."]
pub mod tsv0 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::TSV0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CRCERRR {
bits: bool,
}
impl CRCERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LCER {
bits: bool,
}
impl LCER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LORR {
bits: bool,
}
impl LORR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DONER {
bits: bool,
}
impl DONER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MULTICASTR {
bits: bool,
}
impl MULTICASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BROADCASTR {
bits: bool,
}
impl BROADCASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PACKETDEFERR {
bits: bool,
}
impl PACKETDEFERR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EXDFR {
bits: bool,
}
impl EXDFR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EXCOLR {
bits: bool,
}
impl EXCOLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LCOLR {
bits: bool,
}
impl LCOLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct GIANTR {
bits: bool,
}
impl GIANTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct UNDERRUNR {
bits: bool,
}
impl UNDERRUNR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TOTALBYTESR {
bits: u16,
}
impl TOTALBYTESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct CONTROLFRAMER {
bits: bool,
}
impl CONTROLFRAMER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PAUSER {
bits: bool,
}
impl PAUSER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BACKPRESSURER {
bits: bool,
}
impl BACKPRESSURER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct VLANR {
bits: bool,
}
impl VLANR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - CRC error. The attached CRC in the packet did not match the internally generated CRC."]
#[inline]
pub fn crcerr(&self) -> CRCERRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CRCERRR { bits }
}
#[doc = "Bit 1 - Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field."]
#[inline]
pub fn lce(&self) -> LCER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LCER { bits }
}
#[doc = "Bit 2 - Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the \"Length out of range\" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame."]
#[inline]
pub fn lor(&self) -> LORR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LORR { bits }
}
#[doc = "Bit 3 - Transmission of packet was completed."]
#[inline]
pub fn done(&self) -> DONER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DONER { bits }
}
#[doc = "Bit 4 - Packet's destination was a multicast address."]
#[inline]
pub fn multicast(&self) -> MULTICASTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MULTICASTR { bits }
}
#[doc = "Bit 5 - Packet's destination was a broadcast address."]
#[inline]
pub fn broadcast(&self) -> BROADCASTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BROADCASTR { bits }
}
#[doc = "Bit 6 - Packet was deferred for at least one attempt, but less than an excessive defer."]
#[inline]
pub fn packetdefer(&self) -> PACKETDEFERR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PACKETDEFERR { bits }
}
#[doc = "Bit 7 - Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode."]
#[inline]
pub fn exdf(&self) -> EXDFR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EXDFR { bits }
}
#[doc = "Bit 8 - Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions."]
#[inline]
pub fn excol(&self) -> EXCOLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EXCOLR { bits }
}
#[doc = "Bit 9 - Late Collision. Collision occurred beyond collision window, 512 bit times."]
#[inline]
pub fn lcol(&self) -> LCOLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LCOLR { bits }
}
#[doc = "Bit 10 - Byte count in frame was greater than can be represented in the transmit byte count field in TSV1."]
#[inline]
pub fn giant(&self) -> GIANTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
GIANTR { bits }
}
#[doc = "Bit 11 - Host side caused buffer underrun."]
#[inline]
pub fn underrun(&self) -> UNDERRUNR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
UNDERRUNR { bits }
}
#[doc = "Bits 12:27 - The total number of bytes transferred including collided attempts."]
#[inline]
pub fn totalbytes(&self) -> TOTALBYTESR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TOTALBYTESR { bits }
}
#[doc = "Bit 28 - The frame was a control frame."]
#[inline]
pub fn controlframe(&self) -> CONTROLFRAMER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CONTROLFRAMER { bits }
}
#[doc = "Bit 29 - The frame was a control frame with a valid PAUSE opcode."]
#[inline]
pub fn pause(&self) -> PAUSER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PAUSER { bits }
}
#[doc = "Bit 30 - Carrier-sense method backpressure was previously applied."]
#[inline]
pub fn backpressure(&self) -> BACKPRESSURER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BACKPRESSURER { bits }
}
#[doc = "Bit 31 - Frame's length/type field contained 0x8100 which is the VLAN protocol identifier."]
#[inline]
pub fn vlan(&self) -> VLANR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
VLANR { bits }
}
}
}
#[doc = "Transmit status vector 1 register."]
pub struct TSV1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Transmit status vector 1 register."]
pub mod tsv1 {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::TSV1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct TBCR {
bits: u16,
}
impl TBCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TCCR {
bits: u8,
}
impl TCCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Transmit byte count. The total number of bytes in the frame, not counting the collided bytes."]
#[inline]
pub fn tbc(&self) -> TBCR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TBCR { bits }
}
#[doc = "Bits 16:19 - Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented."]
#[inline]
pub fn tcc(&self) -> TCCR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TCCR { bits }
}
}
}
#[doc = "Receive status vector register."]
pub struct RSV {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive status vector register."]
pub mod rsv {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RSV {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RBCR {
bits: u16,
}
impl RBCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PPIR {
bits: bool,
}
impl PPIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXDVSEENR {
bits: bool,
}
impl RXDVSEENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CESEENR {
bits: bool,
}
impl CESEENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RCVR {
bits: bool,
}
impl RCVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CRCERRR {
bits: bool,
}
impl CRCERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LCERRR {
bits: bool,
}
impl LCERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LORR {
bits: bool,
}
impl LORR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ROKR {
bits: bool,
}
impl ROKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MULTICASTR {
bits: bool,
}
impl MULTICASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct BROADCASTR {
bits: bool,
}
impl BROADCASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DRIBBLENIBBLER {
bits: bool,
}
impl DRIBBLENIBBLER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CONTROLFRAMER {
bits: bool,
}
impl CONTROLFRAMER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PAUSER {
bits: bool,
}
impl PAUSER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct UOR {
bits: bool,
}
impl UOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct VLANR {
bits: bool,
}
impl VLANR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Received byte count. Indicates length of received frame."]
#[inline]
pub fn rbc(&self) -> RBCR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RBCR { bits }
}
#[doc = "Bit 16 - Packet previously ignored. Indicates that a packet was dropped."]
#[inline]
pub fn ppi(&self) -> PPIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PPIR { bits }
}
#[doc = "Bit 17 - RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet."]
#[inline]
pub fn rxdvseen(&self) -> RXDVSEENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXDVSEENR { bits }
}
#[doc = "Bit 18 - Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected."]
#[inline]
pub fn ceseen(&self) -> CESEENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CESEENR { bits }
}
#[doc = "Bit 19 - Receive code violation. Indicates that received PHY data does not represent a valid receive code."]
#[inline]
pub fn rcv(&self) -> RCVR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RCVR { bits }
}
#[doc = "Bit 20 - CRC error. The attached CRC in the packet did not match the internally generated CRC."]
#[inline]
pub fn crcerr(&self) -> CRCERRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CRCERRR { bits }
}
#[doc = "Bit 21 - Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field."]
#[inline]
pub fn lcerr(&self) -> LCERRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LCERRR { bits }
}
#[doc = "Bit 22 - Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the \"Length out of range\" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame."]
#[inline]
pub fn lor(&self) -> LORR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LORR { bits }
}
#[doc = "Bit 23 - Receive OK. The packet had valid CRC and no symbol errors."]
#[inline]
pub fn rok(&self) -> ROKR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ROKR { bits }
}
#[doc = "Bit 24 - The packet destination was a multicast address."]
#[inline]
pub fn multicast(&self) -> MULTICASTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MULTICASTR { bits }
}
#[doc = "Bit 25 - The packet destination was a broadcast address."]
#[inline]
pub fn broadcast(&self) -> BROADCASTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
BROADCASTR { bits }
}
#[doc = "Bit 26 - Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out."]
#[inline]
pub fn dribblenibble(&self) -> DRIBBLENIBBLER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DRIBBLENIBBLER { bits }
}
#[doc = "Bit 27 - The frame was a control frame."]
#[inline]
pub fn controlframe(&self) -> CONTROLFRAMER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CONTROLFRAMER { bits }
}
#[doc = "Bit 28 - The frame was a control frame with a valid PAUSE opcode."]
#[inline]
pub fn pause(&self) -> PAUSER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PAUSER { bits }
}
#[doc = "Bit 29 - Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode."]
#[inline]
pub fn uo(&self) -> UOR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
UOR { bits }
}
#[doc = "Bit 30 - Frame's length/type field contained 0x8100 which is the VLAN protocol identifier."]
#[inline]
pub fn vlan(&self) -> VLANR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
VLANR { bits }
}
}
}
#[doc = "Flow control counter register."]
pub struct FLOWCONTROLCOUNTER {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Flow control counter register."]
pub mod flowcontrolcounter {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FLOWCONTROLCOUNTER {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MCR {
bits: u16,
}
impl MCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct PTR {
bits: u16,
}
impl PTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MCW<'a> {
w: &'a mut W,
}
impl<'a> _MCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PTW<'a> {
w: &'a mut W,
}
impl<'a> _PTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame."]
#[inline]
pub fn mc(&self) -> MCR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MCR { bits }
}
#[doc = "Bits 16:31 - PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles."]
#[inline]
pub fn pt(&self) -> PTR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u16
};
PTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame."]
#[inline]
pub fn mc(&mut self) -> _MCW {
_MCW { w: self }
}
#[doc = "Bits 16:31 - PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles."]
#[inline]
pub fn pt(&mut self) -> _PTW {
_PTW { w: self }
}
}
}
#[doc = "Flow control status register."]
pub struct FLOWCONTROLSTATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Flow control status register."]
pub mod flowcontrolstatus {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::FLOWCONTROLSTATUS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct MCCR {
bits: u16,
}
impl MCCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register."]
#[inline]
pub fn mcc(&self) -> MCCR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MCCR { bits }
}
}
}
#[doc = "Receive filter control register."]
pub struct RXFILTERCTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive filter control register."]
pub mod rxfilterctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXFILTERCTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct AUER {
bits: bool,
}
impl AUER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ABER {
bits: bool,
}
impl ABER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMER {
bits: bool,
}
impl AMER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AUHER {
bits: bool,
}
impl AUHER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMHER {
bits: bool,
}
impl AMHER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct APER {
bits: bool,
}
impl APER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MPEWR {
bits: bool,
}
impl MPEWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RFEWR {
bits: bool,
}
impl RFEWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _AUEW<'a> {
w: &'a mut W,
}
impl<'a> _AUEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ABEW<'a> {
w: &'a mut W,
}
impl<'a> _ABEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMEW<'a> {
w: &'a mut W,
}
impl<'a> _AMEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AUHEW<'a> {
w: &'a mut W,
}
impl<'a> _AUHEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMHEW<'a> {
w: &'a mut W,
}
impl<'a> _AMHEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _APEW<'a> {
w: &'a mut W,
}
impl<'a> _APEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MPEWW<'a> {
w: &'a mut W,
}
impl<'a> _MPEWW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RFEWW<'a> {
w: &'a mut W,
}
impl<'a> _RFEWW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - AcceptUnicastEn. When set to 1, all unicast frames are accepted."]
#[inline]
pub fn aue(&self) -> AUER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AUER { bits }
}
#[doc = "Bit 1 - AcceptBroadcastEn. When set to 1, all broadcast frames are accepted."]
#[inline]
pub fn abe(&self) -> ABER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABER { bits }
}
#[doc = "Bit 2 - AcceptMulticastEn. When set to 1, all multicast frames are accepted."]
#[inline]
pub fn ame(&self) -> AMER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMER { bits }
}
#[doc = "Bit 3 - AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted."]
#[inline]
pub fn auhe(&self) -> AUHER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AUHER { bits }
}
#[doc = "Bit 4 - AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted."]
#[inline]
pub fn amhe(&self) -> AMHER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMHER { bits }
}
#[doc = "Bit 5 - AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted."]
#[inline]
pub fn ape(&self) -> APER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
APER { bits }
}
#[doc = "Bit 12 - MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match."]
#[inline]
pub fn mpew(&self) -> MPEWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MPEWR { bits }
}
#[doc = "Bit 13 - RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match."]
#[inline]
pub fn rfew(&self) -> RFEWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RFEWR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - AcceptUnicastEn. When set to 1, all unicast frames are accepted."]
#[inline]
pub fn aue(&mut self) -> _AUEW {
_AUEW { w: self }
}
#[doc = "Bit 1 - AcceptBroadcastEn. When set to 1, all broadcast frames are accepted."]
#[inline]
pub fn abe(&mut self) -> _ABEW {
_ABEW { w: self }
}
#[doc = "Bit 2 - AcceptMulticastEn. When set to 1, all multicast frames are accepted."]
#[inline]
pub fn ame(&mut self) -> _AMEW {
_AMEW { w: self }
}
#[doc = "Bit 3 - AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted."]
#[inline]
pub fn auhe(&mut self) -> _AUHEW {
_AUHEW { w: self }
}
#[doc = "Bit 4 - AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted."]
#[inline]
pub fn amhe(&mut self) -> _AMHEW {
_AMHEW { w: self }
}
#[doc = "Bit 5 - AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted."]
#[inline]
pub fn ape(&mut self) -> _APEW {
_APEW { w: self }
}
#[doc = "Bit 12 - MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match."]
#[inline]
pub fn mpew(&mut self) -> _MPEWW {
_MPEWW { w: self }
}
#[doc = "Bit 13 - RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match."]
#[inline]
pub fn rfew(&mut self) -> _RFEWW {
_RFEWW { w: self }
}
}
}
#[doc = "Receive filter WoL status register."]
pub struct RXFILTERWOLSTATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive filter WoL status register."]
pub mod rxfilterwolstatus {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RXFILTERWOLSTATUS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct AUWR {
bits: bool,
}
impl AUWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ABWR {
bits: bool,
}
impl ABWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMWR {
bits: bool,
}
impl AMWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AUHWR {
bits: bool,
}
impl AUHWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AMHWR {
bits: bool,
}
impl AMHWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct APWR {
bits: bool,
}
impl APWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RFWR {
bits: bool,
}
impl RFWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MPWR {
bits: bool,
}
impl MPWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL."]
#[inline]
pub fn auw(&self) -> AUWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AUWR { bits }
}
#[doc = "Bit 1 - AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL."]
#[inline]
pub fn abw(&self) -> ABWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ABWR { bits }
}
#[doc = "Bit 2 - AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL."]
#[inline]
pub fn amw(&self) -> AMWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMWR { bits }
}
#[doc = "Bit 3 - AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL."]
#[inline]
pub fn auhw(&self) -> AUHWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AUHWR { bits }
}
#[doc = "Bit 4 - AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL."]
#[inline]
pub fn amhw(&self) -> AMHWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AMHWR { bits }
}
#[doc = "Bit 5 - AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL."]
#[inline]
pub fn apw(&self) -> APWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
APWR { bits }
}
#[doc = "Bit 7 - RxFilterWoL. When the value is 1, the receive filter caused WoL."]
#[inline]
pub fn rfw(&self) -> RFWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RFWR { bits }
}
#[doc = "Bit 8 - MagicPacketWoL. When the value is 1, the magic packet filter caused WoL."]
#[inline]
pub fn mpw(&self) -> MPWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MPWR { bits }
}
}
}
#[doc = "Receive filter WoL clear register."]
pub struct RXFILTERWOLCLEAR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Receive filter WoL clear register."]
pub mod rxfilterwolclear {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RXFILTERWOLCLEAR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _AUWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _AUWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ABWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _ABWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _AMWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AUHWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _AUHWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AMHWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _AMHWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _APWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _APWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RFWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RFWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MPWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _MPWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn auwclr(&mut self) -> _AUWCLRW {
_AUWCLRW { w: self }
}
#[doc = "Bit 1 - AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn abwclr(&mut self) -> _ABWCLRW {
_ABWCLRW { w: self }
}
#[doc = "Bit 2 - AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn amwclr(&mut self) -> _AMWCLRW {
_AMWCLRW { w: self }
}
#[doc = "Bit 3 - AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn auhwclr(&mut self) -> _AUHWCLRW {
_AUHWCLRW { w: self }
}
#[doc = "Bit 4 - AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn amhwclr(&mut self) -> _AMHWCLRW {
_AMHWCLRW { w: self }
}
#[doc = "Bit 5 - AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn apwclr(&mut self) -> _APWCLRW {
_APWCLRW { w: self }
}
#[doc = "Bit 7 - RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn rfwclr(&mut self) -> _RFWCLRW {
_RFWCLRW { w: self }
}
#[doc = "Bit 8 - MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared."]
#[inline]
pub fn mpwclr(&mut self) -> _MPWCLRW {
_MPWCLRW { w: self }
}
}
}
#[doc = "Hash filter table LSBs register."]
pub struct HASHFILTERL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Hash filter table LSBs register."]
pub mod hashfilterl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::HASHFILTERL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct HFLR {
bits: u32,
}
impl HFLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _HFLW<'a> {
w: &'a mut W,
}
impl<'a> _HFLW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering."]
#[inline]
pub fn hfl(&self) -> HFLR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
HFLR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering."]
#[inline]
pub fn hfl(&mut self) -> _HFLW {
_HFLW { w: self }
}
}
}
#[doc = "Hash filter table MSBs register."]
pub struct HASHFILTERH {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Hash filter table MSBs register."]
pub mod hashfilterh {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::HASHFILTERH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct HFHR {
bits: u32,
}
impl HFHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _HFHW<'a> {
w: &'a mut W,
}
impl<'a> _HFHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Bits 63:32 of the imperfect filter hash table for receive filtering."]
#[inline]
pub fn hfh(&self) -> HFHR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
HFHR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Bits 63:32 of the imperfect filter hash table for receive filtering."]
#[inline]
pub fn hfh(&mut self) -> _HFHW {
_HFHW { w: self }
}
}
}
#[doc = "Interrupt status register."]
pub struct INTSTATUS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt status register."]
pub mod intstatus {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTSTATUS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RXOVERRUNINTR {
bits: bool,
}
impl RXOVERRUNINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXERRORINTR {
bits: bool,
}
impl RXERRORINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXFINISHEDINTR {
bits: bool,
}
impl RXFINISHEDINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXDONEINTR {
bits: bool,
}
impl RXDONEINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXUNDERRUNINTR {
bits: bool,
}
impl TXUNDERRUNINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXERRORINTR {
bits: bool,
}
impl TXERRORINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXFINISHEDINTR {
bits: bool,
}
impl TXFINISHEDINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXDONEINTR {
bits: bool,
}
impl TXDONEINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTINTR {
bits: bool,
}
impl SOFTINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WAKEUPINTR {
bits: bool,
}
impl WAKEUPINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error."]
#[inline]
pub fn rxoverrunint(&self) -> RXOVERRUNINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXOVERRUNINTR { bits }
}
#[doc = "Bit 1 - Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun."]
#[inline]
pub fn rxerrorint(&self) -> RXERRORINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXERRORINTR { bits }
}
#[doc = "Bit 2 - Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex."]
#[inline]
pub fn rxfinishedint(&self) -> RXFINISHEDINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXFINISHEDINTR { bits }
}
#[doc = "Bit 3 - Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set."]
#[inline]
pub fn rxdoneint(&self) -> RXDONEINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXDONEINTR { bits }
}
#[doc = "Bit 4 - Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error."]
#[inline]
pub fn txunderrunint(&self) -> TXUNDERRUNINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXUNDERRUNINTR { bits }
}
#[doc = "Bit 5 - Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun."]
#[inline]
pub fn txerrorint(&self) -> TXERRORINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXERRORINTR { bits }
}
#[doc = "Bit 6 - Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex."]
#[inline]
pub fn txfinishedint(&self) -> TXFINISHEDINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXFINISHEDINTR { bits }
}
#[doc = "Bit 7 - Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set."]
#[inline]
pub fn txdoneint(&self) -> TXDONEINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXDONEINTR { bits }
}
#[doc = "Bit 12 - Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register."]
#[inline]
pub fn softint(&self) -> SOFTINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTINTR { bits }
}
#[doc = "Bit 13 - Interrupt triggered by a Wake-up event detected by the receive filter."]
#[inline]
pub fn wakeupint(&self) -> WAKEUPINTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WAKEUPINTR { bits }
}
}
}
#[doc = "Interrupt enable register."]
pub struct INTENABLE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt enable register."]
pub mod intenable {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTENABLE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct RXOVERRUNINTENR {
bits: bool,
}
impl RXOVERRUNINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXERRORINTENR {
bits: bool,
}
impl RXERRORINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXFINISHEDINTENR {
bits: bool,
}
impl RXFINISHEDINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXDONEINTENR {
bits: bool,
}
impl RXDONEINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXUNDERRUNINTENR {
bits: bool,
}
impl TXUNDERRUNINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXERRORINTENR {
bits: bool,
}
impl TXERRORINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXFINISHEDINTENR {
bits: bool,
}
impl TXFINISHEDINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXDONEINTENR {
bits: bool,
}
impl TXDONEINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTINTENR {
bits: bool,
}
impl SOFTINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct WAKEUPINTENR {
bits: bool,
}
impl WAKEUPINTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _RXOVERRUNINTENW<'a> {
w: &'a mut W,
}
impl<'a> _RXOVERRUNINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXERRORINTENW<'a> {
w: &'a mut W,
}
impl<'a> _RXERRORINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXFINISHEDINTENW<'a> {
w: &'a mut W,
}
impl<'a> _RXFINISHEDINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXDONEINTENW<'a> {
w: &'a mut W,
}
impl<'a> _RXDONEINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXUNDERRUNINTENW<'a> {
w: &'a mut W,
}
impl<'a> _TXUNDERRUNINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXERRORINTENW<'a> {
w: &'a mut W,
}
impl<'a> _TXERRORINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXFINISHEDINTENW<'a> {
w: &'a mut W,
}
impl<'a> _TXFINISHEDINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXDONEINTENW<'a> {
w: &'a mut W,
}
impl<'a> _TXDONEINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTINTENW<'a> {
w: &'a mut W,
}
impl<'a> _SOFTINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WAKEUPINTENW<'a> {
w: &'a mut W,
}
impl<'a> _WAKEUPINTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations."]
#[inline]
pub fn rxoverruninten(&self) -> RXOVERRUNINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXOVERRUNINTENR { bits }
}
#[doc = "Bit 1 - Enable for interrupt trigger on receive errors."]
#[inline]
pub fn rxerrorinten(&self) -> RXERRORINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXERRORINTENR { bits }
}
#[doc = "Bit 2 - Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex."]
#[inline]
pub fn rxfinishedinten(&self) -> RXFINISHEDINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXFINISHEDINTENR { bits }
}
#[doc = "Bit 3 - Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set."]
#[inline]
pub fn rxdoneinten(&self) -> RXDONEINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXDONEINTENR { bits }
}
#[doc = "Bit 4 - Enable for interrupt trigger on transmit buffer or descriptor underrun situations."]
#[inline]
pub fn txunderruninten(&self) -> TXUNDERRUNINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXUNDERRUNINTENR { bits }
}
#[doc = "Bit 5 - Enable for interrupt trigger on transmit errors."]
#[inline]
pub fn txerrorinten(&self) -> TXERRORINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXERRORINTENR { bits }
}
#[doc = "Bit 6 - Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex."]
#[inline]
pub fn txfinishedinten(&self) -> TXFINISHEDINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXFINISHEDINTENR { bits }
}
#[doc = "Bit 7 - Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set."]
#[inline]
pub fn txdoneinten(&self) -> TXDONEINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXDONEINTENR { bits }
}
#[doc = "Bit 12 - Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register."]
#[inline]
pub fn softinten(&self) -> SOFTINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTINTENR { bits }
}
#[doc = "Bit 13 - Enable for interrupt triggered by a Wake-up event detected by the receive filter."]
#[inline]
pub fn wakeupinten(&self) -> WAKEUPINTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
WAKEUPINTENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations."]
#[inline]
pub fn rxoverruninten(&mut self) -> _RXOVERRUNINTENW {
_RXOVERRUNINTENW { w: self }
}
#[doc = "Bit 1 - Enable for interrupt trigger on receive errors."]
#[inline]
pub fn rxerrorinten(&mut self) -> _RXERRORINTENW {
_RXERRORINTENW { w: self }
}
#[doc = "Bit 2 - Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex."]
#[inline]
pub fn rxfinishedinten(&mut self) -> _RXFINISHEDINTENW {
_RXFINISHEDINTENW { w: self }
}
#[doc = "Bit 3 - Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set."]
#[inline]
pub fn rxdoneinten(&mut self) -> _RXDONEINTENW {
_RXDONEINTENW { w: self }
}
#[doc = "Bit 4 - Enable for interrupt trigger on transmit buffer or descriptor underrun situations."]
#[inline]
pub fn txunderruninten(&mut self) -> _TXUNDERRUNINTENW {
_TXUNDERRUNINTENW { w: self }
}
#[doc = "Bit 5 - Enable for interrupt trigger on transmit errors."]
#[inline]
pub fn txerrorinten(&mut self) -> _TXERRORINTENW {
_TXERRORINTENW { w: self }
}
#[doc = "Bit 6 - Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex."]
#[inline]
pub fn txfinishedinten(&mut self) -> _TXFINISHEDINTENW {
_TXFINISHEDINTENW { w: self }
}
#[doc = "Bit 7 - Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set."]
#[inline]
pub fn txdoneinten(&mut self) -> _TXDONEINTENW {
_TXDONEINTENW { w: self }
}
#[doc = "Bit 12 - Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register."]
#[inline]
pub fn softinten(&mut self) -> _SOFTINTENW {
_SOFTINTENW { w: self }
}
#[doc = "Bit 13 - Enable for interrupt triggered by a Wake-up event detected by the receive filter."]
#[inline]
pub fn wakeupinten(&mut self) -> _WAKEUPINTENW {
_WAKEUPINTENW { w: self }
}
}
}
#[doc = "Interrupt clear register."]
pub struct INTCLEAR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt clear register."]
pub mod intclear {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTCLEAR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _RXOVERRUNINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RXOVERRUNINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXERRORINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RXERRORINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXFINISHEDINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RXFINISHEDINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXDONEINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RXDONEINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXUNDERRUNINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _TXUNDERRUNINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXERRORINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _TXERRORINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXFINISHEDINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _TXFINISHEDINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXDONEINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _TXDONEINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _SOFTINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WAKEUPINTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _WAKEUPINTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxoverrunintclr(&mut self) -> _RXOVERRUNINTCLRW {
_RXOVERRUNINTCLRW { w: self }
}
#[doc = "Bit 1 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxerrorintclr(&mut self) -> _RXERRORINTCLRW {
_RXERRORINTCLRW { w: self }
}
#[doc = "Bit 2 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxfinishedintclr(&mut self) -> _RXFINISHEDINTCLRW {
_RXFINISHEDINTCLRW { w: self }
}
#[doc = "Bit 3 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxdoneintclr(&mut self) -> _RXDONEINTCLRW {
_RXDONEINTCLRW { w: self }
}
#[doc = "Bit 4 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txunderrunintclr(&mut self) -> _TXUNDERRUNINTCLRW {
_TXUNDERRUNINTCLRW { w: self }
}
#[doc = "Bit 5 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txerrorintclr(&mut self) -> _TXERRORINTCLRW {
_TXERRORINTCLRW { w: self }
}
#[doc = "Bit 6 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txfinishedintclr(&mut self) -> _TXFINISHEDINTCLRW {
_TXFINISHEDINTCLRW { w: self }
}
#[doc = "Bit 7 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txdoneintclr(&mut self) -> _TXDONEINTCLRW {
_TXDONEINTCLRW { w: self }
}
#[doc = "Bit 12 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn softintclr(&mut self) -> _SOFTINTCLRW {
_SOFTINTCLRW { w: self }
}
#[doc = "Bit 13 - Writing a 1 clears the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn wakeupintclr(&mut self) -> _WAKEUPINTCLRW {
_WAKEUPINTCLRW { w: self }
}
}
}
#[doc = "Interrupt set register."]
pub struct INTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Interrupt set register."]
pub mod intset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _RXOVERRUNINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _RXOVERRUNINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXERRORINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _RXERRORINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXFINISHEDINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _RXFINISHEDINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXDONEINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _RXDONEINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXUNDERRUNINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _TXUNDERRUNINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXERRORINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _TXERRORINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXFINISHEDINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _TXFINISHEDINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXDONEINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _TXDONEINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _SOFTINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _WAKEUPINTSETW<'a> {
w: &'a mut W,
}
impl<'a> _WAKEUPINTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxoverrunintset(&mut self) -> _RXOVERRUNINTSETW {
_RXOVERRUNINTSETW { w: self }
}
#[doc = "Bit 1 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxerrorintset(&mut self) -> _RXERRORINTSETW {
_RXERRORINTSETW { w: self }
}
#[doc = "Bit 2 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxfinishedintset(&mut self) -> _RXFINISHEDINTSETW {
_RXFINISHEDINTSETW { w: self }
}
#[doc = "Bit 3 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn rxdoneintset(&mut self) -> _RXDONEINTSETW {
_RXDONEINTSETW { w: self }
}
#[doc = "Bit 4 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txunderrunintset(&mut self) -> _TXUNDERRUNINTSETW {
_TXUNDERRUNINTSETW { w: self }
}
#[doc = "Bit 5 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txerrorintset(&mut self) -> _TXERRORINTSETW {
_TXERRORINTSETW { w: self }
}
#[doc = "Bit 6 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txfinishedintset(&mut self) -> _TXFINISHEDINTSETW {
_TXFINISHEDINTSETW { w: self }
}
#[doc = "Bit 7 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn txdoneintset(&mut self) -> _TXDONEINTSETW {
_TXDONEINTSETW { w: self }
}
#[doc = "Bit 12 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn softintset(&mut self) -> _SOFTINTSETW {
_SOFTINTSETW { w: self }
}
#[doc = "Bit 13 - Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus."]
#[inline]
pub fn wakeupintset(&mut self) -> _WAKEUPINTSETW {
_WAKEUPINTSETW { w: self }
}
}
}
#[doc = "Power-down register."]
pub struct POWERDOWN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Power-down register."]
pub mod powerdown {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::POWERDOWN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PDR {
bits: bool,
}
impl PDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PDW<'a> {
w: &'a mut W,
}
impl<'a> _PDW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 31 - PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register."]
#[inline]
pub fn pd(&self) -> PDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PDR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 31 - PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register."]
#[inline]
pub fn pd(&mut self) -> _PDW {
_PDW { w: self }
}
}
}
}
#[doc = "General purpose DMA controller"]
pub struct GPDMA {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPDMA {}
impl GPDMA {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const gpdma::RegisterBlock {
0x5000_4000 as *const _
}
}
impl Deref for GPDMA {
type Target = gpdma::RegisterBlock;
fn deref(&self) -> &gpdma::RegisterBlock {
unsafe { &*GPDMA::ptr() }
}
}
#[doc = "General purpose DMA controller"]
pub mod gpdma {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - DMA Interrupt Status Register"]
pub intstat: INTSTAT,
#[doc = "0x04 - DMA Interrupt Terminal Count Request Status Register"]
pub inttcstat: INTTCSTAT,
#[doc = "0x08 - DMA Interrupt Terminal Count Request Clear Register"]
pub inttcclear: INTTCCLEAR,
#[doc = "0x0c - DMA Interrupt Error Status Register"]
pub interrstat: INTERRSTAT,
#[doc = "0x10 - DMA Interrupt Error Clear Register"]
pub interrclr: INTERRCLR,
#[doc = "0x14 - DMA Raw Interrupt Terminal Count Status Register"]
pub rawinttcstat: RAWINTTCSTAT,
#[doc = "0x18 - DMA Raw Error Interrupt Status Register"]
pub rawinterrstat: RAWINTERRSTAT,
#[doc = "0x1c - DMA Enabled Channel Register"]
pub enbldchns: ENBLDCHNS,
#[doc = "0x20 - DMA Software Burst Request Register"]
pub softbreq: SOFTBREQ,
#[doc = "0x24 - DMA Software Single Request Register"]
pub softsreq: SOFTSREQ,
#[doc = "0x28 - DMA Software Last Burst Request Register"]
pub softlbreq: SOFTLBREQ,
#[doc = "0x2c - DMA Software Last Single Request Register"]
pub softlsreq: SOFTLSREQ,
#[doc = "0x30 - DMA Configuration Register"]
pub config: DMA_CONFIG,
#[doc = "0x34 - DMA Synchronization Register"]
pub sync: SYNC,
_reserved14: [u8; 200usize],
#[doc = "0x100 - DMA Channel 0 Source Address Register"]
pub srcaddr0: SRCADDR,
#[doc = "0x104 - DMA Channel 0 Destination Address Register"]
pub destaddr0: DESTADDR,
#[doc = "0x108 - DMA Channel 0 Linked List Item Register"]
pub lli0: LLI,
#[doc = "0x10c - DMA Channel 0 Control Register"]
pub control0: CONTROL,
#[doc = "0x110 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config0: DMA0_CONFIG,
_reserved19: [u8; 12usize],
#[doc = "0x120 - DMA Channel 0 Source Address Register"]
pub srcaddr1: SRCADDR,
#[doc = "0x124 - DMA Channel 0 Destination Address Register"]
pub destaddr1: DESTADDR,
#[doc = "0x128 - DMA Channel 0 Linked List Item Register"]
pub lli1: LLI,
#[doc = "0x12c - DMA Channel 0 Control Register"]
pub control1: CONTROL,
#[doc = "0x130 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config1: DMA0_CONFIG,
_reserved24: [u8; 12usize],
#[doc = "0x140 - DMA Channel 0 Source Address Register"]
pub srcaddr2: SRCADDR,
#[doc = "0x144 - DMA Channel 0 Destination Address Register"]
pub destaddr2: DESTADDR,
#[doc = "0x148 - DMA Channel 0 Linked List Item Register"]
pub lli2: LLI,
#[doc = "0x14c - DMA Channel 0 Control Register"]
pub control2: CONTROL,
#[doc = "0x150 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config2: DMA0_CONFIG,
_reserved29: [u8; 12usize],
#[doc = "0x160 - DMA Channel 0 Source Address Register"]
pub srcaddr3: SRCADDR,
#[doc = "0x164 - DMA Channel 0 Destination Address Register"]
pub destaddr3: DESTADDR,
#[doc = "0x168 - DMA Channel 0 Linked List Item Register"]
pub lli3: LLI,
#[doc = "0x16c - DMA Channel 0 Control Register"]
pub control3: CONTROL,
#[doc = "0x170 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config3: DMA0_CONFIG,
_reserved4: [u8; 12usize],
#[doc = "0x180 - DMA Channel 0 Source Address Register"]
pub srcaddr4: SRCADDR,
#[doc = "0x184 - DMA Channel 0 Destination Address Register"]
pub destaddr4: DESTADDR,
#[doc = "0x188 - DMA Channel 0 Linked List Item Register"]
pub lli4: LLI,
#[doc = "0x18c - DMA Channel 0 Control Register"]
pub control4: CONTROL,
#[doc = "0x190 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config4: DMA0_CONFIG,
_reserved5: [u8; 12usize],
#[doc = "0x1a0 - DMA Channel 0 Source Address Register"]
pub srcaddr5: SRCADDR,
#[doc = "0x1a4 - DMA Channel 0 Destination Address Register"]
pub destaddr5: DESTADDR,
#[doc = "0x1a8 - DMA Channel 0 Linked List Item Register"]
pub lli5: LLI,
#[doc = "0x1ac - DMA Channel 0 Control Register"]
pub control5: CONTROL,
#[doc = "0x1b0 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config5: DMA0_CONFIG,
_reserved6: [u8; 12usize],
#[doc = "0x1c0 - DMA Channel 0 Source Address Register"]
pub srcaddr6: SRCADDR,
#[doc = "0x1c4 - DMA Channel 0 Destination Address Register"]
pub destaddr6: DESTADDR,
#[doc = "0x1c8 - DMA Channel 0 Linked List Item Register"]
pub lli6: LLI,
#[doc = "0x1cc - DMA Channel 0 Control Register"]
pub control6: CONTROL,
#[doc = "0x1d0 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config6: DMA0_CONFIG,
_reserved7: [u8; 12usize],
#[doc = "0x1e0 - DMA Channel 0 Source Address Register"]
pub srcaddr7: SRCADDR,
#[doc = "0x1e4 - DMA Channel 0 Destination Address Register"]
pub destaddr7: DESTADDR,
#[doc = "0x1e8 - DMA Channel 0 Linked List Item Register"]
pub lli7: LLI,
#[doc = "0x1ec - DMA Channel 0 Control Register"]
pub control7: CONTROL,
#[doc = "0x1f0 - DMA Channel 0 Configuration Register\\[1\\]"]
pub config7: DMA0_CONFIG,
}
#[doc = "DMA Interrupt Status Register"]
pub struct INTSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Interrupt Status Register"]
pub mod intstat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTSTAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT0R {
bits: bool,
}
impl INTSTAT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT1R {
bits: bool,
}
impl INTSTAT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT2R {
bits: bool,
}
impl INTSTAT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT3R {
bits: bool,
}
impl INTSTAT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT4R {
bits: bool,
}
impl INTSTAT4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT5R {
bits: bool,
}
impl INTSTAT5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT6R {
bits: bool,
}
impl INTSTAT6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTSTAT7R {
bits: bool,
}
impl INTSTAT7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat0(&self) -> INTSTAT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT0R { bits }
}
#[doc = "Bit 1 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat1(&self) -> INTSTAT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT1R { bits }
}
#[doc = "Bit 2 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat2(&self) -> INTSTAT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT2R { bits }
}
#[doc = "Bit 3 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat3(&self) -> INTSTAT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT3R { bits }
}
#[doc = "Bit 4 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat4(&self) -> INTSTAT4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT4R { bits }
}
#[doc = "Bit 5 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat5(&self) -> INTSTAT5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT5R { bits }
}
#[doc = "Bit 6 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat6(&self) -> INTSTAT6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT6R { bits }
}
#[doc = "Bit 7 - Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request."]
#[inline]
pub fn intstat7(&self) -> INTSTAT7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTSTAT7R { bits }
}
}
}
#[doc = "DMA Interrupt Terminal Count Request Status Register"]
pub struct INTTCSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Interrupt Terminal Count Request Status Register"]
pub mod inttcstat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTTCSTAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT0R {
bits: bool,
}
impl INTTCSTAT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT1R {
bits: bool,
}
impl INTTCSTAT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT2R {
bits: bool,
}
impl INTTCSTAT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT3R {
bits: bool,
}
impl INTTCSTAT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT4R {
bits: bool,
}
impl INTTCSTAT4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT5R {
bits: bool,
}
impl INTTCSTAT5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT6R {
bits: bool,
}
impl INTTCSTAT6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTTCSTAT7R {
bits: bool,
}
impl INTTCSTAT7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat0(&self) -> INTTCSTAT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT0R { bits }
}
#[doc = "Bit 1 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat1(&self) -> INTTCSTAT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT1R { bits }
}
#[doc = "Bit 2 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat2(&self) -> INTTCSTAT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT2R { bits }
}
#[doc = "Bit 3 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat3(&self) -> INTTCSTAT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT3R { bits }
}
#[doc = "Bit 4 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat4(&self) -> INTTCSTAT4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT4R { bits }
}
#[doc = "Bit 5 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat5(&self) -> INTTCSTAT5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT5R { bits }
}
#[doc = "Bit 6 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat6(&self) -> INTTCSTAT6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT6R { bits }
}
#[doc = "Bit 7 - Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn inttcstat7(&self) -> INTTCSTAT7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTTCSTAT7R { bits }
}
}
}
#[doc = "DMA Interrupt Terminal Count Request Clear Register"]
pub struct INTTCCLEAR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Interrupt Terminal Count Request Clear Register"]
pub mod inttcclear {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTTCCLEAR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR0W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR1W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR2W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR3W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR4W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR5W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR6W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTTCCLEAR7W<'a> {
w: &'a mut W,
}
impl<'a> _INTTCCLEAR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear0(&mut self) -> _INTTCCLEAR0W {
_INTTCCLEAR0W { w: self }
}
#[doc = "Bit 1 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear1(&mut self) -> _INTTCCLEAR1W {
_INTTCCLEAR1W { w: self }
}
#[doc = "Bit 2 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear2(&mut self) -> _INTTCCLEAR2W {
_INTTCCLEAR2W { w: self }
}
#[doc = "Bit 3 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear3(&mut self) -> _INTTCCLEAR3W {
_INTTCCLEAR3W { w: self }
}
#[doc = "Bit 4 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear4(&mut self) -> _INTTCCLEAR4W {
_INTTCCLEAR4W { w: self }
}
#[doc = "Bit 5 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear5(&mut self) -> _INTTCCLEAR5W {
_INTTCCLEAR5W { w: self }
}
#[doc = "Bit 6 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear6(&mut self) -> _INTTCCLEAR6W {
_INTTCCLEAR6W { w: self }
}
#[doc = "Bit 7 - Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt."]
#[inline]
pub fn inttcclear7(&mut self) -> _INTTCCLEAR7W {
_INTTCCLEAR7W { w: self }
}
}
}
#[doc = "DMA Interrupt Error Status Register"]
pub struct INTERRSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Interrupt Error Status Register"]
pub mod interrstat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTERRSTAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT0R {
bits: bool,
}
impl INTERRSTAT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT1R {
bits: bool,
}
impl INTERRSTAT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT2R {
bits: bool,
}
impl INTERRSTAT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT3R {
bits: bool,
}
impl INTERRSTAT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT4R {
bits: bool,
}
impl INTERRSTAT4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT5R {
bits: bool,
}
impl INTERRSTAT5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT6R {
bits: bool,
}
impl INTERRSTAT6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct INTERRSTAT7R {
bits: bool,
}
impl INTERRSTAT7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat0(&self) -> INTERRSTAT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT0R { bits }
}
#[doc = "Bit 1 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat1(&self) -> INTERRSTAT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT1R { bits }
}
#[doc = "Bit 2 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat2(&self) -> INTERRSTAT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT2R { bits }
}
#[doc = "Bit 3 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat3(&self) -> INTERRSTAT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT3R { bits }
}
#[doc = "Bit 4 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat4(&self) -> INTERRSTAT4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT4R { bits }
}
#[doc = "Bit 5 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat5(&self) -> INTERRSTAT5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT5R { bits }
}
#[doc = "Bit 6 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat6(&self) -> INTERRSTAT6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT6R { bits }
}
#[doc = "Bit 7 - Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn interrstat7(&self) -> INTERRSTAT7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
INTERRSTAT7R { bits }
}
}
}
#[doc = "DMA Interrupt Error Clear Register"]
pub struct INTERRCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Interrupt Error Clear Register"]
pub mod interrclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTERRCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _INTERRCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _INTERRCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr0(&mut self) -> _INTERRCLR0W {
_INTERRCLR0W { w: self }
}
#[doc = "Bit 1 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr1(&mut self) -> _INTERRCLR1W {
_INTERRCLR1W { w: self }
}
#[doc = "Bit 2 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr2(&mut self) -> _INTERRCLR2W {
_INTERRCLR2W { w: self }
}
#[doc = "Bit 3 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr3(&mut self) -> _INTERRCLR3W {
_INTERRCLR3W { w: self }
}
#[doc = "Bit 4 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr4(&mut self) -> _INTERRCLR4W {
_INTERRCLR4W { w: self }
}
#[doc = "Bit 5 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr5(&mut self) -> _INTERRCLR5W {
_INTERRCLR5W { w: self }
}
#[doc = "Bit 6 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr6(&mut self) -> _INTERRCLR6W {
_INTERRCLR6W { w: self }
}
#[doc = "Bit 7 - Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt."]
#[inline]
pub fn interrclr7(&mut self) -> _INTERRCLR7W {
_INTERRCLR7W { w: self }
}
}
}
#[doc = "DMA Raw Interrupt Terminal Count Status Register"]
pub struct RAWINTTCSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Raw Interrupt Terminal Count Status Register"]
pub mod rawinttcstat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RAWINTTCSTAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT0R {
bits: bool,
}
impl RAWINTTCSTAT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT1R {
bits: bool,
}
impl RAWINTTCSTAT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT2R {
bits: bool,
}
impl RAWINTTCSTAT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT3R {
bits: bool,
}
impl RAWINTTCSTAT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT4R {
bits: bool,
}
impl RAWINTTCSTAT4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT5R {
bits: bool,
}
impl RAWINTTCSTAT5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT6R {
bits: bool,
}
impl RAWINTTCSTAT6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTTCSTAT7R {
bits: bool,
}
impl RAWINTTCSTAT7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat0(&self) -> RAWINTTCSTAT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT0R { bits }
}
#[doc = "Bit 1 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat1(&self) -> RAWINTTCSTAT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT1R { bits }
}
#[doc = "Bit 2 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat2(&self) -> RAWINTTCSTAT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT2R { bits }
}
#[doc = "Bit 3 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat3(&self) -> RAWINTTCSTAT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT3R { bits }
}
#[doc = "Bit 4 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat4(&self) -> RAWINTTCSTAT4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT4R { bits }
}
#[doc = "Bit 5 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat5(&self) -> RAWINTTCSTAT5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT5R { bits }
}
#[doc = "Bit 6 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat6(&self) -> RAWINTTCSTAT6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT6R { bits }
}
#[doc = "Bit 7 - Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request."]
#[inline]
pub fn rawinttcstat7(&self) -> RAWINTTCSTAT7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTTCSTAT7R { bits }
}
}
}
#[doc = "DMA Raw Error Interrupt Status Register"]
pub struct RAWINTERRSTAT {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Raw Error Interrupt Status Register"]
pub mod rawinterrstat {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RAWINTERRSTAT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT0R {
bits: bool,
}
impl RAWINTERRSTAT0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT1R {
bits: bool,
}
impl RAWINTERRSTAT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT2R {
bits: bool,
}
impl RAWINTERRSTAT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT3R {
bits: bool,
}
impl RAWINTERRSTAT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT4R {
bits: bool,
}
impl RAWINTERRSTAT4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT5R {
bits: bool,
}
impl RAWINTERRSTAT5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT6R {
bits: bool,
}
impl RAWINTERRSTAT6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RAWINTERRSTAT7R {
bits: bool,
}
impl RAWINTERRSTAT7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat0(&self) -> RAWINTERRSTAT0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT0R { bits }
}
#[doc = "Bit 1 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat1(&self) -> RAWINTERRSTAT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT1R { bits }
}
#[doc = "Bit 2 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat2(&self) -> RAWINTERRSTAT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT2R { bits }
}
#[doc = "Bit 3 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat3(&self) -> RAWINTERRSTAT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT3R { bits }
}
#[doc = "Bit 4 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat4(&self) -> RAWINTERRSTAT4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT4R { bits }
}
#[doc = "Bit 5 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat5(&self) -> RAWINTERRSTAT5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT5R { bits }
}
#[doc = "Bit 6 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat6(&self) -> RAWINTERRSTAT6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT6R { bits }
}
#[doc = "Bit 7 - Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request."]
#[inline]
pub fn rawinterrstat7(&self) -> RAWINTERRSTAT7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RAWINTERRSTAT7R { bits }
}
}
}
#[doc = "DMA Enabled Channel Register"]
pub struct ENBLDCHNS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Enabled Channel Register"]
pub mod enbldchns {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::ENBLDCHNS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS0R {
bits: bool,
}
impl ENABLEDCHANNELS0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS1R {
bits: bool,
}
impl ENABLEDCHANNELS1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS2R {
bits: bool,
}
impl ENABLEDCHANNELS2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS3R {
bits: bool,
}
impl ENABLEDCHANNELS3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS4R {
bits: bool,
}
impl ENABLEDCHANNELS4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS5R {
bits: bool,
}
impl ENABLEDCHANNELS5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS6R {
bits: bool,
}
impl ENABLEDCHANNELS6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ENABLEDCHANNELS7R {
bits: bool,
}
impl ENABLEDCHANNELS7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels0(&self) -> ENABLEDCHANNELS0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS0R { bits }
}
#[doc = "Bit 1 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels1(&self) -> ENABLEDCHANNELS1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS1R { bits }
}
#[doc = "Bit 2 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels2(&self) -> ENABLEDCHANNELS2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS2R { bits }
}
#[doc = "Bit 3 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels3(&self) -> ENABLEDCHANNELS3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS3R { bits }
}
#[doc = "Bit 4 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels4(&self) -> ENABLEDCHANNELS4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS4R { bits }
}
#[doc = "Bit 5 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels5(&self) -> ENABLEDCHANNELS5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS5R { bits }
}
#[doc = "Bit 6 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels6(&self) -> ENABLEDCHANNELS6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS6R { bits }
}
#[doc = "Bit 7 - Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled."]
#[inline]
pub fn enabledchannels7(&self) -> ENABLEDCHANNELS7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ENABLEDCHANNELS7R { bits }
}
}
}
#[doc = "DMA Software Burst Request Register"]
pub struct SOFTBREQ {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Software Burst Request Register"]
pub mod softbreq {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOFTBREQ {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ0R {
bits: bool,
}
impl SOFTBREQ0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ1R {
bits: bool,
}
impl SOFTBREQ1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ2R {
bits: bool,
}
impl SOFTBREQ2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ3R {
bits: bool,
}
impl SOFTBREQ3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ4R {
bits: bool,
}
impl SOFTBREQ4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ5R {
bits: bool,
}
impl SOFTBREQ5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ6R {
bits: bool,
}
impl SOFTBREQ6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ7R {
bits: bool,
}
impl SOFTBREQ7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ8R {
bits: bool,
}
impl SOFTBREQ8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ9R {
bits: bool,
}
impl SOFTBREQ9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ10R {
bits: bool,
}
impl SOFTBREQ10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ11R {
bits: bool,
}
impl SOFTBREQ11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ12R {
bits: bool,
}
impl SOFTBREQ12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ13R {
bits: bool,
}
impl SOFTBREQ13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ14R {
bits: bool,
}
impl SOFTBREQ14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTBREQ15R {
bits: bool,
}
impl SOFTBREQ15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ0W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ1W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ2W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ3W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ4W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ5W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ6W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ7W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ8W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ9W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ10W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ11W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ12W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ13W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ14W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTBREQ15W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTBREQ15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq0(&self) -> SOFTBREQ0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ0R { bits }
}
#[doc = "Bit 1 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq1(&self) -> SOFTBREQ1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ1R { bits }
}
#[doc = "Bit 2 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq2(&self) -> SOFTBREQ2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ2R { bits }
}
#[doc = "Bit 3 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq3(&self) -> SOFTBREQ3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ3R { bits }
}
#[doc = "Bit 4 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq4(&self) -> SOFTBREQ4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ4R { bits }
}
#[doc = "Bit 5 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq5(&self) -> SOFTBREQ5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ5R { bits }
}
#[doc = "Bit 6 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq6(&self) -> SOFTBREQ6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ6R { bits }
}
#[doc = "Bit 7 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq7(&self) -> SOFTBREQ7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ7R { bits }
}
#[doc = "Bit 8 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq8(&self) -> SOFTBREQ8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ8R { bits }
}
#[doc = "Bit 9 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq9(&self) -> SOFTBREQ9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ9R { bits }
}
#[doc = "Bit 10 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq10(&self) -> SOFTBREQ10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ10R { bits }
}
#[doc = "Bit 11 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq11(&self) -> SOFTBREQ11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ11R { bits }
}
#[doc = "Bit 12 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq12(&self) -> SOFTBREQ12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ12R { bits }
}
#[doc = "Bit 13 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq13(&self) -> SOFTBREQ13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ13R { bits }
}
#[doc = "Bit 14 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq14(&self) -> SOFTBREQ14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ14R { bits }
}
#[doc = "Bit 15 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq15(&self) -> SOFTBREQ15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTBREQ15R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq0(&mut self) -> _SOFTBREQ0W {
_SOFTBREQ0W { w: self }
}
#[doc = "Bit 1 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq1(&mut self) -> _SOFTBREQ1W {
_SOFTBREQ1W { w: self }
}
#[doc = "Bit 2 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq2(&mut self) -> _SOFTBREQ2W {
_SOFTBREQ2W { w: self }
}
#[doc = "Bit 3 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq3(&mut self) -> _SOFTBREQ3W {
_SOFTBREQ3W { w: self }
}
#[doc = "Bit 4 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq4(&mut self) -> _SOFTBREQ4W {
_SOFTBREQ4W { w: self }
}
#[doc = "Bit 5 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq5(&mut self) -> _SOFTBREQ5W {
_SOFTBREQ5W { w: self }
}
#[doc = "Bit 6 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq6(&mut self) -> _SOFTBREQ6W {
_SOFTBREQ6W { w: self }
}
#[doc = "Bit 7 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq7(&mut self) -> _SOFTBREQ7W {
_SOFTBREQ7W { w: self }
}
#[doc = "Bit 8 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq8(&mut self) -> _SOFTBREQ8W {
_SOFTBREQ8W { w: self }
}
#[doc = "Bit 9 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq9(&mut self) -> _SOFTBREQ9W {
_SOFTBREQ9W { w: self }
}
#[doc = "Bit 10 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq10(&mut self) -> _SOFTBREQ10W {
_SOFTBREQ10W { w: self }
}
#[doc = "Bit 11 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq11(&mut self) -> _SOFTBREQ11W {
_SOFTBREQ11W { w: self }
}
#[doc = "Bit 12 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq12(&mut self) -> _SOFTBREQ12W {
_SOFTBREQ12W { w: self }
}
#[doc = "Bit 13 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq13(&mut self) -> _SOFTBREQ13W {
_SOFTBREQ13W { w: self }
}
#[doc = "Bit 14 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq14(&mut self) -> _SOFTBREQ14W {
_SOFTBREQ14W { w: self }
}
#[doc = "Bit 15 - Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line."]
#[inline]
pub fn softbreq15(&mut self) -> _SOFTBREQ15W {
_SOFTBREQ15W { w: self }
}
}
}
#[doc = "DMA Software Single Request Register"]
pub struct SOFTSREQ {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Software Single Request Register"]
pub mod softsreq {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOFTSREQ {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ0R {
bits: bool,
}
impl SOFTSREQ0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ1R {
bits: bool,
}
impl SOFTSREQ1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ2R {
bits: bool,
}
impl SOFTSREQ2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ3R {
bits: bool,
}
impl SOFTSREQ3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ4R {
bits: bool,
}
impl SOFTSREQ4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ5R {
bits: bool,
}
impl SOFTSREQ5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ6R {
bits: bool,
}
impl SOFTSREQ6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ7R {
bits: bool,
}
impl SOFTSREQ7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ8R {
bits: bool,
}
impl SOFTSREQ8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ9R {
bits: bool,
}
impl SOFTSREQ9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ10R {
bits: bool,
}
impl SOFTSREQ10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ11R {
bits: bool,
}
impl SOFTSREQ11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ12R {
bits: bool,
}
impl SOFTSREQ12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ13R {
bits: bool,
}
impl SOFTSREQ13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ14R {
bits: bool,
}
impl SOFTSREQ14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTSREQ15R {
bits: bool,
}
impl SOFTSREQ15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ0W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ1W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ2W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ3W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ4W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ5W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ6W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ7W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ8W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ9W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ10W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ11W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ12W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ13W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ14W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTSREQ15W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTSREQ15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq0(&self) -> SOFTSREQ0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ0R { bits }
}
#[doc = "Bit 1 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq1(&self) -> SOFTSREQ1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ1R { bits }
}
#[doc = "Bit 2 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq2(&self) -> SOFTSREQ2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ2R { bits }
}
#[doc = "Bit 3 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq3(&self) -> SOFTSREQ3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ3R { bits }
}
#[doc = "Bit 4 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq4(&self) -> SOFTSREQ4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ4R { bits }
}
#[doc = "Bit 5 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq5(&self) -> SOFTSREQ5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ5R { bits }
}
#[doc = "Bit 6 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq6(&self) -> SOFTSREQ6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ6R { bits }
}
#[doc = "Bit 7 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq7(&self) -> SOFTSREQ7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ7R { bits }
}
#[doc = "Bit 8 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq8(&self) -> SOFTSREQ8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ8R { bits }
}
#[doc = "Bit 9 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq9(&self) -> SOFTSREQ9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ9R { bits }
}
#[doc = "Bit 10 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq10(&self) -> SOFTSREQ10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ10R { bits }
}
#[doc = "Bit 11 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq11(&self) -> SOFTSREQ11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ11R { bits }
}
#[doc = "Bit 12 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq12(&self) -> SOFTSREQ12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ12R { bits }
}
#[doc = "Bit 13 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq13(&self) -> SOFTSREQ13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ13R { bits }
}
#[doc = "Bit 14 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq14(&self) -> SOFTSREQ14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ14R { bits }
}
#[doc = "Bit 15 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq15(&self) -> SOFTSREQ15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTSREQ15R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq0(&mut self) -> _SOFTSREQ0W {
_SOFTSREQ0W { w: self }
}
#[doc = "Bit 1 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq1(&mut self) -> _SOFTSREQ1W {
_SOFTSREQ1W { w: self }
}
#[doc = "Bit 2 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq2(&mut self) -> _SOFTSREQ2W {
_SOFTSREQ2W { w: self }
}
#[doc = "Bit 3 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq3(&mut self) -> _SOFTSREQ3W {
_SOFTSREQ3W { w: self }
}
#[doc = "Bit 4 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq4(&mut self) -> _SOFTSREQ4W {
_SOFTSREQ4W { w: self }
}
#[doc = "Bit 5 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq5(&mut self) -> _SOFTSREQ5W {
_SOFTSREQ5W { w: self }
}
#[doc = "Bit 6 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq6(&mut self) -> _SOFTSREQ6W {
_SOFTSREQ6W { w: self }
}
#[doc = "Bit 7 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq7(&mut self) -> _SOFTSREQ7W {
_SOFTSREQ7W { w: self }
}
#[doc = "Bit 8 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq8(&mut self) -> _SOFTSREQ8W {
_SOFTSREQ8W { w: self }
}
#[doc = "Bit 9 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq9(&mut self) -> _SOFTSREQ9W {
_SOFTSREQ9W { w: self }
}
#[doc = "Bit 10 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq10(&mut self) -> _SOFTSREQ10W {
_SOFTSREQ10W { w: self }
}
#[doc = "Bit 11 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq11(&mut self) -> _SOFTSREQ11W {
_SOFTSREQ11W { w: self }
}
#[doc = "Bit 12 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq12(&mut self) -> _SOFTSREQ12W {
_SOFTSREQ12W { w: self }
}
#[doc = "Bit 13 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq13(&mut self) -> _SOFTSREQ13W {
_SOFTSREQ13W { w: self }
}
#[doc = "Bit 14 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq14(&mut self) -> _SOFTSREQ14W {
_SOFTSREQ14W { w: self }
}
#[doc = "Bit 15 - Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line."]
#[inline]
pub fn softsreq15(&mut self) -> _SOFTSREQ15W {
_SOFTSREQ15W { w: self }
}
}
}
#[doc = "DMA Software Last Burst Request Register"]
pub struct SOFTLBREQ {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Software Last Burst Request Register"]
pub mod softlbreq {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOFTLBREQ {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ0R {
bits: bool,
}
impl SOFTLBREQ0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ1R {
bits: bool,
}
impl SOFTLBREQ1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ2R {
bits: bool,
}
impl SOFTLBREQ2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ3R {
bits: bool,
}
impl SOFTLBREQ3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ4R {
bits: bool,
}
impl SOFTLBREQ4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ5R {
bits: bool,
}
impl SOFTLBREQ5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ6R {
bits: bool,
}
impl SOFTLBREQ6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ7R {
bits: bool,
}
impl SOFTLBREQ7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ8R {
bits: bool,
}
impl SOFTLBREQ8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ9R {
bits: bool,
}
impl SOFTLBREQ9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ10R {
bits: bool,
}
impl SOFTLBREQ10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ11R {
bits: bool,
}
impl SOFTLBREQ11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ12R {
bits: bool,
}
impl SOFTLBREQ12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ13R {
bits: bool,
}
impl SOFTLBREQ13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ14R {
bits: bool,
}
impl SOFTLBREQ14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLBREQ15R {
bits: bool,
}
impl SOFTLBREQ15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ0W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ1W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ2W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ3W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ4W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ5W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ6W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ7W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ8W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ9W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ10W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ11W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ12W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ13W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ14W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLBREQ15W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLBREQ15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq0(&self) -> SOFTLBREQ0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ0R { bits }
}
#[doc = "Bit 1 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq1(&self) -> SOFTLBREQ1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ1R { bits }
}
#[doc = "Bit 2 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq2(&self) -> SOFTLBREQ2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ2R { bits }
}
#[doc = "Bit 3 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq3(&self) -> SOFTLBREQ3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ3R { bits }
}
#[doc = "Bit 4 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq4(&self) -> SOFTLBREQ4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ4R { bits }
}
#[doc = "Bit 5 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq5(&self) -> SOFTLBREQ5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ5R { bits }
}
#[doc = "Bit 6 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq6(&self) -> SOFTLBREQ6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ6R { bits }
}
#[doc = "Bit 7 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq7(&self) -> SOFTLBREQ7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ7R { bits }
}
#[doc = "Bit 8 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq8(&self) -> SOFTLBREQ8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ8R { bits }
}
#[doc = "Bit 9 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq9(&self) -> SOFTLBREQ9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ9R { bits }
}
#[doc = "Bit 10 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq10(&self) -> SOFTLBREQ10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ10R { bits }
}
#[doc = "Bit 11 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq11(&self) -> SOFTLBREQ11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ11R { bits }
}
#[doc = "Bit 12 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq12(&self) -> SOFTLBREQ12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ12R { bits }
}
#[doc = "Bit 13 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq13(&self) -> SOFTLBREQ13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ13R { bits }
}
#[doc = "Bit 14 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq14(&self) -> SOFTLBREQ14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ14R { bits }
}
#[doc = "Bit 15 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq15(&self) -> SOFTLBREQ15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLBREQ15R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq0(&mut self) -> _SOFTLBREQ0W {
_SOFTLBREQ0W { w: self }
}
#[doc = "Bit 1 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq1(&mut self) -> _SOFTLBREQ1W {
_SOFTLBREQ1W { w: self }
}
#[doc = "Bit 2 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq2(&mut self) -> _SOFTLBREQ2W {
_SOFTLBREQ2W { w: self }
}
#[doc = "Bit 3 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq3(&mut self) -> _SOFTLBREQ3W {
_SOFTLBREQ3W { w: self }
}
#[doc = "Bit 4 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq4(&mut self) -> _SOFTLBREQ4W {
_SOFTLBREQ4W { w: self }
}
#[doc = "Bit 5 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq5(&mut self) -> _SOFTLBREQ5W {
_SOFTLBREQ5W { w: self }
}
#[doc = "Bit 6 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq6(&mut self) -> _SOFTLBREQ6W {
_SOFTLBREQ6W { w: self }
}
#[doc = "Bit 7 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq7(&mut self) -> _SOFTLBREQ7W {
_SOFTLBREQ7W { w: self }
}
#[doc = "Bit 8 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq8(&mut self) -> _SOFTLBREQ8W {
_SOFTLBREQ8W { w: self }
}
#[doc = "Bit 9 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq9(&mut self) -> _SOFTLBREQ9W {
_SOFTLBREQ9W { w: self }
}
#[doc = "Bit 10 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq10(&mut self) -> _SOFTLBREQ10W {
_SOFTLBREQ10W { w: self }
}
#[doc = "Bit 11 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq11(&mut self) -> _SOFTLBREQ11W {
_SOFTLBREQ11W { w: self }
}
#[doc = "Bit 12 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq12(&mut self) -> _SOFTLBREQ12W {
_SOFTLBREQ12W { w: self }
}
#[doc = "Bit 13 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq13(&mut self) -> _SOFTLBREQ13W {
_SOFTLBREQ13W { w: self }
}
#[doc = "Bit 14 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq14(&mut self) -> _SOFTLBREQ14W {
_SOFTLBREQ14W { w: self }
}
#[doc = "Bit 15 - Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line."]
#[inline]
pub fn softlbreq15(&mut self) -> _SOFTLBREQ15W {
_SOFTLBREQ15W { w: self }
}
}
}
#[doc = "DMA Software Last Single Request Register"]
pub struct SOFTLSREQ {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Software Last Single Request Register"]
pub mod softlsreq {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOFTLSREQ {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ0R {
bits: bool,
}
impl SOFTLSREQ0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ1R {
bits: bool,
}
impl SOFTLSREQ1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ2R {
bits: bool,
}
impl SOFTLSREQ2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ3R {
bits: bool,
}
impl SOFTLSREQ3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ4R {
bits: bool,
}
impl SOFTLSREQ4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ5R {
bits: bool,
}
impl SOFTLSREQ5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ6R {
bits: bool,
}
impl SOFTLSREQ6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ7R {
bits: bool,
}
impl SOFTLSREQ7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ8R {
bits: bool,
}
impl SOFTLSREQ8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ9R {
bits: bool,
}
impl SOFTLSREQ9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ10R {
bits: bool,
}
impl SOFTLSREQ10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ11R {
bits: bool,
}
impl SOFTLSREQ11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ12R {
bits: bool,
}
impl SOFTLSREQ12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ13R {
bits: bool,
}
impl SOFTLSREQ13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ14R {
bits: bool,
}
impl SOFTLSREQ14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SOFTLSREQ15R {
bits: bool,
}
impl SOFTLSREQ15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ0W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ1W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ2W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ3W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ4W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ5W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ6W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ7W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ8W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ9W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ10W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ11W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ12W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ13W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ14W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SOFTLSREQ15W<'a> {
w: &'a mut W,
}
impl<'a> _SOFTLSREQ15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq0(&self) -> SOFTLSREQ0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ0R { bits }
}
#[doc = "Bit 1 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq1(&self) -> SOFTLSREQ1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ1R { bits }
}
#[doc = "Bit 2 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq2(&self) -> SOFTLSREQ2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ2R { bits }
}
#[doc = "Bit 3 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq3(&self) -> SOFTLSREQ3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ3R { bits }
}
#[doc = "Bit 4 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq4(&self) -> SOFTLSREQ4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ4R { bits }
}
#[doc = "Bit 5 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq5(&self) -> SOFTLSREQ5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ5R { bits }
}
#[doc = "Bit 6 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq6(&self) -> SOFTLSREQ6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ6R { bits }
}
#[doc = "Bit 7 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq7(&self) -> SOFTLSREQ7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ7R { bits }
}
#[doc = "Bit 8 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq8(&self) -> SOFTLSREQ8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ8R { bits }
}
#[doc = "Bit 9 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq9(&self) -> SOFTLSREQ9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ9R { bits }
}
#[doc = "Bit 10 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq10(&self) -> SOFTLSREQ10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ10R { bits }
}
#[doc = "Bit 11 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq11(&self) -> SOFTLSREQ11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ11R { bits }
}
#[doc = "Bit 12 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq12(&self) -> SOFTLSREQ12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ12R { bits }
}
#[doc = "Bit 13 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq13(&self) -> SOFTLSREQ13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ13R { bits }
}
#[doc = "Bit 14 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq14(&self) -> SOFTLSREQ14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ14R { bits }
}
#[doc = "Bit 15 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq15(&self) -> SOFTLSREQ15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SOFTLSREQ15R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq0(&mut self) -> _SOFTLSREQ0W {
_SOFTLSREQ0W { w: self }
}
#[doc = "Bit 1 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq1(&mut self) -> _SOFTLSREQ1W {
_SOFTLSREQ1W { w: self }
}
#[doc = "Bit 2 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq2(&mut self) -> _SOFTLSREQ2W {
_SOFTLSREQ2W { w: self }
}
#[doc = "Bit 3 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq3(&mut self) -> _SOFTLSREQ3W {
_SOFTLSREQ3W { w: self }
}
#[doc = "Bit 4 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq4(&mut self) -> _SOFTLSREQ4W {
_SOFTLSREQ4W { w: self }
}
#[doc = "Bit 5 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq5(&mut self) -> _SOFTLSREQ5W {
_SOFTLSREQ5W { w: self }
}
#[doc = "Bit 6 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq6(&mut self) -> _SOFTLSREQ6W {
_SOFTLSREQ6W { w: self }
}
#[doc = "Bit 7 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq7(&mut self) -> _SOFTLSREQ7W {
_SOFTLSREQ7W { w: self }
}
#[doc = "Bit 8 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq8(&mut self) -> _SOFTLSREQ8W {
_SOFTLSREQ8W { w: self }
}
#[doc = "Bit 9 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq9(&mut self) -> _SOFTLSREQ9W {
_SOFTLSREQ9W { w: self }
}
#[doc = "Bit 10 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq10(&mut self) -> _SOFTLSREQ10W {
_SOFTLSREQ10W { w: self }
}
#[doc = "Bit 11 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq11(&mut self) -> _SOFTLSREQ11W {
_SOFTLSREQ11W { w: self }
}
#[doc = "Bit 12 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq12(&mut self) -> _SOFTLSREQ12W {
_SOFTLSREQ12W { w: self }
}
#[doc = "Bit 13 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq13(&mut self) -> _SOFTLSREQ13W {
_SOFTLSREQ13W { w: self }
}
#[doc = "Bit 14 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq14(&mut self) -> _SOFTLSREQ14W {
_SOFTLSREQ14W { w: self }
}
#[doc = "Bit 15 - Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line."]
#[inline]
pub fn softlsreq15(&mut self) -> _SOFTLSREQ15W {
_SOFTLSREQ15W { w: self }
}
}
}
#[doc = "DMA Configuration Register"]
pub struct DMA_CONFIG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Configuration Register"]
pub mod dma_config {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMA_CONFIG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ER {
bits: bool,
}
impl ER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct MR {
bits: bool,
}
impl MR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _EW<'a> {
w: &'a mut W,
}
impl<'a> _EW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MW<'a> {
w: &'a mut W,
}
impl<'a> _MW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled."]
#[inline]
pub fn e(&self) -> ER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ER { bits }
}
#[doc = "Bit 1 - AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode."]
#[inline]
pub fn m(&self) -> MR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
MR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled."]
#[inline]
pub fn e(&mut self) -> _EW {
_EW { w: self }
}
#[doc = "Bit 1 - AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode."]
#[inline]
pub fn m(&mut self) -> _MW {
_MW { w: self }
}
}
}
#[doc = "DMA Synchronization Register"]
pub struct SYNC {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Synchronization Register"]
pub mod sync {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SYNC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC0R {
bits: bool,
}
impl DMACSYNC0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC1R {
bits: bool,
}
impl DMACSYNC1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC2R {
bits: bool,
}
impl DMACSYNC2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC3R {
bits: bool,
}
impl DMACSYNC3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC4R {
bits: bool,
}
impl DMACSYNC4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC5R {
bits: bool,
}
impl DMACSYNC5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC6R {
bits: bool,
}
impl DMACSYNC6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC7R {
bits: bool,
}
impl DMACSYNC7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC8R {
bits: bool,
}
impl DMACSYNC8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC9R {
bits: bool,
}
impl DMACSYNC9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC10R {
bits: bool,
}
impl DMACSYNC10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC11R {
bits: bool,
}
impl DMACSYNC11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC12R {
bits: bool,
}
impl DMACSYNC12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC13R {
bits: bool,
}
impl DMACSYNC13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC14R {
bits: bool,
}
impl DMACSYNC14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DMACSYNC15R {
bits: bool,
}
impl DMACSYNC15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC0W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC1W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC2W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC3W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC4W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC5W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC6W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC7W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC8W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC9W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC10W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC11W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC12W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC13W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC14W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DMACSYNC15W<'a> {
w: &'a mut W,
}
impl<'a> _DMACSYNC15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync0(&self) -> DMACSYNC0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC0R { bits }
}
#[doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync1(&self) -> DMACSYNC1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC1R { bits }
}
#[doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync2(&self) -> DMACSYNC2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC2R { bits }
}
#[doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync3(&self) -> DMACSYNC3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC3R { bits }
}
#[doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync4(&self) -> DMACSYNC4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC4R { bits }
}
#[doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync5(&self) -> DMACSYNC5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC5R { bits }
}
#[doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync6(&self) -> DMACSYNC6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC6R { bits }
}
#[doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync7(&self) -> DMACSYNC7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC7R { bits }
}
#[doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync8(&self) -> DMACSYNC8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC8R { bits }
}
#[doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync9(&self) -> DMACSYNC9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC9R { bits }
}
#[doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync10(&self) -> DMACSYNC10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC10R { bits }
}
#[doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync11(&self) -> DMACSYNC11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC11R { bits }
}
#[doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync12(&self) -> DMACSYNC12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC12R { bits }
}
#[doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync13(&self) -> DMACSYNC13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC13R { bits }
}
#[doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync14(&self) -> DMACSYNC14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC14R { bits }
}
#[doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync15(&self) -> DMACSYNC15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DMACSYNC15R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync0(&mut self) -> _DMACSYNC0W {
_DMACSYNC0W { w: self }
}
#[doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync1(&mut self) -> _DMACSYNC1W {
_DMACSYNC1W { w: self }
}
#[doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync2(&mut self) -> _DMACSYNC2W {
_DMACSYNC2W { w: self }
}
#[doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync3(&mut self) -> _DMACSYNC3W {
_DMACSYNC3W { w: self }
}
#[doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync4(&mut self) -> _DMACSYNC4W {
_DMACSYNC4W { w: self }
}
#[doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync5(&mut self) -> _DMACSYNC5W {
_DMACSYNC5W { w: self }
}
#[doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync6(&mut self) -> _DMACSYNC6W {
_DMACSYNC6W { w: self }
}
#[doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync7(&mut self) -> _DMACSYNC7W {
_DMACSYNC7W { w: self }
}
#[doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync8(&mut self) -> _DMACSYNC8W {
_DMACSYNC8W { w: self }
}
#[doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync9(&mut self) -> _DMACSYNC9W {
_DMACSYNC9W { w: self }
}
#[doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync10(&mut self) -> _DMACSYNC10W {
_DMACSYNC10W { w: self }
}
#[doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync11(&mut self) -> _DMACSYNC11W {
_DMACSYNC11W { w: self }
}
#[doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync12(&mut self) -> _DMACSYNC12W {
_DMACSYNC12W { w: self }
}
#[doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync13(&mut self) -> _DMACSYNC13W {
_DMACSYNC13W { w: self }
}
#[doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync14(&mut self) -> _DMACSYNC14W {
_DMACSYNC14W { w: self }
}
#[doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
#[inline]
pub fn dmacsync15(&mut self) -> _DMACSYNC15W {
_DMACSYNC15W { w: self }
}
}
}
#[doc = "DMA Channel 0 Source Address Register"]
pub struct SRCADDR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Channel 0 Source Address Register"]
pub mod srcaddr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SRCADDR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SRCADDRR {
bits: u32,
}
impl SRCADDRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SRCADDRW<'a> {
w: &'a mut W,
}
impl<'a> _SRCADDRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - DMA source address. Reading this register will return the current source address."]
#[inline]
pub fn srcaddr(&self) -> SRCADDRR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
SRCADDRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - DMA source address. Reading this register will return the current source address."]
#[inline]
pub fn srcaddr(&mut self) -> _SRCADDRW {
_SRCADDRW { w: self }
}
}
}
#[doc = "DMA Channel 0 Destination Address Register"]
pub struct DESTADDR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Channel 0 Destination Address Register"]
pub mod destaddr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DESTADDR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DESTADDRR {
bits: u32,
}
impl DESTADDRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DESTADDRW<'a> {
w: &'a mut W,
}
impl<'a> _DESTADDRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - DMA Destination address. Reading this register will return the current destination address."]
#[inline]
pub fn destaddr(&self) -> DESTADDRR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
DESTADDRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - DMA Destination address. Reading this register will return the current destination address."]
#[inline]
pub fn destaddr(&mut self) -> _DESTADDRW {
_DESTADDRW { w: self }
}
}
}
#[doc = "DMA Channel 0 Linked List Item Register"]
pub struct LLI {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Channel 0 Linked List Item Register"]
pub mod lli {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::LLI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct LLIR {
bits: u32,
}
impl LLIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _LLIW<'a> {
w: &'a mut W,
}
impl<'a> _LLIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 2:31 - Linked list item. Bits \\[31:2\\] of the address for the next LLI. Address bits \\[1:0\\] are 0."]
#[inline]
pub fn lli(&self) -> LLIR {
let bits = {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u32
};
LLIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 2:31 - Linked list item. Bits \\[31:2\\] of the address for the next LLI. Address bits \\[1:0\\] are 0."]
#[inline]
pub fn lli(&mut self) -> _LLIW {
_LLIW { w: self }
}
}
}
#[doc = "DMA Channel 0 Control Register"]
pub struct CONTROL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Channel 0 Control Register"]
pub mod control {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CONTROL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TRANSFERSIZER {
bits: u16,
}
impl TRANSFERSIZER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SBSIZER {
bits: u8,
}
impl SBSIZER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DBSIZER {
bits: u8,
}
impl DBSIZER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SWIDTHR {
bits: u8,
}
impl SWIDTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DWIDTHR {
bits: u8,
}
impl DWIDTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SIR {
bits: bool,
}
impl SIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DIR {
bits: bool,
}
impl DIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PROT1R {
bits: bool,
}
impl PROT1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PROT2R {
bits: bool,
}
impl PROT2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PROT3R {
bits: bool,
}
impl PROT3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct IR {
bits: bool,
}
impl IR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _TRANSFERSIZEW<'a> {
w: &'a mut W,
}
impl<'a> _TRANSFERSIZEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SBSIZEW<'a> {
w: &'a mut W,
}
impl<'a> _SBSIZEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DBSIZEW<'a> {
w: &'a mut W,
}
impl<'a> _DBSIZEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SWIDTHW<'a> {
w: &'a mut W,
}
impl<'a> _SWIDTHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DWIDTHW<'a> {
w: &'a mut W,
}
impl<'a> _DWIDTHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SIW<'a> {
w: &'a mut W,
}
impl<'a> _SIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DIW<'a> {
w: &'a mut W,
}
impl<'a> _DIW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PROT1W<'a> {
w: &'a mut W,
}
impl<'a> _PROT1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PROT2W<'a> {
w: &'a mut W,
}
impl<'a> _PROT2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PROT3W<'a> {
w: &'a mut W,
}
impl<'a> _PROT3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IW<'a> {
w: &'a mut W,
}
impl<'a> _IW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller."]
#[inline]
pub fn transfersize(&self) -> TRANSFERSIZER {
let bits = {
const MASK: u16 = 0x0fff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TRANSFERSIZER { bits }
}
#[doc = "Bits 12:14 - Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256"]
#[inline]
pub fn sbsize(&self) -> SBSIZER {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SBSIZER { bits }
}
#[doc = "Bits 15:17 - Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256"]
#[inline]
pub fn dbsize(&self) -> DBSIZER {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DBSIZER { bits }
}
#[doc = "Bits 18:20 - Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved"]
#[inline]
pub fn swidth(&self) -> SWIDTHR {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SWIDTHR { bits }
}
#[doc = "Bits 21:23 - Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved"]
#[inline]
pub fn dwidth(&self) -> DWIDTHR {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DWIDTHR { bits }
}
#[doc = "Bit 26 - Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer."]
#[inline]
pub fn si(&self) -> SIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SIR { bits }
}
#[doc = "Bit 27 - Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer."]
#[inline]
pub fn di(&self) -> DIR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DIR { bits }
}
#[doc = "Bit 28 - This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode."]
#[inline]
pub fn prot1(&self) -> PROT1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PROT1R { bits }
}
#[doc = "Bit 29 - This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable."]
#[inline]
pub fn prot2(&self) -> PROT2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PROT2R { bits }
}
#[doc = "Bit 30 - This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable."]
#[inline]
pub fn prot3(&self) -> PROT3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PROT3R { bits }
}
#[doc = "Bit 31 - Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled."]
#[inline]
pub fn i(&self) -> IR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller."]
#[inline]
pub fn transfersize(&mut self) -> _TRANSFERSIZEW {
_TRANSFERSIZEW { w: self }
}
#[doc = "Bits 12:14 - Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256"]
#[inline]
pub fn sbsize(&mut self) -> _SBSIZEW {
_SBSIZEW { w: self }
}
#[doc = "Bits 15:17 - Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256"]
#[inline]
pub fn dbsize(&mut self) -> _DBSIZEW {
_DBSIZEW { w: self }
}
#[doc = "Bits 18:20 - Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved"]
#[inline]
pub fn swidth(&mut self) -> _SWIDTHW {
_SWIDTHW { w: self }
}
#[doc = "Bits 21:23 - Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved"]
#[inline]
pub fn dwidth(&mut self) -> _DWIDTHW {
_DWIDTHW { w: self }
}
#[doc = "Bit 26 - Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer."]
#[inline]
pub fn si(&mut self) -> _SIW {
_SIW { w: self }
}
#[doc = "Bit 27 - Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer."]
#[inline]
pub fn di(&mut self) -> _DIW {
_DIW { w: self }
}
#[doc = "Bit 28 - This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode."]
#[inline]
pub fn prot1(&mut self) -> _PROT1W {
_PROT1W { w: self }
}
#[doc = "Bit 29 - This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable."]
#[inline]
pub fn prot2(&mut self) -> _PROT2W {
_PROT2W { w: self }
}
#[doc = "Bit 30 - This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable."]
#[inline]
pub fn prot3(&mut self) -> _PROT3W {
_PROT3W { w: self }
}
#[doc = "Bit 31 - Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled."]
#[inline]
pub fn i(&mut self) -> _IW {
_IW { w: self }
}
}
}
#[doc = "DMA Channel 0 Configuration Register\\[1\\]"]
pub struct DMA0_CONFIG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA Channel 0 Configuration Register\\[1\\]"]
pub mod dma0_config {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMA0_CONFIG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ER {
bits: bool,
}
impl ER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SRCPERIPHERALR {
bits: u8,
}
impl SRCPERIPHERALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DESTPERIPHERALR {
bits: u8,
}
impl DESTPERIPHERALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TRANSFERTYPER {
bits: u8,
}
impl TRANSFERTYPER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct IER {
bits: bool,
}
impl IER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ITCR {
bits: bool,
}
impl ITCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct LR {
bits: bool,
}
impl LR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AR {
bits: bool,
}
impl AR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct HR {
bits: bool,
}
impl HR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _EW<'a> {
w: &'a mut W,
}
impl<'a> _EW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SRCPERIPHERALW<'a> {
w: &'a mut W,
}
impl<'a> _SRCPERIPHERALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DESTPERIPHERALW<'a> {
w: &'a mut W,
}
impl<'a> _DESTPERIPHERALW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TRANSFERTYPEW<'a> {
w: &'a mut W,
}
impl<'a> _TRANSFERTYPEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x07;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _IEW<'a> {
w: &'a mut W,
}
impl<'a> _IEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ITCW<'a> {
w: &'a mut W,
}
impl<'a> _ITCW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _LW<'a> {
w: &'a mut W,
}
impl<'a> _LW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AW<'a> {
w: &'a mut W,
}
impl<'a> _AW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HW<'a> {
w: &'a mut W,
}
impl<'a> _HW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared."]
#[inline]
pub fn e(&self) -> ER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ER { bits }
}
#[doc = "Bits 1:5 - Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification."]
#[inline]
pub fn srcperipheral(&self) -> SRCPERIPHERALR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SRCPERIPHERALR { bits }
}
#[doc = "Bits 6:10 - Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification."]
#[inline]
pub fn destperipheral(&self) -> DESTPERIPHERALR {
let bits = {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DESTPERIPHERALR { bits }
}
#[doc = "Bits 11:13 - This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field."]
#[inline]
pub fn transfertype(&self) -> TRANSFERTYPER {
let bits = {
const MASK: u8 = 0x07;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TRANSFERTYPER { bits }
}
#[doc = "Bit 14 - Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel."]
#[inline]
pub fn ie(&self) -> IER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
IER { bits }
}
#[doc = "Bit 15 - Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel."]
#[inline]
pub fn itc(&self) -> ITCR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ITCR { bits }
}
#[doc = "Bit 16 - Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x."]
#[inline]
pub fn l(&self) -> LR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
LR { bits }
}
#[doc = "Bit 17 - Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit."]
#[inline]
pub fn a(&self) -> AR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AR { bits }
}
#[doc = "Bit 18 - Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel."]
#[inline]
pub fn h(&self) -> HR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
HR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared."]
#[inline]
pub fn e(&mut self) -> _EW {
_EW { w: self }
}
#[doc = "Bits 1:5 - Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification."]
#[inline]
pub fn srcperipheral(&mut self) -> _SRCPERIPHERALW {
_SRCPERIPHERALW { w: self }
}
#[doc = "Bits 6:10 - Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification."]
#[inline]
pub fn destperipheral(&mut self) -> _DESTPERIPHERALW {
_DESTPERIPHERALW { w: self }
}
#[doc = "Bits 11:13 - This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field."]
#[inline]
pub fn transfertype(&mut self) -> _TRANSFERTYPEW {
_TRANSFERTYPEW { w: self }
}
#[doc = "Bit 14 - Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel."]
#[inline]
pub fn ie(&mut self) -> _IEW {
_IEW { w: self }
}
#[doc = "Bit 15 - Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel."]
#[inline]
pub fn itc(&mut self) -> _ITCW {
_ITCW { w: self }
}
#[doc = "Bit 16 - Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x."]
#[inline]
pub fn l(&mut self) -> _LW {
_LW { w: self }
}
#[doc = "Bit 17 - Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit."]
#[inline]
pub fn a(&mut self) -> _AW {
_AW { w: self }
}
#[doc = "Bit 18 - Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel."]
#[inline]
pub fn h(&mut self) -> _HW {
_HW { w: self }
}
}
}
}
#[doc = "USB device/host/OTG controller"]
pub struct USB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for USB {}
impl USB {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const usb::RegisterBlock {
0x5000_8000 as *const _
}
}
impl Deref for USB {
type Target = usb::RegisterBlock;
fn deref(&self) -> &usb::RegisterBlock {
unsafe { &*USB::ptr() }
}
}
#[doc = "USB device/host/OTG controller"]
pub mod usb {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 220usize],
#[doc = "0xdc - USB Receive Packet Length"]
pub rxplen: RXPLEN,
_reserved1: [u8; 32usize],
#[doc = "0x100 - OTG Interrupt Status"]
pub intst: INTST,
#[doc = "0x104 - OTG Interrupt Enable"]
pub inten: INTEN,
#[doc = "0x108 - OTG Interrupt Set"]
pub intset: INTSET,
#[doc = "0x10c - OTG Interrupt Clear"]
pub intclr: INTCLR,
#[doc = "0x110 - OTG Status and Control and USB port select"]
pub stctrl: STCTRL,
#[doc = "0x114 - OTG Timer"]
pub tmr: TMR,
_reserved7: [u8; 232usize],
#[doc = "0x200 - USB Device Interrupt Status"]
pub devintst: DEVINTST,
#[doc = "0x204 - USB Device Interrupt Enable"]
pub devinten: DEVINTEN,
#[doc = "0x208 - USB Device Interrupt Clear"]
pub devintclr: DEVINTCLR,
#[doc = "0x20c - USB Device Interrupt Set"]
pub devintset: DEVINTSET,
#[doc = "0x210 - USB Command Code"]
pub cmdcode: CMDCODE,
#[doc = "0x214 - USB Command Data"]
pub cmddata: CMDDATA,
#[doc = "0x218 - USB Receive Data"]
pub rxdata: RXDATA,
#[doc = "0x21c - USB Transmit Data"]
pub txdata: TXDATA,
_reserved15: [u8; 4usize],
#[doc = "0x224 - USB Transmit Packet Length"]
pub txplen: TXPLEN,
#[doc = "0x228 - USB Control"]
pub ctrl: CTRL,
#[doc = "0x22c - USB Device Interrupt Priority"]
pub devintpri: DEVINTPRI,
#[doc = "0x230 - USB Endpoint Interrupt Status"]
pub epintst: EPINTST,
#[doc = "0x234 - USB Endpoint Interrupt Enable"]
pub epinten: EPINTEN,
#[doc = "0x238 - USB Endpoint Interrupt Clear"]
pub epintclr: EPINTCLR,
#[doc = "0x23c - USB Endpoint Interrupt Set"]
pub epintset: EPINTSET,
#[doc = "0x240 - USB Endpoint Priority"]
pub epintpri: EPINTPRI,
#[doc = "0x244 - USB Realize Endpoint"]
pub reep: REEP,
#[doc = "0x248 - USB Endpoint Index"]
pub epind: EPIND,
#[doc = "0x24c - USB MaxPacketSize"]
pub maxpsize: MAXPSIZE,
#[doc = "0x250 - USB DMA Request Status"]
pub dmarst: DMARST,
#[doc = "0x254 - USB DMA Request Clear"]
pub dmarclr: DMARCLR,
#[doc = "0x258 - USB DMA Request Set"]
pub dmarset: DMARSET,
_reserved29: [u8; 36usize],
#[doc = "0x280 - USB UDCA Head"]
pub udcah: UDCAH,
#[doc = "0x284 - USB Endpoint DMA Status"]
pub epdmast: EPDMAST,
#[doc = "0x288 - USB Endpoint DMA Enable"]
pub epdmaen: EPDMAEN,
#[doc = "0x28c - USB Endpoint DMA Disable"]
pub epdmadis: EPDMADIS,
#[doc = "0x290 - USB DMA Interrupt Status"]
pub dmaintst: DMAINTST,
#[doc = "0x294 - USB DMA Interrupt Enable"]
pub dmainten: DMAINTEN,
_reserved35: [u8; 8usize],
#[doc = "0x2a0 - USB End of Transfer Interrupt Status"]
pub eotintst: EOTINTST,
#[doc = "0x2a4 - USB End of Transfer Interrupt Clear"]
pub eotintclr: EOTINTCLR,
#[doc = "0x2a8 - USB End of Transfer Interrupt Set"]
pub eotintset: EOTINTSET,
#[doc = "0x2ac - USB New DD Request Interrupt Status"]
pub nddrintst: NDDRINTST,
#[doc = "0x2b0 - USB New DD Request Interrupt Clear"]
pub nddrintclr: NDDRINTCLR,
#[doc = "0x2b4 - USB New DD Request Interrupt Set"]
pub nddrintset: NDDRINTSET,
#[doc = "0x2b8 - USB System Error Interrupt Status"]
pub syserrintst: SYSERRINTST,
#[doc = "0x2bc - USB System Error Interrupt Clear"]
pub syserrintclr: SYSERRINTCLR,
#[doc = "0x2c0 - USB System Error Interrupt Set"]
pub syserrintset: SYSERRINTSET,
_reserved44: [u8; 60usize],
#[doc = "I2C Transmit I2C Receive"]
pub i2c: I2C_UNION,
#[doc = "0x304 - I2C Status"]
pub i2c_sts: I2C_STS,
#[doc = "0x308 - I2C Control"]
pub i2c_ctl: I2C_CTL,
#[doc = "0x30c - I2C Clock High"]
pub i2c_clkhi: I2C_CLKHI,
#[doc = "0x310 - I2C Clock Low"]
pub i2c_clklo: I2C_CLKLO,
_reserved49: [u8; 3296usize],
#[doc = "OTG clock controller USB Clock Control"]
pub otgclkctrl: OTGCLKCTRL_UNION,
#[doc = "OTG clock status USB Clock Status"]
pub otgclkst: OTGCLKST_UNION,
}
#[doc = "I2C Transmit I2C Receive"]
#[repr(C)]
pub union I2C_UNION {
#[doc = "0x300 - I2C Transmit"]
pub i2c_wo: I2C_WO,
#[doc = "0x300 - I2C Receive"]
pub i2c_rx: I2C_RX,
}
#[doc = "OTG clock controller USB Clock Control"]
#[repr(C)]
pub union OTGCLKCTRL_UNION {
#[doc = "0xff4 - OTG clock controller"]
pub otgclkctrl: OTGCLKCTRL,
#[doc = "0xff4 - USB Clock Control"]
pub usbclkctrl: USBCLKCTRL,
}
#[doc = "OTG clock status USB Clock Status"]
#[repr(C)]
pub union OTGCLKST_UNION {
#[doc = "0xff8 - OTG clock status"]
pub otgclkst: OTGCLKST,
#[doc = "0xff8 - USB Clock Status"]
pub usbclkst: USBCLKST,
}
#[doc = "OTG Interrupt Status"]
pub struct INTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG Interrupt Status"]
pub mod intst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::INTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct TMRR {
bits: bool,
}
impl TMRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REMOVE_PUR {
bits: bool,
}
impl REMOVE_PUR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct HNP_FAILURER {
bits: bool,
}
impl HNP_FAILURER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct HNP_SUCCESSR {
bits: bool,
}
impl HNP_SUCCESSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Timer time-out."]
#[inline]
pub fn tmr(&self) -> TMRR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TMRR { bits }
}
#[doc = "Bit 1 - Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor."]
#[inline]
pub fn remove_pu(&self) -> REMOVE_PUR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REMOVE_PUR { bits }
}
#[doc = "Bit 2 - HNP failed. This bit is set by hardware to indicate that the HNP switching has failed."]
#[inline]
pub fn hnp_failure(&self) -> HNP_FAILURER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
HNP_FAILURER { bits }
}
#[doc = "Bit 3 - HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded."]
#[inline]
pub fn hnp_success(&self) -> HNP_SUCCESSR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
HNP_SUCCESSR { bits }
}
}
}
#[doc = "OTG Interrupt Enable"]
pub struct INTEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG Interrupt Enable"]
pub mod inten {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTEN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TMR_ENR {
bits: bool,
}
impl TMR_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct REMOVE_PU_ENR {
bits: bool,
}
impl REMOVE_PU_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct HNP_FAILURE_ENR {
bits: bool,
}
impl HNP_FAILURE_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct HNP_SUCCES_ENR {
bits: bool,
}
impl HNP_SUCCES_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _TMR_ENW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REMOVE_PU_ENW<'a> {
w: &'a mut W,
}
impl<'a> _REMOVE_PU_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HNP_FAILURE_ENW<'a> {
w: &'a mut W,
}
impl<'a> _HNP_FAILURE_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HNP_SUCCES_ENW<'a> {
w: &'a mut W,
}
impl<'a> _HNP_SUCCES_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn tmr_en(&self) -> TMR_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TMR_ENR { bits }
}
#[doc = "Bit 1 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn remove_pu_en(&self) -> REMOVE_PU_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
REMOVE_PU_ENR { bits }
}
#[doc = "Bit 2 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_failure_en(&self) -> HNP_FAILURE_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
HNP_FAILURE_ENR { bits }
}
#[doc = "Bit 3 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_succes_en(&self) -> HNP_SUCCES_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
HNP_SUCCES_ENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn tmr_en(&mut self) -> _TMR_ENW {
_TMR_ENW { w: self }
}
#[doc = "Bit 1 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn remove_pu_en(&mut self) -> _REMOVE_PU_ENW {
_REMOVE_PU_ENW { w: self }
}
#[doc = "Bit 2 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_failure_en(&mut self) -> _HNP_FAILURE_ENW {
_HNP_FAILURE_ENW { w: self }
}
#[doc = "Bit 3 - 1 = enable the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_succes_en(&mut self) -> _HNP_SUCCES_ENW {
_HNP_SUCCES_ENW { w: self }
}
}
}
#[doc = "OTG Interrupt Set"]
pub struct INTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG Interrupt Set"]
pub mod intset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _TMR_SETW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REMOVE_PU_SETW<'a> {
w: &'a mut W,
}
impl<'a> _REMOVE_PU_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HNP_FAILURE_SETW<'a> {
w: &'a mut W,
}
impl<'a> _HNP_FAILURE_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HNP_SUCCES_SETW<'a> {
w: &'a mut W,
}
impl<'a> _HNP_SUCCES_SETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = no effect. 1 = set the corresponding bit in the IntSt register."]
#[inline]
pub fn tmr_set(&mut self) -> _TMR_SETW {
_TMR_SETW { w: self }
}
#[doc = "Bit 1 - 0 = no effect. 1 = set the corresponding bit in the IntSt register."]
#[inline]
pub fn remove_pu_set(&mut self) -> _REMOVE_PU_SETW {
_REMOVE_PU_SETW { w: self }
}
#[doc = "Bit 2 - 0 = no effect. 1 = set the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_failure_set(&mut self) -> _HNP_FAILURE_SETW {
_HNP_FAILURE_SETW { w: self }
}
#[doc = "Bit 3 - 0 = no effect. 1 = set the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_succes_set(&mut self) -> _HNP_SUCCES_SETW {
_HNP_SUCCES_SETW { w: self }
}
}
}
#[doc = "OTG Interrupt Clear"]
pub struct INTCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG Interrupt Clear"]
pub mod intclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::INTCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _TMR_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _REMOVE_PU_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _REMOVE_PU_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HNP_FAILURE_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _HNP_FAILURE_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _HNP_SUCCES_CLRW<'a> {
w: &'a mut W,
}
impl<'a> _HNP_SUCCES_CLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = no effect. 1 = clear the corresponding bit in the IntSt register."]
#[inline]
pub fn tmr_clr(&mut self) -> _TMR_CLRW {
_TMR_CLRW { w: self }
}
#[doc = "Bit 1 - 0 = no effect. 1 = clear the corresponding bit in the IntSt register."]
#[inline]
pub fn remove_pu_clr(&mut self) -> _REMOVE_PU_CLRW {
_REMOVE_PU_CLRW { w: self }
}
#[doc = "Bit 2 - 0 = no effect. 1 = clear the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_failure_clr(&mut self) -> _HNP_FAILURE_CLRW {
_HNP_FAILURE_CLRW { w: self }
}
#[doc = "Bit 3 - 0 = no effect. 1 = clear the corresponding bit in the IntSt register."]
#[inline]
pub fn hnp_succes_clr(&mut self) -> _HNP_SUCCES_CLRW {
_HNP_SUCCES_CLRW { w: self }
}
}
}
#[doc = "OTG Status and Control and USB port select"]
pub struct STCTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG Status and Control and USB port select"]
pub mod stctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::STCTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PORT_FUNCR {
bits: u8,
}
impl PORT_FUNCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TMR_SCALER {
bits: u8,
}
impl TMR_SCALER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct TMR_MODER {
bits: bool,
}
impl TMR_MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TMR_ENR {
bits: bool,
}
impl TMR_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TMR_RSTR {
bits: bool,
}
impl TMR_RSTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct B_HNP_TRACKR {
bits: bool,
}
impl B_HNP_TRACKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct A_HNP_TRACKR {
bits: bool,
}
impl A_HNP_TRACKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PU_REMOVEDR {
bits: bool,
}
impl PU_REMOVEDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TMR_CNTR {
bits: u16,
}
impl TMR_CNTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PORT_FUNCW<'a> {
w: &'a mut W,
}
impl<'a> _PORT_FUNCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TMR_SCALEW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_SCALEW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TMR_MODEW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_MODEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TMR_ENW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TMR_RSTW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_RSTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _B_HNP_TRACKW<'a> {
w: &'a mut W,
}
impl<'a> _B_HNP_TRACKW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _A_HNP_TRACKW<'a> {
w: &'a mut W,
}
impl<'a> _A_HNP_TRACKW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PU_REMOVEDW<'a> {
w: &'a mut W,
}
impl<'a> _PU_REMOVEDW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TMR_CNTW<'a> {
w: &'a mut W,
}
impl<'a> _TMR_CNTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2."]
#[inline]
pub fn port_func(&self) -> PORT_FUNCR {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PORT_FUNCR { bits }
}
#[doc = "Bits 2:3 - Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved"]
#[inline]
pub fn tmr_scale(&self) -> TMR_SCALER {
let bits = {
const MASK: u8 = 0x03;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TMR_SCALER { bits }
}
#[doc = "Bit 4 - Timer mode selection. 0: monoshot 1: free running"]
#[inline]
pub fn tmr_mode(&self) -> TMR_MODER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TMR_MODER { bits }
}
#[doc = "Bit 5 - Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0."]
#[inline]
pub fn tmr_en(&self) -> TMR_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TMR_ENR { bits }
}
#[doc = "Bit 6 - Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled."]
#[inline]
pub fn tmr_rst(&self) -> TMR_RSTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TMR_RSTR { bits }
}
#[doc = "Bit 8 - Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set."]
#[inline]
pub fn b_hnp_track(&self) -> B_HNP_TRACKR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
B_HNP_TRACKR { bits }
}
#[doc = "Bit 9 - Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set."]
#[inline]
pub fn a_hnp_track(&self) -> A_HNP_TRACKR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
A_HNP_TRACKR { bits }
}
#[doc = "Bit 10 - When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set."]
#[inline]
pub fn pu_removed(&self) -> PU_REMOVEDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PU_REMOVEDR { bits }
}
#[doc = "Bits 16:31 - Current timer count value."]
#[inline]
pub fn tmr_cnt(&self) -> TMR_CNTR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TMR_CNTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2."]
#[inline]
pub fn port_func(&mut self) -> _PORT_FUNCW {
_PORT_FUNCW { w: self }
}
#[doc = "Bits 2:3 - Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved"]
#[inline]
pub fn tmr_scale(&mut self) -> _TMR_SCALEW {
_TMR_SCALEW { w: self }
}
#[doc = "Bit 4 - Timer mode selection. 0: monoshot 1: free running"]
#[inline]
pub fn tmr_mode(&mut self) -> _TMR_MODEW {
_TMR_MODEW { w: self }
}
#[doc = "Bit 5 - Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0."]
#[inline]
pub fn tmr_en(&mut self) -> _TMR_ENW {
_TMR_ENW { w: self }
}
#[doc = "Bit 6 - Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled."]
#[inline]
pub fn tmr_rst(&mut self) -> _TMR_RSTW {
_TMR_RSTW { w: self }
}
#[doc = "Bit 8 - Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set."]
#[inline]
pub fn b_hnp_track(&mut self) -> _B_HNP_TRACKW {
_B_HNP_TRACKW { w: self }
}
#[doc = "Bit 9 - Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set."]
#[inline]
pub fn a_hnp_track(&mut self) -> _A_HNP_TRACKW {
_A_HNP_TRACKW { w: self }
}
#[doc = "Bit 10 - When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set."]
#[inline]
pub fn pu_removed(&mut self) -> _PU_REMOVEDW {
_PU_REMOVEDW { w: self }
}
#[doc = "Bits 16:31 - Current timer count value."]
#[inline]
pub fn tmr_cnt(&mut self) -> _TMR_CNTW {
_TMR_CNTW { w: self }
}
}
}
#[doc = "OTG Timer"]
pub struct TMR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG Timer"]
pub mod tmr {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TMR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct TIMEOUT_CNTR {
bits: u16,
}
impl TIMEOUT_CNTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _TIMEOUT_CNTW<'a> {
w: &'a mut W,
}
impl<'a> _TIMEOUT_CNTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - The TMR interrupt is set when TMR_CNT reaches this value."]
#[inline]
pub fn timeout_cnt(&self) -> TIMEOUT_CNTR {
let bits = {
const MASK: u16 = 0xffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TIMEOUT_CNTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xffff }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - The TMR interrupt is set when TMR_CNT reaches this value."]
#[inline]
pub fn timeout_cnt(&mut self) -> _TIMEOUT_CNTW {
_TIMEOUT_CNTW { w: self }
}
}
}
#[doc = "USB Device Interrupt Status"]
pub struct DEVINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Device Interrupt Status"]
pub mod devintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DEVINTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct FRAMER {
bits: bool,
}
impl FRAMER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_FASTR {
bits: bool,
}
impl EP_FASTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_SLOWR {
bits: bool,
}
impl EP_SLOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DEV_STATR {
bits: bool,
}
impl DEV_STATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CCEMPTYR {
bits: bool,
}
impl CCEMPTYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CDFULLR {
bits: bool,
}
impl CDFULLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXENDPKTR {
bits: bool,
}
impl RXENDPKTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXENDPKTR {
bits: bool,
}
impl TXENDPKTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_RLZEDR {
bits: bool,
}
impl EP_RLZEDR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ERR_INTR {
bits: bool,
}
impl ERR_INTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers."]
#[inline]
pub fn frame(&self) -> FRAMER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FRAMER { bits }
}
#[doc = "Bit 1 - Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit."]
#[inline]
pub fn ep_fast(&self) -> EP_FASTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_FASTR { bits }
}
#[doc = "Bit 2 - Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit."]
#[inline]
pub fn ep_slow(&self) -> EP_SLOWR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_SLOWR { bits }
}
#[doc = "Bit 3 - Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366."]
#[inline]
pub fn dev_stat(&self) -> DEV_STATR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DEV_STATR { bits }
}
#[doc = "Bit 4 - The command code register (USBCmdCode) is empty (New command can be written)."]
#[inline]
pub fn ccempty(&self) -> CCEMPTYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CCEMPTYR { bits }
}
#[doc = "Bit 5 - Command data register (USBCmdData) is full (Data can be read now)."]
#[inline]
pub fn cdfull(&self) -> CDFULLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CDFULLR { bits }
}
#[doc = "Bit 6 - The current packet in the endpoint buffer is transferred to the CPU."]
#[inline]
pub fn rx_endpkt(&self) -> RXENDPKTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXENDPKTR { bits }
}
#[doc = "Bit 7 - The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)."]
#[inline]
pub fn tx_endpkt(&self) -> TXENDPKTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXENDPKTR { bits }
}
#[doc = "Bit 8 - Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed."]
#[inline]
pub fn ep_rlzed(&self) -> EP_RLZEDR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_RLZEDR { bits }
}
#[doc = "Bit 9 - Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368"]
#[inline]
pub fn err_int(&self) -> ERR_INTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ERR_INTR { bits }
}
}
}
#[doc = "USB Device Interrupt Enable"]
pub struct DEVINTEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Device Interrupt Enable"]
pub mod devinten {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DEVINTEN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct FRAMEENR {
bits: bool,
}
impl FRAMEENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_FASTENR {
bits: bool,
}
impl EP_FASTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_SLOWENR {
bits: bool,
}
impl EP_SLOWENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct DEV_STATENR {
bits: bool,
}
impl DEV_STATENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CCEMPTYENR {
bits: bool,
}
impl CCEMPTYENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct CDFULLENR {
bits: bool,
}
impl CDFULLENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct RXENDPKTENR {
bits: bool,
}
impl RXENDPKTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TXENDPKTENR {
bits: bool,
}
impl TXENDPKTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_RLZEDENR {
bits: bool,
}
impl EP_RLZEDENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ERR_INTENR {
bits: bool,
}
impl ERR_INTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _FRAMEENW<'a> {
w: &'a mut W,
}
impl<'a> _FRAMEENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_FASTENW<'a> {
w: &'a mut W,
}
impl<'a> _EP_FASTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_SLOWENW<'a> {
w: &'a mut W,
}
impl<'a> _EP_SLOWENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DEV_STATENW<'a> {
w: &'a mut W,
}
impl<'a> _DEV_STATENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CCEMPTYENW<'a> {
w: &'a mut W,
}
impl<'a> _CCEMPTYENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CDFULLENW<'a> {
w: &'a mut W,
}
impl<'a> _CDFULLENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXENDPKTENW<'a> {
w: &'a mut W,
}
impl<'a> _RXENDPKTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXENDPKTENW<'a> {
w: &'a mut W,
}
impl<'a> _TXENDPKTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_RLZEDENW<'a> {
w: &'a mut W,
}
impl<'a> _EP_RLZEDENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTENW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn frameen(&self) -> FRAMEENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
FRAMEENR { bits }
}
#[doc = "Bit 1 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ep_fasten(&self) -> EP_FASTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_FASTENR { bits }
}
#[doc = "Bit 2 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ep_slowen(&self) -> EP_SLOWENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_SLOWENR { bits }
}
#[doc = "Bit 3 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn dev_staten(&self) -> DEV_STATENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DEV_STATENR { bits }
}
#[doc = "Bit 4 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ccemptyen(&self) -> CCEMPTYENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CCEMPTYENR { bits }
}
#[doc = "Bit 5 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn cdfullen(&self) -> CDFULLENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CDFULLENR { bits }
}
#[doc = "Bit 6 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn rx_endpkten(&self) -> RXENDPKTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
RXENDPKTENR { bits }
}
#[doc = "Bit 7 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn tx_endpkten(&self) -> TXENDPKTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TXENDPKTENR { bits }
}
#[doc = "Bit 8 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ep_rlzeden(&self) -> EP_RLZEDENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_RLZEDENR { bits }
}
#[doc = "Bit 9 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn err_inten(&self) -> ERR_INTENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ERR_INTENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn frameen(&mut self) -> _FRAMEENW {
_FRAMEENW { w: self }
}
#[doc = "Bit 1 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ep_fasten(&mut self) -> _EP_FASTENW {
_EP_FASTENW { w: self }
}
#[doc = "Bit 2 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ep_slowen(&mut self) -> _EP_SLOWENW {
_EP_SLOWENW { w: self }
}
#[doc = "Bit 3 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn dev_staten(&mut self) -> _DEV_STATENW {
_DEV_STATENW { w: self }
}
#[doc = "Bit 4 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ccemptyen(&mut self) -> _CCEMPTYENW {
_CCEMPTYENW { w: self }
}
#[doc = "Bit 5 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn cdfullen(&mut self) -> _CDFULLENW {
_CDFULLENW { w: self }
}
#[doc = "Bit 6 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn rx_endpkten(&mut self) -> _RXENDPKTENW {
_RXENDPKTENW { w: self }
}
#[doc = "Bit 7 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn tx_endpkten(&mut self) -> _TXENDPKTENW {
_TXENDPKTENW { w: self }
}
#[doc = "Bit 8 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn ep_rlzeden(&mut self) -> _EP_RLZEDENW {
_EP_RLZEDENW { w: self }
}
#[doc = "Bit 9 - 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri."]
#[inline]
pub fn err_inten(&mut self) -> _ERR_INTENW {
_ERR_INTENW { w: self }
}
}
}
#[doc = "USB Device Interrupt Clear"]
pub struct DEVINTCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Device Interrupt Clear"]
pub mod devintclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DEVINTCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _FRAMECLRW<'a> {
w: &'a mut W,
}
impl<'a> _FRAMECLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_FASTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _EP_FASTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_SLOWCLRW<'a> {
w: &'a mut W,
}
impl<'a> _EP_SLOWCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DEV_STATCLRW<'a> {
w: &'a mut W,
}
impl<'a> _DEV_STATCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CCEMPTYCLRW<'a> {
w: &'a mut W,
}
impl<'a> _CCEMPTYCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CDFULLCLRW<'a> {
w: &'a mut W,
}
impl<'a> _CDFULLCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXENDPKTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _RXENDPKTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXENDPKTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _TXENDPKTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_RLZEDCLRW<'a> {
w: &'a mut W,
}
impl<'a> _EP_RLZEDCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTCLRW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTCLRW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn frameclr(&mut self) -> _FRAMECLRW {
_FRAMECLRW { w: self }
}
#[doc = "Bit 1 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn ep_fastclr(&mut self) -> _EP_FASTCLRW {
_EP_FASTCLRW { w: self }
}
#[doc = "Bit 2 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn ep_slowclr(&mut self) -> _EP_SLOWCLRW {
_EP_SLOWCLRW { w: self }
}
#[doc = "Bit 3 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn dev_statclr(&mut self) -> _DEV_STATCLRW {
_DEV_STATCLRW { w: self }
}
#[doc = "Bit 4 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn ccemptyclr(&mut self) -> _CCEMPTYCLRW {
_CCEMPTYCLRW { w: self }
}
#[doc = "Bit 5 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn cdfullclr(&mut self) -> _CDFULLCLRW {
_CDFULLCLRW { w: self }
}
#[doc = "Bit 6 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn rx_endpktclr(&mut self) -> _RXENDPKTCLRW {
_RXENDPKTCLRW { w: self }
}
#[doc = "Bit 7 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn tx_endpktclr(&mut self) -> _TXENDPKTCLRW {
_TXENDPKTCLRW { w: self }
}
#[doc = "Bit 8 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn ep_rlzedclr(&mut self) -> _EP_RLZEDCLRW {
_EP_RLZEDCLRW { w: self }
}
#[doc = "Bit 9 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared."]
#[inline]
pub fn err_intclr(&mut self) -> _ERR_INTCLRW {
_ERR_INTCLRW { w: self }
}
}
}
#[doc = "USB Device Interrupt Set"]
pub struct DEVINTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Device Interrupt Set"]
pub mod devintset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DEVINTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _FRAMESETW<'a> {
w: &'a mut W,
}
impl<'a> _FRAMESETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_FASTSETW<'a> {
w: &'a mut W,
}
impl<'a> _EP_FASTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_SLOWSETW<'a> {
w: &'a mut W,
}
impl<'a> _EP_SLOWSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DEV_STATSETW<'a> {
w: &'a mut W,
}
impl<'a> _DEV_STATSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CCEMPTYSETW<'a> {
w: &'a mut W,
}
impl<'a> _CCEMPTYSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CDFULLSETW<'a> {
w: &'a mut W,
}
impl<'a> _CDFULLSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXENDPKTSETW<'a> {
w: &'a mut W,
}
impl<'a> _RXENDPKTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXENDPKTSETW<'a> {
w: &'a mut W,
}
impl<'a> _TXENDPKTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_RLZEDSETW<'a> {
w: &'a mut W,
}
impl<'a> _EP_RLZEDSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ERR_INTSETW<'a> {
w: &'a mut W,
}
impl<'a> _ERR_INTSETW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn frameset(&mut self) -> _FRAMESETW {
_FRAMESETW { w: self }
}
#[doc = "Bit 1 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn ep_fastset(&mut self) -> _EP_FASTSETW {
_EP_FASTSETW { w: self }
}
#[doc = "Bit 2 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn ep_slowset(&mut self) -> _EP_SLOWSETW {
_EP_SLOWSETW { w: self }
}
#[doc = "Bit 3 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn dev_statset(&mut self) -> _DEV_STATSETW {
_DEV_STATSETW { w: self }
}
#[doc = "Bit 4 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn ccemptyset(&mut self) -> _CCEMPTYSETW {
_CCEMPTYSETW { w: self }
}
#[doc = "Bit 5 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn cdfullset(&mut self) -> _CDFULLSETW {
_CDFULLSETW { w: self }
}
#[doc = "Bit 6 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn rx_endpktset(&mut self) -> _RXENDPKTSETW {
_RXENDPKTSETW { w: self }
}
#[doc = "Bit 7 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn tx_endpktset(&mut self) -> _TXENDPKTSETW {
_TXENDPKTSETW { w: self }
}
#[doc = "Bit 8 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn ep_rlzedset(&mut self) -> _EP_RLZEDSETW {
_EP_RLZEDSETW { w: self }
}
#[doc = "Bit 9 - 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set."]
#[inline]
pub fn err_intset(&mut self) -> _ERR_INTSETW {
_ERR_INTSETW { w: self }
}
}
}
#[doc = "USB Command Code"]
pub struct CMDCODE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Command Code"]
pub mod cmdcode {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CMDCODE {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `CMD_PHASE`"]
pub enum CMD_PHASEW {
#[doc = "Read"]
READ,
#[doc = "Write"]
WRITE,
#[doc = "Command"]
COMMAND,
}
impl CMD_PHASEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CMD_PHASEW::READ => 2,
CMD_PHASEW::WRITE => 1,
CMD_PHASEW::COMMAND => 5,
}
}
}
#[doc = r" Proxy"]
pub struct _CMD_PHASEW<'a> {
w: &'a mut W,
}
impl<'a> _CMD_PHASEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CMD_PHASEW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Read"]
#[inline]
pub fn read(self) -> &'a mut W {
self.variant(CMD_PHASEW::READ)
}
#[doc = "Write"]
#[inline]
pub fn write(self) -> &'a mut W {
self.variant(CMD_PHASEW::WRITE)
}
#[doc = "Command"]
#[inline]
pub fn command(self) -> &'a mut W {
self.variant(CMD_PHASEW::COMMAND)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CMD_CODE_WDATAW<'a> {
w: &'a mut W,
}
impl<'a> _CMD_CODE_WDATAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 8:15 - The command phase:"]
#[inline]
pub fn cmd_phase(&mut self) -> _CMD_PHASEW {
_CMD_PHASEW { w: self }
}
#[doc = "Bits 16:23 - This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)."]
#[inline]
pub fn cmd_code_wdata(&mut self) -> _CMD_CODE_WDATAW {
_CMD_CODE_WDATAW { w: self }
}
}
}
#[doc = "USB Command Data"]
pub struct CMDDATA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Command Data"]
pub mod cmddata {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CMDDATA {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct CMD_RDATAR {
bits: u8,
}
impl CMD_RDATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Command Read Data."]
#[inline]
pub fn cmd_rdata(&self) -> CMD_RDATAR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CMD_RDATAR { bits }
}
}
}
#[doc = "USB Receive Data"]
pub struct RXDATA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Receive Data"]
pub mod rxdata {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RXDATA {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RX_DATAR {
bits: u32,
}
impl RX_DATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Data received."]
#[inline]
pub fn rx_data(&self) -> RX_DATAR {
let bits = {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
RX_DATAR { bits }
}
}
}
#[doc = "USB Transmit Data"]
pub struct TXDATA {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Transmit Data"]
pub mod txdata {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXDATA {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _TX_DATAW<'a> {
w: &'a mut W,
}
impl<'a> _TX_DATAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0xffff_ffff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Transmit Data."]
#[inline]
pub fn tx_data(&mut self) -> _TX_DATAW {
_TX_DATAW { w: self }
}
}
}
#[doc = "USB Receive Packet Length"]
pub struct RXPLEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Receive Packet Length"]
pub mod rxplen {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::RXPLEN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct PKT_LNGTHR {
bits: u16,
}
impl PKT_LNGTHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = "Possible values of the field `DV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DVR {
#[doc = "Data is invalid."]
DATA_IS_INVALID_,
#[doc = "Data is valid."]
DATA_IS_VALID_,
}
impl DVR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DVR::DATA_IS_INVALID_ => false,
DVR::DATA_IS_VALID_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DVR {
match value {
false => DVR::DATA_IS_INVALID_,
true => DVR::DATA_IS_VALID_,
}
}
#[doc = "Checks if the value of the field is `DATA_IS_INVALID_`"]
#[inline]
pub fn is_data_is_invalid_(&self) -> bool {
*self == DVR::DATA_IS_INVALID_
}
#[doc = "Checks if the value of the field is `DATA_IS_VALID_`"]
#[inline]
pub fn is_data_is_valid_(&self) -> bool {
*self == DVR::DATA_IS_VALID_
}
}
#[doc = r" Value of the field"]
pub struct PKT_RDYR {
bits: bool,
}
impl PKT_RDYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt."]
#[inline]
pub fn pkt_lngth(&self) -> PKT_LNGTHR {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
PKT_LNGTHR { bits }
}
#[doc = "Bit 10 - Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet."]
#[inline]
pub fn dv(&self) -> DVR {
DVR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - The PKT_LNGTH field is valid and the packet is ready for reading."]
#[inline]
pub fn pkt_rdy(&self) -> PKT_RDYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PKT_RDYR { bits }
}
}
}
#[doc = "USB Transmit Packet Length"]
pub struct TXPLEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Transmit Packet Length"]
pub mod txplen {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::TXPLEN {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _PKT_LNGTHW<'a> {
w: &'a mut W,
}
impl<'a> _PKT_LNGTHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt."]
#[inline]
pub fn pkt_lngth(&mut self) -> _PKT_LNGTHW {
_PKT_LNGTHW { w: self }
}
}
}
#[doc = "USB Control"]
pub struct CTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Control"]
pub mod ctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RD_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RD_ENR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl RD_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RD_ENR::DISABLED_ => false,
RD_ENR::ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RD_ENR {
match value {
false => RD_ENR::DISABLED_,
true => RD_ENR::ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == RD_ENR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == RD_ENR::ENABLED_
}
}
#[doc = "Possible values of the field `WR_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WR_ENR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl WR_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WR_ENR::DISABLED_ => false,
WR_ENR::ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WR_ENR {
match value {
false => WR_ENR::DISABLED_,
true => WR_ENR::ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == WR_ENR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == WR_ENR::ENABLED_
}
}
#[doc = r" Value of the field"]
pub struct LOG_ENDPOINTR {
bits: u8,
}
impl LOG_ENDPOINTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Values that can be written to the field `RD_EN`"]
pub enum RD_ENW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl RD_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RD_ENW::DISABLED_ => false,
RD_ENW::ENABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RD_ENW<'a> {
w: &'a mut W,
}
impl<'a> _RD_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RD_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(RD_ENW::DISABLED_)
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(RD_ENW::ENABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WR_EN`"]
pub enum WR_ENW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl WR_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WR_ENW::DISABLED_ => false,
WR_ENW::ENABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WR_ENW<'a> {
w: &'a mut W,
}
impl<'a> _WR_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WR_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(WR_ENW::DISABLED_)
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(WR_ENW::ENABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _LOG_ENDPOINTW<'a> {
w: &'a mut W,
}
impl<'a> _LOG_ENDPOINTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."]
#[inline]
pub fn rd_en(&self) -> RD_ENR {
RD_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."]
#[inline]
pub fn wr_en(&self) -> WR_ENR {
WR_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 2:5 - Logical Endpoint number."]
#[inline]
pub fn log_endpoint(&self) -> LOG_ENDPOINTR {
let bits = {
const MASK: u8 = 0x0f;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
};
LOG_ENDPOINTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."]
#[inline]
pub fn rd_en(&mut self) -> _RD_ENW {
_RD_ENW { w: self }
}
#[doc = "Bit 1 - Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."]
#[inline]
pub fn wr_en(&mut self) -> _WR_ENW {
_WR_ENW { w: self }
}
#[doc = "Bits 2:5 - Logical Endpoint number."]
#[inline]
pub fn log_endpoint(&mut self) -> _LOG_ENDPOINTW {
_LOG_ENDPOINTW { w: self }
}
}
}
#[doc = "USB Device Interrupt Priority"]
pub struct DEVINTPRI {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Device Interrupt Priority"]
pub mod devintpri {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DEVINTPRI {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = "Values that can be written to the field `FRAME`"]
pub enum FRAMEW {
#[doc = "FRAME interrupt is routed to USB_INT_REQ_LP."]
LP,
#[doc = "FRAME interrupt is routed to USB_INT_REQ_HP."]
HP,
}
impl FRAMEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FRAMEW::LP => false,
FRAMEW::HP => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FRAMEW<'a> {
w: &'a mut W,
}
impl<'a> _FRAMEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FRAMEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "FRAME interrupt is routed to USB_INT_REQ_LP."]
#[inline]
pub fn lp(self) -> &'a mut W {
self.variant(FRAMEW::LP)
}
#[doc = "FRAME interrupt is routed to USB_INT_REQ_HP."]
#[inline]
pub fn hp(self) -> &'a mut W {
self.variant(FRAMEW::HP)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EP_FAST`"]
pub enum EP_FASTW {
#[doc = "EP_FAST interrupt is routed to USB_INT_REQ_LP."]
LP,
#[doc = "EP_FAST interrupt is routed to USB_INT_REQ_HP."]
HP,
}
impl EP_FASTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EP_FASTW::LP => false,
EP_FASTW::HP => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EP_FASTW<'a> {
w: &'a mut W,
}
impl<'a> _EP_FASTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EP_FASTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "EP_FAST interrupt is routed to USB_INT_REQ_LP."]
#[inline]
pub fn lp(self) -> &'a mut W {
self.variant(EP_FASTW::LP)
}
#[doc = "EP_FAST interrupt is routed to USB_INT_REQ_HP."]
#[inline]
pub fn hp(self) -> &'a mut W {
self.variant(EP_FASTW::HP)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Frame interrupt routing"]
#[inline]
pub fn frame(&mut self) -> _FRAMEW {
_FRAMEW { w: self }
}
#[doc = "Bit 1 - Fast endpoint interrupt routing"]
#[inline]
pub fn ep_fast(&mut self) -> _EP_FASTW {
_EP_FASTW { w: self }
}
}
}
#[doc = "USB Endpoint Interrupt Status"]
pub struct EPINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint Interrupt Status"]
pub mod epintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::EPINTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct EPST0R {
bits: bool,
}
impl EPST0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST1R {
bits: bool,
}
impl EPST1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST2R {
bits: bool,
}
impl EPST2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST3R {
bits: bool,
}
impl EPST3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST4R {
bits: bool,
}
impl EPST4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST5R {
bits: bool,
}
impl EPST5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST6R {
bits: bool,
}
impl EPST6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST7R {
bits: bool,
}
impl EPST7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST8R {
bits: bool,
}
impl EPST8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST9R {
bits: bool,
}
impl EPST9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST10R {
bits: bool,
}
impl EPST10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST11R {
bits: bool,
}
impl EPST11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST12R {
bits: bool,
}
impl EPST12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST13R {
bits: bool,
}
impl EPST13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST14R {
bits: bool,
}
impl EPST14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST15R {
bits: bool,
}
impl EPST15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST16R {
bits: bool,
}
impl EPST16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST17R {
bits: bool,
}
impl EPST17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST18R {
bits: bool,
}
impl EPST18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST19R {
bits: bool,
}
impl EPST19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST20R {
bits: bool,
}
impl EPST20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST21R {
bits: bool,
}
impl EPST21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST22R {
bits: bool,
}
impl EPST22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST23R {
bits: bool,
}
impl EPST23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST24R {
bits: bool,
}
impl EPST24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST25R {
bits: bool,
}
impl EPST25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST26R {
bits: bool,
}
impl EPST26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST27R {
bits: bool,
}
impl EPST27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST28R {
bits: bool,
}
impl EPST28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST29R {
bits: bool,
}
impl EPST29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST30R {
bits: bool,
}
impl EPST30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPST31R {
bits: bool,
}
impl EPST31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst0(&self) -> EPST0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST0R { bits }
}
#[doc = "Bit 1 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst1(&self) -> EPST1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST1R { bits }
}
#[doc = "Bit 2 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst2(&self) -> EPST2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST2R { bits }
}
#[doc = "Bit 3 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst3(&self) -> EPST3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST3R { bits }
}
#[doc = "Bit 4 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst4(&self) -> EPST4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST4R { bits }
}
#[doc = "Bit 5 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst5(&self) -> EPST5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST5R { bits }
}
#[doc = "Bit 6 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst6(&self) -> EPST6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST6R { bits }
}
#[doc = "Bit 7 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst7(&self) -> EPST7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST7R { bits }
}
#[doc = "Bit 8 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst8(&self) -> EPST8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST8R { bits }
}
#[doc = "Bit 9 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst9(&self) -> EPST9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST9R { bits }
}
#[doc = "Bit 10 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst10(&self) -> EPST10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST10R { bits }
}
#[doc = "Bit 11 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst11(&self) -> EPST11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST11R { bits }
}
#[doc = "Bit 12 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst12(&self) -> EPST12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST12R { bits }
}
#[doc = "Bit 13 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst13(&self) -> EPST13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST13R { bits }
}
#[doc = "Bit 14 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst14(&self) -> EPST14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST14R { bits }
}
#[doc = "Bit 15 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst15(&self) -> EPST15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST15R { bits }
}
#[doc = "Bit 16 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst16(&self) -> EPST16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST16R { bits }
}
#[doc = "Bit 17 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst17(&self) -> EPST17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST17R { bits }
}
#[doc = "Bit 18 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst18(&self) -> EPST18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST18R { bits }
}
#[doc = "Bit 19 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst19(&self) -> EPST19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST19R { bits }
}
#[doc = "Bit 20 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst20(&self) -> EPST20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST20R { bits }
}
#[doc = "Bit 21 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst21(&self) -> EPST21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST21R { bits }
}
#[doc = "Bit 22 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst22(&self) -> EPST22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST22R { bits }
}
#[doc = "Bit 23 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst23(&self) -> EPST23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST23R { bits }
}
#[doc = "Bit 24 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst24(&self) -> EPST24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST24R { bits }
}
#[doc = "Bit 25 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst25(&self) -> EPST25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST25R { bits }
}
#[doc = "Bit 26 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst26(&self) -> EPST26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST26R { bits }
}
#[doc = "Bit 27 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst27(&self) -> EPST27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST27R { bits }
}
#[doc = "Bit 28 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst28(&self) -> EPST28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST28R { bits }
}
#[doc = "Bit 29 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst29(&self) -> EPST29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST29R { bits }
}
#[doc = "Bit 30 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst30(&self) -> EPST30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST30R { bits }
}
#[doc = "Bit 31 - 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received."]
#[inline]
pub fn epst31(&self) -> EPST31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPST31R { bits }
}
}
}
#[doc = "USB Endpoint Interrupt Enable"]
pub struct EPINTEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint Interrupt Enable"]
pub mod epinten {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPINTEN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EPEN0R {
bits: bool,
}
impl EPEN0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN1R {
bits: bool,
}
impl EPEN1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN2R {
bits: bool,
}
impl EPEN2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN3R {
bits: bool,
}
impl EPEN3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN4R {
bits: bool,
}
impl EPEN4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN5R {
bits: bool,
}
impl EPEN5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN6R {
bits: bool,
}
impl EPEN6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN7R {
bits: bool,
}
impl EPEN7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN8R {
bits: bool,
}
impl EPEN8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN9R {
bits: bool,
}
impl EPEN9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN10R {
bits: bool,
}
impl EPEN10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN11R {
bits: bool,
}
impl EPEN11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN12R {
bits: bool,
}
impl EPEN12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN13R {
bits: bool,
}
impl EPEN13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN14R {
bits: bool,
}
impl EPEN14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN15R {
bits: bool,
}
impl EPEN15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN16R {
bits: bool,
}
impl EPEN16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN17R {
bits: bool,
}
impl EPEN17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN18R {
bits: bool,
}
impl EPEN18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN19R {
bits: bool,
}
impl EPEN19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN20R {
bits: bool,
}
impl EPEN20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN21R {
bits: bool,
}
impl EPEN21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN22R {
bits: bool,
}
impl EPEN22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN23R {
bits: bool,
}
impl EPEN23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN24R {
bits: bool,
}
impl EPEN24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN25R {
bits: bool,
}
impl EPEN25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN26R {
bits: bool,
}
impl EPEN26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN27R {
bits: bool,
}
impl EPEN27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN28R {
bits: bool,
}
impl EPEN28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN29R {
bits: bool,
}
impl EPEN29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN30R {
bits: bool,
}
impl EPEN30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPEN31R {
bits: bool,
}
impl EPEN31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _EPEN0W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN1W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN2W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN3W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN4W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN5W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN6W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN7W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN8W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN9W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN10W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN11W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN12W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN13W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN14W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN15W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN16W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN17W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN18W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN19W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN20W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN21W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN22W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN23W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN24W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN25W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN26W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN27W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN28W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN29W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN30W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPEN31W<'a> {
w: &'a mut W,
}
impl<'a> _EPEN31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen0(&self) -> EPEN0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN0R { bits }
}
#[doc = "Bit 1 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen1(&self) -> EPEN1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN1R { bits }
}
#[doc = "Bit 2 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen2(&self) -> EPEN2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN2R { bits }
}
#[doc = "Bit 3 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen3(&self) -> EPEN3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN3R { bits }
}
#[doc = "Bit 4 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen4(&self) -> EPEN4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN4R { bits }
}
#[doc = "Bit 5 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen5(&self) -> EPEN5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN5R { bits }
}
#[doc = "Bit 6 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen6(&self) -> EPEN6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN6R { bits }
}
#[doc = "Bit 7 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen7(&self) -> EPEN7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN7R { bits }
}
#[doc = "Bit 8 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen8(&self) -> EPEN8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN8R { bits }
}
#[doc = "Bit 9 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen9(&self) -> EPEN9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN9R { bits }
}
#[doc = "Bit 10 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen10(&self) -> EPEN10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN10R { bits }
}
#[doc = "Bit 11 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen11(&self) -> EPEN11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN11R { bits }
}
#[doc = "Bit 12 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen12(&self) -> EPEN12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN12R { bits }
}
#[doc = "Bit 13 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen13(&self) -> EPEN13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN13R { bits }
}
#[doc = "Bit 14 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen14(&self) -> EPEN14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN14R { bits }
}
#[doc = "Bit 15 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen15(&self) -> EPEN15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN15R { bits }
}
#[doc = "Bit 16 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen16(&self) -> EPEN16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN16R { bits }
}
#[doc = "Bit 17 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen17(&self) -> EPEN17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN17R { bits }
}
#[doc = "Bit 18 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen18(&self) -> EPEN18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN18R { bits }
}
#[doc = "Bit 19 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen19(&self) -> EPEN19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN19R { bits }
}
#[doc = "Bit 20 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen20(&self) -> EPEN20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN20R { bits }
}
#[doc = "Bit 21 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen21(&self) -> EPEN21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN21R { bits }
}
#[doc = "Bit 22 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen22(&self) -> EPEN22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN22R { bits }
}
#[doc = "Bit 23 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen23(&self) -> EPEN23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN23R { bits }
}
#[doc = "Bit 24 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen24(&self) -> EPEN24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN24R { bits }
}
#[doc = "Bit 25 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen25(&self) -> EPEN25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN25R { bits }
}
#[doc = "Bit 26 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen26(&self) -> EPEN26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN26R { bits }
}
#[doc = "Bit 27 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen27(&self) -> EPEN27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN27R { bits }
}
#[doc = "Bit 28 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen28(&self) -> EPEN28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN28R { bits }
}
#[doc = "Bit 29 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen29(&self) -> EPEN29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN29R { bits }
}
#[doc = "Bit 30 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen30(&self) -> EPEN30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN30R { bits }
}
#[doc = "Bit 31 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen31(&self) -> EPEN31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPEN31R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen0(&mut self) -> _EPEN0W {
_EPEN0W { w: self }
}
#[doc = "Bit 1 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen1(&mut self) -> _EPEN1W {
_EPEN1W { w: self }
}
#[doc = "Bit 2 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen2(&mut self) -> _EPEN2W {
_EPEN2W { w: self }
}
#[doc = "Bit 3 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen3(&mut self) -> _EPEN3W {
_EPEN3W { w: self }
}
#[doc = "Bit 4 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen4(&mut self) -> _EPEN4W {
_EPEN4W { w: self }
}
#[doc = "Bit 5 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen5(&mut self) -> _EPEN5W {
_EPEN5W { w: self }
}
#[doc = "Bit 6 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen6(&mut self) -> _EPEN6W {
_EPEN6W { w: self }
}
#[doc = "Bit 7 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen7(&mut self) -> _EPEN7W {
_EPEN7W { w: self }
}
#[doc = "Bit 8 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen8(&mut self) -> _EPEN8W {
_EPEN8W { w: self }
}
#[doc = "Bit 9 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen9(&mut self) -> _EPEN9W {
_EPEN9W { w: self }
}
#[doc = "Bit 10 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen10(&mut self) -> _EPEN10W {
_EPEN10W { w: self }
}
#[doc = "Bit 11 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen11(&mut self) -> _EPEN11W {
_EPEN11W { w: self }
}
#[doc = "Bit 12 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen12(&mut self) -> _EPEN12W {
_EPEN12W { w: self }
}
#[doc = "Bit 13 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen13(&mut self) -> _EPEN13W {
_EPEN13W { w: self }
}
#[doc = "Bit 14 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen14(&mut self) -> _EPEN14W {
_EPEN14W { w: self }
}
#[doc = "Bit 15 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen15(&mut self) -> _EPEN15W {
_EPEN15W { w: self }
}
#[doc = "Bit 16 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen16(&mut self) -> _EPEN16W {
_EPEN16W { w: self }
}
#[doc = "Bit 17 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen17(&mut self) -> _EPEN17W {
_EPEN17W { w: self }
}
#[doc = "Bit 18 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen18(&mut self) -> _EPEN18W {
_EPEN18W { w: self }
}
#[doc = "Bit 19 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen19(&mut self) -> _EPEN19W {
_EPEN19W { w: self }
}
#[doc = "Bit 20 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen20(&mut self) -> _EPEN20W {
_EPEN20W { w: self }
}
#[doc = "Bit 21 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen21(&mut self) -> _EPEN21W {
_EPEN21W { w: self }
}
#[doc = "Bit 22 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen22(&mut self) -> _EPEN22W {
_EPEN22W { w: self }
}
#[doc = "Bit 23 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen23(&mut self) -> _EPEN23W {
_EPEN23W { w: self }
}
#[doc = "Bit 24 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen24(&mut self) -> _EPEN24W {
_EPEN24W { w: self }
}
#[doc = "Bit 25 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen25(&mut self) -> _EPEN25W {
_EPEN25W { w: self }
}
#[doc = "Bit 26 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen26(&mut self) -> _EPEN26W {
_EPEN26W { w: self }
}
#[doc = "Bit 27 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen27(&mut self) -> _EPEN27W {
_EPEN27W { w: self }
}
#[doc = "Bit 28 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen28(&mut self) -> _EPEN28W {
_EPEN28W { w: self }
}
#[doc = "Bit 29 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen29(&mut self) -> _EPEN29W {
_EPEN29W { w: self }
}
#[doc = "Bit 30 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen30(&mut self) -> _EPEN30W {
_EPEN30W { w: self }
}
#[doc = "Bit 31 - 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint."]
#[inline]
pub fn epen31(&mut self) -> _EPEN31W {
_EPEN31W { w: self }
}
}
}
#[doc = "USB Endpoint Interrupt Clear"]
pub struct EPINTCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint Interrupt Clear"]
pub mod epintclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPINTCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR8W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR9W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR10W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR11W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR12W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR13W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR14W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR15W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR16W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR17W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR18W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR19W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR20W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR21W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR22W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR23W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR24W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR25W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR26W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR27W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR28W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR29W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR30W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPCLR31W<'a> {
w: &'a mut W,
}
impl<'a> _EPCLR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr0(&mut self) -> _EPCLR0W {
_EPCLR0W { w: self }
}
#[doc = "Bit 1 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr1(&mut self) -> _EPCLR1W {
_EPCLR1W { w: self }
}
#[doc = "Bit 2 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr2(&mut self) -> _EPCLR2W {
_EPCLR2W { w: self }
}
#[doc = "Bit 3 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr3(&mut self) -> _EPCLR3W {
_EPCLR3W { w: self }
}
#[doc = "Bit 4 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr4(&mut self) -> _EPCLR4W {
_EPCLR4W { w: self }
}
#[doc = "Bit 5 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr5(&mut self) -> _EPCLR5W {
_EPCLR5W { w: self }
}
#[doc = "Bit 6 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr6(&mut self) -> _EPCLR6W {
_EPCLR6W { w: self }
}
#[doc = "Bit 7 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr7(&mut self) -> _EPCLR7W {
_EPCLR7W { w: self }
}
#[doc = "Bit 8 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr8(&mut self) -> _EPCLR8W {
_EPCLR8W { w: self }
}
#[doc = "Bit 9 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr9(&mut self) -> _EPCLR9W {
_EPCLR9W { w: self }
}
#[doc = "Bit 10 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr10(&mut self) -> _EPCLR10W {
_EPCLR10W { w: self }
}
#[doc = "Bit 11 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr11(&mut self) -> _EPCLR11W {
_EPCLR11W { w: self }
}
#[doc = "Bit 12 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr12(&mut self) -> _EPCLR12W {
_EPCLR12W { w: self }
}
#[doc = "Bit 13 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr13(&mut self) -> _EPCLR13W {
_EPCLR13W { w: self }
}
#[doc = "Bit 14 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr14(&mut self) -> _EPCLR14W {
_EPCLR14W { w: self }
}
#[doc = "Bit 15 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr15(&mut self) -> _EPCLR15W {
_EPCLR15W { w: self }
}
#[doc = "Bit 16 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr16(&mut self) -> _EPCLR16W {
_EPCLR16W { w: self }
}
#[doc = "Bit 17 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr17(&mut self) -> _EPCLR17W {
_EPCLR17W { w: self }
}
#[doc = "Bit 18 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr18(&mut self) -> _EPCLR18W {
_EPCLR18W { w: self }
}
#[doc = "Bit 19 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr19(&mut self) -> _EPCLR19W {
_EPCLR19W { w: self }
}
#[doc = "Bit 20 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr20(&mut self) -> _EPCLR20W {
_EPCLR20W { w: self }
}
#[doc = "Bit 21 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr21(&mut self) -> _EPCLR21W {
_EPCLR21W { w: self }
}
#[doc = "Bit 22 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr22(&mut self) -> _EPCLR22W {
_EPCLR22W { w: self }
}
#[doc = "Bit 23 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr23(&mut self) -> _EPCLR23W {
_EPCLR23W { w: self }
}
#[doc = "Bit 24 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr24(&mut self) -> _EPCLR24W {
_EPCLR24W { w: self }
}
#[doc = "Bit 25 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr25(&mut self) -> _EPCLR25W {
_EPCLR25W { w: self }
}
#[doc = "Bit 26 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr26(&mut self) -> _EPCLR26W {
_EPCLR26W { w: self }
}
#[doc = "Bit 27 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr27(&mut self) -> _EPCLR27W {
_EPCLR27W { w: self }
}
#[doc = "Bit 28 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr28(&mut self) -> _EPCLR28W {
_EPCLR28W { w: self }
}
#[doc = "Bit 29 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr29(&mut self) -> _EPCLR29W {
_EPCLR29W { w: self }
}
#[doc = "Bit 30 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr30(&mut self) -> _EPCLR30W {
_EPCLR30W { w: self }
}
#[doc = "Bit 31 - 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint."]
#[inline]
pub fn epclr31(&mut self) -> _EPCLR31W {
_EPCLR31W { w: self }
}
}
}
#[doc = "USB Endpoint Interrupt Set"]
pub struct EPINTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint Interrupt Set"]
pub mod epintset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPINTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPSET0W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET1W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET2W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET3W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET4W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET5W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET6W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET7W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET8W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET9W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET10W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET11W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET12W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET13W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET14W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET15W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET16W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET17W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET18W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET19W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET20W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET21W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET22W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET23W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET24W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET25W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET26W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET27W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET28W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET29W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET30W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPSET31W<'a> {
w: &'a mut W,
}
impl<'a> _EPSET31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset0(&mut self) -> _EPSET0W {
_EPSET0W { w: self }
}
#[doc = "Bit 1 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset1(&mut self) -> _EPSET1W {
_EPSET1W { w: self }
}
#[doc = "Bit 2 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset2(&mut self) -> _EPSET2W {
_EPSET2W { w: self }
}
#[doc = "Bit 3 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset3(&mut self) -> _EPSET3W {
_EPSET3W { w: self }
}
#[doc = "Bit 4 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset4(&mut self) -> _EPSET4W {
_EPSET4W { w: self }
}
#[doc = "Bit 5 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset5(&mut self) -> _EPSET5W {
_EPSET5W { w: self }
}
#[doc = "Bit 6 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset6(&mut self) -> _EPSET6W {
_EPSET6W { w: self }
}
#[doc = "Bit 7 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset7(&mut self) -> _EPSET7W {
_EPSET7W { w: self }
}
#[doc = "Bit 8 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset8(&mut self) -> _EPSET8W {
_EPSET8W { w: self }
}
#[doc = "Bit 9 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset9(&mut self) -> _EPSET9W {
_EPSET9W { w: self }
}
#[doc = "Bit 10 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset10(&mut self) -> _EPSET10W {
_EPSET10W { w: self }
}
#[doc = "Bit 11 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset11(&mut self) -> _EPSET11W {
_EPSET11W { w: self }
}
#[doc = "Bit 12 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset12(&mut self) -> _EPSET12W {
_EPSET12W { w: self }
}
#[doc = "Bit 13 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset13(&mut self) -> _EPSET13W {
_EPSET13W { w: self }
}
#[doc = "Bit 14 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset14(&mut self) -> _EPSET14W {
_EPSET14W { w: self }
}
#[doc = "Bit 15 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset15(&mut self) -> _EPSET15W {
_EPSET15W { w: self }
}
#[doc = "Bit 16 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset16(&mut self) -> _EPSET16W {
_EPSET16W { w: self }
}
#[doc = "Bit 17 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset17(&mut self) -> _EPSET17W {
_EPSET17W { w: self }
}
#[doc = "Bit 18 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset18(&mut self) -> _EPSET18W {
_EPSET18W { w: self }
}
#[doc = "Bit 19 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset19(&mut self) -> _EPSET19W {
_EPSET19W { w: self }
}
#[doc = "Bit 20 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset20(&mut self) -> _EPSET20W {
_EPSET20W { w: self }
}
#[doc = "Bit 21 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset21(&mut self) -> _EPSET21W {
_EPSET21W { w: self }
}
#[doc = "Bit 22 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset22(&mut self) -> _EPSET22W {
_EPSET22W { w: self }
}
#[doc = "Bit 23 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset23(&mut self) -> _EPSET23W {
_EPSET23W { w: self }
}
#[doc = "Bit 24 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset24(&mut self) -> _EPSET24W {
_EPSET24W { w: self }
}
#[doc = "Bit 25 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset25(&mut self) -> _EPSET25W {
_EPSET25W { w: self }
}
#[doc = "Bit 26 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset26(&mut self) -> _EPSET26W {
_EPSET26W { w: self }
}
#[doc = "Bit 27 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset27(&mut self) -> _EPSET27W {
_EPSET27W { w: self }
}
#[doc = "Bit 28 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset28(&mut self) -> _EPSET28W {
_EPSET28W { w: self }
}
#[doc = "Bit 29 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset29(&mut self) -> _EPSET29W {
_EPSET29W { w: self }
}
#[doc = "Bit 30 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset30(&mut self) -> _EPSET30W {
_EPSET30W { w: self }
}
#[doc = "Bit 31 - 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt."]
#[inline]
pub fn epset31(&mut self) -> _EPSET31W {
_EPSET31W { w: self }
}
}
}
#[doc = "USB Endpoint Priority"]
pub struct EPINTPRI {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint Priority"]
pub mod epintpri {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPINTPRI {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPPRI0W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI1W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI2W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI3W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI4W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI5W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI6W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI7W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI8W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI9W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI10W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI11W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI12W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI13W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI14W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI15W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI16W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI17W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI18W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI19W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI20W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI21W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI22W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI23W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI24W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI25W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI26W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI27W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI28W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI29W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI30W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPPRI31W<'a> {
w: &'a mut W,
}
impl<'a> _EPPRI31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri0(&mut self) -> _EPPRI0W {
_EPPRI0W { w: self }
}
#[doc = "Bit 1 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri1(&mut self) -> _EPPRI1W {
_EPPRI1W { w: self }
}
#[doc = "Bit 2 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri2(&mut self) -> _EPPRI2W {
_EPPRI2W { w: self }
}
#[doc = "Bit 3 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri3(&mut self) -> _EPPRI3W {
_EPPRI3W { w: self }
}
#[doc = "Bit 4 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri4(&mut self) -> _EPPRI4W {
_EPPRI4W { w: self }
}
#[doc = "Bit 5 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri5(&mut self) -> _EPPRI5W {
_EPPRI5W { w: self }
}
#[doc = "Bit 6 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri6(&mut self) -> _EPPRI6W {
_EPPRI6W { w: self }
}
#[doc = "Bit 7 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri7(&mut self) -> _EPPRI7W {
_EPPRI7W { w: self }
}
#[doc = "Bit 8 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri8(&mut self) -> _EPPRI8W {
_EPPRI8W { w: self }
}
#[doc = "Bit 9 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri9(&mut self) -> _EPPRI9W {
_EPPRI9W { w: self }
}
#[doc = "Bit 10 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri10(&mut self) -> _EPPRI10W {
_EPPRI10W { w: self }
}
#[doc = "Bit 11 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri11(&mut self) -> _EPPRI11W {
_EPPRI11W { w: self }
}
#[doc = "Bit 12 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri12(&mut self) -> _EPPRI12W {
_EPPRI12W { w: self }
}
#[doc = "Bit 13 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri13(&mut self) -> _EPPRI13W {
_EPPRI13W { w: self }
}
#[doc = "Bit 14 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri14(&mut self) -> _EPPRI14W {
_EPPRI14W { w: self }
}
#[doc = "Bit 15 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri15(&mut self) -> _EPPRI15W {
_EPPRI15W { w: self }
}
#[doc = "Bit 16 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri16(&mut self) -> _EPPRI16W {
_EPPRI16W { w: self }
}
#[doc = "Bit 17 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri17(&mut self) -> _EPPRI17W {
_EPPRI17W { w: self }
}
#[doc = "Bit 18 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri18(&mut self) -> _EPPRI18W {
_EPPRI18W { w: self }
}
#[doc = "Bit 19 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri19(&mut self) -> _EPPRI19W {
_EPPRI19W { w: self }
}
#[doc = "Bit 20 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri20(&mut self) -> _EPPRI20W {
_EPPRI20W { w: self }
}
#[doc = "Bit 21 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri21(&mut self) -> _EPPRI21W {
_EPPRI21W { w: self }
}
#[doc = "Bit 22 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri22(&mut self) -> _EPPRI22W {
_EPPRI22W { w: self }
}
#[doc = "Bit 23 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri23(&mut self) -> _EPPRI23W {
_EPPRI23W { w: self }
}
#[doc = "Bit 24 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri24(&mut self) -> _EPPRI24W {
_EPPRI24W { w: self }
}
#[doc = "Bit 25 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri25(&mut self) -> _EPPRI25W {
_EPPRI25W { w: self }
}
#[doc = "Bit 26 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri26(&mut self) -> _EPPRI26W {
_EPPRI26W { w: self }
}
#[doc = "Bit 27 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri27(&mut self) -> _EPPRI27W {
_EPPRI27W { w: self }
}
#[doc = "Bit 28 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri28(&mut self) -> _EPPRI28W {
_EPPRI28W { w: self }
}
#[doc = "Bit 29 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri29(&mut self) -> _EPPRI29W {
_EPPRI29W { w: self }
}
#[doc = "Bit 30 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri30(&mut self) -> _EPPRI30W {
_EPPRI30W { w: self }
}
#[doc = "Bit 31 - 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt"]
#[inline]
pub fn eppri31(&mut self) -> _EPPRI31W {
_EPPRI31W { w: self }
}
}
}
#[doc = "USB Realize Endpoint"]
pub struct REEP {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Realize Endpoint"]
pub mod reep {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::REEP {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct EPR0R {
bits: bool,
}
impl EPR0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR1R {
bits: bool,
}
impl EPR1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR2R {
bits: bool,
}
impl EPR2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR3R {
bits: bool,
}
impl EPR3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR4R {
bits: bool,
}
impl EPR4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR5R {
bits: bool,
}
impl EPR5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR6R {
bits: bool,
}
impl EPR6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR7R {
bits: bool,
}
impl EPR7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR8R {
bits: bool,
}
impl EPR8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR9R {
bits: bool,
}
impl EPR9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR10R {
bits: bool,
}
impl EPR10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR11R {
bits: bool,
}
impl EPR11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR12R {
bits: bool,
}
impl EPR12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR13R {
bits: bool,
}
impl EPR13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR14R {
bits: bool,
}
impl EPR14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR15R {
bits: bool,
}
impl EPR15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR16R {
bits: bool,
}
impl EPR16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR17R {
bits: bool,
}
impl EPR17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR18R {
bits: bool,
}
impl EPR18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR19R {
bits: bool,
}
impl EPR19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR20R {
bits: bool,
}
impl EPR20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR21R {
bits: bool,
}
impl EPR21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR22R {
bits: bool,
}
impl EPR22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR23R {
bits: bool,
}
impl EPR23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR24R {
bits: bool,
}
impl EPR24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR25R {
bits: bool,
}
impl EPR25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR26R {
bits: bool,
}
impl EPR26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR27R {
bits: bool,
}
impl EPR27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR28R {
bits: bool,
}
impl EPR28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR29R {
bits: bool,
}
impl EPR29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR30R {
bits: bool,
}
impl EPR30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPR31R {
bits: bool,
}
impl EPR31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _EPR0W<'a> {
w: &'a mut W,
}
impl<'a> _EPR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR1W<'a> {
w: &'a mut W,
}
impl<'a> _EPR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR2W<'a> {
w: &'a mut W,
}
impl<'a> _EPR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR3W<'a> {
w: &'a mut W,
}
impl<'a> _EPR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR4W<'a> {
w: &'a mut W,
}
impl<'a> _EPR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR5W<'a> {
w: &'a mut W,
}
impl<'a> _EPR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR6W<'a> {
w: &'a mut W,
}
impl<'a> _EPR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR7W<'a> {
w: &'a mut W,
}
impl<'a> _EPR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR8W<'a> {
w: &'a mut W,
}
impl<'a> _EPR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR9W<'a> {
w: &'a mut W,
}
impl<'a> _EPR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR10W<'a> {
w: &'a mut W,
}
impl<'a> _EPR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR11W<'a> {
w: &'a mut W,
}
impl<'a> _EPR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR12W<'a> {
w: &'a mut W,
}
impl<'a> _EPR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR13W<'a> {
w: &'a mut W,
}
impl<'a> _EPR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR14W<'a> {
w: &'a mut W,
}
impl<'a> _EPR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR15W<'a> {
w: &'a mut W,
}
impl<'a> _EPR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR16W<'a> {
w: &'a mut W,
}
impl<'a> _EPR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR17W<'a> {
w: &'a mut W,
}
impl<'a> _EPR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR18W<'a> {
w: &'a mut W,
}
impl<'a> _EPR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR19W<'a> {
w: &'a mut W,
}
impl<'a> _EPR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR20W<'a> {
w: &'a mut W,
}
impl<'a> _EPR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR21W<'a> {
w: &'a mut W,
}
impl<'a> _EPR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR22W<'a> {
w: &'a mut W,
}
impl<'a> _EPR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR23W<'a> {
w: &'a mut W,
}
impl<'a> _EPR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR24W<'a> {
w: &'a mut W,
}
impl<'a> _EPR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR25W<'a> {
w: &'a mut W,
}
impl<'a> _EPR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR26W<'a> {
w: &'a mut W,
}
impl<'a> _EPR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR27W<'a> {
w: &'a mut W,
}
impl<'a> _EPR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR28W<'a> {
w: &'a mut W,
}
impl<'a> _EPR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR29W<'a> {
w: &'a mut W,
}
impl<'a> _EPR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR30W<'a> {
w: &'a mut W,
}
impl<'a> _EPR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPR31W<'a> {
w: &'a mut W,
}
impl<'a> _EPR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr0(&self) -> EPR0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR0R { bits }
}
#[doc = "Bit 1 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr1(&self) -> EPR1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR1R { bits }
}
#[doc = "Bit 2 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr2(&self) -> EPR2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR2R { bits }
}
#[doc = "Bit 3 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr3(&self) -> EPR3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR3R { bits }
}
#[doc = "Bit 4 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr4(&self) -> EPR4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR4R { bits }
}
#[doc = "Bit 5 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr5(&self) -> EPR5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR5R { bits }
}
#[doc = "Bit 6 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr6(&self) -> EPR6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR6R { bits }
}
#[doc = "Bit 7 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr7(&self) -> EPR7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR7R { bits }
}
#[doc = "Bit 8 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr8(&self) -> EPR8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR8R { bits }
}
#[doc = "Bit 9 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr9(&self) -> EPR9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR9R { bits }
}
#[doc = "Bit 10 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr10(&self) -> EPR10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR10R { bits }
}
#[doc = "Bit 11 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr11(&self) -> EPR11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR11R { bits }
}
#[doc = "Bit 12 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr12(&self) -> EPR12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR12R { bits }
}
#[doc = "Bit 13 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr13(&self) -> EPR13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR13R { bits }
}
#[doc = "Bit 14 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr14(&self) -> EPR14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR14R { bits }
}
#[doc = "Bit 15 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr15(&self) -> EPR15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR15R { bits }
}
#[doc = "Bit 16 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr16(&self) -> EPR16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR16R { bits }
}
#[doc = "Bit 17 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr17(&self) -> EPR17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR17R { bits }
}
#[doc = "Bit 18 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr18(&self) -> EPR18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR18R { bits }
}
#[doc = "Bit 19 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr19(&self) -> EPR19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR19R { bits }
}
#[doc = "Bit 20 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr20(&self) -> EPR20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR20R { bits }
}
#[doc = "Bit 21 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr21(&self) -> EPR21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR21R { bits }
}
#[doc = "Bit 22 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr22(&self) -> EPR22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR22R { bits }
}
#[doc = "Bit 23 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr23(&self) -> EPR23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR23R { bits }
}
#[doc = "Bit 24 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr24(&self) -> EPR24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR24R { bits }
}
#[doc = "Bit 25 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr25(&self) -> EPR25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR25R { bits }
}
#[doc = "Bit 26 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr26(&self) -> EPR26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR26R { bits }
}
#[doc = "Bit 27 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr27(&self) -> EPR27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR27R { bits }
}
#[doc = "Bit 28 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr28(&self) -> EPR28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR28R { bits }
}
#[doc = "Bit 29 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr29(&self) -> EPR29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR29R { bits }
}
#[doc = "Bit 30 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr30(&self) -> EPR30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR30R { bits }
}
#[doc = "Bit 31 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr31(&self) -> EPR31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPR31R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x03 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr0(&mut self) -> _EPR0W {
_EPR0W { w: self }
}
#[doc = "Bit 1 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr1(&mut self) -> _EPR1W {
_EPR1W { w: self }
}
#[doc = "Bit 2 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr2(&mut self) -> _EPR2W {
_EPR2W { w: self }
}
#[doc = "Bit 3 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr3(&mut self) -> _EPR3W {
_EPR3W { w: self }
}
#[doc = "Bit 4 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr4(&mut self) -> _EPR4W {
_EPR4W { w: self }
}
#[doc = "Bit 5 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr5(&mut self) -> _EPR5W {
_EPR5W { w: self }
}
#[doc = "Bit 6 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr6(&mut self) -> _EPR6W {
_EPR6W { w: self }
}
#[doc = "Bit 7 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr7(&mut self) -> _EPR7W {
_EPR7W { w: self }
}
#[doc = "Bit 8 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr8(&mut self) -> _EPR8W {
_EPR8W { w: self }
}
#[doc = "Bit 9 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr9(&mut self) -> _EPR9W {
_EPR9W { w: self }
}
#[doc = "Bit 10 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr10(&mut self) -> _EPR10W {
_EPR10W { w: self }
}
#[doc = "Bit 11 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr11(&mut self) -> _EPR11W {
_EPR11W { w: self }
}
#[doc = "Bit 12 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr12(&mut self) -> _EPR12W {
_EPR12W { w: self }
}
#[doc = "Bit 13 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr13(&mut self) -> _EPR13W {
_EPR13W { w: self }
}
#[doc = "Bit 14 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr14(&mut self) -> _EPR14W {
_EPR14W { w: self }
}
#[doc = "Bit 15 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr15(&mut self) -> _EPR15W {
_EPR15W { w: self }
}
#[doc = "Bit 16 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr16(&mut self) -> _EPR16W {
_EPR16W { w: self }
}
#[doc = "Bit 17 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr17(&mut self) -> _EPR17W {
_EPR17W { w: self }
}
#[doc = "Bit 18 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr18(&mut self) -> _EPR18W {
_EPR18W { w: self }
}
#[doc = "Bit 19 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr19(&mut self) -> _EPR19W {
_EPR19W { w: self }
}
#[doc = "Bit 20 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr20(&mut self) -> _EPR20W {
_EPR20W { w: self }
}
#[doc = "Bit 21 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr21(&mut self) -> _EPR21W {
_EPR21W { w: self }
}
#[doc = "Bit 22 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr22(&mut self) -> _EPR22W {
_EPR22W { w: self }
}
#[doc = "Bit 23 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr23(&mut self) -> _EPR23W {
_EPR23W { w: self }
}
#[doc = "Bit 24 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr24(&mut self) -> _EPR24W {
_EPR24W { w: self }
}
#[doc = "Bit 25 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr25(&mut self) -> _EPR25W {
_EPR25W { w: self }
}
#[doc = "Bit 26 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr26(&mut self) -> _EPR26W {
_EPR26W { w: self }
}
#[doc = "Bit 27 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr27(&mut self) -> _EPR27W {
_EPR27W { w: self }
}
#[doc = "Bit 28 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr28(&mut self) -> _EPR28W {
_EPR28W { w: self }
}
#[doc = "Bit 29 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr29(&mut self) -> _EPR29W {
_EPR29W { w: self }
}
#[doc = "Bit 30 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr30(&mut self) -> _EPR30W {
_EPR30W { w: self }
}
#[doc = "Bit 31 - 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized."]
#[inline]
pub fn epr31(&mut self) -> _EPR31W {
_EPR31W { w: self }
}
}
}
#[doc = "USB Endpoint Index"]
pub struct EPIND {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint Index"]
pub mod epind {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPIND {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _PHY_EPW<'a> {
w: &'a mut W,
}
impl<'a> _PHY_EPW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0x1f;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Physical endpoint number (0-31)"]
#[inline]
pub fn phy_ep(&mut self) -> _PHY_EPW {
_PHY_EPW { w: self }
}
}
}
#[doc = "USB MaxPacketSize"]
pub struct MAXPSIZE {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB MaxPacketSize"]
pub mod maxpsize {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MAXPSIZE {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct MPSR {
bits: u16,
}
impl MPSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MPSW<'a> {
w: &'a mut W,
}
impl<'a> _MPSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - The maximum packet size value."]
#[inline]
pub fn mps(&self) -> MPSR {
let bits = {
const MASK: u16 = 0x03ff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MPSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0x08 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - The maximum packet size value."]
#[inline]
pub fn mps(&mut self) -> _MPSW {
_MPSW { w: self }
}
}
}
#[doc = "USB DMA Request Status"]
pub struct DMARST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB DMA Request Status"]
pub mod dmarst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DMARST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct EPRST0R {
bits: bool,
}
impl EPRST0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST1R {
bits: bool,
}
impl EPRST1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST2R {
bits: bool,
}
impl EPRST2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST3R {
bits: bool,
}
impl EPRST3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST4R {
bits: bool,
}
impl EPRST4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST5R {
bits: bool,
}
impl EPRST5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST6R {
bits: bool,
}
impl EPRST6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST7R {
bits: bool,
}
impl EPRST7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST8R {
bits: bool,
}
impl EPRST8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST9R {
bits: bool,
}
impl EPRST9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST10R {
bits: bool,
}
impl EPRST10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST11R {
bits: bool,
}
impl EPRST11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST12R {
bits: bool,
}
impl EPRST12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST13R {
bits: bool,
}
impl EPRST13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST14R {
bits: bool,
}
impl EPRST14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST15R {
bits: bool,
}
impl EPRST15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST16R {
bits: bool,
}
impl EPRST16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST17R {
bits: bool,
}
impl EPRST17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST18R {
bits: bool,
}
impl EPRST18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST19R {
bits: bool,
}
impl EPRST19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST20R {
bits: bool,
}
impl EPRST20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST21R {
bits: bool,
}
impl EPRST21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST22R {
bits: bool,
}
impl EPRST22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST23R {
bits: bool,
}
impl EPRST23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST24R {
bits: bool,
}
impl EPRST24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST25R {
bits: bool,
}
impl EPRST25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST26R {
bits: bool,
}
impl EPRST26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST27R {
bits: bool,
}
impl EPRST27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST28R {
bits: bool,
}
impl EPRST28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST29R {
bits: bool,
}
impl EPRST29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST30R {
bits: bool,
}
impl EPRST30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPRST31R {
bits: bool,
}
impl EPRST31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)."]
#[inline]
pub fn eprst0(&self) -> EPRST0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST0R { bits }
}
#[doc = "Bit 1 - Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)."]
#[inline]
pub fn eprst1(&self) -> EPRST1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST1R { bits }
}
#[doc = "Bit 2 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst2(&self) -> EPRST2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST2R { bits }
}
#[doc = "Bit 3 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst3(&self) -> EPRST3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST3R { bits }
}
#[doc = "Bit 4 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst4(&self) -> EPRST4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST4R { bits }
}
#[doc = "Bit 5 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst5(&self) -> EPRST5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST5R { bits }
}
#[doc = "Bit 6 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst6(&self) -> EPRST6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST6R { bits }
}
#[doc = "Bit 7 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst7(&self) -> EPRST7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST7R { bits }
}
#[doc = "Bit 8 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst8(&self) -> EPRST8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST8R { bits }
}
#[doc = "Bit 9 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst9(&self) -> EPRST9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST9R { bits }
}
#[doc = "Bit 10 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst10(&self) -> EPRST10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST10R { bits }
}
#[doc = "Bit 11 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst11(&self) -> EPRST11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST11R { bits }
}
#[doc = "Bit 12 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst12(&self) -> EPRST12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST12R { bits }
}
#[doc = "Bit 13 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst13(&self) -> EPRST13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST13R { bits }
}
#[doc = "Bit 14 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst14(&self) -> EPRST14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST14R { bits }
}
#[doc = "Bit 15 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst15(&self) -> EPRST15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST15R { bits }
}
#[doc = "Bit 16 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst16(&self) -> EPRST16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST16R { bits }
}
#[doc = "Bit 17 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst17(&self) -> EPRST17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST17R { bits }
}
#[doc = "Bit 18 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst18(&self) -> EPRST18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST18R { bits }
}
#[doc = "Bit 19 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst19(&self) -> EPRST19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST19R { bits }
}
#[doc = "Bit 20 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst20(&self) -> EPRST20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST20R { bits }
}
#[doc = "Bit 21 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst21(&self) -> EPRST21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST21R { bits }
}
#[doc = "Bit 22 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst22(&self) -> EPRST22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST22R { bits }
}
#[doc = "Bit 23 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst23(&self) -> EPRST23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST23R { bits }
}
#[doc = "Bit 24 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst24(&self) -> EPRST24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST24R { bits }
}
#[doc = "Bit 25 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst25(&self) -> EPRST25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST25R { bits }
}
#[doc = "Bit 26 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst26(&self) -> EPRST26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST26R { bits }
}
#[doc = "Bit 27 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst27(&self) -> EPRST27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST27R { bits }
}
#[doc = "Bit 28 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst28(&self) -> EPRST28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST28R { bits }
}
#[doc = "Bit 29 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst29(&self) -> EPRST29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST29R { bits }
}
#[doc = "Bit 30 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst30(&self) -> EPRST30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST30R { bits }
}
#[doc = "Bit 31 - Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx."]
#[inline]
pub fn eprst31(&self) -> EPRST31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPRST31R { bits }
}
}
}
#[doc = "USB DMA Request Clear"]
pub struct DMARCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB DMA Request Clear"]
pub mod dmarclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMARCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR8W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR9W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR10W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR11W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR12W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR13W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR14W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR15W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR16W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR17W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR18W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR19W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR20W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR21W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR22W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR23W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR24W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR25W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR26W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR27W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR28W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR29W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR30W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRCLR31W<'a> {
w: &'a mut W,
}
impl<'a> _EPRCLR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)."]
#[inline]
pub fn eprclr0(&mut self) -> _EPRCLR0W {
_EPRCLR0W { w: self }
}
#[doc = "Bit 1 - Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)."]
#[inline]
pub fn eprclr1(&mut self) -> _EPRCLR1W {
_EPRCLR1W { w: self }
}
#[doc = "Bit 2 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr2(&mut self) -> _EPRCLR2W {
_EPRCLR2W { w: self }
}
#[doc = "Bit 3 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr3(&mut self) -> _EPRCLR3W {
_EPRCLR3W { w: self }
}
#[doc = "Bit 4 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr4(&mut self) -> _EPRCLR4W {
_EPRCLR4W { w: self }
}
#[doc = "Bit 5 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr5(&mut self) -> _EPRCLR5W {
_EPRCLR5W { w: self }
}
#[doc = "Bit 6 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr6(&mut self) -> _EPRCLR6W {
_EPRCLR6W { w: self }
}
#[doc = "Bit 7 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr7(&mut self) -> _EPRCLR7W {
_EPRCLR7W { w: self }
}
#[doc = "Bit 8 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr8(&mut self) -> _EPRCLR8W {
_EPRCLR8W { w: self }
}
#[doc = "Bit 9 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr9(&mut self) -> _EPRCLR9W {
_EPRCLR9W { w: self }
}
#[doc = "Bit 10 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr10(&mut self) -> _EPRCLR10W {
_EPRCLR10W { w: self }
}
#[doc = "Bit 11 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr11(&mut self) -> _EPRCLR11W {
_EPRCLR11W { w: self }
}
#[doc = "Bit 12 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr12(&mut self) -> _EPRCLR12W {
_EPRCLR12W { w: self }
}
#[doc = "Bit 13 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr13(&mut self) -> _EPRCLR13W {
_EPRCLR13W { w: self }
}
#[doc = "Bit 14 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr14(&mut self) -> _EPRCLR14W {
_EPRCLR14W { w: self }
}
#[doc = "Bit 15 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr15(&mut self) -> _EPRCLR15W {
_EPRCLR15W { w: self }
}
#[doc = "Bit 16 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr16(&mut self) -> _EPRCLR16W {
_EPRCLR16W { w: self }
}
#[doc = "Bit 17 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr17(&mut self) -> _EPRCLR17W {
_EPRCLR17W { w: self }
}
#[doc = "Bit 18 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr18(&mut self) -> _EPRCLR18W {
_EPRCLR18W { w: self }
}
#[doc = "Bit 19 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr19(&mut self) -> _EPRCLR19W {
_EPRCLR19W { w: self }
}
#[doc = "Bit 20 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr20(&mut self) -> _EPRCLR20W {
_EPRCLR20W { w: self }
}
#[doc = "Bit 21 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr21(&mut self) -> _EPRCLR21W {
_EPRCLR21W { w: self }
}
#[doc = "Bit 22 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr22(&mut self) -> _EPRCLR22W {
_EPRCLR22W { w: self }
}
#[doc = "Bit 23 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr23(&mut self) -> _EPRCLR23W {
_EPRCLR23W { w: self }
}
#[doc = "Bit 24 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr24(&mut self) -> _EPRCLR24W {
_EPRCLR24W { w: self }
}
#[doc = "Bit 25 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr25(&mut self) -> _EPRCLR25W {
_EPRCLR25W { w: self }
}
#[doc = "Bit 26 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr26(&mut self) -> _EPRCLR26W {
_EPRCLR26W { w: self }
}
#[doc = "Bit 27 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr27(&mut self) -> _EPRCLR27W {
_EPRCLR27W { w: self }
}
#[doc = "Bit 28 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr28(&mut self) -> _EPRCLR28W {
_EPRCLR28W { w: self }
}
#[doc = "Bit 29 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr29(&mut self) -> _EPRCLR29W {
_EPRCLR29W { w: self }
}
#[doc = "Bit 30 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr30(&mut self) -> _EPRCLR30W {
_EPRCLR30W { w: self }
}
#[doc = "Bit 31 - Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprclr31(&mut self) -> _EPRCLR31W {
_EPRCLR31W { w: self }
}
}
}
#[doc = "USB DMA Request Set"]
pub struct DMARSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB DMA Request Set"]
pub mod dmarset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMARSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPRSET0W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET1W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET2W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET3W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET4W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET5W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET6W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET7W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET8W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET9W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET10W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET11W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET12W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET13W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET14W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET15W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET16W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET17W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET18W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET19W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET20W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET21W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET22W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET23W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET24W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET25W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET26W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET27W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET28W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET29W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET30W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPRSET31W<'a> {
w: &'a mut W,
}
impl<'a> _EPRSET31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)."]
#[inline]
pub fn eprset0(&mut self) -> _EPRSET0W {
_EPRSET0W { w: self }
}
#[doc = "Bit 1 - Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)."]
#[inline]
pub fn eprset1(&mut self) -> _EPRSET1W {
_EPRSET1W { w: self }
}
#[doc = "Bit 2 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset2(&mut self) -> _EPRSET2W {
_EPRSET2W { w: self }
}
#[doc = "Bit 3 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset3(&mut self) -> _EPRSET3W {
_EPRSET3W { w: self }
}
#[doc = "Bit 4 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset4(&mut self) -> _EPRSET4W {
_EPRSET4W { w: self }
}
#[doc = "Bit 5 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset5(&mut self) -> _EPRSET5W {
_EPRSET5W { w: self }
}
#[doc = "Bit 6 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset6(&mut self) -> _EPRSET6W {
_EPRSET6W { w: self }
}
#[doc = "Bit 7 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset7(&mut self) -> _EPRSET7W {
_EPRSET7W { w: self }
}
#[doc = "Bit 8 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset8(&mut self) -> _EPRSET8W {
_EPRSET8W { w: self }
}
#[doc = "Bit 9 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset9(&mut self) -> _EPRSET9W {
_EPRSET9W { w: self }
}
#[doc = "Bit 10 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset10(&mut self) -> _EPRSET10W {
_EPRSET10W { w: self }
}
#[doc = "Bit 11 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset11(&mut self) -> _EPRSET11W {
_EPRSET11W { w: self }
}
#[doc = "Bit 12 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset12(&mut self) -> _EPRSET12W {
_EPRSET12W { w: self }
}
#[doc = "Bit 13 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset13(&mut self) -> _EPRSET13W {
_EPRSET13W { w: self }
}
#[doc = "Bit 14 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset14(&mut self) -> _EPRSET14W {
_EPRSET14W { w: self }
}
#[doc = "Bit 15 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset15(&mut self) -> _EPRSET15W {
_EPRSET15W { w: self }
}
#[doc = "Bit 16 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset16(&mut self) -> _EPRSET16W {
_EPRSET16W { w: self }
}
#[doc = "Bit 17 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset17(&mut self) -> _EPRSET17W {
_EPRSET17W { w: self }
}
#[doc = "Bit 18 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset18(&mut self) -> _EPRSET18W {
_EPRSET18W { w: self }
}
#[doc = "Bit 19 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset19(&mut self) -> _EPRSET19W {
_EPRSET19W { w: self }
}
#[doc = "Bit 20 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset20(&mut self) -> _EPRSET20W {
_EPRSET20W { w: self }
}
#[doc = "Bit 21 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset21(&mut self) -> _EPRSET21W {
_EPRSET21W { w: self }
}
#[doc = "Bit 22 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset22(&mut self) -> _EPRSET22W {
_EPRSET22W { w: self }
}
#[doc = "Bit 23 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset23(&mut self) -> _EPRSET23W {
_EPRSET23W { w: self }
}
#[doc = "Bit 24 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset24(&mut self) -> _EPRSET24W {
_EPRSET24W { w: self }
}
#[doc = "Bit 25 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset25(&mut self) -> _EPRSET25W {
_EPRSET25W { w: self }
}
#[doc = "Bit 26 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset26(&mut self) -> _EPRSET26W {
_EPRSET26W { w: self }
}
#[doc = "Bit 27 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset27(&mut self) -> _EPRSET27W {
_EPRSET27W { w: self }
}
#[doc = "Bit 28 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset28(&mut self) -> _EPRSET28W {
_EPRSET28W { w: self }
}
#[doc = "Bit 29 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset29(&mut self) -> _EPRSET29W {
_EPRSET29W { w: self }
}
#[doc = "Bit 30 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset30(&mut self) -> _EPRSET30W {
_EPRSET30W { w: self }
}
#[doc = "Bit 31 - Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt."]
#[inline]
pub fn eprset31(&mut self) -> _EPRSET31W {
_EPRSET31W { w: self }
}
}
}
#[doc = "USB UDCA Head"]
pub struct UDCAH {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB UDCA Head"]
pub mod udcah {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::UDCAH {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct UDCA_ADDRR {
bits: u32,
}
impl UDCA_ADDRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _UDCA_ADDRW<'a> {
w: &'a mut W,
}
impl<'a> _UDCA_ADDRW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x01ff_ffff;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 7:31 - Start address of the UDCA."]
#[inline]
pub fn udca_addr(&self) -> UDCA_ADDRR {
let bits = {
const MASK: u32 = 0x01ff_ffff;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) as u32
};
UDCA_ADDRR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 7:31 - Start address of the UDCA."]
#[inline]
pub fn udca_addr(&mut self) -> _UDCA_ADDRW {
_UDCA_ADDRW { w: self }
}
}
}
#[doc = "USB Endpoint DMA Status"]
pub struct EPDMAST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint DMA Status"]
pub mod epdmast {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::EPDMAST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST0R {
bits: bool,
}
impl EP_DMA_ST0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST1R {
bits: bool,
}
impl EP_DMA_ST1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST2R {
bits: bool,
}
impl EP_DMA_ST2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST3R {
bits: bool,
}
impl EP_DMA_ST3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST4R {
bits: bool,
}
impl EP_DMA_ST4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST5R {
bits: bool,
}
impl EP_DMA_ST5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST6R {
bits: bool,
}
impl EP_DMA_ST6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST7R {
bits: bool,
}
impl EP_DMA_ST7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST8R {
bits: bool,
}
impl EP_DMA_ST8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST9R {
bits: bool,
}
impl EP_DMA_ST9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST10R {
bits: bool,
}
impl EP_DMA_ST10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST11R {
bits: bool,
}
impl EP_DMA_ST11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST12R {
bits: bool,
}
impl EP_DMA_ST12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST13R {
bits: bool,
}
impl EP_DMA_ST13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST14R {
bits: bool,
}
impl EP_DMA_ST14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST15R {
bits: bool,
}
impl EP_DMA_ST15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST16R {
bits: bool,
}
impl EP_DMA_ST16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST17R {
bits: bool,
}
impl EP_DMA_ST17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST18R {
bits: bool,
}
impl EP_DMA_ST18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST19R {
bits: bool,
}
impl EP_DMA_ST19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST20R {
bits: bool,
}
impl EP_DMA_ST20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST21R {
bits: bool,
}
impl EP_DMA_ST21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST22R {
bits: bool,
}
impl EP_DMA_ST22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST23R {
bits: bool,
}
impl EP_DMA_ST23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST24R {
bits: bool,
}
impl EP_DMA_ST24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST25R {
bits: bool,
}
impl EP_DMA_ST25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST26R {
bits: bool,
}
impl EP_DMA_ST26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST27R {
bits: bool,
}
impl EP_DMA_ST27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST28R {
bits: bool,
}
impl EP_DMA_ST28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST29R {
bits: bool,
}
impl EP_DMA_ST29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST30R {
bits: bool,
}
impl EP_DMA_ST30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EP_DMA_ST31R {
bits: bool,
}
impl EP_DMA_ST31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)."]
#[inline]
pub fn ep_dma_st0(&self) -> EP_DMA_ST0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST0R { bits }
}
#[doc = "Bit 1 - Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)."]
#[inline]
pub fn ep_dma_st1(&self) -> EP_DMA_ST1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST1R { bits }
}
#[doc = "Bit 2 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st2(&self) -> EP_DMA_ST2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST2R { bits }
}
#[doc = "Bit 3 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st3(&self) -> EP_DMA_ST3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST3R { bits }
}
#[doc = "Bit 4 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st4(&self) -> EP_DMA_ST4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST4R { bits }
}
#[doc = "Bit 5 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st5(&self) -> EP_DMA_ST5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST5R { bits }
}
#[doc = "Bit 6 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st6(&self) -> EP_DMA_ST6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST6R { bits }
}
#[doc = "Bit 7 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st7(&self) -> EP_DMA_ST7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST7R { bits }
}
#[doc = "Bit 8 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st8(&self) -> EP_DMA_ST8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST8R { bits }
}
#[doc = "Bit 9 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st9(&self) -> EP_DMA_ST9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST9R { bits }
}
#[doc = "Bit 10 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st10(&self) -> EP_DMA_ST10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST10R { bits }
}
#[doc = "Bit 11 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st11(&self) -> EP_DMA_ST11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST11R { bits }
}
#[doc = "Bit 12 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st12(&self) -> EP_DMA_ST12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST12R { bits }
}
#[doc = "Bit 13 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st13(&self) -> EP_DMA_ST13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST13R { bits }
}
#[doc = "Bit 14 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st14(&self) -> EP_DMA_ST14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST14R { bits }
}
#[doc = "Bit 15 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st15(&self) -> EP_DMA_ST15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST15R { bits }
}
#[doc = "Bit 16 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st16(&self) -> EP_DMA_ST16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST16R { bits }
}
#[doc = "Bit 17 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st17(&self) -> EP_DMA_ST17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST17R { bits }
}
#[doc = "Bit 18 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st18(&self) -> EP_DMA_ST18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST18R { bits }
}
#[doc = "Bit 19 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st19(&self) -> EP_DMA_ST19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST19R { bits }
}
#[doc = "Bit 20 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st20(&self) -> EP_DMA_ST20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST20R { bits }
}
#[doc = "Bit 21 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st21(&self) -> EP_DMA_ST21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST21R { bits }
}
#[doc = "Bit 22 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st22(&self) -> EP_DMA_ST22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST22R { bits }
}
#[doc = "Bit 23 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st23(&self) -> EP_DMA_ST23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST23R { bits }
}
#[doc = "Bit 24 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st24(&self) -> EP_DMA_ST24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST24R { bits }
}
#[doc = "Bit 25 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st25(&self) -> EP_DMA_ST25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST25R { bits }
}
#[doc = "Bit 26 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st26(&self) -> EP_DMA_ST26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST26R { bits }
}
#[doc = "Bit 27 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st27(&self) -> EP_DMA_ST27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST27R { bits }
}
#[doc = "Bit 28 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st28(&self) -> EP_DMA_ST28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST28R { bits }
}
#[doc = "Bit 29 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st29(&self) -> EP_DMA_ST29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST29R { bits }
}
#[doc = "Bit 30 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st30(&self) -> EP_DMA_ST30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST30R { bits }
}
#[doc = "Bit 31 - Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled."]
#[inline]
pub fn ep_dma_st31(&self) -> EP_DMA_ST31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EP_DMA_ST31R { bits }
}
}
}
#[doc = "USB Endpoint DMA Enable"]
pub struct EPDMAEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint DMA Enable"]
pub mod epdmaen {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPDMAEN {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_EN0W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_EN0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_EN1W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_EN1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_ENW<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_ENW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 0x3fff_ffff;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)."]
#[inline]
pub fn ep_dma_en0(&mut self) -> _EP_DMA_EN0W {
_EP_DMA_EN0W { w: self }
}
#[doc = "Bit 1 - Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)."]
#[inline]
pub fn ep_dma_en1(&mut self) -> _EP_DMA_EN1W {
_EP_DMA_EN1W { w: self }
}
#[doc = "Bits 2:31 - Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_en(&mut self) -> _EP_DMA_ENW {
_EP_DMA_ENW { w: self }
}
}
}
#[doc = "USB Endpoint DMA Disable"]
pub struct EPDMADIS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Endpoint DMA Disable"]
pub mod epdmadis {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EPDMADIS {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS0W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS1W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS2W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS3W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS4W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS5W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS6W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS7W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS8W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS9W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS10W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS11W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS12W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS13W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS14W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS15W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS16W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS17W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS18W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS19W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS20W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS21W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS22W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS23W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS24W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS25W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS26W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS27W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS28W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS29W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS30W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EP_DMA_DIS31W<'a> {
w: &'a mut W,
}
impl<'a> _EP_DMA_DIS31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)."]
#[inline]
pub fn ep_dma_dis0(&mut self) -> _EP_DMA_DIS0W {
_EP_DMA_DIS0W { w: self }
}
#[doc = "Bit 1 - Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)."]
#[inline]
pub fn ep_dma_dis1(&mut self) -> _EP_DMA_DIS1W {
_EP_DMA_DIS1W { w: self }
}
#[doc = "Bit 2 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis2(&mut self) -> _EP_DMA_DIS2W {
_EP_DMA_DIS2W { w: self }
}
#[doc = "Bit 3 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis3(&mut self) -> _EP_DMA_DIS3W {
_EP_DMA_DIS3W { w: self }
}
#[doc = "Bit 4 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis4(&mut self) -> _EP_DMA_DIS4W {
_EP_DMA_DIS4W { w: self }
}
#[doc = "Bit 5 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis5(&mut self) -> _EP_DMA_DIS5W {
_EP_DMA_DIS5W { w: self }
}
#[doc = "Bit 6 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis6(&mut self) -> _EP_DMA_DIS6W {
_EP_DMA_DIS6W { w: self }
}
#[doc = "Bit 7 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis7(&mut self) -> _EP_DMA_DIS7W {
_EP_DMA_DIS7W { w: self }
}
#[doc = "Bit 8 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis8(&mut self) -> _EP_DMA_DIS8W {
_EP_DMA_DIS8W { w: self }
}
#[doc = "Bit 9 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis9(&mut self) -> _EP_DMA_DIS9W {
_EP_DMA_DIS9W { w: self }
}
#[doc = "Bit 10 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis10(&mut self) -> _EP_DMA_DIS10W {
_EP_DMA_DIS10W { w: self }
}
#[doc = "Bit 11 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis11(&mut self) -> _EP_DMA_DIS11W {
_EP_DMA_DIS11W { w: self }
}
#[doc = "Bit 12 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis12(&mut self) -> _EP_DMA_DIS12W {
_EP_DMA_DIS12W { w: self }
}
#[doc = "Bit 13 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis13(&mut self) -> _EP_DMA_DIS13W {
_EP_DMA_DIS13W { w: self }
}
#[doc = "Bit 14 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis14(&mut self) -> _EP_DMA_DIS14W {
_EP_DMA_DIS14W { w: self }
}
#[doc = "Bit 15 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis15(&mut self) -> _EP_DMA_DIS15W {
_EP_DMA_DIS15W { w: self }
}
#[doc = "Bit 16 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis16(&mut self) -> _EP_DMA_DIS16W {
_EP_DMA_DIS16W { w: self }
}
#[doc = "Bit 17 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis17(&mut self) -> _EP_DMA_DIS17W {
_EP_DMA_DIS17W { w: self }
}
#[doc = "Bit 18 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis18(&mut self) -> _EP_DMA_DIS18W {
_EP_DMA_DIS18W { w: self }
}
#[doc = "Bit 19 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis19(&mut self) -> _EP_DMA_DIS19W {
_EP_DMA_DIS19W { w: self }
}
#[doc = "Bit 20 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis20(&mut self) -> _EP_DMA_DIS20W {
_EP_DMA_DIS20W { w: self }
}
#[doc = "Bit 21 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis21(&mut self) -> _EP_DMA_DIS21W {
_EP_DMA_DIS21W { w: self }
}
#[doc = "Bit 22 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis22(&mut self) -> _EP_DMA_DIS22W {
_EP_DMA_DIS22W { w: self }
}
#[doc = "Bit 23 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis23(&mut self) -> _EP_DMA_DIS23W {
_EP_DMA_DIS23W { w: self }
}
#[doc = "Bit 24 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis24(&mut self) -> _EP_DMA_DIS24W {
_EP_DMA_DIS24W { w: self }
}
#[doc = "Bit 25 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis25(&mut self) -> _EP_DMA_DIS25W {
_EP_DMA_DIS25W { w: self }
}
#[doc = "Bit 26 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis26(&mut self) -> _EP_DMA_DIS26W {
_EP_DMA_DIS26W { w: self }
}
#[doc = "Bit 27 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis27(&mut self) -> _EP_DMA_DIS27W {
_EP_DMA_DIS27W { w: self }
}
#[doc = "Bit 28 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis28(&mut self) -> _EP_DMA_DIS28W {
_EP_DMA_DIS28W { w: self }
}
#[doc = "Bit 29 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis29(&mut self) -> _EP_DMA_DIS29W {
_EP_DMA_DIS29W { w: self }
}
#[doc = "Bit 30 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis30(&mut self) -> _EP_DMA_DIS30W {
_EP_DMA_DIS30W { w: self }
}
#[doc = "Bit 31 - Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx."]
#[inline]
pub fn ep_dma_dis31(&mut self) -> _EP_DMA_DIS31W {
_EP_DMA_DIS31W { w: self }
}
}
}
#[doc = "USB DMA Interrupt Status"]
pub struct DMAINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB DMA Interrupt Status"]
pub mod dmaintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::DMAINTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `EOT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EOTR {
#[doc = "All bits in the USBEoTIntSt register are 0."]
ALL_BITS_IN_THE_USBE,
#[doc = "At least one bit in the USBEoTIntSt is set."]
AT_LEAST_ONE_BIT_IN_,
}
impl EOTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EOTR::ALL_BITS_IN_THE_USBE => false,
EOTR::AT_LEAST_ONE_BIT_IN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EOTR {
match value {
false => EOTR::ALL_BITS_IN_THE_USBE,
true => EOTR::AT_LEAST_ONE_BIT_IN_,
}
}
#[doc = "Checks if the value of the field is `ALL_BITS_IN_THE_USBE`"]
#[inline]
pub fn is_all_bits_in_the_usbe(&self) -> bool {
*self == EOTR::ALL_BITS_IN_THE_USBE
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_BIT_IN_`"]
#[inline]
pub fn is_at_least_one_bit_in_(&self) -> bool {
*self == EOTR::AT_LEAST_ONE_BIT_IN_
}
}
#[doc = "Possible values of the field `NDDR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NDDRR {
#[doc = "All bits in the USBNDDRIntSt register are 0."]
ALL_BITS_IN_THE_USBN,
#[doc = "At least one bit in the USBNDDRIntSt is set."]
AT_LEAST_ONE_BIT_IN_,
}
impl NDDRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
NDDRR::ALL_BITS_IN_THE_USBN => false,
NDDRR::AT_LEAST_ONE_BIT_IN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> NDDRR {
match value {
false => NDDRR::ALL_BITS_IN_THE_USBN,
true => NDDRR::AT_LEAST_ONE_BIT_IN_,
}
}
#[doc = "Checks if the value of the field is `ALL_BITS_IN_THE_USBN`"]
#[inline]
pub fn is_all_bits_in_the_usbn(&self) -> bool {
*self == NDDRR::ALL_BITS_IN_THE_USBN
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_BIT_IN_`"]
#[inline]
pub fn is_at_least_one_bit_in_(&self) -> bool {
*self == NDDRR::AT_LEAST_ONE_BIT_IN_
}
}
#[doc = "Possible values of the field `ERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRR {
#[doc = "All bits in the USBSysErrIntSt register are 0."]
ALL_BITS_IN_THE_USBS,
#[doc = "At least one bit in the USBSysErrIntSt is set."]
AT_LEAST_ONE_BIT_IN_,
}
impl ERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ERRR::ALL_BITS_IN_THE_USBS => false,
ERRR::AT_LEAST_ONE_BIT_IN_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ERRR {
match value {
false => ERRR::ALL_BITS_IN_THE_USBS,
true => ERRR::AT_LEAST_ONE_BIT_IN_,
}
}
#[doc = "Checks if the value of the field is `ALL_BITS_IN_THE_USBS`"]
#[inline]
pub fn is_all_bits_in_the_usbs(&self) -> bool {
*self == ERRR::ALL_BITS_IN_THE_USBS
}
#[doc = "Checks if the value of the field is `AT_LEAST_ONE_BIT_IN_`"]
#[inline]
pub fn is_at_least_one_bit_in_(&self) -> bool {
*self == ERRR::AT_LEAST_ONE_BIT_IN_
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - End of Transfer Interrupt bit."]
#[inline]
pub fn eot(&self) -> EOTR {
EOTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - New DD Request Interrupt bit."]
#[inline]
pub fn nddr(&self) -> NDDRR {
NDDRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - System Error Interrupt bit."]
#[inline]
pub fn err(&self) -> ERRR {
ERRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "USB DMA Interrupt Enable"]
pub struct DMAINTEN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB DMA Interrupt Enable"]
pub mod dmainten {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DMAINTEN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `EOT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EOTR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl EOTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EOTR::DISABLED_ => false,
EOTR::ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EOTR {
match value {
false => EOTR::DISABLED_,
true => EOTR::ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == EOTR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == EOTR::ENABLED_
}
}
#[doc = "Possible values of the field `NDDR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NDDRR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl NDDRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
NDDRR::DISABLED_ => false,
NDDRR::ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> NDDRR {
match value {
false => NDDRR::DISABLED_,
true => NDDRR::ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == NDDRR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == NDDRR::ENABLED_
}
}
#[doc = "Possible values of the field `ERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ERRR {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl ERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ERRR::DISABLED_ => false,
ERRR::ENABLED_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ERRR {
match value {
false => ERRR::DISABLED_,
true => ERRR::ENABLED_,
}
}
#[doc = "Checks if the value of the field is `DISABLED_`"]
#[inline]
pub fn is_disabled_(&self) -> bool {
*self == ERRR::DISABLED_
}
#[doc = "Checks if the value of the field is `ENABLED_`"]
#[inline]
pub fn is_enabled_(&self) -> bool {
*self == ERRR::ENABLED_
}
}
#[doc = "Values that can be written to the field `EOT`"]
pub enum EOTW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl EOTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EOTW::DISABLED_ => false,
EOTW::ENABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EOTW<'a> {
w: &'a mut W,
}
impl<'a> _EOTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EOTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(EOTW::DISABLED_)
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(EOTW::ENABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `NDDR`"]
pub enum NDDRW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl NDDRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
NDDRW::DISABLED_ => false,
NDDRW::ENABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _NDDRW<'a> {
w: &'a mut W,
}
impl<'a> _NDDRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: NDDRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(NDDRW::DISABLED_)
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(NDDRW::ENABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ERR`"]
pub enum ERRW {
#[doc = "Disabled."]
DISABLED_,
#[doc = "Enabled."]
ENABLED_,
}
impl ERRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ERRW::DISABLED_ => false,
ERRW::ENABLED_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ERRW<'a> {
w: &'a mut W,
}
impl<'a> _ERRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ERRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disabled."]
#[inline]
pub fn disabled_(self) -> &'a mut W {
self.variant(ERRW::DISABLED_)
}
#[doc = "Enabled."]
#[inline]
pub fn enabled_(self) -> &'a mut W {
self.variant(ERRW::ENABLED_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - End of Transfer Interrupt enable bit."]
#[inline]
pub fn eot(&self) -> EOTR {
EOTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - New DD Request Interrupt enable bit."]
#[inline]
pub fn nddr(&self) -> NDDRR {
NDDRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - System Error Interrupt enable bit."]
#[inline]
pub fn err(&self) -> ERRR {
ERRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - End of Transfer Interrupt enable bit."]
#[inline]
pub fn eot(&mut self) -> _EOTW {
_EOTW { w: self }
}
#[doc = "Bit 1 - New DD Request Interrupt enable bit."]
#[inline]
pub fn nddr(&mut self) -> _NDDRW {
_NDDRW { w: self }
}
#[doc = "Bit 2 - System Error Interrupt enable bit."]
#[inline]
pub fn err(&mut self) -> _ERRW {
_ERRW { w: self }
}
}
}
#[doc = "USB End of Transfer Interrupt Status"]
pub struct EOTINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB End of Transfer Interrupt Status"]
pub mod eotintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::EOTINTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST0R {
bits: bool,
}
impl EPTXINTST0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST1R {
bits: bool,
}
impl EPTXINTST1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST2R {
bits: bool,
}
impl EPTXINTST2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST3R {
bits: bool,
}
impl EPTXINTST3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST4R {
bits: bool,
}
impl EPTXINTST4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST5R {
bits: bool,
}
impl EPTXINTST5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST6R {
bits: bool,
}
impl EPTXINTST6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST7R {
bits: bool,
}
impl EPTXINTST7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST8R {
bits: bool,
}
impl EPTXINTST8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST9R {
bits: bool,
}
impl EPTXINTST9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST10R {
bits: bool,
}
impl EPTXINTST10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST11R {
bits: bool,
}
impl EPTXINTST11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST12R {
bits: bool,
}
impl EPTXINTST12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST13R {
bits: bool,
}
impl EPTXINTST13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST14R {
bits: bool,
}
impl EPTXINTST14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST15R {
bits: bool,
}
impl EPTXINTST15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST16R {
bits: bool,
}
impl EPTXINTST16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST17R {
bits: bool,
}
impl EPTXINTST17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST18R {
bits: bool,
}
impl EPTXINTST18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST19R {
bits: bool,
}
impl EPTXINTST19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST20R {
bits: bool,
}
impl EPTXINTST20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST21R {
bits: bool,
}
impl EPTXINTST21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST22R {
bits: bool,
}
impl EPTXINTST22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST23R {
bits: bool,
}
impl EPTXINTST23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST24R {
bits: bool,
}
impl EPTXINTST24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST25R {
bits: bool,
}
impl EPTXINTST25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST26R {
bits: bool,
}
impl EPTXINTST26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST27R {
bits: bool,
}
impl EPTXINTST27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST28R {
bits: bool,
}
impl EPTXINTST28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST29R {
bits: bool,
}
impl EPTXINTST29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST30R {
bits: bool,
}
impl EPTXINTST30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPTXINTST31R {
bits: bool,
}
impl EPTXINTST31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst0(&self) -> EPTXINTST0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST0R { bits }
}
#[doc = "Bit 1 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst1(&self) -> EPTXINTST1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST1R { bits }
}
#[doc = "Bit 2 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst2(&self) -> EPTXINTST2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST2R { bits }
}
#[doc = "Bit 3 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst3(&self) -> EPTXINTST3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST3R { bits }
}
#[doc = "Bit 4 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst4(&self) -> EPTXINTST4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST4R { bits }
}
#[doc = "Bit 5 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst5(&self) -> EPTXINTST5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST5R { bits }
}
#[doc = "Bit 6 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst6(&self) -> EPTXINTST6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST6R { bits }
}
#[doc = "Bit 7 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst7(&self) -> EPTXINTST7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST7R { bits }
}
#[doc = "Bit 8 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst8(&self) -> EPTXINTST8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST8R { bits }
}
#[doc = "Bit 9 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst9(&self) -> EPTXINTST9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST9R { bits }
}
#[doc = "Bit 10 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst10(&self) -> EPTXINTST10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST10R { bits }
}
#[doc = "Bit 11 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst11(&self) -> EPTXINTST11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST11R { bits }
}
#[doc = "Bit 12 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst12(&self) -> EPTXINTST12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST12R { bits }
}
#[doc = "Bit 13 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst13(&self) -> EPTXINTST13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST13R { bits }
}
#[doc = "Bit 14 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst14(&self) -> EPTXINTST14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST14R { bits }
}
#[doc = "Bit 15 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst15(&self) -> EPTXINTST15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST15R { bits }
}
#[doc = "Bit 16 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst16(&self) -> EPTXINTST16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST16R { bits }
}
#[doc = "Bit 17 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst17(&self) -> EPTXINTST17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST17R { bits }
}
#[doc = "Bit 18 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst18(&self) -> EPTXINTST18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST18R { bits }
}
#[doc = "Bit 19 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst19(&self) -> EPTXINTST19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST19R { bits }
}
#[doc = "Bit 20 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst20(&self) -> EPTXINTST20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST20R { bits }
}
#[doc = "Bit 21 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst21(&self) -> EPTXINTST21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST21R { bits }
}
#[doc = "Bit 22 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst22(&self) -> EPTXINTST22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST22R { bits }
}
#[doc = "Bit 23 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst23(&self) -> EPTXINTST23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST23R { bits }
}
#[doc = "Bit 24 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst24(&self) -> EPTXINTST24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST24R { bits }
}
#[doc = "Bit 25 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst25(&self) -> EPTXINTST25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST25R { bits }
}
#[doc = "Bit 26 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst26(&self) -> EPTXINTST26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST26R { bits }
}
#[doc = "Bit 27 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst27(&self) -> EPTXINTST27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST27R { bits }
}
#[doc = "Bit 28 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst28(&self) -> EPTXINTST28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST28R { bits }
}
#[doc = "Bit 29 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst29(&self) -> EPTXINTST29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST29R { bits }
}
#[doc = "Bit 30 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst30(&self) -> EPTXINTST30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST30R { bits }
}
#[doc = "Bit 31 - Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx."]
#[inline]
pub fn eptxintst31(&self) -> EPTXINTST31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPTXINTST31R { bits }
}
}
}
#[doc = "USB End of Transfer Interrupt Clear"]
pub struct EOTINTCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB End of Transfer Interrupt Clear"]
pub mod eotintclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EOTINTCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR8W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR9W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR10W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR11W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR12W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR13W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR14W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR15W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR16W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR17W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR18W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR19W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR20W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR21W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR22W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR23W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR24W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR25W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR26W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR27W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR28W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR29W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR30W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTCLR31W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTCLR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr0(&mut self) -> _EPTXINTCLR0W {
_EPTXINTCLR0W { w: self }
}
#[doc = "Bit 1 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr1(&mut self) -> _EPTXINTCLR1W {
_EPTXINTCLR1W { w: self }
}
#[doc = "Bit 2 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr2(&mut self) -> _EPTXINTCLR2W {
_EPTXINTCLR2W { w: self }
}
#[doc = "Bit 3 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr3(&mut self) -> _EPTXINTCLR3W {
_EPTXINTCLR3W { w: self }
}
#[doc = "Bit 4 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr4(&mut self) -> _EPTXINTCLR4W {
_EPTXINTCLR4W { w: self }
}
#[doc = "Bit 5 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr5(&mut self) -> _EPTXINTCLR5W {
_EPTXINTCLR5W { w: self }
}
#[doc = "Bit 6 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr6(&mut self) -> _EPTXINTCLR6W {
_EPTXINTCLR6W { w: self }
}
#[doc = "Bit 7 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr7(&mut self) -> _EPTXINTCLR7W {
_EPTXINTCLR7W { w: self }
}
#[doc = "Bit 8 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr8(&mut self) -> _EPTXINTCLR8W {
_EPTXINTCLR8W { w: self }
}
#[doc = "Bit 9 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr9(&mut self) -> _EPTXINTCLR9W {
_EPTXINTCLR9W { w: self }
}
#[doc = "Bit 10 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr10(&mut self) -> _EPTXINTCLR10W {
_EPTXINTCLR10W { w: self }
}
#[doc = "Bit 11 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr11(&mut self) -> _EPTXINTCLR11W {
_EPTXINTCLR11W { w: self }
}
#[doc = "Bit 12 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr12(&mut self) -> _EPTXINTCLR12W {
_EPTXINTCLR12W { w: self }
}
#[doc = "Bit 13 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr13(&mut self) -> _EPTXINTCLR13W {
_EPTXINTCLR13W { w: self }
}
#[doc = "Bit 14 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr14(&mut self) -> _EPTXINTCLR14W {
_EPTXINTCLR14W { w: self }
}
#[doc = "Bit 15 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr15(&mut self) -> _EPTXINTCLR15W {
_EPTXINTCLR15W { w: self }
}
#[doc = "Bit 16 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr16(&mut self) -> _EPTXINTCLR16W {
_EPTXINTCLR16W { w: self }
}
#[doc = "Bit 17 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr17(&mut self) -> _EPTXINTCLR17W {
_EPTXINTCLR17W { w: self }
}
#[doc = "Bit 18 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr18(&mut self) -> _EPTXINTCLR18W {
_EPTXINTCLR18W { w: self }
}
#[doc = "Bit 19 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr19(&mut self) -> _EPTXINTCLR19W {
_EPTXINTCLR19W { w: self }
}
#[doc = "Bit 20 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr20(&mut self) -> _EPTXINTCLR20W {
_EPTXINTCLR20W { w: self }
}
#[doc = "Bit 21 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr21(&mut self) -> _EPTXINTCLR21W {
_EPTXINTCLR21W { w: self }
}
#[doc = "Bit 22 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr22(&mut self) -> _EPTXINTCLR22W {
_EPTXINTCLR22W { w: self }
}
#[doc = "Bit 23 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr23(&mut self) -> _EPTXINTCLR23W {
_EPTXINTCLR23W { w: self }
}
#[doc = "Bit 24 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr24(&mut self) -> _EPTXINTCLR24W {
_EPTXINTCLR24W { w: self }
}
#[doc = "Bit 25 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr25(&mut self) -> _EPTXINTCLR25W {
_EPTXINTCLR25W { w: self }
}
#[doc = "Bit 26 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr26(&mut self) -> _EPTXINTCLR26W {
_EPTXINTCLR26W { w: self }
}
#[doc = "Bit 27 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr27(&mut self) -> _EPTXINTCLR27W {
_EPTXINTCLR27W { w: self }
}
#[doc = "Bit 28 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr28(&mut self) -> _EPTXINTCLR28W {
_EPTXINTCLR28W { w: self }
}
#[doc = "Bit 29 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr29(&mut self) -> _EPTXINTCLR29W {
_EPTXINTCLR29W { w: self }
}
#[doc = "Bit 30 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr30(&mut self) -> _EPTXINTCLR30W {
_EPTXINTCLR30W { w: self }
}
#[doc = "Bit 31 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintclr31(&mut self) -> _EPTXINTCLR31W {
_EPTXINTCLR31W { w: self }
}
}
}
#[doc = "USB End of Transfer Interrupt Set"]
pub struct EOTINTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB End of Transfer Interrupt Set"]
pub mod eotintset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EOTINTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET0W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET1W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET2W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET3W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET4W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET5W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET6W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET7W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET8W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET9W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET10W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET11W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET12W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET13W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET14W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET15W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET16W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET17W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET18W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET19W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET20W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET21W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET22W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET23W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET24W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET25W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET26W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET27W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET28W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET29W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET30W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPTXINTSET31W<'a> {
w: &'a mut W,
}
impl<'a> _EPTXINTSET31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset0(&mut self) -> _EPTXINTSET0W {
_EPTXINTSET0W { w: self }
}
#[doc = "Bit 1 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset1(&mut self) -> _EPTXINTSET1W {
_EPTXINTSET1W { w: self }
}
#[doc = "Bit 2 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset2(&mut self) -> _EPTXINTSET2W {
_EPTXINTSET2W { w: self }
}
#[doc = "Bit 3 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset3(&mut self) -> _EPTXINTSET3W {
_EPTXINTSET3W { w: self }
}
#[doc = "Bit 4 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset4(&mut self) -> _EPTXINTSET4W {
_EPTXINTSET4W { w: self }
}
#[doc = "Bit 5 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset5(&mut self) -> _EPTXINTSET5W {
_EPTXINTSET5W { w: self }
}
#[doc = "Bit 6 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset6(&mut self) -> _EPTXINTSET6W {
_EPTXINTSET6W { w: self }
}
#[doc = "Bit 7 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset7(&mut self) -> _EPTXINTSET7W {
_EPTXINTSET7W { w: self }
}
#[doc = "Bit 8 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset8(&mut self) -> _EPTXINTSET8W {
_EPTXINTSET8W { w: self }
}
#[doc = "Bit 9 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset9(&mut self) -> _EPTXINTSET9W {
_EPTXINTSET9W { w: self }
}
#[doc = "Bit 10 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset10(&mut self) -> _EPTXINTSET10W {
_EPTXINTSET10W { w: self }
}
#[doc = "Bit 11 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset11(&mut self) -> _EPTXINTSET11W {
_EPTXINTSET11W { w: self }
}
#[doc = "Bit 12 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset12(&mut self) -> _EPTXINTSET12W {
_EPTXINTSET12W { w: self }
}
#[doc = "Bit 13 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset13(&mut self) -> _EPTXINTSET13W {
_EPTXINTSET13W { w: self }
}
#[doc = "Bit 14 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset14(&mut self) -> _EPTXINTSET14W {
_EPTXINTSET14W { w: self }
}
#[doc = "Bit 15 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset15(&mut self) -> _EPTXINTSET15W {
_EPTXINTSET15W { w: self }
}
#[doc = "Bit 16 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset16(&mut self) -> _EPTXINTSET16W {
_EPTXINTSET16W { w: self }
}
#[doc = "Bit 17 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset17(&mut self) -> _EPTXINTSET17W {
_EPTXINTSET17W { w: self }
}
#[doc = "Bit 18 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset18(&mut self) -> _EPTXINTSET18W {
_EPTXINTSET18W { w: self }
}
#[doc = "Bit 19 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset19(&mut self) -> _EPTXINTSET19W {
_EPTXINTSET19W { w: self }
}
#[doc = "Bit 20 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset20(&mut self) -> _EPTXINTSET20W {
_EPTXINTSET20W { w: self }
}
#[doc = "Bit 21 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset21(&mut self) -> _EPTXINTSET21W {
_EPTXINTSET21W { w: self }
}
#[doc = "Bit 22 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset22(&mut self) -> _EPTXINTSET22W {
_EPTXINTSET22W { w: self }
}
#[doc = "Bit 23 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset23(&mut self) -> _EPTXINTSET23W {
_EPTXINTSET23W { w: self }
}
#[doc = "Bit 24 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset24(&mut self) -> _EPTXINTSET24W {
_EPTXINTSET24W { w: self }
}
#[doc = "Bit 25 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset25(&mut self) -> _EPTXINTSET25W {
_EPTXINTSET25W { w: self }
}
#[doc = "Bit 26 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset26(&mut self) -> _EPTXINTSET26W {
_EPTXINTSET26W { w: self }
}
#[doc = "Bit 27 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset27(&mut self) -> _EPTXINTSET27W {
_EPTXINTSET27W { w: self }
}
#[doc = "Bit 28 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset28(&mut self) -> _EPTXINTSET28W {
_EPTXINTSET28W { w: self }
}
#[doc = "Bit 29 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset29(&mut self) -> _EPTXINTSET29W {
_EPTXINTSET29W { w: self }
}
#[doc = "Bit 30 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset30(&mut self) -> _EPTXINTSET30W {
_EPTXINTSET30W { w: self }
}
#[doc = "Bit 31 - Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
#[inline]
pub fn eptxintset31(&mut self) -> _EPTXINTSET31W {
_EPTXINTSET31W { w: self }
}
}
}
#[doc = "USB New DD Request Interrupt Status"]
pub struct NDDRINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB New DD Request Interrupt Status"]
pub mod nddrintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::NDDRINTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST0R {
bits: bool,
}
impl EPNDDINTST0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST1R {
bits: bool,
}
impl EPNDDINTST1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST2R {
bits: bool,
}
impl EPNDDINTST2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST3R {
bits: bool,
}
impl EPNDDINTST3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST4R {
bits: bool,
}
impl EPNDDINTST4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST5R {
bits: bool,
}
impl EPNDDINTST5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST6R {
bits: bool,
}
impl EPNDDINTST6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST7R {
bits: bool,
}
impl EPNDDINTST7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST8R {
bits: bool,
}
impl EPNDDINTST8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST9R {
bits: bool,
}
impl EPNDDINTST9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST10R {
bits: bool,
}
impl EPNDDINTST10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST11R {
bits: bool,
}
impl EPNDDINTST11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST12R {
bits: bool,
}
impl EPNDDINTST12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST13R {
bits: bool,
}
impl EPNDDINTST13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST14R {
bits: bool,
}
impl EPNDDINTST14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST15R {
bits: bool,
}
impl EPNDDINTST15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST16R {
bits: bool,
}
impl EPNDDINTST16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST17R {
bits: bool,
}
impl EPNDDINTST17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST18R {
bits: bool,
}
impl EPNDDINTST18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST19R {
bits: bool,
}
impl EPNDDINTST19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST20R {
bits: bool,
}
impl EPNDDINTST20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST21R {
bits: bool,
}
impl EPNDDINTST21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST22R {
bits: bool,
}
impl EPNDDINTST22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST23R {
bits: bool,
}
impl EPNDDINTST23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST24R {
bits: bool,
}
impl EPNDDINTST24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST25R {
bits: bool,
}
impl EPNDDINTST25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST26R {
bits: bool,
}
impl EPNDDINTST26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST27R {
bits: bool,
}
impl EPNDDINTST27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST28R {
bits: bool,
}
impl EPNDDINTST28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST29R {
bits: bool,
}
impl EPNDDINTST29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST30R {
bits: bool,
}
impl EPNDDINTST30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPNDDINTST31R {
bits: bool,
}
impl EPNDDINTST31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst0(&self) -> EPNDDINTST0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST0R { bits }
}
#[doc = "Bit 1 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst1(&self) -> EPNDDINTST1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST1R { bits }
}
#[doc = "Bit 2 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst2(&self) -> EPNDDINTST2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST2R { bits }
}
#[doc = "Bit 3 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst3(&self) -> EPNDDINTST3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST3R { bits }
}
#[doc = "Bit 4 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst4(&self) -> EPNDDINTST4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST4R { bits }
}
#[doc = "Bit 5 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst5(&self) -> EPNDDINTST5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST5R { bits }
}
#[doc = "Bit 6 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst6(&self) -> EPNDDINTST6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST6R { bits }
}
#[doc = "Bit 7 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst7(&self) -> EPNDDINTST7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST7R { bits }
}
#[doc = "Bit 8 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst8(&self) -> EPNDDINTST8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST8R { bits }
}
#[doc = "Bit 9 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst9(&self) -> EPNDDINTST9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST9R { bits }
}
#[doc = "Bit 10 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst10(&self) -> EPNDDINTST10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST10R { bits }
}
#[doc = "Bit 11 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst11(&self) -> EPNDDINTST11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST11R { bits }
}
#[doc = "Bit 12 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst12(&self) -> EPNDDINTST12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST12R { bits }
}
#[doc = "Bit 13 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst13(&self) -> EPNDDINTST13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST13R { bits }
}
#[doc = "Bit 14 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst14(&self) -> EPNDDINTST14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST14R { bits }
}
#[doc = "Bit 15 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst15(&self) -> EPNDDINTST15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST15R { bits }
}
#[doc = "Bit 16 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst16(&self) -> EPNDDINTST16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST16R { bits }
}
#[doc = "Bit 17 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst17(&self) -> EPNDDINTST17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST17R { bits }
}
#[doc = "Bit 18 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst18(&self) -> EPNDDINTST18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST18R { bits }
}
#[doc = "Bit 19 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst19(&self) -> EPNDDINTST19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST19R { bits }
}
#[doc = "Bit 20 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst20(&self) -> EPNDDINTST20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST20R { bits }
}
#[doc = "Bit 21 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst21(&self) -> EPNDDINTST21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST21R { bits }
}
#[doc = "Bit 22 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst22(&self) -> EPNDDINTST22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST22R { bits }
}
#[doc = "Bit 23 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst23(&self) -> EPNDDINTST23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST23R { bits }
}
#[doc = "Bit 24 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst24(&self) -> EPNDDINTST24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST24R { bits }
}
#[doc = "Bit 25 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst25(&self) -> EPNDDINTST25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST25R { bits }
}
#[doc = "Bit 26 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst26(&self) -> EPNDDINTST26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST26R { bits }
}
#[doc = "Bit 27 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst27(&self) -> EPNDDINTST27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST27R { bits }
}
#[doc = "Bit 28 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst28(&self) -> EPNDDINTST28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST28R { bits }
}
#[doc = "Bit 29 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst29(&self) -> EPNDDINTST29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST29R { bits }
}
#[doc = "Bit 30 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst30(&self) -> EPNDDINTST30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST30R { bits }
}
#[doc = "Bit 31 - Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx."]
#[inline]
pub fn epnddintst31(&self) -> EPNDDINTST31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPNDDINTST31R { bits }
}
}
}
#[doc = "USB New DD Request Interrupt Clear"]
pub struct NDDRINTCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB New DD Request Interrupt Clear"]
pub mod nddrintclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::NDDRINTCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR8W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR9W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR10W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR11W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR12W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR13W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR14W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR15W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR16W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR17W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR18W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR19W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR20W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR21W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR22W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR23W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR24W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR25W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR26W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR27W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR28W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR29W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR30W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTCLR31W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTCLR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr0(&mut self) -> _EPNDDINTCLR0W {
_EPNDDINTCLR0W { w: self }
}
#[doc = "Bit 1 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr1(&mut self) -> _EPNDDINTCLR1W {
_EPNDDINTCLR1W { w: self }
}
#[doc = "Bit 2 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr2(&mut self) -> _EPNDDINTCLR2W {
_EPNDDINTCLR2W { w: self }
}
#[doc = "Bit 3 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr3(&mut self) -> _EPNDDINTCLR3W {
_EPNDDINTCLR3W { w: self }
}
#[doc = "Bit 4 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr4(&mut self) -> _EPNDDINTCLR4W {
_EPNDDINTCLR4W { w: self }
}
#[doc = "Bit 5 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr5(&mut self) -> _EPNDDINTCLR5W {
_EPNDDINTCLR5W { w: self }
}
#[doc = "Bit 6 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr6(&mut self) -> _EPNDDINTCLR6W {
_EPNDDINTCLR6W { w: self }
}
#[doc = "Bit 7 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr7(&mut self) -> _EPNDDINTCLR7W {
_EPNDDINTCLR7W { w: self }
}
#[doc = "Bit 8 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr8(&mut self) -> _EPNDDINTCLR8W {
_EPNDDINTCLR8W { w: self }
}
#[doc = "Bit 9 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr9(&mut self) -> _EPNDDINTCLR9W {
_EPNDDINTCLR9W { w: self }
}
#[doc = "Bit 10 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr10(&mut self) -> _EPNDDINTCLR10W {
_EPNDDINTCLR10W { w: self }
}
#[doc = "Bit 11 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr11(&mut self) -> _EPNDDINTCLR11W {
_EPNDDINTCLR11W { w: self }
}
#[doc = "Bit 12 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr12(&mut self) -> _EPNDDINTCLR12W {
_EPNDDINTCLR12W { w: self }
}
#[doc = "Bit 13 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr13(&mut self) -> _EPNDDINTCLR13W {
_EPNDDINTCLR13W { w: self }
}
#[doc = "Bit 14 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr14(&mut self) -> _EPNDDINTCLR14W {
_EPNDDINTCLR14W { w: self }
}
#[doc = "Bit 15 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr15(&mut self) -> _EPNDDINTCLR15W {
_EPNDDINTCLR15W { w: self }
}
#[doc = "Bit 16 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr16(&mut self) -> _EPNDDINTCLR16W {
_EPNDDINTCLR16W { w: self }
}
#[doc = "Bit 17 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr17(&mut self) -> _EPNDDINTCLR17W {
_EPNDDINTCLR17W { w: self }
}
#[doc = "Bit 18 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr18(&mut self) -> _EPNDDINTCLR18W {
_EPNDDINTCLR18W { w: self }
}
#[doc = "Bit 19 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr19(&mut self) -> _EPNDDINTCLR19W {
_EPNDDINTCLR19W { w: self }
}
#[doc = "Bit 20 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr20(&mut self) -> _EPNDDINTCLR20W {
_EPNDDINTCLR20W { w: self }
}
#[doc = "Bit 21 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr21(&mut self) -> _EPNDDINTCLR21W {
_EPNDDINTCLR21W { w: self }
}
#[doc = "Bit 22 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr22(&mut self) -> _EPNDDINTCLR22W {
_EPNDDINTCLR22W { w: self }
}
#[doc = "Bit 23 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr23(&mut self) -> _EPNDDINTCLR23W {
_EPNDDINTCLR23W { w: self }
}
#[doc = "Bit 24 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr24(&mut self) -> _EPNDDINTCLR24W {
_EPNDDINTCLR24W { w: self }
}
#[doc = "Bit 25 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr25(&mut self) -> _EPNDDINTCLR25W {
_EPNDDINTCLR25W { w: self }
}
#[doc = "Bit 26 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr26(&mut self) -> _EPNDDINTCLR26W {
_EPNDDINTCLR26W { w: self }
}
#[doc = "Bit 27 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr27(&mut self) -> _EPNDDINTCLR27W {
_EPNDDINTCLR27W { w: self }
}
#[doc = "Bit 28 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr28(&mut self) -> _EPNDDINTCLR28W {
_EPNDDINTCLR28W { w: self }
}
#[doc = "Bit 29 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr29(&mut self) -> _EPNDDINTCLR29W {
_EPNDDINTCLR29W { w: self }
}
#[doc = "Bit 30 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr30(&mut self) -> _EPNDDINTCLR30W {
_EPNDDINTCLR30W { w: self }
}
#[doc = "Bit 31 - Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintclr31(&mut self) -> _EPNDDINTCLR31W {
_EPNDDINTCLR31W { w: self }
}
}
}
#[doc = "USB New DD Request Interrupt Set"]
pub struct NDDRINTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB New DD Request Interrupt Set"]
pub mod nddrintset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::NDDRINTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET0W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET1W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET2W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET3W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET4W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET5W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET6W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET7W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET8W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET9W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET10W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET11W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET12W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET13W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET14W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET15W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET16W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET17W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET18W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET19W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET20W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET21W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET22W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET23W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET24W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET25W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET26W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET27W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET28W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET29W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET30W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPNDDINTSET31W<'a> {
w: &'a mut W,
}
impl<'a> _EPNDDINTSET31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset0(&mut self) -> _EPNDDINTSET0W {
_EPNDDINTSET0W { w: self }
}
#[doc = "Bit 1 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset1(&mut self) -> _EPNDDINTSET1W {
_EPNDDINTSET1W { w: self }
}
#[doc = "Bit 2 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset2(&mut self) -> _EPNDDINTSET2W {
_EPNDDINTSET2W { w: self }
}
#[doc = "Bit 3 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset3(&mut self) -> _EPNDDINTSET3W {
_EPNDDINTSET3W { w: self }
}
#[doc = "Bit 4 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset4(&mut self) -> _EPNDDINTSET4W {
_EPNDDINTSET4W { w: self }
}
#[doc = "Bit 5 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset5(&mut self) -> _EPNDDINTSET5W {
_EPNDDINTSET5W { w: self }
}
#[doc = "Bit 6 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset6(&mut self) -> _EPNDDINTSET6W {
_EPNDDINTSET6W { w: self }
}
#[doc = "Bit 7 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset7(&mut self) -> _EPNDDINTSET7W {
_EPNDDINTSET7W { w: self }
}
#[doc = "Bit 8 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset8(&mut self) -> _EPNDDINTSET8W {
_EPNDDINTSET8W { w: self }
}
#[doc = "Bit 9 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset9(&mut self) -> _EPNDDINTSET9W {
_EPNDDINTSET9W { w: self }
}
#[doc = "Bit 10 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset10(&mut self) -> _EPNDDINTSET10W {
_EPNDDINTSET10W { w: self }
}
#[doc = "Bit 11 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset11(&mut self) -> _EPNDDINTSET11W {
_EPNDDINTSET11W { w: self }
}
#[doc = "Bit 12 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset12(&mut self) -> _EPNDDINTSET12W {
_EPNDDINTSET12W { w: self }
}
#[doc = "Bit 13 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset13(&mut self) -> _EPNDDINTSET13W {
_EPNDDINTSET13W { w: self }
}
#[doc = "Bit 14 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset14(&mut self) -> _EPNDDINTSET14W {
_EPNDDINTSET14W { w: self }
}
#[doc = "Bit 15 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset15(&mut self) -> _EPNDDINTSET15W {
_EPNDDINTSET15W { w: self }
}
#[doc = "Bit 16 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset16(&mut self) -> _EPNDDINTSET16W {
_EPNDDINTSET16W { w: self }
}
#[doc = "Bit 17 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset17(&mut self) -> _EPNDDINTSET17W {
_EPNDDINTSET17W { w: self }
}
#[doc = "Bit 18 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset18(&mut self) -> _EPNDDINTSET18W {
_EPNDDINTSET18W { w: self }
}
#[doc = "Bit 19 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset19(&mut self) -> _EPNDDINTSET19W {
_EPNDDINTSET19W { w: self }
}
#[doc = "Bit 20 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset20(&mut self) -> _EPNDDINTSET20W {
_EPNDDINTSET20W { w: self }
}
#[doc = "Bit 21 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset21(&mut self) -> _EPNDDINTSET21W {
_EPNDDINTSET21W { w: self }
}
#[doc = "Bit 22 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset22(&mut self) -> _EPNDDINTSET22W {
_EPNDDINTSET22W { w: self }
}
#[doc = "Bit 23 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset23(&mut self) -> _EPNDDINTSET23W {
_EPNDDINTSET23W { w: self }
}
#[doc = "Bit 24 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset24(&mut self) -> _EPNDDINTSET24W {
_EPNDDINTSET24W { w: self }
}
#[doc = "Bit 25 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset25(&mut self) -> _EPNDDINTSET25W {
_EPNDDINTSET25W { w: self }
}
#[doc = "Bit 26 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset26(&mut self) -> _EPNDDINTSET26W {
_EPNDDINTSET26W { w: self }
}
#[doc = "Bit 27 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset27(&mut self) -> _EPNDDINTSET27W {
_EPNDDINTSET27W { w: self }
}
#[doc = "Bit 28 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset28(&mut self) -> _EPNDDINTSET28W {
_EPNDDINTSET28W { w: self }
}
#[doc = "Bit 29 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset29(&mut self) -> _EPNDDINTSET29W {
_EPNDDINTSET29W { w: self }
}
#[doc = "Bit 30 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset30(&mut self) -> _EPNDDINTSET30W {
_EPNDDINTSET30W { w: self }
}
#[doc = "Bit 31 - Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register."]
#[inline]
pub fn epnddintset31(&mut self) -> _EPNDDINTSET31W {
_EPNDDINTSET31W { w: self }
}
}
}
#[doc = "USB System Error Interrupt Status"]
pub struct SYSERRINTST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB System Error Interrupt Status"]
pub mod syserrintst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::SYSERRINTST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST0R {
bits: bool,
}
impl EPERRINTST0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST1R {
bits: bool,
}
impl EPERRINTST1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST2R {
bits: bool,
}
impl EPERRINTST2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST3R {
bits: bool,
}
impl EPERRINTST3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST4R {
bits: bool,
}
impl EPERRINTST4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST5R {
bits: bool,
}
impl EPERRINTST5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST6R {
bits: bool,
}
impl EPERRINTST6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST7R {
bits: bool,
}
impl EPERRINTST7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST8R {
bits: bool,
}
impl EPERRINTST8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST9R {
bits: bool,
}
impl EPERRINTST9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST10R {
bits: bool,
}
impl EPERRINTST10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST11R {
bits: bool,
}
impl EPERRINTST11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST12R {
bits: bool,
}
impl EPERRINTST12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST13R {
bits: bool,
}
impl EPERRINTST13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST14R {
bits: bool,
}
impl EPERRINTST14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST15R {
bits: bool,
}
impl EPERRINTST15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST16R {
bits: bool,
}
impl EPERRINTST16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST17R {
bits: bool,
}
impl EPERRINTST17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST18R {
bits: bool,
}
impl EPERRINTST18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST19R {
bits: bool,
}
impl EPERRINTST19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST20R {
bits: bool,
}
impl EPERRINTST20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST21R {
bits: bool,
}
impl EPERRINTST21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST22R {
bits: bool,
}
impl EPERRINTST22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST23R {
bits: bool,
}
impl EPERRINTST23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST24R {
bits: bool,
}
impl EPERRINTST24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST25R {
bits: bool,
}
impl EPERRINTST25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST26R {
bits: bool,
}
impl EPERRINTST26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST27R {
bits: bool,
}
impl EPERRINTST27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST28R {
bits: bool,
}
impl EPERRINTST28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST29R {
bits: bool,
}
impl EPERRINTST29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST30R {
bits: bool,
}
impl EPERRINTST30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct EPERRINTST31R {
bits: bool,
}
impl EPERRINTST31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst0(&self) -> EPERRINTST0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST0R { bits }
}
#[doc = "Bit 1 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst1(&self) -> EPERRINTST1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST1R { bits }
}
#[doc = "Bit 2 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst2(&self) -> EPERRINTST2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST2R { bits }
}
#[doc = "Bit 3 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst3(&self) -> EPERRINTST3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST3R { bits }
}
#[doc = "Bit 4 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst4(&self) -> EPERRINTST4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST4R { bits }
}
#[doc = "Bit 5 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst5(&self) -> EPERRINTST5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST5R { bits }
}
#[doc = "Bit 6 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst6(&self) -> EPERRINTST6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST6R { bits }
}
#[doc = "Bit 7 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst7(&self) -> EPERRINTST7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST7R { bits }
}
#[doc = "Bit 8 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst8(&self) -> EPERRINTST8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST8R { bits }
}
#[doc = "Bit 9 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst9(&self) -> EPERRINTST9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST9R { bits }
}
#[doc = "Bit 10 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst10(&self) -> EPERRINTST10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST10R { bits }
}
#[doc = "Bit 11 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst11(&self) -> EPERRINTST11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST11R { bits }
}
#[doc = "Bit 12 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst12(&self) -> EPERRINTST12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST12R { bits }
}
#[doc = "Bit 13 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst13(&self) -> EPERRINTST13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST13R { bits }
}
#[doc = "Bit 14 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst14(&self) -> EPERRINTST14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST14R { bits }
}
#[doc = "Bit 15 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst15(&self) -> EPERRINTST15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST15R { bits }
}
#[doc = "Bit 16 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst16(&self) -> EPERRINTST16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST16R { bits }
}
#[doc = "Bit 17 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst17(&self) -> EPERRINTST17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST17R { bits }
}
#[doc = "Bit 18 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst18(&self) -> EPERRINTST18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST18R { bits }
}
#[doc = "Bit 19 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst19(&self) -> EPERRINTST19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST19R { bits }
}
#[doc = "Bit 20 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst20(&self) -> EPERRINTST20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST20R { bits }
}
#[doc = "Bit 21 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst21(&self) -> EPERRINTST21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST21R { bits }
}
#[doc = "Bit 22 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst22(&self) -> EPERRINTST22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST22R { bits }
}
#[doc = "Bit 23 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst23(&self) -> EPERRINTST23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST23R { bits }
}
#[doc = "Bit 24 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst24(&self) -> EPERRINTST24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST24R { bits }
}
#[doc = "Bit 25 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst25(&self) -> EPERRINTST25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST25R { bits }
}
#[doc = "Bit 26 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst26(&self) -> EPERRINTST26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST26R { bits }
}
#[doc = "Bit 27 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst27(&self) -> EPERRINTST27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST27R { bits }
}
#[doc = "Bit 28 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst28(&self) -> EPERRINTST28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST28R { bits }
}
#[doc = "Bit 29 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst29(&self) -> EPERRINTST29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST29R { bits }
}
#[doc = "Bit 30 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst30(&self) -> EPERRINTST30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST30R { bits }
}
#[doc = "Bit 31 - Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx."]
#[inline]
pub fn eperrintst31(&self) -> EPERRINTST31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
EPERRINTST31R { bits }
}
}
}
#[doc = "USB System Error Interrupt Clear"]
pub struct SYSERRINTCLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB System Error Interrupt Clear"]
pub mod syserrintclr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SYSERRINTCLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR8W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR9W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR10W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR11W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR12W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR13W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR14W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR15W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR16W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR17W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR18W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR19W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR20W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR21W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR22W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR23W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR24W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR25W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR26W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR27W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR28W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR29W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR30W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTCLR31W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTCLR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr0(&mut self) -> _EPERRINTCLR0W {
_EPERRINTCLR0W { w: self }
}
#[doc = "Bit 1 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr1(&mut self) -> _EPERRINTCLR1W {
_EPERRINTCLR1W { w: self }
}
#[doc = "Bit 2 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr2(&mut self) -> _EPERRINTCLR2W {
_EPERRINTCLR2W { w: self }
}
#[doc = "Bit 3 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr3(&mut self) -> _EPERRINTCLR3W {
_EPERRINTCLR3W { w: self }
}
#[doc = "Bit 4 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr4(&mut self) -> _EPERRINTCLR4W {
_EPERRINTCLR4W { w: self }
}
#[doc = "Bit 5 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr5(&mut self) -> _EPERRINTCLR5W {
_EPERRINTCLR5W { w: self }
}
#[doc = "Bit 6 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr6(&mut self) -> _EPERRINTCLR6W {
_EPERRINTCLR6W { w: self }
}
#[doc = "Bit 7 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr7(&mut self) -> _EPERRINTCLR7W {
_EPERRINTCLR7W { w: self }
}
#[doc = "Bit 8 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr8(&mut self) -> _EPERRINTCLR8W {
_EPERRINTCLR8W { w: self }
}
#[doc = "Bit 9 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr9(&mut self) -> _EPERRINTCLR9W {
_EPERRINTCLR9W { w: self }
}
#[doc = "Bit 10 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr10(&mut self) -> _EPERRINTCLR10W {
_EPERRINTCLR10W { w: self }
}
#[doc = "Bit 11 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr11(&mut self) -> _EPERRINTCLR11W {
_EPERRINTCLR11W { w: self }
}
#[doc = "Bit 12 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr12(&mut self) -> _EPERRINTCLR12W {
_EPERRINTCLR12W { w: self }
}
#[doc = "Bit 13 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr13(&mut self) -> _EPERRINTCLR13W {
_EPERRINTCLR13W { w: self }
}
#[doc = "Bit 14 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr14(&mut self) -> _EPERRINTCLR14W {
_EPERRINTCLR14W { w: self }
}
#[doc = "Bit 15 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr15(&mut self) -> _EPERRINTCLR15W {
_EPERRINTCLR15W { w: self }
}
#[doc = "Bit 16 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr16(&mut self) -> _EPERRINTCLR16W {
_EPERRINTCLR16W { w: self }
}
#[doc = "Bit 17 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr17(&mut self) -> _EPERRINTCLR17W {
_EPERRINTCLR17W { w: self }
}
#[doc = "Bit 18 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr18(&mut self) -> _EPERRINTCLR18W {
_EPERRINTCLR18W { w: self }
}
#[doc = "Bit 19 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr19(&mut self) -> _EPERRINTCLR19W {
_EPERRINTCLR19W { w: self }
}
#[doc = "Bit 20 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr20(&mut self) -> _EPERRINTCLR20W {
_EPERRINTCLR20W { w: self }
}
#[doc = "Bit 21 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr21(&mut self) -> _EPERRINTCLR21W {
_EPERRINTCLR21W { w: self }
}
#[doc = "Bit 22 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr22(&mut self) -> _EPERRINTCLR22W {
_EPERRINTCLR22W { w: self }
}
#[doc = "Bit 23 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr23(&mut self) -> _EPERRINTCLR23W {
_EPERRINTCLR23W { w: self }
}
#[doc = "Bit 24 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr24(&mut self) -> _EPERRINTCLR24W {
_EPERRINTCLR24W { w: self }
}
#[doc = "Bit 25 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr25(&mut self) -> _EPERRINTCLR25W {
_EPERRINTCLR25W { w: self }
}
#[doc = "Bit 26 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr26(&mut self) -> _EPERRINTCLR26W {
_EPERRINTCLR26W { w: self }
}
#[doc = "Bit 27 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr27(&mut self) -> _EPERRINTCLR27W {
_EPERRINTCLR27W { w: self }
}
#[doc = "Bit 28 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr28(&mut self) -> _EPERRINTCLR28W {
_EPERRINTCLR28W { w: self }
}
#[doc = "Bit 29 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr29(&mut self) -> _EPERRINTCLR29W {
_EPERRINTCLR29W { w: self }
}
#[doc = "Bit 30 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr30(&mut self) -> _EPERRINTCLR30W {
_EPERRINTCLR30W { w: self }
}
#[doc = "Bit 31 - Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintclr31(&mut self) -> _EPERRINTCLR31W {
_EPERRINTCLR31W { w: self }
}
}
}
#[doc = "USB System Error Interrupt Set"]
pub struct SYSERRINTSET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB System Error Interrupt Set"]
pub mod syserrintset {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SYSERRINTSET {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET0W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET1W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET2W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET3W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET4W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET5W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET6W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET7W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET8W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET9W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET10W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET11W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET12W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET13W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET14W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET15W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET16W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET17W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET18W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET19W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET20W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET21W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET22W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET23W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET24W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET25W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET26W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET27W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET28W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET29W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET30W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _EPERRINTSET31W<'a> {
w: &'a mut W,
}
impl<'a> _EPERRINTSET31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset0(&mut self) -> _EPERRINTSET0W {
_EPERRINTSET0W { w: self }
}
#[doc = "Bit 1 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset1(&mut self) -> _EPERRINTSET1W {
_EPERRINTSET1W { w: self }
}
#[doc = "Bit 2 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset2(&mut self) -> _EPERRINTSET2W {
_EPERRINTSET2W { w: self }
}
#[doc = "Bit 3 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset3(&mut self) -> _EPERRINTSET3W {
_EPERRINTSET3W { w: self }
}
#[doc = "Bit 4 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset4(&mut self) -> _EPERRINTSET4W {
_EPERRINTSET4W { w: self }
}
#[doc = "Bit 5 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset5(&mut self) -> _EPERRINTSET5W {
_EPERRINTSET5W { w: self }
}
#[doc = "Bit 6 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset6(&mut self) -> _EPERRINTSET6W {
_EPERRINTSET6W { w: self }
}
#[doc = "Bit 7 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset7(&mut self) -> _EPERRINTSET7W {
_EPERRINTSET7W { w: self }
}
#[doc = "Bit 8 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset8(&mut self) -> _EPERRINTSET8W {
_EPERRINTSET8W { w: self }
}
#[doc = "Bit 9 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset9(&mut self) -> _EPERRINTSET9W {
_EPERRINTSET9W { w: self }
}
#[doc = "Bit 10 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset10(&mut self) -> _EPERRINTSET10W {
_EPERRINTSET10W { w: self }
}
#[doc = "Bit 11 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset11(&mut self) -> _EPERRINTSET11W {
_EPERRINTSET11W { w: self }
}
#[doc = "Bit 12 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset12(&mut self) -> _EPERRINTSET12W {
_EPERRINTSET12W { w: self }
}
#[doc = "Bit 13 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset13(&mut self) -> _EPERRINTSET13W {
_EPERRINTSET13W { w: self }
}
#[doc = "Bit 14 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset14(&mut self) -> _EPERRINTSET14W {
_EPERRINTSET14W { w: self }
}
#[doc = "Bit 15 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset15(&mut self) -> _EPERRINTSET15W {
_EPERRINTSET15W { w: self }
}
#[doc = "Bit 16 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset16(&mut self) -> _EPERRINTSET16W {
_EPERRINTSET16W { w: self }
}
#[doc = "Bit 17 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset17(&mut self) -> _EPERRINTSET17W {
_EPERRINTSET17W { w: self }
}
#[doc = "Bit 18 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset18(&mut self) -> _EPERRINTSET18W {
_EPERRINTSET18W { w: self }
}
#[doc = "Bit 19 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset19(&mut self) -> _EPERRINTSET19W {
_EPERRINTSET19W { w: self }
}
#[doc = "Bit 20 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset20(&mut self) -> _EPERRINTSET20W {
_EPERRINTSET20W { w: self }
}
#[doc = "Bit 21 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset21(&mut self) -> _EPERRINTSET21W {
_EPERRINTSET21W { w: self }
}
#[doc = "Bit 22 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset22(&mut self) -> _EPERRINTSET22W {
_EPERRINTSET22W { w: self }
}
#[doc = "Bit 23 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset23(&mut self) -> _EPERRINTSET23W {
_EPERRINTSET23W { w: self }
}
#[doc = "Bit 24 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset24(&mut self) -> _EPERRINTSET24W {
_EPERRINTSET24W { w: self }
}
#[doc = "Bit 25 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset25(&mut self) -> _EPERRINTSET25W {
_EPERRINTSET25W { w: self }
}
#[doc = "Bit 26 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset26(&mut self) -> _EPERRINTSET26W {
_EPERRINTSET26W { w: self }
}
#[doc = "Bit 27 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset27(&mut self) -> _EPERRINTSET27W {
_EPERRINTSET27W { w: self }
}
#[doc = "Bit 28 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset28(&mut self) -> _EPERRINTSET28W {
_EPERRINTSET28W { w: self }
}
#[doc = "Bit 29 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset29(&mut self) -> _EPERRINTSET29W {
_EPERRINTSET29W { w: self }
}
#[doc = "Bit 30 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset30(&mut self) -> _EPERRINTSET30W {
_EPERRINTSET30W { w: self }
}
#[doc = "Bit 31 - Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register."]
#[inline]
pub fn eperrintset31(&mut self) -> _EPERRINTSET31W {
_EPERRINTSET31W { w: self }
}
}
}
#[doc = "I2C Receive"]
pub struct I2C_RX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Receive"]
pub mod i2c_rx {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::I2C_RX {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct RXDATAR {
bits: u8,
}
impl RXDATAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Receive data."]
#[inline]
pub fn rxdata(&self) -> RXDATAR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RXDATAR { bits }
}
}
}
#[doc = "I2C Transmit"]
pub struct I2C_WO {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Transmit"]
pub mod i2c_wo {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::I2C_WO {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _TXDATAW<'a> {
w: &'a mut W,
}
impl<'a> _TXDATAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STARTW<'a> {
w: &'a mut W,
}
impl<'a> _STARTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _STOPW<'a> {
w: &'a mut W,
}
impl<'a> _STOPW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Transmit data."]
#[inline]
pub fn txdata(&mut self) -> _TXDATAW {
_TXDATAW { w: self }
}
#[doc = "Bit 8 - When 1, issue a START condition before transmitting this byte."]
#[inline]
pub fn start(&mut self) -> _STARTW {
_STARTW { w: self }
}
#[doc = "Bit 9 - When 1, issue a STOP condition after transmitting this byte."]
#[inline]
pub fn stop(&mut self) -> _STOPW {
_STOPW { w: self }
}
}
}
#[doc = "I2C Status"]
pub struct I2C_STS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Status"]
pub mod i2c_sts {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::I2C_STS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `TDI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TDIR {
#[doc = "Transaction has not completed."]
NOT_COMPLETE,
#[doc = "Transaction completed."]
COMPLETE,
}
impl TDIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TDIR::NOT_COMPLETE => false,
TDIR::COMPLETE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TDIR {
match value {
false => TDIR::NOT_COMPLETE,
true => TDIR::COMPLETE,
}
}
#[doc = "Checks if the value of the field is `NOT_COMPLETE`"]
#[inline]
pub fn is_not_complete(&self) -> bool {
*self == TDIR::NOT_COMPLETE
}
#[doc = "Checks if the value of the field is `COMPLETE`"]
#[inline]
pub fn is_complete(&self) -> bool {
*self == TDIR::COMPLETE
}
}
#[doc = "Possible values of the field `AFI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AFIR {
#[doc = "No arbitration failure on last transmission."]
NO_ARBITRATION_FAILU,
#[doc = "Arbitration failure occurred on last transmission."]
ARBITRATION_FAILURE_,
}
impl AFIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AFIR::NO_ARBITRATION_FAILU => false,
AFIR::ARBITRATION_FAILURE_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AFIR {
match value {
false => AFIR::NO_ARBITRATION_FAILU,
true => AFIR::ARBITRATION_FAILURE_,
}
}
#[doc = "Checks if the value of the field is `NO_ARBITRATION_FAILU`"]
#[inline]
pub fn is_no_arbitration_failu(&self) -> bool {
*self == AFIR::NO_ARBITRATION_FAILU
}
#[doc = "Checks if the value of the field is `ARBITRATION_FAILURE_`"]
#[inline]
pub fn is_arbitration_failure_(&self) -> bool {
*self == AFIR::ARBITRATION_FAILURE_
}
}
#[doc = "Possible values of the field `NAI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NAIR {
#[doc = "Last transmission received an acknowledge."]
ACKNOWLEDGE_RCVD,
#[doc = "Last transmission did not receive an acknowledge."]
NO_ACKNOWLEDGE_RCVD,
}
impl NAIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
NAIR::ACKNOWLEDGE_RCVD => false,
NAIR::NO_ACKNOWLEDGE_RCVD => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> NAIR {
match value {
false => NAIR::ACKNOWLEDGE_RCVD,
true => NAIR::NO_ACKNOWLEDGE_RCVD,
}
}
#[doc = "Checks if the value of the field is `ACKNOWLEDGE_RCVD`"]
#[inline]
pub fn is_acknowledge_rcvd(&self) -> bool {
*self == NAIR::ACKNOWLEDGE_RCVD
}
#[doc = "Checks if the value of the field is `NO_ACKNOWLEDGE_RCVD`"]
#[inline]
pub fn is_no_acknowledge_rcvd(&self) -> bool {
*self == NAIR::NO_ACKNOWLEDGE_RCVD
}
}
#[doc = "Possible values of the field `DRMI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DRMIR {
#[doc = "Master transmitter does not need data."]
BUSY,
#[doc = "Master transmitter needs data."]
NEED_DATA,
}
impl DRMIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DRMIR::BUSY => false,
DRMIR::NEED_DATA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DRMIR {
match value {
false => DRMIR::BUSY,
true => DRMIR::NEED_DATA,
}
}
#[doc = "Checks if the value of the field is `BUSY`"]
#[inline]
pub fn is_busy(&self) -> bool {
*self == DRMIR::BUSY
}
#[doc = "Checks if the value of the field is `NEED_DATA`"]
#[inline]
pub fn is_need_data(&self) -> bool {
*self == DRMIR::NEED_DATA
}
}
#[doc = "Possible values of the field `DRSI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DRSIR {
#[doc = "Slave transmitter does not need data."]
BUSY,
#[doc = "Slave transmitter needs data."]
NEED_DATA,
}
impl DRSIR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DRSIR::BUSY => false,
DRSIR::NEED_DATA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DRSIR {
match value {
false => DRSIR::BUSY,
true => DRSIR::NEED_DATA,
}
}
#[doc = "Checks if the value of the field is `BUSY`"]
#[inline]
pub fn is_busy(&self) -> bool {
*self == DRSIR::BUSY
}
#[doc = "Checks if the value of the field is `NEED_DATA`"]
#[inline]
pub fn is_need_data(&self) -> bool {
*self == DRSIR::NEED_DATA
}
}
#[doc = r" Value of the field"]
pub struct ACTIVER {
bits: bool,
}
impl ACTIVER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SCLR {
bits: bool,
}
impl SCLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SDAR {
bits: bool,
}
impl SDAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `RFF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RFFR {
#[doc = "RX FIFO is not full"]
RX_FIFO_IS_NOT_FULL,
#[doc = "RX FIFO is full"]
RX_FIFO_IS_FULL,
}
impl RFFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RFFR::RX_FIFO_IS_NOT_FULL => false,
RFFR::RX_FIFO_IS_FULL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RFFR {
match value {
false => RFFR::RX_FIFO_IS_NOT_FULL,
true => RFFR::RX_FIFO_IS_FULL,
}
}
#[doc = "Checks if the value of the field is `RX_FIFO_IS_NOT_FULL`"]
#[inline]
pub fn is_rx_fifo_is_not_full(&self) -> bool {
*self == RFFR::RX_FIFO_IS_NOT_FULL
}
#[doc = "Checks if the value of the field is `RX_FIFO_IS_FULL`"]
#[inline]
pub fn is_rx_fifo_is_full(&self) -> bool {
*self == RFFR::RX_FIFO_IS_FULL
}
}
#[doc = "Possible values of the field `RFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RFER {
#[doc = "RX FIFO contains data."]
DATA,
#[doc = "RX FIFO is empty"]
EMPTY,
}
impl RFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RFER::DATA => false,
RFER::EMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RFER {
match value {
false => RFER::DATA,
true => RFER::EMPTY,
}
}
#[doc = "Checks if the value of the field is `DATA`"]
#[inline]
pub fn is_data(&self) -> bool {
*self == RFER::DATA
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == RFER::EMPTY
}
}
#[doc = "Possible values of the field `TFF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TFFR {
#[doc = "TX FIFO is not full."]
TX_FIFO_IS_NOT_FULL_,
#[doc = "TX FIFO is full"]
TX_FIFO_IS_FULL,
}
impl TFFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TFFR::TX_FIFO_IS_NOT_FULL_ => false,
TFFR::TX_FIFO_IS_FULL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TFFR {
match value {
false => TFFR::TX_FIFO_IS_NOT_FULL_,
true => TFFR::TX_FIFO_IS_FULL,
}
}
#[doc = "Checks if the value of the field is `TX_FIFO_IS_NOT_FULL_`"]
#[inline]
pub fn is_tx_fifo_is_not_full_(&self) -> bool {
*self == TFFR::TX_FIFO_IS_NOT_FULL_
}
#[doc = "Checks if the value of the field is `TX_FIFO_IS_FULL`"]
#[inline]
pub fn is_tx_fifo_is_full(&self) -> bool {
*self == TFFR::TX_FIFO_IS_FULL
}
}
#[doc = "Possible values of the field `TFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TFER {
#[doc = "TX FIFO contains valid data."]
VALID_DATA,
#[doc = "TX FIFO is empty"]
EMPTY,
}
impl TFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TFER::VALID_DATA => false,
TFER::EMPTY => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TFER {
match value {
false => TFER::VALID_DATA,
true => TFER::EMPTY,
}
}
#[doc = "Checks if the value of the field is `VALID_DATA`"]
#[inline]
pub fn is_valid_data(&self) -> bool {
*self == TFER::VALID_DATA
}
#[doc = "Checks if the value of the field is `EMPTY`"]
#[inline]
pub fn is_empty(&self) -> bool {
*self == TFER::EMPTY
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions."]
#[inline]
pub fn tdi(&self) -> TDIR {
TDIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register."]
#[inline]
pub fn afi(&self) -> AFIR {
AFIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO."]
#[inline]
pub fn nai(&self) -> NAIR {
NAIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO."]
#[inline]
pub fn drmi(&self) -> DRMIR {
DRMIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO."]
#[inline]
pub fn drsi(&self) -> DRSIR {
DRSIR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.."]
#[inline]
pub fn active(&self) -> ACTIVER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACTIVER { bits }
}
#[doc = "Bit 6 - The current value of the SCL signal."]
#[inline]
pub fn scl(&self) -> SCLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SCLR { bits }
}
#[doc = "Bit 7 - The current value of the SDA signal."]
#[inline]
pub fn sda(&self) -> SDAR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SDAR { bits }
}
#[doc = "Bit 8 - Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it."]
#[inline]
pub fn rff(&self) -> RFFR {
RFFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 9 - Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data."]
#[inline]
pub fn rfe(&self) -> RFER {
RFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 10 - Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full."]
#[inline]
pub fn tff(&self) -> TFFR {
TFFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 11 - Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data."]
#[inline]
pub fn tfe(&self) -> TFER {
TFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
#[doc = "I2C Control"]
pub struct I2C_CTL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Control"]
pub mod i2c_ctl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::I2C_CTL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `TDIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TDIER {
#[doc = "Disable the TDI interrupt."]
DISABLE_THE_TDI_INTE,
#[doc = "Enable the TDI interrupt."]
ENABLE_THE_TDI_INTER,
}
impl TDIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TDIER::DISABLE_THE_TDI_INTE => false,
TDIER::ENABLE_THE_TDI_INTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TDIER {
match value {
false => TDIER::DISABLE_THE_TDI_INTE,
true => TDIER::ENABLE_THE_TDI_INTER,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_TDI_INTE`"]
#[inline]
pub fn is_disable_the_tdi_inte(&self) -> bool {
*self == TDIER::DISABLE_THE_TDI_INTE
}
#[doc = "Checks if the value of the field is `ENABLE_THE_TDI_INTER`"]
#[inline]
pub fn is_enable_the_tdi_inter(&self) -> bool {
*self == TDIER::ENABLE_THE_TDI_INTER
}
}
#[doc = "Possible values of the field `AFIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AFIER {
#[doc = "Disable the AFI."]
DISABLE_THE_AFI_,
#[doc = "Enable the AFI."]
ENABLE_THE_AFI_,
}
impl AFIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AFIER::DISABLE_THE_AFI_ => false,
AFIER::ENABLE_THE_AFI_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AFIER {
match value {
false => AFIER::DISABLE_THE_AFI_,
true => AFIER::ENABLE_THE_AFI_,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_AFI_`"]
#[inline]
pub fn is_disable_the_afi_(&self) -> bool {
*self == AFIER::DISABLE_THE_AFI_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_AFI_`"]
#[inline]
pub fn is_enable_the_afi_(&self) -> bool {
*self == AFIER::ENABLE_THE_AFI_
}
}
#[doc = "Possible values of the field `NAIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum NAIER {
#[doc = "Disable the NAI."]
DISABLE_THE_NAI_,
#[doc = "Enable the NAI."]
ENABLE_THE_NAI_,
}
impl NAIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
NAIER::DISABLE_THE_NAI_ => false,
NAIER::ENABLE_THE_NAI_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> NAIER {
match value {
false => NAIER::DISABLE_THE_NAI_,
true => NAIER::ENABLE_THE_NAI_,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_NAI_`"]
#[inline]
pub fn is_disable_the_nai_(&self) -> bool {
*self == NAIER::DISABLE_THE_NAI_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_NAI_`"]
#[inline]
pub fn is_enable_the_nai_(&self) -> bool {
*self == NAIER::ENABLE_THE_NAI_
}
}
#[doc = "Possible values of the field `DRMIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DRMIER {
#[doc = "Disable the DRMI interrupt."]
DISABLE_THE_DRMI_INT,
#[doc = "Enable the DRMI interrupt."]
ENABLE_THE_DRMI_INTE,
}
impl DRMIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DRMIER::DISABLE_THE_DRMI_INT => false,
DRMIER::ENABLE_THE_DRMI_INTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DRMIER {
match value {
false => DRMIER::DISABLE_THE_DRMI_INT,
true => DRMIER::ENABLE_THE_DRMI_INTE,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_DRMI_INT`"]
#[inline]
pub fn is_disable_the_drmi_int(&self) -> bool {
*self == DRMIER::DISABLE_THE_DRMI_INT
}
#[doc = "Checks if the value of the field is `ENABLE_THE_DRMI_INTE`"]
#[inline]
pub fn is_enable_the_drmi_inte(&self) -> bool {
*self == DRMIER::ENABLE_THE_DRMI_INTE
}
}
#[doc = "Possible values of the field `DRSIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DRSIER {
#[doc = "Disable the DRSI interrupt."]
DISABLE_THE_DRSI_INT,
#[doc = "Enable the DRSI interrupt."]
ENABLE_THE_DRSI_INTE,
}
impl DRSIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DRSIER::DISABLE_THE_DRSI_INT => false,
DRSIER::ENABLE_THE_DRSI_INTE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DRSIER {
match value {
false => DRSIER::DISABLE_THE_DRSI_INT,
true => DRSIER::ENABLE_THE_DRSI_INTE,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_DRSI_INT`"]
#[inline]
pub fn is_disable_the_drsi_int(&self) -> bool {
*self == DRSIER::DISABLE_THE_DRSI_INT
}
#[doc = "Checks if the value of the field is `ENABLE_THE_DRSI_INTE`"]
#[inline]
pub fn is_enable_the_drsi_inte(&self) -> bool {
*self == DRSIER::ENABLE_THE_DRSI_INTE
}
}
#[doc = "Possible values of the field `REFIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum REFIER {
#[doc = "Disable the RFFI."]
DISABLE_THE_RFFI_,
#[doc = "Enable the RFFI."]
ENABLE_THE_RFFI_,
}
impl REFIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
REFIER::DISABLE_THE_RFFI_ => false,
REFIER::ENABLE_THE_RFFI_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> REFIER {
match value {
false => REFIER::DISABLE_THE_RFFI_,
true => REFIER::ENABLE_THE_RFFI_,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_RFFI_`"]
#[inline]
pub fn is_disable_the_rffi_(&self) -> bool {
*self == REFIER::DISABLE_THE_RFFI_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_RFFI_`"]
#[inline]
pub fn is_enable_the_rffi_(&self) -> bool {
*self == REFIER::ENABLE_THE_RFFI_
}
}
#[doc = "Possible values of the field `RFDAIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RFDAIER {
#[doc = "Disable the DAI."]
DISABLE_THE_DAI_,
#[doc = "Enable the DAI."]
ENABLE_THE_DAI_,
}
impl RFDAIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RFDAIER::DISABLE_THE_DAI_ => false,
RFDAIER::ENABLE_THE_DAI_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RFDAIER {
match value {
false => RFDAIER::DISABLE_THE_DAI_,
true => RFDAIER::ENABLE_THE_DAI_,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_DAI_`"]
#[inline]
pub fn is_disable_the_dai_(&self) -> bool {
*self == RFDAIER::DISABLE_THE_DAI_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_DAI_`"]
#[inline]
pub fn is_enable_the_dai_(&self) -> bool {
*self == RFDAIER::ENABLE_THE_DAI_
}
}
#[doc = "Possible values of the field `TFFIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TFFIER {
#[doc = "Disable the TFFI."]
DISABLE_THE_TFFI_,
#[doc = "Enable the TFFI."]
ENABLE_THE_TFFI_,
}
impl TFFIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
TFFIER::DISABLE_THE_TFFI_ => false,
TFFIER::ENABLE_THE_TFFI_ => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> TFFIER {
match value {
false => TFFIER::DISABLE_THE_TFFI_,
true => TFFIER::ENABLE_THE_TFFI_,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_TFFI_`"]
#[inline]
pub fn is_disable_the_tffi_(&self) -> bool {
*self == TFFIER::DISABLE_THE_TFFI_
}
#[doc = "Checks if the value of the field is `ENABLE_THE_TFFI_`"]
#[inline]
pub fn is_enable_the_tffi_(&self) -> bool {
*self == TFFIER::ENABLE_THE_TFFI_
}
}
#[doc = "Possible values of the field `SRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SRSTR {
#[doc = "No reset."]
NO_RESET,
#[doc = "Reset the I2C to idle state. Self clearing."]
RESET,
}
impl SRSTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SRSTR::NO_RESET => false,
SRSTR::RESET => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SRSTR {
match value {
false => SRSTR::NO_RESET,
true => SRSTR::RESET,
}
}
#[doc = "Checks if the value of the field is `NO_RESET`"]
#[inline]
pub fn is_no_reset(&self) -> bool {
*self == SRSTR::NO_RESET
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline]
pub fn is_reset(&self) -> bool {
*self == SRSTR::RESET
}
}
#[doc = "Values that can be written to the field `TDIE`"]
pub enum TDIEW {
#[doc = "Disable the TDI interrupt."]
DISABLE_THE_TDI_INTE,
#[doc = "Enable the TDI interrupt."]
ENABLE_THE_TDI_INTER,
}
impl TDIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TDIEW::DISABLE_THE_TDI_INTE => false,
TDIEW::ENABLE_THE_TDI_INTER => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TDIEW<'a> {
w: &'a mut W,
}
impl<'a> _TDIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TDIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the TDI interrupt."]
#[inline]
pub fn disable_the_tdi_inte(self) -> &'a mut W {
self.variant(TDIEW::DISABLE_THE_TDI_INTE)
}
#[doc = "Enable the TDI interrupt."]
#[inline]
pub fn enable_the_tdi_inter(self) -> &'a mut W {
self.variant(TDIEW::ENABLE_THE_TDI_INTER)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AFIE`"]
pub enum AFIEW {
#[doc = "Disable the AFI."]
DISABLE_THE_AFI_,
#[doc = "Enable the AFI."]
ENABLE_THE_AFI_,
}
impl AFIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AFIEW::DISABLE_THE_AFI_ => false,
AFIEW::ENABLE_THE_AFI_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AFIEW<'a> {
w: &'a mut W,
}
impl<'a> _AFIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AFIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the AFI."]
#[inline]
pub fn disable_the_afi_(self) -> &'a mut W {
self.variant(AFIEW::DISABLE_THE_AFI_)
}
#[doc = "Enable the AFI."]
#[inline]
pub fn enable_the_afi_(self) -> &'a mut W {
self.variant(AFIEW::ENABLE_THE_AFI_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `NAIE`"]
pub enum NAIEW {
#[doc = "Disable the NAI."]
DISABLE_THE_NAI_,
#[doc = "Enable the NAI."]
ENABLE_THE_NAI_,
}
impl NAIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
NAIEW::DISABLE_THE_NAI_ => false,
NAIEW::ENABLE_THE_NAI_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _NAIEW<'a> {
w: &'a mut W,
}
impl<'a> _NAIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: NAIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the NAI."]
#[inline]
pub fn disable_the_nai_(self) -> &'a mut W {
self.variant(NAIEW::DISABLE_THE_NAI_)
}
#[doc = "Enable the NAI."]
#[inline]
pub fn enable_the_nai_(self) -> &'a mut W {
self.variant(NAIEW::ENABLE_THE_NAI_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DRMIE`"]
pub enum DRMIEW {
#[doc = "Disable the DRMI interrupt."]
DISABLE_THE_DRMI_INT,
#[doc = "Enable the DRMI interrupt."]
ENABLE_THE_DRMI_INTE,
}
impl DRMIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DRMIEW::DISABLE_THE_DRMI_INT => false,
DRMIEW::ENABLE_THE_DRMI_INTE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DRMIEW<'a> {
w: &'a mut W,
}
impl<'a> _DRMIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DRMIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the DRMI interrupt."]
#[inline]
pub fn disable_the_drmi_int(self) -> &'a mut W {
self.variant(DRMIEW::DISABLE_THE_DRMI_INT)
}
#[doc = "Enable the DRMI interrupt."]
#[inline]
pub fn enable_the_drmi_inte(self) -> &'a mut W {
self.variant(DRMIEW::ENABLE_THE_DRMI_INTE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DRSIE`"]
pub enum DRSIEW {
#[doc = "Disable the DRSI interrupt."]
DISABLE_THE_DRSI_INT,
#[doc = "Enable the DRSI interrupt."]
ENABLE_THE_DRSI_INTE,
}
impl DRSIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DRSIEW::DISABLE_THE_DRSI_INT => false,
DRSIEW::ENABLE_THE_DRSI_INTE => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DRSIEW<'a> {
w: &'a mut W,
}
impl<'a> _DRSIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DRSIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the DRSI interrupt."]
#[inline]
pub fn disable_the_drsi_int(self) -> &'a mut W {
self.variant(DRSIEW::DISABLE_THE_DRSI_INT)
}
#[doc = "Enable the DRSI interrupt."]
#[inline]
pub fn enable_the_drsi_inte(self) -> &'a mut W {
self.variant(DRSIEW::ENABLE_THE_DRSI_INTE)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `REFIE`"]
pub enum REFIEW {
#[doc = "Disable the RFFI."]
DISABLE_THE_RFFI_,
#[doc = "Enable the RFFI."]
ENABLE_THE_RFFI_,
}
impl REFIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
REFIEW::DISABLE_THE_RFFI_ => false,
REFIEW::ENABLE_THE_RFFI_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _REFIEW<'a> {
w: &'a mut W,
}
impl<'a> _REFIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: REFIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the RFFI."]
#[inline]
pub fn disable_the_rffi_(self) -> &'a mut W {
self.variant(REFIEW::DISABLE_THE_RFFI_)
}
#[doc = "Enable the RFFI."]
#[inline]
pub fn enable_the_rffi_(self) -> &'a mut W {
self.variant(REFIEW::ENABLE_THE_RFFI_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RFDAIE`"]
pub enum RFDAIEW {
#[doc = "Disable the DAI."]
DISABLE_THE_DAI_,
#[doc = "Enable the DAI."]
ENABLE_THE_DAI_,
}
impl RFDAIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RFDAIEW::DISABLE_THE_DAI_ => false,
RFDAIEW::ENABLE_THE_DAI_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RFDAIEW<'a> {
w: &'a mut W,
}
impl<'a> _RFDAIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RFDAIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the DAI."]
#[inline]
pub fn disable_the_dai_(self) -> &'a mut W {
self.variant(RFDAIEW::DISABLE_THE_DAI_)
}
#[doc = "Enable the DAI."]
#[inline]
pub fn enable_the_dai_(self) -> &'a mut W {
self.variant(RFDAIEW::ENABLE_THE_DAI_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `TFFIE`"]
pub enum TFFIEW {
#[doc = "Disable the TFFI."]
DISABLE_THE_TFFI_,
#[doc = "Enable the TFFI."]
ENABLE_THE_TFFI_,
}
impl TFFIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
TFFIEW::DISABLE_THE_TFFI_ => false,
TFFIEW::ENABLE_THE_TFFI_ => true,
}
}
}
#[doc = r" Proxy"]
pub struct _TFFIEW<'a> {
w: &'a mut W,
}
impl<'a> _TFFIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: TFFIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the TFFI."]
#[inline]
pub fn disable_the_tffi_(self) -> &'a mut W {
self.variant(TFFIEW::DISABLE_THE_TFFI_)
}
#[doc = "Enable the TFFI."]
#[inline]
pub fn enable_the_tffi_(self) -> &'a mut W {
self.variant(TFFIEW::ENABLE_THE_TFFI_)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SRST`"]
pub enum SRSTW {
#[doc = "No reset."]
NO_RESET,
#[doc = "Reset the I2C to idle state. Self clearing."]
RESET,
}
impl SRSTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SRSTW::NO_RESET => false,
SRSTW::RESET => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SRSTW<'a> {
w: &'a mut W,
}
impl<'a> _SRSTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SRSTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "No reset."]
#[inline]
pub fn no_reset(self) -> &'a mut W {
self.variant(SRSTW::NO_RESET)
}
#[doc = "Reset the I2C to idle state. Self clearing."]
#[inline]
pub fn reset(self) -> &'a mut W {
self.variant(SRSTW::RESET)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition."]
#[inline]
pub fn tdie(&self) -> TDIER {
TDIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device."]
#[inline]
pub fn afie(&self) -> AFIER {
AFIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged."]
#[inline]
pub fn naie(&self) -> NAIER {
NAIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low."]
#[inline]
pub fn drmie(&self) -> DRMIER {
DRMIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low."]
#[inline]
pub fn drsie(&self) -> DRSIER {
DRSIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 5 - Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data."]
#[inline]
pub fn refie(&self) -> REFIER {
REFIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty)."]
#[inline]
pub fn rfdaie(&self) -> RFDAIER {
RFDAIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register."]
#[inline]
pub fn tffie(&self) -> TFFIER {
TFFIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 8 - Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset."]
#[inline]
pub fn srst(&self) -> SRSTR {
SRSTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition."]
#[inline]
pub fn tdie(&mut self) -> _TDIEW {
_TDIEW { w: self }
}
#[doc = "Bit 1 - Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device."]
#[inline]
pub fn afie(&mut self) -> _AFIEW {
_AFIEW { w: self }
}
#[doc = "Bit 2 - Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged."]
#[inline]
pub fn naie(&mut self) -> _NAIEW {
_NAIEW { w: self }
}
#[doc = "Bit 3 - Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low."]
#[inline]
pub fn drmie(&mut self) -> _DRMIEW {
_DRMIEW { w: self }
}
#[doc = "Bit 4 - Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low."]
#[inline]
pub fn drsie(&mut self) -> _DRSIEW {
_DRSIEW { w: self }
}
#[doc = "Bit 5 - Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data."]
#[inline]
pub fn refie(&mut self) -> _REFIEW {
_REFIEW { w: self }
}
#[doc = "Bit 6 - Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty)."]
#[inline]
pub fn rfdaie(&mut self) -> _RFDAIEW {
_RFDAIEW { w: self }
}
#[doc = "Bit 7 - Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register."]
#[inline]
pub fn tffie(&mut self) -> _TFFIEW {
_TFFIEW { w: self }
}
#[doc = "Bit 8 - Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset."]
#[inline]
pub fn srst(&mut self) -> _SRSTW {
_SRSTW { w: self }
}
}
}
#[doc = "I2C Clock High"]
pub struct I2C_CLKHI {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Clock High"]
pub mod i2c_clkhi {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::I2C_CLKHI {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CDHIR {
bits: u8,
}
impl CDHIR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CDHIW<'a> {
w: &'a mut W,
}
impl<'a> _CDHIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high."]
#[inline]
pub fn cdhi(&self) -> CDHIR {
let bits = {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CDHIR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xb9 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high."]
#[inline]
pub fn cdhi(&mut self) -> _CDHIW {
_CDHIW { w: self }
}
}
}
#[doc = "I2C Clock Low"]
pub struct I2C_CLKLO {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "I2C Clock Low"]
pub mod i2c_clklo {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::I2C_CLKLO {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _CDLOW<'a> {
w: &'a mut W,
}
impl<'a> _CDLOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 0xff;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0xb9 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low."]
#[inline]
pub fn cdlo(&mut self) -> _CDLOW {
_CDLOW { w: self }
}
}
}
#[doc = "USB Clock Control"]
pub struct USBCLKCTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Clock Control"]
pub mod usbclkctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::USBCLKCTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DEV_CLK_ENR {
bits: bool,
}
impl DEV_CLK_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PORTSEL_CLK_ENR {
bits: bool,
}
impl PORTSEL_CLK_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AHB_CLK_ENR {
bits: bool,
}
impl AHB_CLK_ENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _DEV_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _DEV_CLK_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PORTSEL_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _PORTSEL_CLK_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AHB_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _AHB_CLK_ENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Device clock enable. Enables the usbclk input to the device controller"]
#[inline]
pub fn dev_clk_en(&self) -> DEV_CLK_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DEV_CLK_ENR { bits }
}
#[doc = "Bit 3 - Port select register clock enable."]
#[inline]
pub fn portsel_clk_en(&self) -> PORTSEL_CLK_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PORTSEL_CLK_ENR { bits }
}
#[doc = "Bit 4 - AHB clock enable"]
#[inline]
pub fn ahb_clk_en(&self) -> AHB_CLK_ENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AHB_CLK_ENR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 1 - Device clock enable. Enables the usbclk input to the device controller"]
#[inline]
pub fn dev_clk_en(&mut self) -> _DEV_CLK_ENW {
_DEV_CLK_ENW { w: self }
}
#[doc = "Bit 3 - Port select register clock enable."]
#[inline]
pub fn portsel_clk_en(&mut self) -> _PORTSEL_CLK_ENW {
_PORTSEL_CLK_ENW { w: self }
}
#[doc = "Bit 4 - AHB clock enable"]
#[inline]
pub fn ahb_clk_en(&mut self) -> _AHB_CLK_ENW {
_AHB_CLK_ENW { w: self }
}
}
}
#[doc = "OTG clock controller"]
pub struct OTGCLKCTRL {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG clock controller"]
pub mod otgclkctrl {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OTGCLKCTRL {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `HOST_CLK_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HOST_CLK_ENR {
#[doc = "Disable the Host clock."]
DISABLE_THE_HOST_CLO,
#[doc = "Enable the Host clock."]
ENABLE_THE_HOST_CLOC,
}
impl HOST_CLK_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
HOST_CLK_ENR::DISABLE_THE_HOST_CLO => false,
HOST_CLK_ENR::ENABLE_THE_HOST_CLOC => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> HOST_CLK_ENR {
match value {
false => HOST_CLK_ENR::DISABLE_THE_HOST_CLO,
true => HOST_CLK_ENR::ENABLE_THE_HOST_CLOC,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_HOST_CLO`"]
#[inline]
pub fn is_disable_the_host_clo(&self) -> bool {
*self == HOST_CLK_ENR::DISABLE_THE_HOST_CLO
}
#[doc = "Checks if the value of the field is `ENABLE_THE_HOST_CLOC`"]
#[inline]
pub fn is_enable_the_host_cloc(&self) -> bool {
*self == HOST_CLK_ENR::ENABLE_THE_HOST_CLOC
}
}
#[doc = "Possible values of the field `DEV_CLK_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DEV_CLK_ENR {
#[doc = "Disable the Device clock."]
DISABLE_THE_DEVICE_C,
#[doc = "Enable the Device clock."]
ENABLE_THE_DEVICE_CL,
}
impl DEV_CLK_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DEV_CLK_ENR::DISABLE_THE_DEVICE_C => false,
DEV_CLK_ENR::ENABLE_THE_DEVICE_CL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DEV_CLK_ENR {
match value {
false => DEV_CLK_ENR::DISABLE_THE_DEVICE_C,
true => DEV_CLK_ENR::ENABLE_THE_DEVICE_CL,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_DEVICE_C`"]
#[inline]
pub fn is_disable_the_device_c(&self) -> bool {
*self == DEV_CLK_ENR::DISABLE_THE_DEVICE_C
}
#[doc = "Checks if the value of the field is `ENABLE_THE_DEVICE_CL`"]
#[inline]
pub fn is_enable_the_device_cl(&self) -> bool {
*self == DEV_CLK_ENR::ENABLE_THE_DEVICE_CL
}
}
#[doc = "Possible values of the field `I2C_CLK_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C_CLK_ENR {
#[doc = "Disable the I2C clock."]
DISABLE_THE_I2C_CLOC,
#[doc = "Enable the I2C clock."]
ENABLE_THE_I2C_CLOCK,
}
impl I2C_CLK_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
I2C_CLK_ENR::DISABLE_THE_I2C_CLOC => false,
I2C_CLK_ENR::ENABLE_THE_I2C_CLOCK => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> I2C_CLK_ENR {
match value {
false => I2C_CLK_ENR::DISABLE_THE_I2C_CLOC,
true => I2C_CLK_ENR::ENABLE_THE_I2C_CLOCK,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_I2C_CLOC`"]
#[inline]
pub fn is_disable_the_i2c_cloc(&self) -> bool {
*self == I2C_CLK_ENR::DISABLE_THE_I2C_CLOC
}
#[doc = "Checks if the value of the field is `ENABLE_THE_I2C_CLOCK`"]
#[inline]
pub fn is_enable_the_i2c_clock(&self) -> bool {
*self == I2C_CLK_ENR::ENABLE_THE_I2C_CLOCK
}
}
#[doc = "Possible values of the field `OTG_CLK_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OTG_CLK_ENR {
#[doc = "Disable the OTG clock."]
DISABLE_THE_OTG_CLOC,
#[doc = "Enable the OTG clock."]
ENABLE_THE_OTG_CLOCK,
}
impl OTG_CLK_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OTG_CLK_ENR::DISABLE_THE_OTG_CLOC => false,
OTG_CLK_ENR::ENABLE_THE_OTG_CLOCK => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OTG_CLK_ENR {
match value {
false => OTG_CLK_ENR::DISABLE_THE_OTG_CLOC,
true => OTG_CLK_ENR::ENABLE_THE_OTG_CLOCK,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_OTG_CLOC`"]
#[inline]
pub fn is_disable_the_otg_cloc(&self) -> bool {
*self == OTG_CLK_ENR::DISABLE_THE_OTG_CLOC
}
#[doc = "Checks if the value of the field is `ENABLE_THE_OTG_CLOCK`"]
#[inline]
pub fn is_enable_the_otg_clock(&self) -> bool {
*self == OTG_CLK_ENR::ENABLE_THE_OTG_CLOCK
}
}
#[doc = "Possible values of the field `AHB_CLK_EN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AHB_CLK_ENR {
#[doc = "Disable the AHB clock."]
DISABLE_THE_AHB_CLOC,
#[doc = "Enable the AHB clock."]
ENABLE_THE_AHB_CLOCK,
}
impl AHB_CLK_ENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AHB_CLK_ENR::DISABLE_THE_AHB_CLOC => false,
AHB_CLK_ENR::ENABLE_THE_AHB_CLOCK => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AHB_CLK_ENR {
match value {
false => AHB_CLK_ENR::DISABLE_THE_AHB_CLOC,
true => AHB_CLK_ENR::ENABLE_THE_AHB_CLOCK,
}
}
#[doc = "Checks if the value of the field is `DISABLE_THE_AHB_CLOC`"]
#[inline]
pub fn is_disable_the_ahb_cloc(&self) -> bool {
*self == AHB_CLK_ENR::DISABLE_THE_AHB_CLOC
}
#[doc = "Checks if the value of the field is `ENABLE_THE_AHB_CLOCK`"]
#[inline]
pub fn is_enable_the_ahb_clock(&self) -> bool {
*self == AHB_CLK_ENR::ENABLE_THE_AHB_CLOCK
}
}
#[doc = "Values that can be written to the field `HOST_CLK_EN`"]
pub enum HOST_CLK_ENW {
#[doc = "Disable the Host clock."]
DISABLE_THE_HOST_CLO,
#[doc = "Enable the Host clock."]
ENABLE_THE_HOST_CLOC,
}
impl HOST_CLK_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
HOST_CLK_ENW::DISABLE_THE_HOST_CLO => false,
HOST_CLK_ENW::ENABLE_THE_HOST_CLOC => true,
}
}
}
#[doc = r" Proxy"]
pub struct _HOST_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _HOST_CLK_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: HOST_CLK_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the Host clock."]
#[inline]
pub fn disable_the_host_clo(self) -> &'a mut W {
self.variant(HOST_CLK_ENW::DISABLE_THE_HOST_CLO)
}
#[doc = "Enable the Host clock."]
#[inline]
pub fn enable_the_host_cloc(self) -> &'a mut W {
self.variant(HOST_CLK_ENW::ENABLE_THE_HOST_CLOC)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DEV_CLK_EN`"]
pub enum DEV_CLK_ENW {
#[doc = "Disable the Device clock."]
DISABLE_THE_DEVICE_C,
#[doc = "Enable the Device clock."]
ENABLE_THE_DEVICE_CL,
}
impl DEV_CLK_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DEV_CLK_ENW::DISABLE_THE_DEVICE_C => false,
DEV_CLK_ENW::ENABLE_THE_DEVICE_CL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DEV_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _DEV_CLK_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DEV_CLK_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the Device clock."]
#[inline]
pub fn disable_the_device_c(self) -> &'a mut W {
self.variant(DEV_CLK_ENW::DISABLE_THE_DEVICE_C)
}
#[doc = "Enable the Device clock."]
#[inline]
pub fn enable_the_device_cl(self) -> &'a mut W {
self.variant(DEV_CLK_ENW::ENABLE_THE_DEVICE_CL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `I2C_CLK_EN`"]
pub enum I2C_CLK_ENW {
#[doc = "Disable the I2C clock."]
DISABLE_THE_I2C_CLOC,
#[doc = "Enable the I2C clock."]
ENABLE_THE_I2C_CLOCK,
}
impl I2C_CLK_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
I2C_CLK_ENW::DISABLE_THE_I2C_CLOC => false,
I2C_CLK_ENW::ENABLE_THE_I2C_CLOCK => true,
}
}
}
#[doc = r" Proxy"]
pub struct _I2C_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _I2C_CLK_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: I2C_CLK_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the I2C clock."]
#[inline]
pub fn disable_the_i2c_cloc(self) -> &'a mut W {
self.variant(I2C_CLK_ENW::DISABLE_THE_I2C_CLOC)
}
#[doc = "Enable the I2C clock."]
#[inline]
pub fn enable_the_i2c_clock(self) -> &'a mut W {
self.variant(I2C_CLK_ENW::ENABLE_THE_I2C_CLOCK)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `OTG_CLK_EN`"]
pub enum OTG_CLK_ENW {
#[doc = "Disable the OTG clock."]
DISABLE_THE_OTG_CLOC,
#[doc = "Enable the OTG clock."]
ENABLE_THE_OTG_CLOCK,
}
impl OTG_CLK_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OTG_CLK_ENW::DISABLE_THE_OTG_CLOC => false,
OTG_CLK_ENW::ENABLE_THE_OTG_CLOCK => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OTG_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _OTG_CLK_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OTG_CLK_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the OTG clock."]
#[inline]
pub fn disable_the_otg_cloc(self) -> &'a mut W {
self.variant(OTG_CLK_ENW::DISABLE_THE_OTG_CLOC)
}
#[doc = "Enable the OTG clock."]
#[inline]
pub fn enable_the_otg_clock(self) -> &'a mut W {
self.variant(OTG_CLK_ENW::ENABLE_THE_OTG_CLOCK)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AHB_CLK_EN`"]
pub enum AHB_CLK_ENW {
#[doc = "Disable the AHB clock."]
DISABLE_THE_AHB_CLOC,
#[doc = "Enable the AHB clock."]
ENABLE_THE_AHB_CLOCK,
}
impl AHB_CLK_ENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AHB_CLK_ENW::DISABLE_THE_AHB_CLOC => false,
AHB_CLK_ENW::ENABLE_THE_AHB_CLOCK => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AHB_CLK_ENW<'a> {
w: &'a mut W,
}
impl<'a> _AHB_CLK_ENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AHB_CLK_ENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable the AHB clock."]
#[inline]
pub fn disable_the_ahb_cloc(self) -> &'a mut W {
self.variant(AHB_CLK_ENW::DISABLE_THE_AHB_CLOC)
}
#[doc = "Enable the AHB clock."]
#[inline]
pub fn enable_the_ahb_clock(self) -> &'a mut W {
self.variant(AHB_CLK_ENW::ENABLE_THE_AHB_CLOCK)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Host clock enable"]
#[inline]
pub fn host_clk_en(&self) -> HOST_CLK_ENR {
HOST_CLK_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Device clock enable"]
#[inline]
pub fn dev_clk_en(&self) -> DEV_CLK_ENR {
DEV_CLK_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - I2C clock enable"]
#[inline]
pub fn i2c_clk_en(&self) -> I2C_CLK_ENR {
I2C_CLK_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register."]
#[inline]
pub fn otg_clk_en(&self) -> OTG_CLK_ENR {
OTG_CLK_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - AHB master clock enable"]
#[inline]
pub fn ahb_clk_en(&self) -> AHB_CLK_ENR {
AHB_CLK_ENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Host clock enable"]
#[inline]
pub fn host_clk_en(&mut self) -> _HOST_CLK_ENW {
_HOST_CLK_ENW { w: self }
}
#[doc = "Bit 1 - Device clock enable"]
#[inline]
pub fn dev_clk_en(&mut self) -> _DEV_CLK_ENW {
_DEV_CLK_ENW { w: self }
}
#[doc = "Bit 2 - I2C clock enable"]
#[inline]
pub fn i2c_clk_en(&mut self) -> _I2C_CLK_ENW {
_I2C_CLK_ENW { w: self }
}
#[doc = "Bit 3 - OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register."]
#[inline]
pub fn otg_clk_en(&mut self) -> _OTG_CLK_ENW {
_OTG_CLK_ENW { w: self }
}
#[doc = "Bit 4 - AHB master clock enable"]
#[inline]
pub fn ahb_clk_en(&mut self) -> _AHB_CLK_ENW {
_AHB_CLK_ENW { w: self }
}
}
}
#[doc = "USB Clock Status"]
pub struct USBCLKST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USB Clock Status"]
pub mod usbclkst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::USBCLKST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = r" Value of the field"]
pub struct DEV_CLK_ONR {
bits: bool,
}
impl DEV_CLK_ONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PORTSEL_CLK_ONR {
bits: bool,
}
impl PORTSEL_CLK_ONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct AHB_CLK_ONR {
bits: bool,
}
impl AHB_CLK_ONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 1 - Device clock on. The usbclk input to the device controller is active ."]
#[inline]
pub fn dev_clk_on(&self) -> DEV_CLK_ONR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
DEV_CLK_ONR { bits }
}
#[doc = "Bit 3 - Port select register clock on."]
#[inline]
pub fn portsel_clk_on(&self) -> PORTSEL_CLK_ONR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PORTSEL_CLK_ONR { bits }
}
#[doc = "Bit 4 - AHB clock on."]
#[inline]
pub fn ahb_clk_on(&self) -> AHB_CLK_ONR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AHB_CLK_ONR { bits }
}
}
}
#[doc = "OTG clock status"]
pub struct OTGCLKST {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "OTG clock status"]
pub mod otgclkst {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::OTGCLKST {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
}
#[doc = "Possible values of the field `HOST_CLK_ON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HOST_CLK_ONR {
#[doc = "Host clock is not available."]
HOST_CLOCK_IS_NOT_AV,
#[doc = "Host clock is available."]
HOST_CLOCK_IS_AVAILA,
}
impl HOST_CLK_ONR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
HOST_CLK_ONR::HOST_CLOCK_IS_NOT_AV => false,
HOST_CLK_ONR::HOST_CLOCK_IS_AVAILA => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> HOST_CLK_ONR {
match value {
false => HOST_CLK_ONR::HOST_CLOCK_IS_NOT_AV,
true => HOST_CLK_ONR::HOST_CLOCK_IS_AVAILA,
}
}
#[doc = "Checks if the value of the field is `HOST_CLOCK_IS_NOT_AV`"]
#[inline]
pub fn is_host_clock_is_not_av(&self) -> bool {
*self == HOST_CLK_ONR::HOST_CLOCK_IS_NOT_AV
}
#[doc = "Checks if the value of the field is `HOST_CLOCK_IS_AVAILA`"]
#[inline]
pub fn is_host_clock_is_availa(&self) -> bool {
*self == HOST_CLK_ONR::HOST_CLOCK_IS_AVAILA
}
}
#[doc = "Possible values of the field `DEV_CLK_ON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DEV_CLK_ONR {
#[doc = "Device clock is not available."]
DEVICE_CLOCK_IS_NOT_,
#[doc = "Device clock is available."]
DEVICE_CLOCK_IS_AVAI,
}
impl DEV_CLK_ONR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DEV_CLK_ONR::DEVICE_CLOCK_IS_NOT_ => false,
DEV_CLK_ONR::DEVICE_CLOCK_IS_AVAI => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DEV_CLK_ONR {
match value {
false => DEV_CLK_ONR::DEVICE_CLOCK_IS_NOT_,
true => DEV_CLK_ONR::DEVICE_CLOCK_IS_AVAI,
}
}
#[doc = "Checks if the value of the field is `DEVICE_CLOCK_IS_NOT_`"]
#[inline]
pub fn is_device_clock_is_not_(&self) -> bool {
*self == DEV_CLK_ONR::DEVICE_CLOCK_IS_NOT_
}
#[doc = "Checks if the value of the field is `DEVICE_CLOCK_IS_AVAI`"]
#[inline]
pub fn is_device_clock_is_avai(&self) -> bool {
*self == DEV_CLK_ONR::DEVICE_CLOCK_IS_AVAI
}
}
#[doc = "Possible values of the field `I2C_CLK_ON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C_CLK_ONR {
#[doc = "I2C clock is not available."]
I2C_CLOCK_IS_NOT_AVA,
#[doc = "I2C clock is available."]
I2C_CLOCK_IS_AVAILAB,
}
impl I2C_CLK_ONR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
I2C_CLK_ONR::I2C_CLOCK_IS_NOT_AVA => false,
I2C_CLK_ONR::I2C_CLOCK_IS_AVAILAB => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> I2C_CLK_ONR {
match value {
false => I2C_CLK_ONR::I2C_CLOCK_IS_NOT_AVA,
true => I2C_CLK_ONR::I2C_CLOCK_IS_AVAILAB,
}
}
#[doc = "Checks if the value of the field is `I2C_CLOCK_IS_NOT_AVA`"]
#[inline]
pub fn is_i2c_clock_is_not_ava(&self) -> bool {
*self == I2C_CLK_ONR::I2C_CLOCK_IS_NOT_AVA
}
#[doc = "Checks if the value of the field is `I2C_CLOCK_IS_AVAILAB`"]
#[inline]
pub fn is_i2c_clock_is_availab(&self) -> bool {
*self == I2C_CLK_ONR::I2C_CLOCK_IS_AVAILAB
}
}
#[doc = "Possible values of the field `OTG_CLK_ON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OTG_CLK_ONR {
#[doc = "OTG clock is not available."]
OTG_CLOCK_IS_NOT_AVA,
#[doc = "OTG clock is available."]
OTG_CLOCK_IS_AVAILAB,
}
impl OTG_CLK_ONR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OTG_CLK_ONR::OTG_CLOCK_IS_NOT_AVA => false,
OTG_CLK_ONR::OTG_CLOCK_IS_AVAILAB => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OTG_CLK_ONR {
match value {
false => OTG_CLK_ONR::OTG_CLOCK_IS_NOT_AVA,
true => OTG_CLK_ONR::OTG_CLOCK_IS_AVAILAB,
}
}
#[doc = "Checks if the value of the field is `OTG_CLOCK_IS_NOT_AVA`"]
#[inline]
pub fn is_otg_clock_is_not_ava(&self) -> bool {
*self == OTG_CLK_ONR::OTG_CLOCK_IS_NOT_AVA
}
#[doc = "Checks if the value of the field is `OTG_CLOCK_IS_AVAILAB`"]
#[inline]
pub fn is_otg_clock_is_availab(&self) -> bool {
*self == OTG_CLK_ONR::OTG_CLOCK_IS_AVAILAB
}
}
#[doc = "Possible values of the field `AHB_CLK_ON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AHB_CLK_ONR {
#[doc = "AHB clock is not available."]
AHB_CLOCK_IS_NOT_AVA,
#[doc = "AHB clock is available."]
AHB_CLOCK_IS_AVAILAB,
}
impl AHB_CLK_ONR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AHB_CLK_ONR::AHB_CLOCK_IS_NOT_AVA => false,
AHB_CLK_ONR::AHB_CLOCK_IS_AVAILAB => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AHB_CLK_ONR {
match value {
false => AHB_CLK_ONR::AHB_CLOCK_IS_NOT_AVA,
true => AHB_CLK_ONR::AHB_CLOCK_IS_AVAILAB,
}
}
#[doc = "Checks if the value of the field is `AHB_CLOCK_IS_NOT_AVA`"]
#[inline]
pub fn is_ahb_clock_is_not_ava(&self) -> bool {
*self == AHB_CLK_ONR::AHB_CLOCK_IS_NOT_AVA
}
#[doc = "Checks if the value of the field is `AHB_CLOCK_IS_AVAILAB`"]
#[inline]
pub fn is_ahb_clock_is_availab(&self) -> bool {
*self == AHB_CLK_ONR::AHB_CLOCK_IS_AVAILAB
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Host clock status."]
#[inline]
pub fn host_clk_on(&self) -> HOST_CLK_ONR {
HOST_CLK_ONR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Device clock status."]
#[inline]
pub fn dev_clk_on(&self) -> DEV_CLK_ONR {
DEV_CLK_ONR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - I2C clock status."]
#[inline]
pub fn i2c_clk_on(&self) -> I2C_CLK_ONR {
I2C_CLK_ONR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - OTG clock status."]
#[inline]
pub fn otg_clk_on(&self) -> OTG_CLK_ONR {
OTG_CLK_ONR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 4 - AHB master clock status."]
#[inline]
pub fn ahb_clk_on(&self) -> AHB_CLK_ONR {
AHB_CLK_ONR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
}
}
#[doc = "General Purpose I/O"]
pub struct GPIO {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIO {}
impl GPIO {
#[doc = r" Returns a pointer to the register block"]
pub fn ptr() -> *const gpio::RegisterBlock {
0x2009_c000 as *const _
}
}
impl Deref for GPIO {
type Target = gpio::RegisterBlock;
fn deref(&self) -> &gpio::RegisterBlock {
unsafe { &*GPIO::ptr() }
}
}
#[doc = "General Purpose I/O"]
pub mod gpio {
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - GPIO Port Direction control register."]
pub dir0: DIR,
_reserved1: [u8; 12usize],
#[doc = "0x10 - Mask register for Port."]
pub mask0: MASK,
#[doc = "0x14 - Port Pin value register using FIOMASK."]
pub pin0: PIN,
#[doc = "0x18 - Port Output Set register using FIOMASK."]
pub set0: SET,
#[doc = "0x1c - Port Output Clear register using FIOMASK."]
pub clr0: CLR,
#[doc = "0x20 - GPIO Port Direction control register."]
pub dir1: DIR,
_reserved6: [u8; 12usize],
#[doc = "0x30 - Mask register for Port."]
pub mask1: MASK,
#[doc = "0x34 - Port Pin value register using FIOMASK."]
pub pin1: PIN,
#[doc = "0x38 - Port Output Set register using FIOMASK."]
pub set1: SET,
#[doc = "0x3c - Port Output Clear register using FIOMASK."]
pub clr1: CLR,
#[doc = "0x40 - GPIO Port Direction control register."]
pub dir2: DIR,
_reserved11: [u8; 12usize],
#[doc = "0x50 - Mask register for Port."]
pub mask2: MASK,
#[doc = "0x54 - Port Pin value register using FIOMASK."]
pub pin2: PIN,
#[doc = "0x58 - Port Output Set register using FIOMASK."]
pub set2: SET,
#[doc = "0x5c - Port Output Clear register using FIOMASK."]
pub clr2: CLR,
#[doc = "0x60 - GPIO Port Direction control register."]
pub dir3: DIR,
_reserved16: [u8; 12usize],
#[doc = "0x70 - Mask register for Port."]
pub mask3: MASK,
#[doc = "0x74 - Port Pin value register using FIOMASK."]
pub pin3: PIN,
#[doc = "0x78 - Port Output Set register using FIOMASK."]
pub set3: SET,
#[doc = "0x7c - Port Output Clear register using FIOMASK."]
pub clr3: CLR,
#[doc = "0x80 - GPIO Port Direction control register."]
pub dir4: DIR,
_reserved21: [u8; 12usize],
#[doc = "0x90 - Mask register for Port."]
pub mask4: MASK,
#[doc = "0x94 - Port Pin value register using FIOMASK."]
pub pin4: PIN,
#[doc = "0x98 - Port Output Set register using FIOMASK."]
pub set4: SET,
#[doc = "0x9c - Port Output Clear register using FIOMASK."]
pub clr4: CLR,
}
#[doc = "GPIO Port Direction control register."]
pub struct DIR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "GPIO Port Direction control register."]
pub mod dir {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::DIR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PINDIR0R {
bits: bool,
}
impl PINDIR0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR1R {
bits: bool,
}
impl PINDIR1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR2R {
bits: bool,
}
impl PINDIR2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR3R {
bits: bool,
}
impl PINDIR3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR4R {
bits: bool,
}
impl PINDIR4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR5R {
bits: bool,
}
impl PINDIR5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR6R {
bits: bool,
}
impl PINDIR6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR7R {
bits: bool,
}
impl PINDIR7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR8R {
bits: bool,
}
impl PINDIR8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR9R {
bits: bool,
}
impl PINDIR9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR10R {
bits: bool,
}
impl PINDIR10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR11R {
bits: bool,
}
impl PINDIR11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR12R {
bits: bool,
}
impl PINDIR12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR13R {
bits: bool,
}
impl PINDIR13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR14R {
bits: bool,
}
impl PINDIR14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR15R {
bits: bool,
}
impl PINDIR15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR16R {
bits: bool,
}
impl PINDIR16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR17R {
bits: bool,
}
impl PINDIR17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR18R {
bits: bool,
}
impl PINDIR18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR19R {
bits: bool,
}
impl PINDIR19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR20R {
bits: bool,
}
impl PINDIR20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR21R {
bits: bool,
}
impl PINDIR21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR22R {
bits: bool,
}
impl PINDIR22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR23R {
bits: bool,
}
impl PINDIR23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR24R {
bits: bool,
}
impl PINDIR24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR25R {
bits: bool,
}
impl PINDIR25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR26R {
bits: bool,
}
impl PINDIR26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR27R {
bits: bool,
}
impl PINDIR27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR28R {
bits: bool,
}
impl PINDIR28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR29R {
bits: bool,
}
impl PINDIR29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR30R {
bits: bool,
}
impl PINDIR30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINDIR31R {
bits: bool,
}
impl PINDIR31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PINDIR0W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR1W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR2W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR3W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR4W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR5W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR6W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR7W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR8W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR9W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR10W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR11W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR12W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR13W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR14W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR15W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR16W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR17W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR18W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR19W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR20W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR21W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR22W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR23W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR24W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR25W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR26W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR27W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR28W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR29W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR30W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINDIR31W<'a> {
w: &'a mut W,
}
impl<'a> _PINDIR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir0(&self) -> PINDIR0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR0R { bits }
}
#[doc = "Bit 1 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir1(&self) -> PINDIR1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR1R { bits }
}
#[doc = "Bit 2 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir2(&self) -> PINDIR2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR2R { bits }
}
#[doc = "Bit 3 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir3(&self) -> PINDIR3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR3R { bits }
}
#[doc = "Bit 4 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir4(&self) -> PINDIR4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR4R { bits }
}
#[doc = "Bit 5 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir5(&self) -> PINDIR5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR5R { bits }
}
#[doc = "Bit 6 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir6(&self) -> PINDIR6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR6R { bits }
}
#[doc = "Bit 7 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir7(&self) -> PINDIR7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR7R { bits }
}
#[doc = "Bit 8 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir8(&self) -> PINDIR8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR8R { bits }
}
#[doc = "Bit 9 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir9(&self) -> PINDIR9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR9R { bits }
}
#[doc = "Bit 10 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir10(&self) -> PINDIR10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR10R { bits }
}
#[doc = "Bit 11 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir11(&self) -> PINDIR11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR11R { bits }
}
#[doc = "Bit 12 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir12(&self) -> PINDIR12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR12R { bits }
}
#[doc = "Bit 13 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir13(&self) -> PINDIR13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR13R { bits }
}
#[doc = "Bit 14 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir14(&self) -> PINDIR14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR14R { bits }
}
#[doc = "Bit 15 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir15(&self) -> PINDIR15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR15R { bits }
}
#[doc = "Bit 16 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir16(&self) -> PINDIR16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR16R { bits }
}
#[doc = "Bit 17 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir17(&self) -> PINDIR17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR17R { bits }
}
#[doc = "Bit 18 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir18(&self) -> PINDIR18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR18R { bits }
}
#[doc = "Bit 19 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir19(&self) -> PINDIR19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR19R { bits }
}
#[doc = "Bit 20 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir20(&self) -> PINDIR20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR20R { bits }
}
#[doc = "Bit 21 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir21(&self) -> PINDIR21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR21R { bits }
}
#[doc = "Bit 22 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir22(&self) -> PINDIR22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR22R { bits }
}
#[doc = "Bit 23 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir23(&self) -> PINDIR23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR23R { bits }
}
#[doc = "Bit 24 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir24(&self) -> PINDIR24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR24R { bits }
}
#[doc = "Bit 25 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir25(&self) -> PINDIR25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR25R { bits }
}
#[doc = "Bit 26 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir26(&self) -> PINDIR26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR26R { bits }
}
#[doc = "Bit 27 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir27(&self) -> PINDIR27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR27R { bits }
}
#[doc = "Bit 28 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir28(&self) -> PINDIR28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR28R { bits }
}
#[doc = "Bit 29 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir29(&self) -> PINDIR29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR29R { bits }
}
#[doc = "Bit 30 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir30(&self) -> PINDIR30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR30R { bits }
}
#[doc = "Bit 31 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir31(&self) -> PINDIR31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINDIR31R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir0(&mut self) -> _PINDIR0W {
_PINDIR0W { w: self }
}
#[doc = "Bit 1 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir1(&mut self) -> _PINDIR1W {
_PINDIR1W { w: self }
}
#[doc = "Bit 2 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir2(&mut self) -> _PINDIR2W {
_PINDIR2W { w: self }
}
#[doc = "Bit 3 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir3(&mut self) -> _PINDIR3W {
_PINDIR3W { w: self }
}
#[doc = "Bit 4 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir4(&mut self) -> _PINDIR4W {
_PINDIR4W { w: self }
}
#[doc = "Bit 5 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir5(&mut self) -> _PINDIR5W {
_PINDIR5W { w: self }
}
#[doc = "Bit 6 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir6(&mut self) -> _PINDIR6W {
_PINDIR6W { w: self }
}
#[doc = "Bit 7 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir7(&mut self) -> _PINDIR7W {
_PINDIR7W { w: self }
}
#[doc = "Bit 8 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir8(&mut self) -> _PINDIR8W {
_PINDIR8W { w: self }
}
#[doc = "Bit 9 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir9(&mut self) -> _PINDIR9W {
_PINDIR9W { w: self }
}
#[doc = "Bit 10 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir10(&mut self) -> _PINDIR10W {
_PINDIR10W { w: self }
}
#[doc = "Bit 11 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir11(&mut self) -> _PINDIR11W {
_PINDIR11W { w: self }
}
#[doc = "Bit 12 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir12(&mut self) -> _PINDIR12W {
_PINDIR12W { w: self }
}
#[doc = "Bit 13 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir13(&mut self) -> _PINDIR13W {
_PINDIR13W { w: self }
}
#[doc = "Bit 14 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir14(&mut self) -> _PINDIR14W {
_PINDIR14W { w: self }
}
#[doc = "Bit 15 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir15(&mut self) -> _PINDIR15W {
_PINDIR15W { w: self }
}
#[doc = "Bit 16 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir16(&mut self) -> _PINDIR16W {
_PINDIR16W { w: self }
}
#[doc = "Bit 17 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir17(&mut self) -> _PINDIR17W {
_PINDIR17W { w: self }
}
#[doc = "Bit 18 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir18(&mut self) -> _PINDIR18W {
_PINDIR18W { w: self }
}
#[doc = "Bit 19 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir19(&mut self) -> _PINDIR19W {
_PINDIR19W { w: self }
}
#[doc = "Bit 20 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir20(&mut self) -> _PINDIR20W {
_PINDIR20W { w: self }
}
#[doc = "Bit 21 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir21(&mut self) -> _PINDIR21W {
_PINDIR21W { w: self }
}
#[doc = "Bit 22 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir22(&mut self) -> _PINDIR22W {
_PINDIR22W { w: self }
}
#[doc = "Bit 23 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir23(&mut self) -> _PINDIR23W {
_PINDIR23W { w: self }
}
#[doc = "Bit 24 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir24(&mut self) -> _PINDIR24W {
_PINDIR24W { w: self }
}
#[doc = "Bit 25 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir25(&mut self) -> _PINDIR25W {
_PINDIR25W { w: self }
}
#[doc = "Bit 26 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir26(&mut self) -> _PINDIR26W {
_PINDIR26W { w: self }
}
#[doc = "Bit 27 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir27(&mut self) -> _PINDIR27W {
_PINDIR27W { w: self }
}
#[doc = "Bit 28 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir28(&mut self) -> _PINDIR28W {
_PINDIR28W { w: self }
}
#[doc = "Bit 29 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir29(&mut self) -> _PINDIR29W {
_PINDIR29W { w: self }
}
#[doc = "Bit 30 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir30(&mut self) -> _PINDIR30W {
_PINDIR30W { w: self }
}
#[doc = "Bit 31 - Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px\\[0\\], bit 31 in DIRx controls pin Px\\[31\\]. 0 = Controlled pin is input. 1 = Controlled pin is output."]
#[inline]
pub fn pindir31(&mut self) -> _PINDIR31W {
_PINDIR31W { w: self }
}
}
}
#[doc = "Mask register for Port."]
pub struct MASK {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Mask register for Port."]
pub mod mask {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MASK {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PINMASK0R {
bits: bool,
}
impl PINMASK0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK1R {
bits: bool,
}
impl PINMASK1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK2R {
bits: bool,
}
impl PINMASK2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK3R {
bits: bool,
}
impl PINMASK3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK4R {
bits: bool,
}
impl PINMASK4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK5R {
bits: bool,
}
impl PINMASK5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK6R {
bits: bool,
}
impl PINMASK6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK7R {
bits: bool,
}
impl PINMASK7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK8R {
bits: bool,
}
impl PINMASK8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK9R {
bits: bool,
}
impl PINMASK9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK10R {
bits: bool,
}
impl PINMASK10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK11R {
bits: bool,
}
impl PINMASK11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK12R {
bits: bool,
}
impl PINMASK12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK13R {
bits: bool,
}
impl PINMASK13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK14R {
bits: bool,
}
impl PINMASK14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK15R {
bits: bool,
}
impl PINMASK15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK16R {
bits: bool,
}
impl PINMASK16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK17R {
bits: bool,
}
impl PINMASK17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK18R {
bits: bool,
}
impl PINMASK18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK19R {
bits: bool,
}
impl PINMASK19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK20R {
bits: bool,
}
impl PINMASK20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK21R {
bits: bool,
}
impl PINMASK21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK22R {
bits: bool,
}
impl PINMASK22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK23R {
bits: bool,
}
impl PINMASK23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK24R {
bits: bool,
}
impl PINMASK24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK25R {
bits: bool,
}
impl PINMASK25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK26R {
bits: bool,
}
impl PINMASK26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK27R {
bits: bool,
}
impl PINMASK27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK28R {
bits: bool,
}
impl PINMASK28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK29R {
bits: bool,
}
impl PINMASK29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK30R {
bits: bool,
}
impl PINMASK30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINMASK31R {
bits: bool,
}
impl PINMASK31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PINMASK0W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK1W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK2W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK3W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK4W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK5W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK6W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK7W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK8W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK9W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK10W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK11W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK12W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK13W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK14W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK15W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK16W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK17W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK18W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK19W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK20W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK21W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK22W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK23W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK24W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK25W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK26W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK27W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK28W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK29W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK30W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINMASK31W<'a> {
w: &'a mut W,
}
impl<'a> _PINMASK31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask0(&self) -> PINMASK0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK0R { bits }
}
#[doc = "Bit 1 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask1(&self) -> PINMASK1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK1R { bits }
}
#[doc = "Bit 2 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask2(&self) -> PINMASK2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK2R { bits }
}
#[doc = "Bit 3 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask3(&self) -> PINMASK3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK3R { bits }
}
#[doc = "Bit 4 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask4(&self) -> PINMASK4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK4R { bits }
}
#[doc = "Bit 5 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask5(&self) -> PINMASK5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK5R { bits }
}
#[doc = "Bit 6 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask6(&self) -> PINMASK6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK6R { bits }
}
#[doc = "Bit 7 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask7(&self) -> PINMASK7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK7R { bits }
}
#[doc = "Bit 8 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask8(&self) -> PINMASK8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK8R { bits }
}
#[doc = "Bit 9 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask9(&self) -> PINMASK9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK9R { bits }
}
#[doc = "Bit 10 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask10(&self) -> PINMASK10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK10R { bits }
}
#[doc = "Bit 11 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask11(&self) -> PINMASK11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK11R { bits }
}
#[doc = "Bit 12 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask12(&self) -> PINMASK12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK12R { bits }
}
#[doc = "Bit 13 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask13(&self) -> PINMASK13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK13R { bits }
}
#[doc = "Bit 14 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask14(&self) -> PINMASK14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK14R { bits }
}
#[doc = "Bit 15 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask15(&self) -> PINMASK15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK15R { bits }
}
#[doc = "Bit 16 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask16(&self) -> PINMASK16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK16R { bits }
}
#[doc = "Bit 17 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask17(&self) -> PINMASK17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK17R { bits }
}
#[doc = "Bit 18 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask18(&self) -> PINMASK18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK18R { bits }
}
#[doc = "Bit 19 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask19(&self) -> PINMASK19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK19R { bits }
}
#[doc = "Bit 20 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask20(&self) -> PINMASK20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK20R { bits }
}
#[doc = "Bit 21 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask21(&self) -> PINMASK21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK21R { bits }
}
#[doc = "Bit 22 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask22(&self) -> PINMASK22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK22R { bits }
}
#[doc = "Bit 23 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask23(&self) -> PINMASK23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK23R { bits }
}
#[doc = "Bit 24 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask24(&self) -> PINMASK24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK24R { bits }
}
#[doc = "Bit 25 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask25(&self) -> PINMASK25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK25R { bits }
}
#[doc = "Bit 26 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask26(&self) -> PINMASK26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK26R { bits }
}
#[doc = "Bit 27 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask27(&self) -> PINMASK27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK27R { bits }
}
#[doc = "Bit 28 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask28(&self) -> PINMASK28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK28R { bits }
}
#[doc = "Bit 29 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask29(&self) -> PINMASK29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK29R { bits }
}
#[doc = "Bit 30 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask30(&self) -> PINMASK30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK30R { bits }
}
#[doc = "Bit 31 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask31(&self) -> PINMASK31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINMASK31R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask0(&mut self) -> _PINMASK0W {
_PINMASK0W { w: self }
}
#[doc = "Bit 1 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask1(&mut self) -> _PINMASK1W {
_PINMASK1W { w: self }
}
#[doc = "Bit 2 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask2(&mut self) -> _PINMASK2W {
_PINMASK2W { w: self }
}
#[doc = "Bit 3 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask3(&mut self) -> _PINMASK3W {
_PINMASK3W { w: self }
}
#[doc = "Bit 4 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask4(&mut self) -> _PINMASK4W {
_PINMASK4W { w: self }
}
#[doc = "Bit 5 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask5(&mut self) -> _PINMASK5W {
_PINMASK5W { w: self }
}
#[doc = "Bit 6 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask6(&mut self) -> _PINMASK6W {
_PINMASK6W { w: self }
}
#[doc = "Bit 7 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask7(&mut self) -> _PINMASK7W {
_PINMASK7W { w: self }
}
#[doc = "Bit 8 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask8(&mut self) -> _PINMASK8W {
_PINMASK8W { w: self }
}
#[doc = "Bit 9 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask9(&mut self) -> _PINMASK9W {
_PINMASK9W { w: self }
}
#[doc = "Bit 10 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask10(&mut self) -> _PINMASK10W {
_PINMASK10W { w: self }
}
#[doc = "Bit 11 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask11(&mut self) -> _PINMASK11W {
_PINMASK11W { w: self }
}
#[doc = "Bit 12 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask12(&mut self) -> _PINMASK12W {
_PINMASK12W { w: self }
}
#[doc = "Bit 13 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask13(&mut self) -> _PINMASK13W {
_PINMASK13W { w: self }
}
#[doc = "Bit 14 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask14(&mut self) -> _PINMASK14W {
_PINMASK14W { w: self }
}
#[doc = "Bit 15 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask15(&mut self) -> _PINMASK15W {
_PINMASK15W { w: self }
}
#[doc = "Bit 16 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask16(&mut self) -> _PINMASK16W {
_PINMASK16W { w: self }
}
#[doc = "Bit 17 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask17(&mut self) -> _PINMASK17W {
_PINMASK17W { w: self }
}
#[doc = "Bit 18 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask18(&mut self) -> _PINMASK18W {
_PINMASK18W { w: self }
}
#[doc = "Bit 19 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask19(&mut self) -> _PINMASK19W {
_PINMASK19W { w: self }
}
#[doc = "Bit 20 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask20(&mut self) -> _PINMASK20W {
_PINMASK20W { w: self }
}
#[doc = "Bit 21 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask21(&mut self) -> _PINMASK21W {
_PINMASK21W { w: self }
}
#[doc = "Bit 22 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask22(&mut self) -> _PINMASK22W {
_PINMASK22W { w: self }
}
#[doc = "Bit 23 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask23(&mut self) -> _PINMASK23W {
_PINMASK23W { w: self }
}
#[doc = "Bit 24 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask24(&mut self) -> _PINMASK24W {
_PINMASK24W { w: self }
}
#[doc = "Bit 25 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask25(&mut self) -> _PINMASK25W {
_PINMASK25W { w: self }
}
#[doc = "Bit 26 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask26(&mut self) -> _PINMASK26W {
_PINMASK26W { w: self }
}
#[doc = "Bit 27 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask27(&mut self) -> _PINMASK27W {
_PINMASK27W { w: self }
}
#[doc = "Bit 28 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask28(&mut self) -> _PINMASK28W {
_PINMASK28W { w: self }
}
#[doc = "Bit 29 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask29(&mut self) -> _PINMASK29W {
_PINMASK29W { w: self }
}
#[doc = "Bit 30 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask30(&mut self) -> _PINMASK30W {
_PINMASK30W { w: self }
}
#[doc = "Bit 31 - Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin."]
#[inline]
pub fn pinmask31(&mut self) -> _PINMASK31W {
_PINMASK31W { w: self }
}
}
}
#[doc = "Port Pin value register using FIOMASK."]
pub struct PIN {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Port Pin value register using FIOMASK."]
pub mod pin {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::PIN {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PINVAL0R {
bits: bool,
}
impl PINVAL0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL1R {
bits: bool,
}
impl PINVAL1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL2R {
bits: bool,
}
impl PINVAL2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL3R {
bits: bool,
}
impl PINVAL3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL4R {
bits: bool,
}
impl PINVAL4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL5R {
bits: bool,
}
impl PINVAL5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL6R {
bits: bool,
}
impl PINVAL6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL7R {
bits: bool,
}
impl PINVAL7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL8R {
bits: bool,
}
impl PINVAL8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL9R {
bits: bool,
}
impl PINVAL9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL10R {
bits: bool,
}
impl PINVAL10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL11R {
bits: bool,
}
impl PINVAL11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL12R {
bits: bool,
}
impl PINVAL12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL13R {
bits: bool,
}
impl PINVAL13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL14R {
bits: bool,
}
impl PINVAL14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL15R {
bits: bool,
}
impl PINVAL15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL16R {
bits: bool,
}
impl PINVAL16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL17R {
bits: bool,
}
impl PINVAL17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL18R {
bits: bool,
}
impl PINVAL18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL19R {
bits: bool,
}
impl PINVAL19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL20R {
bits: bool,
}
impl PINVAL20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL21R {
bits: bool,
}
impl PINVAL21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL22R {
bits: bool,
}
impl PINVAL22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL23R {
bits: bool,
}
impl PINVAL23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL24R {
bits: bool,
}
impl PINVAL24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL25R {
bits: bool,
}
impl PINVAL25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL26R {
bits: bool,
}
impl PINVAL26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL27R {
bits: bool,
}
impl PINVAL27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL28R {
bits: bool,
}
impl PINVAL28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL29R {
bits: bool,
}
impl PINVAL29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL30R {
bits: bool,
}
impl PINVAL30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINVAL31R {
bits: bool,
}
impl PINVAL31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PINVAL0W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL1W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL2W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL3W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL4W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL5W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL6W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL7W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL8W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL9W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL10W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL11W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL12W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL13W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL14W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL15W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL16W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL17W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL18W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL19W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL20W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL21W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL22W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL23W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL24W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL25W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL26W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL27W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL28W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL29W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL30W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINVAL31W<'a> {
w: &'a mut W,
}
impl<'a> _PINVAL31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval0(&self) -> PINVAL0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL0R { bits }
}
#[doc = "Bit 1 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval1(&self) -> PINVAL1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL1R { bits }
}
#[doc = "Bit 2 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval2(&self) -> PINVAL2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL2R { bits }
}
#[doc = "Bit 3 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval3(&self) -> PINVAL3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL3R { bits }
}
#[doc = "Bit 4 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval4(&self) -> PINVAL4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL4R { bits }
}
#[doc = "Bit 5 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval5(&self) -> PINVAL5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL5R { bits }
}
#[doc = "Bit 6 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval6(&self) -> PINVAL6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL6R { bits }
}
#[doc = "Bit 7 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval7(&self) -> PINVAL7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL7R { bits }
}
#[doc = "Bit 8 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval8(&self) -> PINVAL8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL8R { bits }
}
#[doc = "Bit 9 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval9(&self) -> PINVAL9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL9R { bits }
}
#[doc = "Bit 10 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval10(&self) -> PINVAL10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL10R { bits }
}
#[doc = "Bit 11 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval11(&self) -> PINVAL11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL11R { bits }
}
#[doc = "Bit 12 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval12(&self) -> PINVAL12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL12R { bits }
}
#[doc = "Bit 13 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval13(&self) -> PINVAL13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL13R { bits }
}
#[doc = "Bit 14 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval14(&self) -> PINVAL14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL14R { bits }
}
#[doc = "Bit 15 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval15(&self) -> PINVAL15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL15R { bits }
}
#[doc = "Bit 16 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval16(&self) -> PINVAL16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL16R { bits }
}
#[doc = "Bit 17 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval17(&self) -> PINVAL17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL17R { bits }
}
#[doc = "Bit 18 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval18(&self) -> PINVAL18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL18R { bits }
}
#[doc = "Bit 19 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval19(&self) -> PINVAL19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL19R { bits }
}
#[doc = "Bit 20 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval20(&self) -> PINVAL20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL20R { bits }
}
#[doc = "Bit 21 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval21(&self) -> PINVAL21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL21R { bits }
}
#[doc = "Bit 22 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval22(&self) -> PINVAL22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL22R { bits }
}
#[doc = "Bit 23 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval23(&self) -> PINVAL23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL23R { bits }
}
#[doc = "Bit 24 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval24(&self) -> PINVAL24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL24R { bits }
}
#[doc = "Bit 25 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval25(&self) -> PINVAL25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL25R { bits }
}
#[doc = "Bit 26 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval26(&self) -> PINVAL26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL26R { bits }
}
#[doc = "Bit 27 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval27(&self) -> PINVAL27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL27R { bits }
}
#[doc = "Bit 28 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval28(&self) -> PINVAL28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL28R { bits }
}
#[doc = "Bit 29 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval29(&self) -> PINVAL29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL29R { bits }
}
#[doc = "Bit 30 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval30(&self) -> PINVAL30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL30R { bits }
}
#[doc = "Bit 31 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval31(&self) -> PINVAL31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINVAL31R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval0(&mut self) -> _PINVAL0W {
_PINVAL0W { w: self }
}
#[doc = "Bit 1 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval1(&mut self) -> _PINVAL1W {
_PINVAL1W { w: self }
}
#[doc = "Bit 2 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval2(&mut self) -> _PINVAL2W {
_PINVAL2W { w: self }
}
#[doc = "Bit 3 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval3(&mut self) -> _PINVAL3W {
_PINVAL3W { w: self }
}
#[doc = "Bit 4 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval4(&mut self) -> _PINVAL4W {
_PINVAL4W { w: self }
}
#[doc = "Bit 5 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval5(&mut self) -> _PINVAL5W {
_PINVAL5W { w: self }
}
#[doc = "Bit 6 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval6(&mut self) -> _PINVAL6W {
_PINVAL6W { w: self }
}
#[doc = "Bit 7 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval7(&mut self) -> _PINVAL7W {
_PINVAL7W { w: self }
}
#[doc = "Bit 8 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval8(&mut self) -> _PINVAL8W {
_PINVAL8W { w: self }
}
#[doc = "Bit 9 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval9(&mut self) -> _PINVAL9W {
_PINVAL9W { w: self }
}
#[doc = "Bit 10 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval10(&mut self) -> _PINVAL10W {
_PINVAL10W { w: self }
}
#[doc = "Bit 11 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval11(&mut self) -> _PINVAL11W {
_PINVAL11W { w: self }
}
#[doc = "Bit 12 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval12(&mut self) -> _PINVAL12W {
_PINVAL12W { w: self }
}
#[doc = "Bit 13 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval13(&mut self) -> _PINVAL13W {
_PINVAL13W { w: self }
}
#[doc = "Bit 14 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval14(&mut self) -> _PINVAL14W {
_PINVAL14W { w: self }
}
#[doc = "Bit 15 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval15(&mut self) -> _PINVAL15W {
_PINVAL15W { w: self }
}
#[doc = "Bit 16 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval16(&mut self) -> _PINVAL16W {
_PINVAL16W { w: self }
}
#[doc = "Bit 17 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval17(&mut self) -> _PINVAL17W {
_PINVAL17W { w: self }
}
#[doc = "Bit 18 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval18(&mut self) -> _PINVAL18W {
_PINVAL18W { w: self }
}
#[doc = "Bit 19 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval19(&mut self) -> _PINVAL19W {
_PINVAL19W { w: self }
}
#[doc = "Bit 20 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval20(&mut self) -> _PINVAL20W {
_PINVAL20W { w: self }
}
#[doc = "Bit 21 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval21(&mut self) -> _PINVAL21W {
_PINVAL21W { w: self }
}
#[doc = "Bit 22 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval22(&mut self) -> _PINVAL22W {
_PINVAL22W { w: self }
}
#[doc = "Bit 23 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval23(&mut self) -> _PINVAL23W {
_PINVAL23W { w: self }
}
#[doc = "Bit 24 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval24(&mut self) -> _PINVAL24W {
_PINVAL24W { w: self }
}
#[doc = "Bit 25 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval25(&mut self) -> _PINVAL25W {
_PINVAL25W { w: self }
}
#[doc = "Bit 26 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval26(&mut self) -> _PINVAL26W {
_PINVAL26W { w: self }
}
#[doc = "Bit 27 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval27(&mut self) -> _PINVAL27W {
_PINVAL27W { w: self }
}
#[doc = "Bit 28 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval28(&mut self) -> _PINVAL28W {
_PINVAL28W { w: self }
}
#[doc = "Bit 29 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval29(&mut self) -> _PINVAL29W {
_PINVAL29W { w: self }
}
#[doc = "Bit 30 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval30(&mut self) -> _PINVAL30W {
_PINVAL30W { w: self }
}
#[doc = "Bit 31 - Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px\\[0\\], bit 31 in PINx corresponds to pin Px\\[31\\]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinval31(&mut self) -> _PINVAL31W {
_PINVAL31W { w: self }
}
}
}
#[doc = "Port Output Set register using FIOMASK."]
pub struct SET {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Port Output Set register using FIOMASK."]
pub mod set {
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SET {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PINSET0R {
bits: bool,
}
impl PINSET0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET1R {
bits: bool,
}
impl PINSET1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET2R {
bits: bool,
}
impl PINSET2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET3R {
bits: bool,
}
impl PINSET3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET4R {
bits: bool,
}
impl PINSET4R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET5R {
bits: bool,
}
impl PINSET5R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET6R {
bits: bool,
}
impl PINSET6R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET7R {
bits: bool,
}
impl PINSET7R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET8R {
bits: bool,
}
impl PINSET8R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET9R {
bits: bool,
}
impl PINSET9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET10R {
bits: bool,
}
impl PINSET10R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET11R {
bits: bool,
}
impl PINSET11R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET12R {
bits: bool,
}
impl PINSET12R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET13R {
bits: bool,
}
impl PINSET13R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET14R {
bits: bool,
}
impl PINSET14R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET15R {
bits: bool,
}
impl PINSET15R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET16R {
bits: bool,
}
impl PINSET16R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET17R {
bits: bool,
}
impl PINSET17R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET18R {
bits: bool,
}
impl PINSET18R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET19R {
bits: bool,
}
impl PINSET19R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET20R {
bits: bool,
}
impl PINSET20R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET21R {
bits: bool,
}
impl PINSET21R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET22R {
bits: bool,
}
impl PINSET22R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET23R {
bits: bool,
}
impl PINSET23R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET24R {
bits: bool,
}
impl PINSET24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET25R {
bits: bool,
}
impl PINSET25R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET26R {
bits: bool,
}
impl PINSET26R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET27R {
bits: bool,
}
impl PINSET27R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET28R {
bits: bool,
}
impl PINSET28R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET29R {
bits: bool,
}
impl PINSET29R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET30R {
bits: bool,
}
impl PINSET30R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct PINSET31R {
bits: bool,
}
impl PINSET31R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _PINSET0W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET1W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET2W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET3W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET4W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET5W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET6W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET7W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET8W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET9W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET10W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET11W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET12W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET13W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET14W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET15W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET16W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET17W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET18W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET19W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET20W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET21W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET22W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET23W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET24W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET25W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET26W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET27W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET28W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET29W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET30W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINSET31W<'a> {
w: &'a mut W,
}
impl<'a> _PINSET31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset0(&self) -> PINSET0R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET0R { bits }
}
#[doc = "Bit 1 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset1(&self) -> PINSET1R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET1R { bits }
}
#[doc = "Bit 2 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset2(&self) -> PINSET2R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET2R { bits }
}
#[doc = "Bit 3 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset3(&self) -> PINSET3R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET3R { bits }
}
#[doc = "Bit 4 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset4(&self) -> PINSET4R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET4R { bits }
}
#[doc = "Bit 5 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset5(&self) -> PINSET5R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET5R { bits }
}
#[doc = "Bit 6 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset6(&self) -> PINSET6R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET6R { bits }
}
#[doc = "Bit 7 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset7(&self) -> PINSET7R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET7R { bits }
}
#[doc = "Bit 8 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset8(&self) -> PINSET8R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET8R { bits }
}
#[doc = "Bit 9 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset9(&self) -> PINSET9R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 9;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET9R { bits }
}
#[doc = "Bit 10 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset10(&self) -> PINSET10R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET10R { bits }
}
#[doc = "Bit 11 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset11(&self) -> PINSET11R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 11;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET11R { bits }
}
#[doc = "Bit 12 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset12(&self) -> PINSET12R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET12R { bits }
}
#[doc = "Bit 13 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset13(&self) -> PINSET13R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET13R { bits }
}
#[doc = "Bit 14 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset14(&self) -> PINSET14R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET14R { bits }
}
#[doc = "Bit 15 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset15(&self) -> PINSET15R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET15R { bits }
}
#[doc = "Bit 16 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset16(&self) -> PINSET16R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET16R { bits }
}
#[doc = "Bit 17 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset17(&self) -> PINSET17R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET17R { bits }
}
#[doc = "Bit 18 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset18(&self) -> PINSET18R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET18R { bits }
}
#[doc = "Bit 19 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset19(&self) -> PINSET19R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 19;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET19R { bits }
}
#[doc = "Bit 20 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset20(&self) -> PINSET20R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET20R { bits }
}
#[doc = "Bit 21 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset21(&self) -> PINSET21R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET21R { bits }
}
#[doc = "Bit 22 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset22(&self) -> PINSET22R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET22R { bits }
}
#[doc = "Bit 23 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset23(&self) -> PINSET23R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET23R { bits }
}
#[doc = "Bit 24 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset24(&self) -> PINSET24R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET24R { bits }
}
#[doc = "Bit 25 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset25(&self) -> PINSET25R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET25R { bits }
}
#[doc = "Bit 26 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset26(&self) -> PINSET26R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET26R { bits }
}
#[doc = "Bit 27 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset27(&self) -> PINSET27R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET27R { bits }
}
#[doc = "Bit 28 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset28(&self) -> PINSET28R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET28R { bits }
}
#[doc = "Bit 29 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset29(&self) -> PINSET29R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET29R { bits }
}
#[doc = "Bit 30 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset30(&self) -> PINSET30R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET30R { bits }
}
#[doc = "Bit 31 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset31(&self) -> PINSET31R {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
PINSET31R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset0(&mut self) -> _PINSET0W {
_PINSET0W { w: self }
}
#[doc = "Bit 1 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset1(&mut self) -> _PINSET1W {
_PINSET1W { w: self }
}
#[doc = "Bit 2 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset2(&mut self) -> _PINSET2W {
_PINSET2W { w: self }
}
#[doc = "Bit 3 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset3(&mut self) -> _PINSET3W {
_PINSET3W { w: self }
}
#[doc = "Bit 4 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset4(&mut self) -> _PINSET4W {
_PINSET4W { w: self }
}
#[doc = "Bit 5 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset5(&mut self) -> _PINSET5W {
_PINSET5W { w: self }
}
#[doc = "Bit 6 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset6(&mut self) -> _PINSET6W {
_PINSET6W { w: self }
}
#[doc = "Bit 7 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset7(&mut self) -> _PINSET7W {
_PINSET7W { w: self }
}
#[doc = "Bit 8 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset8(&mut self) -> _PINSET8W {
_PINSET8W { w: self }
}
#[doc = "Bit 9 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset9(&mut self) -> _PINSET9W {
_PINSET9W { w: self }
}
#[doc = "Bit 10 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset10(&mut self) -> _PINSET10W {
_PINSET10W { w: self }
}
#[doc = "Bit 11 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset11(&mut self) -> _PINSET11W {
_PINSET11W { w: self }
}
#[doc = "Bit 12 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset12(&mut self) -> _PINSET12W {
_PINSET12W { w: self }
}
#[doc = "Bit 13 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset13(&mut self) -> _PINSET13W {
_PINSET13W { w: self }
}
#[doc = "Bit 14 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset14(&mut self) -> _PINSET14W {
_PINSET14W { w: self }
}
#[doc = "Bit 15 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset15(&mut self) -> _PINSET15W {
_PINSET15W { w: self }
}
#[doc = "Bit 16 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset16(&mut self) -> _PINSET16W {
_PINSET16W { w: self }
}
#[doc = "Bit 17 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset17(&mut self) -> _PINSET17W {
_PINSET17W { w: self }
}
#[doc = "Bit 18 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset18(&mut self) -> _PINSET18W {
_PINSET18W { w: self }
}
#[doc = "Bit 19 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset19(&mut self) -> _PINSET19W {
_PINSET19W { w: self }
}
#[doc = "Bit 20 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset20(&mut self) -> _PINSET20W {
_PINSET20W { w: self }
}
#[doc = "Bit 21 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset21(&mut self) -> _PINSET21W {
_PINSET21W { w: self }
}
#[doc = "Bit 22 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset22(&mut self) -> _PINSET22W {
_PINSET22W { w: self }
}
#[doc = "Bit 23 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset23(&mut self) -> _PINSET23W {
_PINSET23W { w: self }
}
#[doc = "Bit 24 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset24(&mut self) -> _PINSET24W {
_PINSET24W { w: self }
}
#[doc = "Bit 25 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset25(&mut self) -> _PINSET25W {
_PINSET25W { w: self }
}
#[doc = "Bit 26 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset26(&mut self) -> _PINSET26W {
_PINSET26W { w: self }
}
#[doc = "Bit 27 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset27(&mut self) -> _PINSET27W {
_PINSET27W { w: self }
}
#[doc = "Bit 28 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset28(&mut self) -> _PINSET28W {
_PINSET28W { w: self }
}
#[doc = "Bit 29 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset29(&mut self) -> _PINSET29W {
_PINSET29W { w: self }
}
#[doc = "Bit 30 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset30(&mut self) -> _PINSET30W {
_PINSET30W { w: self }
}
#[doc = "Bit 31 - Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px\\[0\\], bit 31 in SETx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH."]
#[inline]
pub fn pinset31(&mut self) -> _PINSET31W {
_PINSET31W { w: self }
}
}
}
#[doc = "Port Output Clear register using FIOMASK."]
pub struct CLR {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Port Output Clear register using FIOMASK."]
pub mod clr {
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLR {
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
}
#[doc = r" Proxy"]
pub struct _PINCLR0W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR0W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR1W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR1W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR2W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR2W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR3W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR3W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR4W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR4W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR5W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR5W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR6W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR6W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR7W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR7W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR8W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR8W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR9W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR9W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 9;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR10W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR10W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR11W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR11W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 11;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR12W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR12W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR13W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR13W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR14W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR14W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR15W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR15W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR16W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR16W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR17W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR17W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR18W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR18W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR19W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR19W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 19;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR20W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR20W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR21W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR21W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR22W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR22W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR23W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR23W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR24W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR24W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR25W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR25W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 25;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR26W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR26W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR27W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR27W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 27;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR28W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR28W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR29W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR29W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR30W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR30W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _PINCLR31W<'a> {
w: &'a mut W,
}
impl<'a> _PINCLR31W<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr0(&mut self) -> _PINCLR0W {
_PINCLR0W { w: self }
}
#[doc = "Bit 1 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr1(&mut self) -> _PINCLR1W {
_PINCLR1W { w: self }
}
#[doc = "Bit 2 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr2(&mut self) -> _PINCLR2W {
_PINCLR2W { w: self }
}
#[doc = "Bit 3 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr3(&mut self) -> _PINCLR3W {
_PINCLR3W { w: self }
}
#[doc = "Bit 4 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr4(&mut self) -> _PINCLR4W {
_PINCLR4W { w: self }
}
#[doc = "Bit 5 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr5(&mut self) -> _PINCLR5W {
_PINCLR5W { w: self }
}
#[doc = "Bit 6 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr6(&mut self) -> _PINCLR6W {
_PINCLR6W { w: self }
}
#[doc = "Bit 7 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr7(&mut self) -> _PINCLR7W {
_PINCLR7W { w: self }
}
#[doc = "Bit 8 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr8(&mut self) -> _PINCLR8W {
_PINCLR8W { w: self }
}
#[doc = "Bit 9 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr9(&mut self) -> _PINCLR9W {
_PINCLR9W { w: self }
}
#[doc = "Bit 10 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr10(&mut self) -> _PINCLR10W {
_PINCLR10W { w: self }
}
#[doc = "Bit 11 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr11(&mut self) -> _PINCLR11W {
_PINCLR11W { w: self }
}
#[doc = "Bit 12 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr12(&mut self) -> _PINCLR12W {
_PINCLR12W { w: self }
}
#[doc = "Bit 13 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr13(&mut self) -> _PINCLR13W {
_PINCLR13W { w: self }
}
#[doc = "Bit 14 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr14(&mut self) -> _PINCLR14W {
_PINCLR14W { w: self }
}
#[doc = "Bit 15 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr15(&mut self) -> _PINCLR15W {
_PINCLR15W { w: self }
}
#[doc = "Bit 16 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr16(&mut self) -> _PINCLR16W {
_PINCLR16W { w: self }
}
#[doc = "Bit 17 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr17(&mut self) -> _PINCLR17W {
_PINCLR17W { w: self }
}
#[doc = "Bit 18 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr18(&mut self) -> _PINCLR18W {
_PINCLR18W { w: self }
}
#[doc = "Bit 19 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr19(&mut self) -> _PINCLR19W {
_PINCLR19W { w: self }
}
#[doc = "Bit 20 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr20(&mut self) -> _PINCLR20W {
_PINCLR20W { w: self }
}
#[doc = "Bit 21 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr21(&mut self) -> _PINCLR21W {
_PINCLR21W { w: self }
}
#[doc = "Bit 22 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr22(&mut self) -> _PINCLR22W {
_PINCLR22W { w: self }
}
#[doc = "Bit 23 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr23(&mut self) -> _PINCLR23W {
_PINCLR23W { w: self }
}
#[doc = "Bit 24 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr24(&mut self) -> _PINCLR24W {
_PINCLR24W { w: self }
}
#[doc = "Bit 25 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr25(&mut self) -> _PINCLR25W {
_PINCLR25W { w: self }
}
#[doc = "Bit 26 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr26(&mut self) -> _PINCLR26W {
_PINCLR26W { w: self }
}
#[doc = "Bit 27 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr27(&mut self) -> _PINCLR27W {
_PINCLR27W { w: self }
}
#[doc = "Bit 28 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr28(&mut self) -> _PINCLR28W {
_PINCLR28W { w: self }
}
#[doc = "Bit 29 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr29(&mut self) -> _PINCLR29W {
_PINCLR29W { w: self }
}
#[doc = "Bit 30 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr30(&mut self) -> _PINCLR30W {
_PINCLR30W { w: self }
}
#[doc = "Bit 31 - Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px\\[0\\], bit 31 in CLRx controls pin Px\\[31\\]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW."]
#[inline]
pub fn pinclr31(&mut self) -> _PINCLR31W {
_PINCLR31W { w: self }
}
}
}
}
#[allow(renamed_and_removed_lints)]
#[allow(private_no_mangle_statics)]
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals"]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "WDT"]
pub WDT: WDT,
#[doc = "TIMER0"]
pub TIMER0: TIMER0,
#[doc = "TIMER1"]
pub TIMER1: TIMER1,
#[doc = "UART0"]
pub UART0: UART0,
#[doc = "UART1"]
pub UART1: UART1,
#[doc = "PWM1"]
pub PWM1: PWM1,
#[doc = "I2C0"]
pub I2C0: I2C0,
#[doc = "SPI"]
pub SPI: SPI,
#[doc = "RTC"]
pub RTC: RTC,
#[doc = "GPIOINT"]
pub GPIOINT: GPIOINT,
#[doc = "PINCONNECT"]
pub PINCONNECT: PINCONNECT,
#[doc = "SSP1"]
pub SSP1: SSP1,
#[doc = "ADC"]
pub ADC: ADC,
#[doc = "CANAFRAM"]
pub CANAFRAM: CANAFRAM,
#[doc = "CANAF"]
pub CANAF: CANAF,
#[doc = "CCAN"]
pub CCAN: CCAN,
#[doc = "CAN1"]
pub CAN1: CAN1,
#[doc = "CAN2"]
pub CAN2: CAN2,
#[doc = "I2C1"]
pub I2C1: I2C1,
#[doc = "SSP0"]
pub SSP0: SSP0,
#[doc = "DAC"]
pub DAC: DAC,
#[doc = "TIMER2"]
pub TIMER2: TIMER2,
#[doc = "TIMER3"]
pub TIMER3: TIMER3,
#[doc = "UART2"]
pub UART2: UART2,
#[doc = "UART3"]
pub UART3: UART3,
#[doc = "I2C2"]
pub I2C2: I2C2,
#[doc = "I2S"]
pub I2S: I2S,
#[doc = "RITIMER"]
pub RITIMER: RITIMER,
#[doc = "MCPWM"]
pub MCPWM: MCPWM,
#[doc = "QEI"]
pub QEI: QEI,
#[doc = "SYSCON"]
pub SYSCON: SYSCON,
#[doc = "EMAC"]
pub EMAC: EMAC,
#[doc = "GPDMA"]
pub GPDMA: GPDMA,
#[doc = "USB"]
pub USB: USB,
#[doc = "GPIO"]
pub GPIO: GPIO,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*"]
#[inline]
pub fn take() -> Option<Self> {
cortex_m::interrupt::free(|_| {
if unsafe { DEVICE_PERIPHERALS } {
None
} else {
Some(unsafe { Peripherals::steal() })
}
})
}
#[doc = r" Unchecked version of `Peripherals::take`"]
pub unsafe fn steal() -> Self {
debug_assert!(!DEVICE_PERIPHERALS);
DEVICE_PERIPHERALS = true;
Peripherals {
WDT: WDT {
_marker: PhantomData,
},
TIMER0: TIMER0 {
_marker: PhantomData,
},
TIMER1: TIMER1 {
_marker: PhantomData,
},
UART0: UART0 {
_marker: PhantomData,
},
UART1: UART1 {
_marker: PhantomData,
},
PWM1: PWM1 {
_marker: PhantomData,
},
I2C0: I2C0 {
_marker: PhantomData,
},
SPI: SPI {
_marker: PhantomData,
},
RTC: RTC {
_marker: PhantomData,
},
GPIOINT: GPIOINT {
_marker: PhantomData,
},
PINCONNECT: PINCONNECT {
_marker: PhantomData,
},
SSP1: SSP1 {
_marker: PhantomData,
},
ADC: ADC {
_marker: PhantomData,
},
CANAFRAM: CANAFRAM {
_marker: PhantomData,
},
CANAF: CANAF {
_marker: PhantomData,
},
CCAN: CCAN {
_marker: PhantomData,
},
CAN1: CAN1 {
_marker: PhantomData,
},
CAN2: CAN2 {
_marker: PhantomData,
},
I2C1: I2C1 {
_marker: PhantomData,
},
SSP0: SSP0 {
_marker: PhantomData,
},
DAC: DAC {
_marker: PhantomData,
},
TIMER2: TIMER2 {
_marker: PhantomData,
},
TIMER3: TIMER3 {
_marker: PhantomData,
},
UART2: UART2 {
_marker: PhantomData,
},
UART3: UART3 {
_marker: PhantomData,
},
I2C2: I2C2 {
_marker: PhantomData,
},
I2S: I2S {
_marker: PhantomData,
},
RITIMER: RITIMER {
_marker: PhantomData,
},
MCPWM: MCPWM {
_marker: PhantomData,
},
QEI: QEI {
_marker: PhantomData,
},
SYSCON: SYSCON {
_marker: PhantomData,
},
EMAC: EMAC {
_marker: PhantomData,
},
GPDMA: GPDMA {
_marker: PhantomData,
},
USB: USB {
_marker: PhantomData,
},
GPIO: GPIO {
_marker: PhantomData,
},
}
}
}