#[doc = "Register `TER` reader"]
pub struct R(crate::R<TER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TER` writer"]
pub struct W(crate::W<TER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXEN` reader - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."]
pub type TXEN_R = crate::BitReader<bool>;
#[doc = "Field `TXEN` writer - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."]
pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, TER_SPEC, bool, O>;
impl R {
#[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."]
#[inline(always)]
pub fn txen(&self) -> TXEN_R {
TXEN_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."]
#[inline(always)]
pub fn txen(&mut self) -> TXEN_W<7> {
TXEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ter](index.html) module"]
pub struct TER_SPEC;
impl crate::RegisterSpec for TER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ter::R](R) reader structure"]
impl crate::Readable for TER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ter::W](W) writer structure"]
impl crate::Writable for TER_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets TER to value 0x80"]
impl crate::Resettable for TER_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0x80
}
}